[PATCH RFC 07/24] drm/lima: add mali 4xx GPU hardware regs

[Qiang Yu <yuq825@gmail.com>]

From: Lima Project Developers <dri-devel@lists.freedesktop.org>

Signed-off-by: Qiang Yu <yuq825@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
---
 drivers/gpu/drm/lima/lima_regs.h | 304 +++++++++++++++++++++++++++++++
 1 file changed, 304 insertions(+)
 create mode 100644 drivers/gpu/drm/lima/lima_regs.h

diff --git a/drivers/gpu/drm/lima/lima_regs.h b/drivers/gpu/drm/lima/lima_regs.h
new file mode 100644
index 000000000000..ea4a37d69b98
--- /dev/null
+++ b/drivers/gpu/drm/lima/lima_regs.h
@@ -0,0 +1,304 @@
+/*
+ * Copyright (C) 2010-2017 ARM Limited. All rights reserved.
+ * Copyright (C) 2017-2018 Lima Project
+ * 
+ * This program is free software and is provided to you under
+ * the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation, and any use by
+ * you of this program is subject to the terms of such GNU
+ * licence.
+ * 
+ * A copy of the licence is included with the program, and
+ * can also be obtained from Free Software Foundation, Inc.,
+ * 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+ */
+
+#ifndef __LIMA_REGS_H__
+#define __LIMA_REGS_H__
+
+/* PMU regs */
+#define LIMA_PMU_POWER_UP                  0x00
+#define LIMA_PMU_POWER_DOWN                0x04
+#define   LIMA_PMU_POWER_GP0_MASK          (1 << 0)
+#define   LIMA_PMU_POWER_L2_MASK           (1 << 1)
+#define   LIMA_PMU_POWER_PP_MASK(i)        (1 << (2 + i))
+
+/*
+ * On Mali450 each block automatically starts up its corresponding L2
+ * and the PPs are not fully independent controllable.
+ * Instead PP0, PP1-3 and PP4-7 can be turned on or off.
+ */
+#define   LIMA450_PMU_POWER_PP0_MASK       BIT(1)
+#define   LIMA450_PMU_POWER_PP13_MASK      BIT(2)
+#define   LIMA450_PMU_POWER_PP47_MASK      BIT(3)
+
+#define LIMA_PMU_STATUS                    0x08
+#define LIMA_PMU_INT_MASK                  0x0C
+#define LIMA_PMU_INT_RAWSTAT               0x10
+#define LIMA_PMU_INT_CLEAR                 0x18
+#define   LIMA_PMU_INT_CMD_MASK            (1 << 0)
+#define LIMA_PMU_SW_DELAY                  0x1C
+
+/* L2 cache regs */
+#define LIMA_L2_CACHE_SIZE		 0x0004
+#define LIMA_L2_CACHE_STATUS		 0x0008
+#define   LIMA_L2_CACHE_STATUS_COMMAND_BUSY  (1 << 0)
+#define   LIMA_L2_CACHE_STATUS_DATA_BUSY     (1 << 1)
+#define LIMA_L2_CACHE_COMMAND		 0x0010
+#define   LIMA_L2_CACHE_COMMAND_CLEAR_ALL    (1 << 0)
+#define LIMA_L2_CACHE_CLEAR_PAGE	 0x0014
+#define LIMA_L2_CACHE_MAX_READS		 0x0018
+#define LIMA_L2_CACHE_ENABLE		 0x001C
+#define   LIMA_L2_CACHE_ENABLE_ACCESS        (1 << 0)
+#define   LIMA_L2_CACHE_ENABLE_READ_ALLOCATE (1 << 1)
+#define LIMA_L2_CACHE_PERFCNT_SRC0	 0x0020
+#define LIMA_L2_CACHE_PERFCNT_VAL0	 0x0024
+#define LIMA_L2_CACHE_PERFCNT_SRC1	 0x0028
+#define LIMA_L2_CACHE_ERFCNT_VAL1	 0x002C
+
+/* GP regs */
+#define LIMA_GP_VSCL_START_ADDR                0x00
+#define LIMA_GP_VSCL_END_ADDR                  0x04
+#define LIMA_GP_PLBUCL_START_ADDR              0x08
+#define LIMA_GP_PLBUCL_END_ADDR                0x0c
+#define LIMA_GP_PLBU_ALLOC_START_ADDR          0x10
+#define LIMA_GP_PLBU_ALLOC_END_ADDR            0x14
+#define LIMA_GP_CMD                            0x20
+#define   LIMA_GP_CMD_START_VS                 (1 << 0)
+#define   LIMA_GP_CMD_START_PLBU               (1 << 1)
+#define   LIMA_GP_CMD_UPDATE_PLBU_ALLOC        (1 << 4)
+#define   LIMA_GP_CMD_RESET                    (1 << 5)
+#define   LIMA_GP_CMD_FORCE_HANG               (1 << 6)
+#define   LIMA_GP_CMD_STOP_BUS                 (1 << 9)
+#define   LIMA_GP_CMD_SOFT_RESET               (1 << 10)
+#define LIMA_GP_INT_RAWSTAT                    0x24
+#define LIMA_GP_INT_CLEAR                      0x28
+#define LIMA_GP_INT_MASK                       0x2C
+#define LIMA_GP_INT_STAT                       0x30
+#define   LIMA_GP_IRQ_VS_END_CMD_LST           (1 << 0)
+#define   LIMA_GP_IRQ_PLBU_END_CMD_LST         (1 << 1)
+#define   LIMA_GP_IRQ_PLBU_OUT_OF_MEM          (1 << 2)
+#define   LIMA_GP_IRQ_VS_SEM_IRQ               (1 << 3)
+#define   LIMA_GP_IRQ_PLBU_SEM_IRQ             (1 << 4)
+#define   LIMA_GP_IRQ_HANG                     (1 << 5)
+#define   LIMA_GP_IRQ_FORCE_HANG               (1 << 6)
+#define   LIMA_GP_IRQ_PERF_CNT_0_LIMIT         (1 << 7)
+#define   LIMA_GP_IRQ_PERF_CNT_1_LIMIT         (1 << 8)
+#define   LIMA_GP_IRQ_WRITE_BOUND_ERR          (1 << 9)
+#define   LIMA_GP_IRQ_SYNC_ERROR               (1 << 10)
+#define   LIMA_GP_IRQ_AXI_BUS_ERROR            (1 << 11)
+#define   LIMA_GP_IRQ_AXI_BUS_STOPPED          (1 << 12)
+#define   LIMA_GP_IRQ_VS_INVALID_CMD           (1 << 13)
+#define   LIMA_GP_IRQ_PLB_INVALID_CMD          (1 << 14)
+#define   LIMA_GP_IRQ_RESET_COMPLETED          (1 << 19)
+#define   LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW      (1 << 20)
+#define   LIMA_GP_IRQ_SEMAPHORE_OVERFLOW       (1 << 21)
+#define   LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS  (1 << 22)
+#define LIMA_GP_WRITE_BOUND_LOW                0x34
+#define LIMA_GP_PERF_CNT_0_ENABLE              0x3C
+#define LIMA_GP_PERF_CNT_1_ENABLE              0x40
+#define LIMA_GP_PERF_CNT_0_SRC                 0x44
+#define LIMA_GP_PERF_CNT_1_SRC                 0x48
+#define LIMA_GP_PERF_CNT_0_VALUE               0x4C
+#define LIMA_GP_PERF_CNT_1_VALUE               0x50
+#define LIMA_GP_PERF_CNT_0_LIMIT               0x54
+#define LIMA_GP_STATUS                         0x68
+#define   LIMA_GP_STATUS_VS_ACTIVE             (1 << 1)
+#define   LIMA_GP_STATUS_BUS_STOPPED	       (1 << 2)
+#define	  LIMA_GP_STATUS_PLBU_ACTIVE	       (1 << 3)
+#define	  LIMA_GP_STATUS_BUS_ERROR	       (1 << 6)
+#define	  LIMA_GP_STATUS_WRITE_BOUND_ERR       (1 << 8)
+#define LIMA_GP_VERSION                        0x6C
+#define LIMA_GP_VSCL_START_ADDR_READ           0x80
+#define LIMA_GP_PLBCL_START_ADDR_READ          0x84
+#define LIMA_GP_CONTR_AXI_BUS_ERROR_STAT       0x94
+
+#define LIMA_GP_IRQ_MASK_ALL		   \
+	(				   \
+	 LIMA_GP_IRQ_VS_END_CMD_LST      | \
+	 LIMA_GP_IRQ_PLBU_END_CMD_LST    | \
+	 LIMA_GP_IRQ_PLBU_OUT_OF_MEM     | \
+	 LIMA_GP_IRQ_VS_SEM_IRQ          | \
+	 LIMA_GP_IRQ_PLBU_SEM_IRQ        | \
+	 LIMA_GP_IRQ_HANG                | \
+	 LIMA_GP_IRQ_FORCE_HANG          | \
+	 LIMA_GP_IRQ_PERF_CNT_0_LIMIT    | \
+	 LIMA_GP_IRQ_PERF_CNT_1_LIMIT    | \
+	 LIMA_GP_IRQ_WRITE_BOUND_ERR     | \
+	 LIMA_GP_IRQ_SYNC_ERROR          | \
+	 LIMA_GP_IRQ_AXI_BUS_ERROR       | \
+	 LIMA_GP_IRQ_AXI_BUS_STOPPED     | \
+	 LIMA_GP_IRQ_VS_INVALID_CMD      | \
+	 LIMA_GP_IRQ_PLB_INVALID_CMD     | \
+	 LIMA_GP_IRQ_RESET_COMPLETED     | \
+	 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \
+	 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW  | \
+	 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+
+#define LIMA_GP_IRQ_MASK_ERROR             \
+	(                                  \
+	 LIMA_GP_IRQ_PLBU_OUT_OF_MEM     | \
+	 LIMA_GP_IRQ_FORCE_HANG          | \
+	 LIMA_GP_IRQ_WRITE_BOUND_ERR     | \
+	 LIMA_GP_IRQ_SYNC_ERROR          | \
+	 LIMA_GP_IRQ_AXI_BUS_ERROR       | \
+	 LIMA_GP_IRQ_VS_INVALID_CMD      | \
+	 LIMA_GP_IRQ_PLB_INVALID_CMD     | \
+	 LIMA_GP_IRQ_SEMAPHORE_UNDERFLOW | \
+	 LIMA_GP_IRQ_SEMAPHORE_OVERFLOW  | \
+	 LIMA_GP_IRQ_PTR_ARRAY_OUT_OF_BOUNDS)
+
+#define LIMA_GP_IRQ_MASK_USED		   \
+	(				   \
+	 LIMA_GP_IRQ_VS_END_CMD_LST      | \
+	 LIMA_GP_IRQ_PLBU_END_CMD_LST    | \
+	 LIMA_GP_IRQ_MASK_ERROR)
+
+/* PP regs */
+#define LIMA_PP_FRAME                        0x0000
+#define LIMA_PP_RSW			     0x0004
+#define LIMA_PP_STACK			     0x0030
+#define LIMA_PP_STACK_SIZE		     0x0034
+#define LIMA_PP_ORIGIN_OFFSET_X	             0x0040
+#define LIMA_PP_WB(i) 			     (0x0100 * (i + 1))
+#define   LIMA_PP_WB_SOURCE_SELECT           0x0000
+#define	  LIMA_PP_WB_SOURCE_ADDR             0x0004
+
+#define LIMA_PP_VERSION                      0x1000
+#define LIMA_PP_CURRENT_REND_LIST_ADDR       0x1004
+#define	LIMA_PP_STATUS                       0x1008
+#define	  LIMA_PP_STATUS_RENDERING_ACTIVE    (1 << 0)
+#define	  LIMA_PP_STATUS_BUS_STOPPED	     (1 << 4)
+#define	LIMA_PP_CTRL                         0x100c
+#define   LIMA_PP_CTRL_STOP_BUS	             (1 << 0)
+#define	  LIMA_PP_CTRL_FLUSH_CACHES          (1 << 3)
+#define	  LIMA_PP_CTRL_FORCE_RESET           (1 << 5)
+#define	  LIMA_PP_CTRL_START_RENDERING       (1 << 6)
+#define	  LIMA_PP_CTRL_SOFT_RESET            (1 << 7)
+#define	LIMA_PP_INT_RAWSTAT                  0x1020
+#define	LIMA_PP_INT_CLEAR                    0x1024
+#define	LIMA_PP_INT_MASK                     0x1028
+#define	LIMA_PP_INT_STATUS                   0x102c
+#define	  LIMA_PP_IRQ_END_OF_FRAME           (1 << 0)
+#define	  LIMA_PP_IRQ_END_OF_TILE	     (1 << 1)
+#define	  LIMA_PP_IRQ_HANG		     (1 << 2)
+#define	  LIMA_PP_IRQ_FORCE_HANG	     (1 << 3)
+#define	  LIMA_PP_IRQ_BUS_ERROR		     (1 << 4)
+#define	  LIMA_PP_IRQ_BUS_STOP		     (1 << 5)
+#define	  LIMA_PP_IRQ_CNT_0_LIMIT	     (1 << 6)
+#define	  LIMA_PP_IRQ_CNT_1_LIMIT	     (1 << 7)
+#define	  LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR   (1 << 8)
+#define	  LIMA_PP_IRQ_INVALID_PLIST_COMMAND  (1 << 9)
+#define	  LIMA_PP_IRQ_CALL_STACK_UNDERFLOW   (1 << 10)
+#define	  LIMA_PP_IRQ_CALL_STACK_OVERFLOW    (1 << 11)
+#define	  LIMA_PP_IRQ_RESET_COMPLETED	     (1 << 12)
+#define	LIMA_PP_WRITE_BOUNDARY_LOW           0x1044
+#define	LIMA_PP_BUS_ERROR_STATUS             0x1050
+#define	LIMA_PP_PERF_CNT_0_ENABLE            0x1080
+#define	LIMA_PP_PERF_CNT_0_SRC               0x1084
+#define	LIMA_PP_PERF_CNT_0_LIMIT             0x1088
+#define	LIMA_PP_PERF_CNT_0_VALUE             0x108c
+#define	LIMA_PP_PERF_CNT_1_ENABLE            0x10a0
+#define	LIMA_PP_PERF_CNT_1_SRC               0x10a4
+#define	LIMA_PP_PERF_CNT_1_LIMIT             0x10a8
+#define	LIMA_PP_PERF_CNT_1_VALUE             0x10ac
+#define LIMA_PP_PERFMON_CONTR                0x10b0
+#define LIMA_PP_PERFMON_BASE                 0x10b4
+
+#define LIMA_PP_IRQ_MASK_ALL                 \
+	(                                    \
+	 LIMA_PP_IRQ_END_OF_FRAME          | \
+	 LIMA_PP_IRQ_END_OF_TILE           | \
+	 LIMA_PP_IRQ_HANG                  | \
+	 LIMA_PP_IRQ_FORCE_HANG            | \
+	 LIMA_PP_IRQ_BUS_ERROR             | \
+	 LIMA_PP_IRQ_BUS_STOP              | \
+	 LIMA_PP_IRQ_CNT_0_LIMIT           | \
+	 LIMA_PP_IRQ_CNT_1_LIMIT           | \
+	 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR  | \
+	 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \
+	 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW  | \
+	 LIMA_PP_IRQ_CALL_STACK_OVERFLOW   | \
+	 LIMA_PP_IRQ_RESET_COMPLETED)
+
+#define LIMA_PP_IRQ_MASK_ERROR               \
+	(                                    \
+	 LIMA_PP_IRQ_FORCE_HANG            | \
+	 LIMA_PP_IRQ_BUS_ERROR             | \
+	 LIMA_PP_IRQ_WRITE_BOUNDARY_ERROR  | \
+	 LIMA_PP_IRQ_INVALID_PLIST_COMMAND | \
+	 LIMA_PP_IRQ_CALL_STACK_UNDERFLOW  | \
+	 LIMA_PP_IRQ_CALL_STACK_OVERFLOW)
+
+#define LIMA_PP_IRQ_MASK_USED                \
+	(                                    \
+	 LIMA_PP_IRQ_END_OF_FRAME          | \
+	 LIMA_PP_IRQ_MASK_ERROR)
+
+/* MMU regs */
+#define LIMA_MMU_DTE_ADDR		  0x0000
+#define LIMA_MMU_STATUS			  0x0004
+#define   LIMA_MMU_STATUS_PAGING_ENABLED      (1 << 0)
+#define   LIMA_MMU_STATUS_PAGE_FAULT_ACTIVE   (1 << 1)
+#define   LIMA_MMU_STATUS_STALL_ACTIVE        (1 << 2)
+#define   LIMA_MMU_STATUS_IDLE                (1 << 3)
+#define   LIMA_MMU_STATUS_REPLAY_BUFFER_EMPTY (1 << 4)
+#define   LIMA_MMU_STATUS_PAGE_FAULT_IS_WRITE (1 << 5)
+#define   LIMA_MMU_STATUS_BUS_ID(x)           ((x >> 6) & 0x1F)
+#define LIMA_MMU_COMMAND		  0x0008
+#define   LIMA_MMU_COMMAND_ENABLE_PAGING    0x00
+#define   LIMA_MMU_COMMAND_DISABLE_PAGING   0x01
+#define   LIMA_MMU_COMMAND_ENABLE_STALL     0x02
+#define   LIMA_MMU_COMMAND_DISABLE_STALL    0x03
+#define   LIMA_MMU_COMMAND_ZAP_CACHE        0x04
+#define   LIMA_MMU_COMMAND_PAGE_FAULT_DONE  0x05
+#define   LIMA_MMU_COMMAND_HARD_RESET       0x06
+#define LIMA_MMU_PAGE_FAULT_ADDR          0x000C
+#define LIMA_MMU_ZAP_ONE_LINE	          0x0010
+#define LIMA_MMU_INT_RAWSTAT	          0x0014
+#define LIMA_MMU_INT_CLEAR		  0x0018
+#define LIMA_MMU_INT_MASK		  0x001C
+#define   LIMA_MMU_INT_PAGE_FAULT           0x01
+#define   LIMA_MMU_INT_READ_BUS_ERROR       0x02
+#define LIMA_MMU_INT_STATUS		  0x0020
+
+#define LIMA_VM_FLAG_PRESENT          (1 << 0)
+#define LIMA_VM_FLAG_READ_PERMISSION  (1 << 1)
+#define LIMA_VM_FLAG_WRITE_PERMISSION (1 << 2)
+#define LIMA_VM_FLAG_OVERRIDE_CACHE   (1 << 3)
+#define LIMA_VM_FLAG_WRITE_CACHEABLE  (1 << 4)
+#define LIMA_VM_FLAG_WRITE_ALLOCATE   (1 << 5)
+#define LIMA_VM_FLAG_WRITE_BUFFERABLE (1 << 6)
+#define LIMA_VM_FLAG_READ_CACHEABLE   (1 << 7)
+#define LIMA_VM_FLAG_READ_ALLOCATE    (1 << 8)
+#define LIMA_VM_FLAG_MASK             0x1FF
+
+#define LIMA_VM_FLAGS_CACHE (			 \
+		LIMA_VM_FLAG_PRESENT |		 \
+		LIMA_VM_FLAG_READ_PERMISSION |	 \
+		LIMA_VM_FLAG_WRITE_PERMISSION |	 \
+		LIMA_VM_FLAG_OVERRIDE_CACHE |	 \
+		LIMA_VM_FLAG_WRITE_CACHEABLE |	 \
+		LIMA_VM_FLAG_WRITE_BUFFERABLE |	 \
+		LIMA_VM_FLAG_READ_CACHEABLE |	 \
+		LIMA_VM_FLAG_READ_ALLOCATE )
+
+#define LIMA_VM_FLAGS_UNCACHE (			\
+		LIMA_VM_FLAG_PRESENT |		\
+		LIMA_VM_FLAG_READ_PERMISSION |	\
+		LIMA_VM_FLAG_WRITE_PERMISSION )
+
+/* DLBU regs */
+#define LIMA_DLBU_MASTER_TLLIST_PHYS_ADDR  0x0000
+#define	LIMA_DLBU_MASTER_TLLIST_VADDR      0x0004
+#define	LIMA_DLBU_TLLIST_VBASEADDR         0x0008
+#define	LIMA_DLBU_FB_DIM                   0x000C
+#define	LIMA_DLBU_TLLIST_CONF              0x0010
+#define	LIMA_DLBU_START_TILE_POS           0x0014
+#define	LIMA_DLBU_PP_ENABLE_MASK           0x0018
+
+/* BCAST regs */
+#define LIMA_BCAST_BROADCAST_MASK    0x0
+#define LIMA_BCAST_INTERRUPT_MASK    0x4
+
+#endif
-- 
2.17.0

_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel