[PATCH v2] drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits

* [PATCH v2] drm/i915/cmdparser: Whitelist INSTPM instruction parsing disable bits
@ 2018-05-18 17:14 Lionel Landwerlin
  2018-05-18 17:27 ` Chris Wilson
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Lionel Landwerlin @ 2018-05-18 17:14 UTC (permalink / raw)
  To: intel-gfx

On Gen8+ this register is not priviledged and we want to use it in
Mesa to implement a feature required by GPA called Null Hardware. The
idea is to have the command parser turn 3DPRIMITIVE/GPGPU_WALKER into
NOOPs.

This patch just whitelists the bits that we need and that are
currently not used by the kernel.

v2: Bump the command parser revision (Chris)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
---
 drivers/gpu/drm/i915/i915_cmd_parser.c | 11 ++++++++++-
 drivers/gpu/drm/i915/i915_reg.h        |  3 +++
 2 files changed, 13 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c
index 95478db9998b..bb51d2c6c4c8 100644
--- a/drivers/gpu/drm/i915/i915_cmd_parser.c
+++ b/drivers/gpu/drm/i915/i915_cmd_parser.c
@@ -534,6 +534,14 @@ struct drm_i915_reg_descriptor {
 	{ .addr = _reg ## _UDW(idx) }
 
 static const struct drm_i915_reg_descriptor gen7_render_regs[] = {
+	REG32(INSTPM,
+	      .mask = ~((INSTPM_3D_STATE_INSTRUCTION_DISABLE |
+			 INSTPM_3D_RENDERING_INSTRUCTION_DISABLE |
+			 INSTPM_3D_MEDIA_INSTRUCTION_DISABLE) << 16 |
+			(INSTPM_3D_STATE_INSTRUCTION_DISABLE |
+			 INSTPM_3D_RENDERING_INSTRUCTION_DISABLE |
+			 INSTPM_3D_MEDIA_INSTRUCTION_DISABLE)),
+	      .value = 0),
 	REG64(GPGPU_THREADS_DISPATCHED),
 	REG64(HS_INVOCATION_COUNT),
 	REG64(DS_INVOCATION_COUNT),
@@ -1382,6 +1390,7 @@ int i915_cmd_parser_get_version(struct drm_i915_private *dev_priv)
 	 *    the parser enabled.
 	 * 9. Don't whitelist or handle oacontrol specially, as ownership
 	 *    for oacontrol state is moving to i915-perf.
+	 * 10. Whitelist INSTPM on Ivybridge & Haswell.
 	 */
-	return 9;
+	return 10;
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 196a0eb79272..86ab1303724a 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2531,6 +2531,9 @@ enum i915_power_well_id {
 #define   INSTPM_FORCE_ORDERING				(1<<7) /* GEN6+ */
 #define   INSTPM_TLB_INVALIDATE	(1<<9)
 #define   INSTPM_SYNC_FLUSH	(1<<5)
+#define   INSTPM_3D_MEDIA_INSTRUCTION_DISABLE     (1 << 3) /* GEN6+ */
+#define   INSTPM_3D_RENDERING_INSTRUCTION_DISABLE (1 << 2) /* GEN6+ */
+#define   INSTPM_3D_STATE_INSTRUCTION_DISABLE     (1 << 1) /* GEN6+ */
 #define ACTHD	        _MMIO(0x20c8)
 #define MEM_MODE	_MMIO(0x20cc)
 #define   MEM_DISPLAY_B_TRICKLE_FEED_DISABLE (1<<3) /* 830 only */
-- 
2.17.0

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