[PATCH 0/3] Exynos DRM - add 2 more planes to Decon on Exynos5433

[PATCH 0/3] Exynos DRM - add 2 more planes to Decon on Exynos5433

[Marek Szyprowski]

Dear all,

This patchset enables support for 2 more hardware windows in Exynos5433
Decon's, what gives us 2 more overlay planes. This require enabling
a few more clocks to get it working properly.

My merge plan for this patchset:
1. dts (patch 2/3) - please schedule for v4.18 merge window
2. driver (patch 3/3) - please schedule for the next release after dts is
   merged
3. bindings (patch 1/3) - probably can go together with the driver patch

Best regards
Marek Szyprowski
Samsung R&D Institute Poland

Marek Szyprowski (3):
  dt-bindings: exynos5433-decon: add more required clocks
  arm64: dts: exynos: Add more clocks to Exynos5433 Decon and DeconTV
  drm/exynos: decon: Add support for hardware windows no 4 and 5

 .../display/exynos/exynos5433-decon.txt       |  9 ++++++--
 arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 14 +++++++++++--
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 +++++++++++--------
 3 files changed, 31 insertions(+), 13 deletions(-)

-- 
2.17.0

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[PATCH 1/3] dt-bindings: exynos5433-decon: add more required clocks

[Marek Szyprowski]

Proper support for Decon's hardware window no 4 and 5 require enabling
a few more clocks ("aclk_smmu_decon1x", "aclk_xiu_decon1x",
"pclk_smmu_decon1x"). Add those clocks to required clocks list in Decon's
dt bindings.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 .../bindings/display/exynos/exynos5433-decon.txt         | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt b/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt
index fc2588292a68..775193e1c641 100644
--- a/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt
+++ b/Documentation/devicetree/bindings/display/exynos/exynos5433-decon.txt
@@ -19,7 +19,8 @@ Required properties:
 	  clock-names property.
 - clock-names: list of clock names sorted in the same order as the clocks
 	       property. Must contain "pclk", "aclk_decon", "aclk_smmu_decon0x",
-	       "aclk_xiu_decon0x", "pclk_smmu_decon0x", clk_decon_vclk",
+	       "aclk_xiu_decon0x", "pclk_smmu_decon0x", "aclk_smmu_decon1x",
+	       "aclk_xiu_decon1x", "pclk_smmu_decon1x", clk_decon_vclk",
 	       "sclk_decon_eclk"
 - ports: contains a port which is connected to mic node. address-cells and
 	 size-cells must 1 and 0, respectively.
@@ -34,10 +35,14 @@ decon: decon@13800000 {
 	clocks = <&cmu_disp CLK_ACLK_DECON>, <&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 		<&cmu_disp CLK_ACLK_XIU_DECON0X>,
 		<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+		<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+		<&cmu_disp CLK_ACLK_XIU_DECON1X>,
+		<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 		<&cmu_disp CLK_SCLK_DECON_VCLK>,
 		<&cmu_disp CLK_SCLK_DECON_ECLK>;
 	clock-names = "aclk_decon", "aclk_smmu_decon0x", "aclk_xiu_decon0x",
-		"pclk_smmu_decon0x", "sclk_decon_vclk", "sclk_decon_eclk";
+		"pclk_smmu_decon0x", "aclk_smmu_decon1x", "aclk_xiu_decon1x",
+		"pclk_smmu_decon1x", "sclk_decon_vclk", "sclk_decon_eclk";
 	interrupt-names = "vsync", "lcd_sys";
 	interrupts = <0 202 0>, <0 203 0>;
 
-- 
2.17.0

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[PATCH 2/3] arm64: dts: exynos: Add more clocks to Exynos5433 Decon/DeconTV

[Marek Szyprowski]

Add all '1x' clocks to decon and decontv devices. Enabling those clocks
is needed to get proper display on hardware windows no 4 and 5.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++--
 1 file changed, 12 insertions(+), 2 deletions(-)

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0ec44180d1b7..038c99792ccb 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -829,11 +829,16 @@
 				<&cmu_disp CLK_ACLK_SMMU_DECON0X>,
 				<&cmu_disp CLK_ACLK_XIU_DECON0X>,
 				<&cmu_disp CLK_PCLK_SMMU_DECON0X>,
+				<&cmu_disp CLK_ACLK_SMMU_DECON1X>,
+				<&cmu_disp CLK_ACLK_XIU_DECON1X>,
+				<&cmu_disp CLK_PCLK_SMMU_DECON1X>,
 				<&cmu_disp CLK_SCLK_DECON_VCLK>,
 				<&cmu_disp CLK_SCLK_DECON_ECLK>;
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				"aclk_xiu_decon0x", "pclk_smmu_decon0x",
-				"sclk_decon_vclk", "sclk_decon_eclk";
+				"aclk_smmu_decon1x", "aclk_xiu_decon1x",
+				"pclk_smmu_decon1x", "sclk_decon_vclk",
+				"sclk_decon_eclk";
 			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
 			interrupts = <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
@@ -866,11 +871,16 @@
 				 <&cmu_disp CLK_ACLK_SMMU_TV0X>,
 				 <&cmu_disp CLK_ACLK_XIU_TV0X>,
 				 <&cmu_disp CLK_PCLK_SMMU_TV0X>,
+				 <&cmu_disp CLK_ACLK_SMMU_TV1X>,
+				 <&cmu_disp CLK_ACLK_XIU_TV1X>,
+				 <&cmu_disp CLK_PCLK_SMMU_TV1X>,
 				 <&cmu_disp CLK_SCLK_DECON_TV_VCLK>,
 				 <&cmu_disp CLK_SCLK_DECON_TV_ECLK>;
 			clock-names = "pclk", "aclk_decon", "aclk_smmu_decon0x",
 				      "aclk_xiu_decon0x", "pclk_smmu_decon0x",
-				      "sclk_decon_vclk", "sclk_decon_eclk";
+				      "aclk_smmu_decon1x", "aclk_xiu_decon1x",
+				      "pclk_smmu_decon1x", "sclk_decon_vclk",
+				      "sclk_decon_eclk";
 			samsung,disp-sysreg = <&syscon_disp>;
 			power-domains = <&pd_disp>;
 			interrupt-names = "fifo", "vsync", "lcd_sys";
-- 
2.17.0

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[PATCH 3/3] drm/exynos: decon: Add support for hardware windows no 4 and 5

[Marek Szyprowski]

Enable support for 2 more hardware windows. This require enabling a few
more clocks and set proper plane type for all windows. In the new
configuration primary plane uses hardware window no 3 and cursor uses
window no 5. The remaining hardware windows are used for overlays. This
gives us an overlay plane both below and above primary plane for both
Decon and DeconTV (which uses hardware window nr 0 for background).

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
---
 drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
index 1c330f2a7a5d..82c95c34447f 100644
--- a/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
+++ b/drivers/gpu/drm/exynos/exynos5433_drm_decon.c
@@ -31,7 +31,10 @@
 #define DSD_CFG_MUX 0x1004
 #define DSD_CFG_MUX_TE_UNMASK_GLOBAL BIT(13)
 
-#define WINDOWS_NR	3
+#define WINDOWS_NR	5
+#define PRIMARY_WIN	2
+#define CURSON_WIN	4
+
 #define MIN_FB_WIDTH_FOR_16WORD_BURST	128
 
 #define I80_HW_TRG	(1 << 0)
@@ -43,6 +46,9 @@ static const char * const decon_clks_name[] = {
 	"aclk_smmu_decon0x",
 	"aclk_xiu_decon0x",
 	"pclk_smmu_decon0x",
+	"aclk_smmu_decon1x",
+	"aclk_xiu_decon1x",
+	"pclk_smmu_decon1x",
 	"sclk_decon_vclk",
 	"sclk_decon_eclk",
 };
@@ -74,9 +80,8 @@ static const uint32_t decon_formats[] = {
 };
 
 static const enum drm_plane_type decon_win_types[WINDOWS_NR] = {
-	DRM_PLANE_TYPE_PRIMARY,
-	DRM_PLANE_TYPE_OVERLAY,
-	DRM_PLANE_TYPE_CURSOR,
+	[PRIMARY_WIN] = DRM_PLANE_TYPE_PRIMARY,
+	[CURSON_WIN] = DRM_PLANE_TYPE_CURSOR,
 };
 
 static inline void decon_set_bits(struct decon_context *ctx, u32 reg, u32 mask,
@@ -552,12 +557,10 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
 	drm_dev->max_vblank_count = 0xffffffff;
 
 	for (win = ctx->first_win; win < WINDOWS_NR; win++) {
-		int tmp = (win == ctx->first_win) ? 0 : win;
-
 		ctx->configs[win].pixel_formats = decon_formats;
 		ctx->configs[win].num_pixel_formats = ARRAY_SIZE(decon_formats);
-		ctx->configs[win].zpos = win;
-		ctx->configs[win].type = decon_win_types[tmp];
+		ctx->configs[win].zpos = win - ctx->first_win;
+		ctx->configs[win].type = decon_win_types[win];
 
 		ret = exynos_plane_init(drm_dev, &ctx->planes[win], win,
 					&ctx->configs[win]);
@@ -565,7 +568,7 @@ static int decon_bind(struct device *dev, struct device *master, void *data)
 			return ret;
 	}
 
-	exynos_plane = &ctx->planes[ctx->first_win];
+	exynos_plane = &ctx->planes[PRIMARY_WIN];
 	out_type = (ctx->out_type & IFTYPE_HDMI) ? EXYNOS_DISPLAY_TYPE_HDMI
 						  : EXYNOS_DISPLAY_TYPE_LCD;
 	ctx->crtc = exynos_drm_crtc_create(drm_dev, &exynos_plane->base,
-- 
2.17.0

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Re: [PATCH 1/3] dt-bindings: exynos5433-decon: add more required clocks

[Krzysztof Kozlowski]

On Wed, May 23, 2018 at 1:00 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Proper support for Decon's hardware window no 4 and 5 require enabling
> a few more clocks ("aclk_smmu_decon1x", "aclk_xiu_decon1x",
> "pclk_smmu_decon1x"). Add those clocks to required clocks list in Decon's
> dt bindings.
>
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  .../bindings/display/exynos/exynos5433-decon.txt         | 9 +++++++--
>  1 file changed, 7 insertions(+), 2 deletions(-)

Acked-by: Krzysztof Kozlowski <krzk@kernel.org>

Best regards,
Krzysztof
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Re: [PATCH 0/3] Exynos DRM - add 2 more planes to Decon on Exynos5433

[Krzysztof Kozlowski]

On Wed, May 23, 2018 at 12:59 PM, Marek Szyprowski
<m.szyprowski@samsung.com> wrote:
> Dear all,
>
> This patchset enables support for 2 more hardware windows in Exynos5433
> Decon's, what gives us 2 more overlay planes. This require enabling
> a few more clocks to get it working properly.
>
> My merge plan for this patchset:
> 1. dts (patch 2/3) - please schedule for v4.18 merge window
> 2. driver (patch 3/3) - please schedule for the next release after dts is
>    merged
> 3. bindings (patch 1/3) - probably can go together with the driver patch

Sounds good, I'll pick up 2/3 for this cycle.

BR,
Krzysztof
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Re: [PATCH 2/3] arm64: dts: exynos: Add more clocks to Exynos5433 Decon/DeconTV

[Krzysztof Kozlowski]

On Wed, May 23, 2018 at 01:00:01PM +0200, Marek Szyprowski wrote:
> Add all '1x' clocks to decon and decontv devices. Enabling those clocks
> is needed to get proper display on hardware windows no 4 and 5.
> 
> Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
> ---
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi | 14 ++++++++++++--
>  1 file changed, 12 insertions(+), 2 deletions(-)
> 

Thanks, applied.

Best regards,
Krzysztof

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Re: [PATCH 0/3] Exynos DRM - add 2 more planes to Decon on Exynos5433

[Inki Dae]

2018년 05월 23일 19:59에 Marek Szyprowski 이(가) 쓴 글:
> Dear all,
> 
> This patchset enables support for 2 more hardware windows in Exynos5433
> Decon's, what gives us 2 more overlay planes. This require enabling
> a few more clocks to get it working properly.
> 
> My merge plan for this patchset:
> 1. dts (patch 2/3) - please schedule for v4.18 merge window
> 2. driver (patch 3/3) - please schedule for the next release after dts is
>    merged
> 3. bindings (patch 1/3) - probably can go together with the driver patch

Merged 1 and 3.

Thanks,
Inki Dae

> 
> Best regards
> Marek Szyprowski
> Samsung R&D Institute Poland
> 
> Marek Szyprowski (3):
>   dt-bindings: exynos5433-decon: add more required clocks
>   arm64: dts: exynos: Add more clocks to Exynos5433 Decon and DeconTV
>   drm/exynos: decon: Add support for hardware windows no 4 and 5
> 
>  .../display/exynos/exynos5433-decon.txt       |  9 ++++++--
>  arch/arm64/boot/dts/exynos/exynos5433.dtsi    | 14 +++++++++++--
>  drivers/gpu/drm/exynos/exynos5433_drm_decon.c | 21 +++++++++++--------
>  3 files changed, 31 insertions(+), 13 deletions(-)
> 
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