From: Simon Horman <horms@verge.net.au>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Mark Rutland <mark.rutland@arm.com>,
devicetree@vger.kernel.org, Magnus Damm <magnus.damm@gmail.com>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-renesas-soc@vger.kernel.org,
Rob Herring <robh+dt@kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
Date: Tue, 29 May 2018 14:10:12 +0100 [thread overview]
Message-ID: <20180529131012.ohyqwmiaxiiw6noi@verge.net.au> (raw)
In-Reply-To: <61f6f4a4-e55c-06e0-cba1-7d90a556950a@cogentembedded.com>
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
WARNING: multiple messages have this Message-ID (diff)
From: Simon Horman <horms@verge.net.au>
To: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will.deacon@arm.com>,
linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org,
Magnus Damm <magnus.damm@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
Date: Tue, 29 May 2018 14:10:12 +0100 [thread overview]
Message-ID: <20180529131012.ohyqwmiaxiiw6noi@verge.net.au> (raw)
In-Reply-To: <61f6f4a4-e55c-06e0-cba1-7d90a556950a@cogentembedded.com>
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio@20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio@21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
WARNING: multiple messages have this Message-ID (diff)
From: horms@verge.net.au (Simon Horman)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support
Date: Tue, 29 May 2018 14:10:12 +0100 [thread overview]
Message-ID: <20180529131012.ohyqwmiaxiiw6noi@verge.net.au> (raw)
In-Reply-To: <61f6f4a4-e55c-06e0-cba1-7d90a556950a@cogentembedded.com>
On Mon, May 28, 2018 at 11:14:07PM +0300, Sergei Shtylyov wrote:
> Define the Condor board dependent part of the I2C0 device node.
>
> The I2C0 bus is populated by 2 ON Semiconductor PCA9654 I/O expanders
> and Analog Devices ADV7511W HDMI transmitter (but we're only describing
> the former chips now).
>
> Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
>
> ---
> arch/arm64/boot/dts/renesas/r8a77980-condor.dts | 27 ++++++++++++++++++++++++
> 1 file changed, 27 insertions(+)
>
> Index: renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> ===================================================================
> --- renesas.orig/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> +++ renesas/arch/arm64/boot/dts/renesas/r8a77980-condor.dts
> @@ -80,6 +80,28 @@
> clock-frequency = <32768>;
> };
>
> +&i2c0 {
> + pinctrl-0 = <&i2c0_pins>;
> + pinctrl-names = "default";
> +
> + status = "okay";
> + clock-frequency = <400000>;
> +
> + io_expander0: gpio at 20 {
Hi Sergei,
I'm a little confused about where 0x20 and 0x21 are derived from.
Could you explain a little?
> + compatible = "onnn,pca9654";
> + reg = <0x20>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +
> + io_expander1: gpio at 21 {
> + compatible = "onnn,pca9654";
> + reg = <0x21>;
> + gpio-controller;
> + #gpio-cells = <2>;
> + };
> +};
> +
> &mmc0 {
> pinctrl-0 = <&mmc_pins>;
> pinctrl-1 = <&mmc_pins_uhs>;
> @@ -104,6 +126,11 @@
> function = "canfd0";
> };
>
> + i2c0_pins: i2c0 {
> + groups = "i2c0";
> + function = "i2c0";
> + };
> +
> mmc_pins: mmc {
> groups = "mmc_data8", "mmc_ctrl", "mmc_ds";
> function = "mmc";
>
next prev parent reply other threads:[~2018-05-29 13:10 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-28 20:10 [PATCH v3 0/2] Add R8A77980/Condor I2C support Sergei Shtylyov
2018-05-28 20:10 ` Sergei Shtylyov
2018-05-28 20:10 ` Sergei Shtylyov
2018-05-28 20:13 ` [PATCH 1/2] arm64: dts: renesas: r8a77980: add " Sergei Shtylyov
2018-05-28 20:13 ` Sergei Shtylyov
2018-05-28 20:13 ` Sergei Shtylyov
2018-05-29 13:05 ` Simon Horman
2018-05-29 13:05 ` Simon Horman
2018-05-29 13:05 ` Simon Horman
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:04 ` Sergei Shtylyov
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:42 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-29 16:41 ` Geert Uytterhoeven
2018-05-28 20:14 ` [PATCH 2/2] arm64: dts: renesas: condor: add I2C0 support Sergei Shtylyov
2018-05-28 20:14 ` Sergei Shtylyov
2018-05-28 20:14 ` Sergei Shtylyov
2018-05-29 13:10 ` Simon Horman [this message]
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-29 15:46 ` Sergei Shtylyov
2018-05-30 9:35 ` Simon Horman
2018-05-30 9:35 ` Simon Horman
2018-05-30 9:35 ` Simon Horman
2018-06-06 7:46 ` Geert Uytterhoeven
2018-06-06 7:46 ` Geert Uytterhoeven
2018-06-06 7:46 ` Geert Uytterhoeven
2018-05-28 20:16 ` [PATCH v3 0/2] Add R8A77980/Condor I2C support Sergei Shtylyov
2018-05-28 20:16 ` Sergei Shtylyov
2018-05-28 20:16 ` Sergei Shtylyov
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
2018-05-29 13:10 ` Simon Horman
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180529131012.ohyqwmiaxiiw6noi@verge.net.au \
--to=horms@verge.net.au \
--cc=catalin.marinas@arm.com \
--cc=devicetree@vger.kernel.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=magnus.damm@gmail.com \
--cc=mark.rutland@arm.com \
--cc=robh+dt@kernel.org \
--cc=sergei.shtylyov@cogentembedded.com \
--cc=will.deacon@arm.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.