* [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
@ 2018-05-30 16:49 ` Krzysztof Kozlowski
0 siblings, 0 replies; 8+ messages in thread
From: Krzysztof Kozlowski @ 2018-05-30 16:49 UTC (permalink / raw)
To: linux-arm-kernel
Secondary CPUs should have the same information in DeviceTree as booting
CPU from both correctness point of view and for possible hotplug
scenarios.
Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
---
arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
2 files changed, 13 insertions(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
index a8e449471304..0ee6e92a3c29 100644
--- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
@@ -38,6 +38,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -49,6 +50,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -60,6 +62,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -83,6 +86,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@@ -94,6 +98,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@@ -105,6 +110,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
index 7c130a00d1a8..e4a5857c135f 100644
--- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
+++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
@@ -37,6 +37,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x101>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@@ -48,6 +49,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x102>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@@ -59,6 +61,7 @@
device_type = "cpu";
compatible = "arm,cortex-a7";
reg = <0x103>;
+ clocks = <&clock CLK_KFC_CLK>;
clock-frequency = <1000000000>;
cci-control-port = <&cci_control0>;
operating-points-v2 = <&cluster_a7_opp_table>;
@@ -69,8 +72,8 @@
cpu4: cpu at 0 {
device_type = "cpu";
compatible = "arm,cortex-a15";
- clocks = <&clock CLK_ARM_CLK>;
reg = <0x0>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -82,6 +85,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x1>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -93,6 +97,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x2>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
@@ -104,6 +109,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <0x3>;
+ clocks = <&clock CLK_ARM_CLK>;
clock-frequency = <1800000000>;
cci-control-port = <&cci_control1>;
operating-points-v2 = <&cluster_a15_opp_table>;
--
2.14.1
^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
2018-05-30 16:49 ` Krzysztof Kozlowski
@ 2018-05-31 5:21 ` Viresh Kumar
-1 siblings, 0 replies; 8+ messages in thread
From: Viresh Kumar @ 2018-05-31 5:21 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Mark Rutland, Kukjin Kim, Marek Szyprowski,
devicetree, linux-arm-kernel, linux-samsung-soc, linux-kernel
On 30-05-18, 18:49, Krzysztof Kozlowski wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
Nice.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 8+ messages in thread
* [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
@ 2018-05-31 5:21 ` Viresh Kumar
0 siblings, 0 replies; 8+ messages in thread
From: Viresh Kumar @ 2018-05-31 5:21 UTC (permalink / raw)
To: linux-arm-kernel
On 30-05-18, 18:49, Krzysztof Kozlowski wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
Nice.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
--
viresh
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
2018-05-30 16:49 ` Krzysztof Kozlowski
@ 2018-06-02 15:39 ` Alim Akhtar
-1 siblings, 0 replies; 8+ messages in thread
From: Alim Akhtar @ 2018-06-02 15:39 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Mark Rutland, Kukjin Kim, Marek Szyprowski,
Viresh Kumar, devicetree, linux-arm-kernel, linux-samsung-soc,
linux-kernel
Hi Krzysztof,
On Wed, May 30, 2018 at 10:19 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested on exynos5800 peach-pi, so feel free to add
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
>
> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> index a8e449471304..0ee6e92a3c29 100644
> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> @@ -38,6 +38,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -49,6 +50,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -60,6 +62,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -83,6 +86,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -94,6 +98,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -105,6 +110,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index 7c130a00d1a8..e4a5857c135f 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -37,6 +37,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -48,6 +49,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -59,6 +61,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -69,8 +72,8 @@
> cpu4: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> - clocks = <&clock CLK_ARM_CLK>;
> reg = <0x0>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -82,6 +85,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -93,6 +97,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -104,6 +109,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> --
> 2.14.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo@vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Regards,
Alim
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
@ 2018-06-02 15:39 ` Alim Akhtar
0 siblings, 0 replies; 8+ messages in thread
From: Alim Akhtar @ 2018-06-02 15:39 UTC (permalink / raw)
To: linux-arm-kernel
Hi Krzysztof,
On Wed, May 30, 2018 at 10:19 PM, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Tested on exynos5800 peach-pi, so feel free to add
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
>
> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> index a8e449471304..0ee6e92a3c29 100644
> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> @@ -38,6 +38,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -49,6 +50,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -60,6 +62,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -83,6 +86,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -94,6 +98,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -105,6 +110,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index 7c130a00d1a8..e4a5857c135f 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -37,6 +37,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -48,6 +49,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -59,6 +61,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -69,8 +72,8 @@
> cpu4: cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> - clocks = <&clock CLK_ARM_CLK>;
> reg = <0x0>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -82,6 +85,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -93,6 +97,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -104,6 +109,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> --
> 2.14.1
>
> --
> To unsubscribe from this list: send the line "unsubscribe linux-samsung-soc" in
> the body of a message to majordomo at vger.kernel.org
> More majordomo info at http://vger.kernel.org/majordomo-info.html
--
Regards,
Alim
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
2018-05-30 16:49 ` Krzysztof Kozlowski
@ 2018-06-18 11:09 ` Anand Moon
-1 siblings, 0 replies; 8+ messages in thread
From: Anand Moon @ 2018-06-18 11:09 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Rob Herring, Mark Rutland, Kukjin Kim, Marek Szyprowski,
Viresh Kumar, devicetree, linux-arm-kernel, linux-samsung-soc,
Linux Kernel
Hi Krzysztof,
On 30 May 2018 at 22:19, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> index a8e449471304..0ee6e92a3c29 100644
> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> @@ -38,6 +38,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -49,6 +50,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -60,6 +62,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -83,6 +86,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -94,6 +98,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -105,6 +110,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index 7c130a00d1a8..e4a5857c135f 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -37,6 +37,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -48,6 +49,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -59,6 +61,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -69,8 +72,8 @@
> cpu4: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> - clocks = <&clock CLK_ARM_CLK>;
> reg = <0x0>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -82,6 +85,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -93,6 +97,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -104,6 +109,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> --
[snip]
Actually cpufreq module have more clock to be enabled below is example
from clk_summary.
fout_kpll 0 0 1400000000
0 0
mout_kpll 0 0 1400000000
0 0
kfcclk 0 0 1400000000
0 0
sclk_kpll 0 0 350000000
0 0
mout_kfc 0 0 1400000000
0 0
div_kfc 0 0 1400000000
0 0
fout_apll 0 0 2000000000
0 0
mout_apll 0 0 2000000000
0 0
armclk 0 0 2000000000
0 0
sclk_apll 0 0 500000000
0 0
mout_cpu 0 0 2000000000
0 0
div_arm 0 0 2000000000
0 0
armclk2 0 0 2000000000
0 0
Best Regards
-Anand
^ permalink raw reply [flat|nested] 8+ messages in thread* [PATCH] ARM: dts: exynos: Add missing CPU clocks to secondary CPUs on Exynos542x
@ 2018-06-18 11:09 ` Anand Moon
0 siblings, 0 replies; 8+ messages in thread
From: Anand Moon @ 2018-06-18 11:09 UTC (permalink / raw)
To: linux-arm-kernel
Hi Krzysztof,
On 30 May 2018 at 22:19, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> Secondary CPUs should have the same information in DeviceTree as booting
> CPU from both correctness point of view and for possible hotplug
> scenarios.
>
> Suggested-by: Viresh Kumar <viresh.kumar@linaro.org>
> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
> ---
> arch/arm/boot/dts/exynos5420-cpus.dtsi | 6 ++++++
> arch/arm/boot/dts/exynos5422-cpus.dtsi | 8 +++++++-
> 2 files changed, 13 insertions(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/exynos5420-cpus.dtsi b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> index a8e449471304..0ee6e92a3c29 100644
> --- a/arch/arm/boot/dts/exynos5420-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5420-cpus.dtsi
> @@ -38,6 +38,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -49,6 +50,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -60,6 +62,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -83,6 +86,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -94,6 +98,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -105,6 +110,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> diff --git a/arch/arm/boot/dts/exynos5422-cpus.dtsi b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> index 7c130a00d1a8..e4a5857c135f 100644
> --- a/arch/arm/boot/dts/exynos5422-cpus.dtsi
> +++ b/arch/arm/boot/dts/exynos5422-cpus.dtsi
> @@ -37,6 +37,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x101>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -48,6 +49,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x102>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -59,6 +61,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a7";
> reg = <0x103>;
> + clocks = <&clock CLK_KFC_CLK>;
> clock-frequency = <1000000000>;
> cci-control-port = <&cci_control0>;
> operating-points-v2 = <&cluster_a7_opp_table>;
> @@ -69,8 +72,8 @@
> cpu4: cpu at 0 {
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> - clocks = <&clock CLK_ARM_CLK>;
> reg = <0x0>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -82,6 +85,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x1>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -93,6 +97,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x2>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> @@ -104,6 +109,7 @@
> device_type = "cpu";
> compatible = "arm,cortex-a15";
> reg = <0x3>;
> + clocks = <&clock CLK_ARM_CLK>;
> clock-frequency = <1800000000>;
> cci-control-port = <&cci_control1>;
> operating-points-v2 = <&cluster_a15_opp_table>;
> --
[snip]
Actually cpufreq module have more clock to be enabled below is example
from clk_summary.
fout_kpll 0 0 1400000000
0 0
mout_kpll 0 0 1400000000
0 0
kfcclk 0 0 1400000000
0 0
sclk_kpll 0 0 350000000
0 0
mout_kfc 0 0 1400000000
0 0
div_kfc 0 0 1400000000
0 0
fout_apll 0 0 2000000000
0 0
mout_apll 0 0 2000000000
0 0
armclk 0 0 2000000000
0 0
sclk_apll 0 0 500000000
0 0
mout_cpu 0 0 2000000000
0 0
div_arm 0 0 2000000000
0 0
armclk2 0 0 2000000000
0 0
Best Regards
-Anand
^ permalink raw reply [flat|nested] 8+ messages in thread