* [Qemu-devel] [PULL 00/25] target-arm queue
@ 2018-05-31 14:23 Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX Peter Maydell
` (26 more replies)
0 siblings, 27 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
target-arm queue. This has the "plumb txattrs through various
bits of exec.c" patches, and a collection of bug fixes from
various people.
thanks
-- PMM
The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
are available in the Git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
----------------------------------------------------------------
target-arm queue:
* target/arm: Honour FPCR.FZ in FRECPX
* MAINTAINERS: Add entries for newer MPS2 boards and devices
* hw/intc/arm_gicv3: Fix APxR<n> register dispatching
* arm_gicv3_kvm: fix bug in writing zero bits back to the in-kernel
GIC state
* tcg: Fix helper function vs host abi for float16
* arm: fix qemu crash on startup with -bios option
* arm: fix malloc type mismatch
* xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
* Correct CPACR reset value for v7 cores
* memory.h: Improve IOMMU related documentation
* exec: Plumb transaction attributes through various functions in
preparation for allowing IOMMUs to see them
* vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
* ARM: ACPI: Fix use-after-free due to memory realloc
* KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
----------------------------------------------------------------
Francisco Iglesias (1):
xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
Igor Mammedov (1):
arm: fix qemu crash on startup with -bios option
Jan Kiszka (1):
hw/intc/arm_gicv3: Fix APxR<n> register dispatching
Paolo Bonzini (1):
arm: fix malloc type mismatch
Peter Maydell (17):
target/arm: Honour FPCR.FZ in FRECPX
MAINTAINERS: Add entries for newer MPS2 boards and devices
Correct CPACR reset value for v7 cores
memory.h: Improve IOMMU related documentation
Make tb_invalidate_phys_addr() take a MemTxAttrs argument
Make address_space_translate{, _cached}() take a MemTxAttrs argument
Make address_space_map() take a MemTxAttrs argument
Make address_space_access_valid() take a MemTxAttrs argument
Make flatview_extend_translation() take a MemTxAttrs argument
Make memory_region_access_valid() take a MemTxAttrs argument
Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
Make flatview_access_valid() take a MemTxAttrs argument
Make flatview_translate() take a MemTxAttrs argument
Make address_space_get_iotlb_entry() take a MemTxAttrs argument
Make flatview_do_translate() take a MemTxAttrs argument
Make address_space_translate_iommu take a MemTxAttrs argument
vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
Richard Henderson (1):
tcg: Fix helper function vs host abi for float16
Shannon Zhao (3):
arm_gicv3_kvm: increase clroffset accordingly
ARM: ACPI: Fix use-after-free due to memory realloc
KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
include/exec/exec-all.h | 5 +-
include/exec/helper-head.h | 2 +-
include/exec/memory-internal.h | 3 +-
include/exec/memory.h | 128 +++++++++++++++++++++++++++++++++++------
include/migration/vmstate.h | 3 +
include/sysemu/dma.h | 6 +-
accel/tcg/translate-all.c | 4 +-
exec.c | 95 ++++++++++++++++++------------
hw/arm/boot.c | 18 +++---
hw/arm/virt-acpi-build.c | 20 +++++--
hw/dma/xlnx-zdma.c | 10 +++-
hw/hppa/dino.c | 3 +-
hw/intc/arm_gic_kvm.c | 1 -
hw/intc/arm_gicv3_cpuif.c | 12 ++--
hw/intc/arm_gicv3_kvm.c | 2 +-
hw/nvram/fw_cfg.c | 12 ++--
hw/s390x/s390-pci-inst.c | 3 +-
hw/scsi/esp.c | 3 +-
hw/vfio/common.c | 3 +-
hw/virtio/vhost.c | 3 +-
hw/xen/xen_pt_msi.c | 3 +-
memory.c | 12 ++--
memory_ldst.inc.c | 18 +++---
target/arm/gdbstub.c | 3 +-
target/arm/helper-a64.c | 41 +++++++------
target/arm/helper.c | 90 ++++++++++++++++-------------
target/ppc/mmu-hash64.c | 3 +-
target/riscv/helper.c | 2 +-
target/s390x/diag.c | 6 +-
target/s390x/excp_helper.c | 3 +-
target/s390x/mmu_helper.c | 3 +-
target/s390x/sigp.c | 3 +-
target/xtensa/op_helper.c | 3 +-
MAINTAINERS | 9 ++-
34 files changed, 353 insertions(+), 182 deletions(-)
^ permalink raw reply [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices Peter Maydell
` (25 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
The FRECPX instructions should (like most other floating point operations)
honour the FPCR.FZ bit which specifies whether input denormals should
be flushed to zero (or FZ16 for the half-precision version).
We forgot to implement this, which doesn't affect the results (since
the calculation doesn't actually care about the mantissa bits) but did
mean we were failing to set the FPSR.IDC bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521172712.19930-1-peter.maydell@linaro.org
---
target/arm/helper-a64.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index f92bdea732..c4d2a04827 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -384,6 +384,8 @@ float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
return nan;
}
+ a = float16_squash_input_denormal(a, fpst);
+
val16 = float16_val(a);
sbit = 0x8000 & val16;
exp = extract32(val16, 10, 5);
@@ -413,6 +415,8 @@ float32 HELPER(frecpx_f32)(float32 a, void *fpstp)
return nan;
}
+ a = float32_squash_input_denormal(a, fpst);
+
val32 = float32_val(a);
sbit = 0x80000000ULL & val32;
exp = extract32(val32, 23, 8);
@@ -442,6 +446,8 @@ float64 HELPER(frecpx_f64)(float64 a, void *fpstp)
return nan;
}
+ a = float64_squash_input_denormal(a, fpst);
+
val64 = float64_val(a);
sbit = 0x8000000000000000ULL & val64;
exp = extract64(float64_val(a), 52, 11);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching Peter Maydell
` (24 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
Add entries to MAINTAINERS to cover the newer MPS2 boards and
the new devices they use.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20180518153157.14899-1-peter.maydell@linaro.org
---
MAINTAINERS | 9 +++++++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index bf482fd4e9..41cd3736a9 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -447,6 +447,8 @@ F: hw/timer/cmsdk-apb-timer.c
F: include/hw/timer/cmsdk-apb-timer.h
F: hw/char/cmsdk-apb-uart.c
F: include/hw/char/cmsdk-apb-uart.h
+F: hw/misc/tz-ppc.c
+F: include/hw/misc/tz-ppc.h
ARM cores
M: Peter Maydell <peter.maydell@linaro.org>
@@ -515,8 +517,11 @@ M: Peter Maydell <peter.maydell@linaro.org>
L: qemu-arm@nongnu.org
S: Maintained
F: hw/arm/mps2.c
-F: hw/misc/mps2-scc.c
-F: include/hw/misc/mps2-scc.h
+F: hw/arm/mps2-tz.c
+F: hw/misc/mps2-*.c
+F: include/hw/misc/mps2-*.h
+F: hw/arm/iotkit.c
+F: include/hw/arm/iotkit.h
Musicpal
M: Jan Kiszka <jan.kiszka@web.de>
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly Peter Maydell
` (23 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Jan Kiszka <jan.kiszka@siemens.com>
There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Cc: qemu-stable@nongnu.org
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Message-id: 28b927d3-da58-bce4-cc13-bfec7f9b1cb9@siemens.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index cb9a3a542d..5c89be1af0 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -427,7 +427,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value = cs->ich_apr[grp][regno];
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -439,7 +439,7 @@ static void icv_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -1461,7 +1461,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
uint64_t value;
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
return icv_ap_read(env, ri);
@@ -1483,7 +1483,7 @@ static void icc_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
icv_ap_write(env, ri, value);
@@ -2292,7 +2292,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value;
value = cs->ich_apr[grp][regno];
@@ -2305,7 +2305,7 @@ static void ich_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (2 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16 Peter Maydell
` (22 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Shannon Zhao <zhaoshenglong@huawei.com>
It forgot to increase clroffset during the loop. So it only clear the
first 4 bytes.
Fixes: 367b9f527becdd20ddf116e17a3c0c2bbc486920
Cc: qemu-stable@nongnu.org
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527047633-12368-1-git-send-email-zhaoshenglong@huawei.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv3_kvm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index ec371772b3..3536795501 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -243,6 +243,7 @@ static void kvm_dist_putbmp(GICv3State *s, uint32_t offset,
if (clroffset != 0) {
reg = 0;
kvm_gicd_access(s, clroffset, ®, true);
+ clroffset += 4;
}
reg = *gic_bmp_ptr32(bmp, irq);
kvm_gicd_access(s, offset, ®, true);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (3 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option Peter Maydell
` (21 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Richard Henderson <richard.henderson@linaro.org>
Depending on the host abi, float16, aka uint16_t, values are
passed and returned either zero-extended in the host register
or with garbage at the top of the host register.
The tcg code generator has so far been assuming garbage, as that
matches the x86 abi, but this is incorrect for other host abis.
Further, target/arm has so far been assuming zero-extended results,
so that it may store the 16-bit value into a 32-bit slot with the
high 16-bits already clear.
Rectify both problems by mapping "f16" in the helper definition
to uint32_t instead of (a typedef for) uint16_t. This forces
the host compiler to assume garbage in the upper 16 bits on input
and to zero-extend the result on output.
Cc: qemu-stable@nongnu.org
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Tested-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Message-id: 20180522175629.24932-1-richard.henderson@linaro.org
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/exec/helper-head.h | 2 +-
target/arm/helper-a64.c | 35 +++++++++--------
target/arm/helper.c | 80 +++++++++++++++++++-------------------
3 files changed, 59 insertions(+), 58 deletions(-)
diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h
index 15b6a68de3..276dd5afce 100644
--- a/include/exec/helper-head.h
+++ b/include/exec/helper-head.h
@@ -39,7 +39,7 @@
#define dh_ctype_int int
#define dh_ctype_i64 uint64_t
#define dh_ctype_s64 int64_t
-#define dh_ctype_f16 float16
+#define dh_ctype_f16 uint32_t
#define dh_ctype_f32 float32
#define dh_ctype_f64 float64
#define dh_ctype_ptr void *
diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c
index c4d2a04827..7f6ad3000b 100644
--- a/target/arm/helper-a64.c
+++ b/target/arm/helper-a64.c
@@ -85,12 +85,12 @@ static inline uint32_t float_rel_to_flags(int res)
return flags;
}
-uint64_t HELPER(vfp_cmph_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmph_a64)(uint32_t x, uint32_t y, void *fp_status)
{
return float_rel_to_flags(float16_compare_quiet(x, y, fp_status));
}
-uint64_t HELPER(vfp_cmpeh_a64)(float16 x, float16 y, void *fp_status)
+uint64_t HELPER(vfp_cmpeh_a64)(uint32_t x, uint32_t y, void *fp_status)
{
return float_rel_to_flags(float16_compare(x, y, fp_status));
}
@@ -214,7 +214,7 @@ uint64_t HELPER(neon_cgt_f64)(float64 a, float64 b, void *fpstp)
#define float64_three make_float64(0x4008000000000000ULL)
#define float64_one_point_five make_float64(0x3FF8000000000000ULL)
-float16 HELPER(recpsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(recpsf_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
@@ -259,7 +259,7 @@ float64 HELPER(recpsf_f64)(float64 a, float64 b, void *fpstp)
return float64_muladd(a, b, float64_two, 0, fpst);
}
-float16 HELPER(rsqrtsf_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(rsqrtsf_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
@@ -366,7 +366,7 @@ uint64_t HELPER(neon_addlp_u16)(uint64_t a)
}
/* Floating-point reciprocal exponent - see FPRecpX in ARM ARM */
-float16 HELPER(frecpx_f16)(float16 a, void *fpstp)
+uint32_t HELPER(frecpx_f16)(uint32_t a, void *fpstp)
{
float_status *fpst = fpstp;
uint16_t val16, sbit;
@@ -701,7 +701,7 @@ void HELPER(casp_be_parallel)(CPUARMState *env, uint32_t rs, uint64_t addr,
#define ADVSIMD_HELPER(name, suffix) HELPER(glue(glue(advsimd_, name), suffix))
#define ADVSIMD_HALFOP(name) \
-float16 ADVSIMD_HELPER(name, h)(float16 a, float16 b, void *fpstp) \
+uint32_t ADVSIMD_HELPER(name, h)(uint32_t a, uint32_t b, void *fpstp) \
{ \
float_status *fpst = fpstp; \
return float16_ ## name(a, b, fpst); \
@@ -761,7 +761,8 @@ ADVSIMD_HALFOP(mulx)
ADVSIMD_TWOHALFOP(mulx)
/* fused multiply-accumulate */
-float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp)
+uint32_t HELPER(advsimd_muladdh)(uint32_t a, uint32_t b, uint32_t c,
+ void *fpstp)
{
float_status *fpst = fpstp;
return float16_muladd(a, b, c, 0, fpst);
@@ -792,14 +793,14 @@ uint32_t HELPER(advsimd_muladd2h)(uint32_t two_a, uint32_t two_b,
#define ADVSIMD_CMPRES(test) (test) ? 0xffff : 0
-uint32_t HELPER(advsimd_ceq_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_ceq_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
int compare = float16_compare_quiet(a, b, fpst);
return ADVSIMD_CMPRES(compare == float_relation_equal);
}
-uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cge_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
int compare = float16_compare(a, b, fpst);
@@ -807,14 +808,14 @@ uint32_t HELPER(advsimd_cge_f16)(float16 a, float16 b, void *fpstp)
compare == float_relation_equal);
}
-uint32_t HELPER(advsimd_cgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_cgt_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
int compare = float16_compare(a, b, fpst);
return ADVSIMD_CMPRES(compare == float_relation_greater);
}
-uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acge_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
float16 f0 = float16_abs(a);
@@ -824,7 +825,7 @@ uint32_t HELPER(advsimd_acge_f16)(float16 a, float16 b, void *fpstp)
compare == float_relation_equal);
}
-uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
+uint32_t HELPER(advsimd_acgt_f16)(uint32_t a, uint32_t b, void *fpstp)
{
float_status *fpst = fpstp;
float16 f0 = float16_abs(a);
@@ -834,12 +835,12 @@ uint32_t HELPER(advsimd_acgt_f16)(float16 a, float16 b, void *fpstp)
}
/* round to integral */
-float16 HELPER(advsimd_rinth_exact)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth_exact)(uint32_t x, void *fp_status)
{
return float16_round_to_int(x, fp_status);
}
-float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
+uint32_t HELPER(advsimd_rinth)(uint32_t x, void *fp_status)
{
int old_flags = get_float_exception_flags(fp_status), new_flags;
float16 ret;
@@ -863,7 +864,7 @@ float16 HELPER(advsimd_rinth)(float16 x, void *fp_status)
* setting the mode appropriately before calling the helper.
*/
-uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16tosinth)(uint32_t a, void *fpstp)
{
float_status *fpst = fpstp;
@@ -875,7 +876,7 @@ uint32_t HELPER(advsimd_f16tosinth)(float16 a, void *fpstp)
return float16_to_int16(a, fpst);
}
-uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
+uint32_t HELPER(advsimd_f16touinth)(uint32_t a, void *fpstp)
{
float_status *fpst = fpstp;
@@ -891,7 +892,7 @@ uint32_t HELPER(advsimd_f16touinth)(float16 a, void *fpstp)
* Square Root and Reciprocal square root
*/
-float16 HELPER(sqrt_f16)(float16 a, void *fpstp)
+uint32_t HELPER(sqrt_f16)(uint32_t a, void *fpstp)
{
float_status *s = fpstp;
diff --git a/target/arm/helper.c b/target/arm/helper.c
index c0f739972e..a4bfac3932 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -11344,35 +11344,35 @@ DO_VFP_cmp(d, float64)
/* Integer to float and float to integer conversions */
-#define CONV_ITOF(name, fsz, sign) \
- float##fsz HELPER(name)(uint32_t x, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
+#define CONV_ITOF(name, ftype, fsz, sign) \
+ftype HELPER(name)(uint32_t x, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
}
-#define CONV_FTOI(name, fsz, sign, round) \
-uint32_t HELPER(name)(float##fsz x, void *fpstp) \
-{ \
- float_status *fpst = fpstp; \
- if (float##fsz##_is_any_nan(x)) { \
- float_raise(float_flag_invalid, fpst); \
- return 0; \
- } \
- return float##fsz##_to_##sign##int32##round(x, fpst); \
+#define CONV_FTOI(name, ftype, fsz, sign, round) \
+uint32_t HELPER(name)(ftype x, void *fpstp) \
+{ \
+ float_status *fpst = fpstp; \
+ if (float##fsz##_is_any_nan(x)) { \
+ float_raise(float_flag_invalid, fpst); \
+ return 0; \
+ } \
+ return float##fsz##_to_##sign##int32##round(x, fpst); \
}
-#define FLOAT_CONVS(name, p, fsz, sign) \
-CONV_ITOF(vfp_##name##to##p, fsz, sign) \
-CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
-CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
+#define FLOAT_CONVS(name, p, ftype, fsz, sign) \
+ CONV_ITOF(vfp_##name##to##p, ftype, fsz, sign) \
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
+ CONV_FTOI(vfp_to##name##z##p, ftype, fsz, sign, _round_to_zero)
-FLOAT_CONVS(si, h, 16, )
-FLOAT_CONVS(si, s, 32, )
-FLOAT_CONVS(si, d, 64, )
-FLOAT_CONVS(ui, h, 16, u)
-FLOAT_CONVS(ui, s, 32, u)
-FLOAT_CONVS(ui, d, 64, u)
+FLOAT_CONVS(si, h, uint32_t, 16, )
+FLOAT_CONVS(si, s, float32, 32, )
+FLOAT_CONVS(si, d, float64, 64, )
+FLOAT_CONVS(ui, h, uint32_t, 16, u)
+FLOAT_CONVS(ui, s, float32, 32, u)
+FLOAT_CONVS(ui, d, float64, 64, u)
#undef CONV_ITOF
#undef CONV_FTOI
@@ -11465,22 +11465,22 @@ static float16 do_postscale_fp16(float64 f, int shift, float_status *fpst)
return float64_to_float16(float64_scalbn(f, -shift, fpst), true, fpst);
}
-float16 HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sltoh)(uint32_t x, uint32_t shift, void *fpst)
{
return do_postscale_fp16(int32_to_float64(x, fpst), shift, fpst);
}
-float16 HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_ultoh)(uint32_t x, uint32_t shift, void *fpst)
{
return do_postscale_fp16(uint32_to_float64(x, fpst), shift, fpst);
}
-float16 HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_sqtoh)(uint64_t x, uint32_t shift, void *fpst)
{
return do_postscale_fp16(int64_to_float64(x, fpst), shift, fpst);
}
-float16 HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_uqtoh)(uint64_t x, uint32_t shift, void *fpst)
{
return do_postscale_fp16(uint64_to_float64(x, fpst), shift, fpst);
}
@@ -11504,32 +11504,32 @@ static float64 do_prescale_fp16(float16 f, int shift, float_status *fpst)
}
}
-uint32_t HELPER(vfp_toshh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toshh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_int16(do_prescale_fp16(x, shift, fpst), fpst);
}
-uint32_t HELPER(vfp_touhh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_touhh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_uint16(do_prescale_fp16(x, shift, fpst), fpst);
}
-uint32_t HELPER(vfp_toslh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toslh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_int32(do_prescale_fp16(x, shift, fpst), fpst);
}
-uint32_t HELPER(vfp_toulh)(float16 x, uint32_t shift, void *fpst)
+uint32_t HELPER(vfp_toulh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_uint32(do_prescale_fp16(x, shift, fpst), fpst);
}
-uint64_t HELPER(vfp_tosqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_tosqh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_int64(do_prescale_fp16(x, shift, fpst), fpst);
}
-uint64_t HELPER(vfp_touqh)(float16 x, uint32_t shift, void *fpst)
+uint64_t HELPER(vfp_touqh)(uint32_t x, uint32_t shift, void *fpst)
{
return float64_to_uint64(do_prescale_fp16(x, shift, fpst), fpst);
}
@@ -11565,7 +11565,7 @@ uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
}
/* Half precision conversions. */
-float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
+float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, void *fpstp, uint32_t ahp_mode)
{
/* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing input denormals.
@@ -11578,7 +11578,7 @@ float32 HELPER(vfp_fcvt_f16_to_f32)(float16 a, void *fpstp, uint32_t ahp_mode)
return r;
}
-float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
{
/* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing output denormals.
@@ -11591,7 +11591,7 @@ float16 HELPER(vfp_fcvt_f32_to_f16)(float32 a, void *fpstp, uint32_t ahp_mode)
return r;
}
-float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
+float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, void *fpstp, uint32_t ahp_mode)
{
/* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing input denormals.
@@ -11604,7 +11604,7 @@ float64 HELPER(vfp_fcvt_f16_to_f64)(float16 a, void *fpstp, uint32_t ahp_mode)
return r;
}
-float16 HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
+uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, void *fpstp, uint32_t ahp_mode)
{
/* Squash FZ16 to 0 for the duration of conversion. In this case,
* it would affect flushing output denormals.
@@ -11742,7 +11742,7 @@ static bool round_to_inf(float_status *fpst, bool sign_bit)
g_assert_not_reached();
}
-float16 HELPER(recpe_f16)(float16 input, void *fpstp)
+uint32_t HELPER(recpe_f16)(uint32_t input, void *fpstp)
{
float_status *fpst = fpstp;
float16 f16 = float16_squash_input_denormal(input, fpst);
@@ -11937,7 +11937,7 @@ static uint64_t recip_sqrt_estimate(int *exp , int exp_off, uint64_t frac)
return extract64(estimate, 0, 8) << 44;
}
-float16 HELPER(rsqrte_f16)(float16 input, void *fpstp)
+uint32_t HELPER(rsqrte_f16)(uint32_t input, void *fpstp)
{
float_status *s = fpstp;
float16 f16 = float16_squash_input_denormal(input, s);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (4 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16 Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch Peter Maydell
` (20 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Igor Mammedov <imammedo@redhat.com>
When QEMU is started with following CLI
-machine virt,gic-version=3,accel=kvm -cpu host -bios AAVMF_CODE.fd
it crashes with abort at
accel/kvm/kvm-all.c:2164:
KVM_SET_DEVICE_ATTR failed: Group 6 attr 0x000000000000c665: Invalid argument
Which is caused by implicit dependency of kvm_arm_gicv3_reset() on
arm_gicv3_icc_reset() where the later is called by CPU reset
reset callback.
However commit:
3b77f6c arm/boot: split load_dtb() from arm_load_kernel()
broke CPU reset callback registration in case
arm_load_kernel()
...
if (!info->kernel_filename || info->firmware_loaded)
branch is taken, i.e. it's sufficient to provide a firmware
or do not provide kernel on CLI to skip cpu reset callback
registration, where before offending commit the callback
has been registered unconditionally.
Fix it by registering the callback right at the beginning of
arm_load_kernel() unconditionally instead of doing it at the end.
NOTE:
we probably should eliminate that dependency anyways as well as
separate arch CPU reset parts from arm_load_kernel() into CPU
itself, but that refactoring that I probably would have to do
anyways later for CPU hotplug to work.
Reported-by: Auger Eric <eric.auger@redhat.com>
Signed-off-by: Igor Mammedov <imammedo@redhat.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Tested-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527070950-208350-1-git-send-email-imammedo@redhat.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/boot.c | 18 +++++++++---------
1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/hw/arm/boot.c b/hw/arm/boot.c
index 9496f331a8..1e481662ad 100644
--- a/hw/arm/boot.c
+++ b/hw/arm/boot.c
@@ -926,6 +926,15 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
static const ARMInsnFixup *primary_loader;
AddressSpace *as = arm_boot_address_space(cpu, info);
+ /* CPU objects (unlike devices) are not automatically reset on system
+ * reset, so we must always register a handler to do so. If we're
+ * actually loading a kernel, the handler is also responsible for
+ * arranging that we start it correctly.
+ */
+ for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
+ qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
+ }
+
/* The board code is not supposed to set secure_board_setup unless
* running its code in secure mode is actually possible, and KVM
* doesn't support secure.
@@ -1143,15 +1152,6 @@ void arm_load_kernel(ARMCPU *cpu, struct arm_boot_info *info)
ARM_CPU(cs)->env.boot_info = info;
}
- /* CPU objects (unlike devices) are not automatically reset on system
- * reset, so we must always register a handler to do so. If we're
- * actually loading a kernel, the handler is also responsible for
- * arranging that we start it correctly.
- */
- for (cs = first_cpu; cs; cs = CPU_NEXT(cs)) {
- qemu_register_reset(do_cpu_reset, ARM_CPU(cs));
- }
-
if (!info->skip_dtb_autoload && have_dtb(info)) {
if (arm_load_dtb(info->dtb_start, info, info->dtb_limit, as) < 0) {
exit(1);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (5 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors Peter Maydell
` (19 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Paolo Bonzini <pbonzini@redhat.com>
cpregs_keys is an uint32_t* so the allocation should use uint32_t.
g_new is even better because it is type-safe.
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/gdbstub.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c
index e80cfb47c7..0c64c0292e 100644
--- a/target/arm/gdbstub.c
+++ b/target/arm/gdbstub.c
@@ -157,8 +157,7 @@ int arm_gen_dynamic_xml(CPUState *cs)
RegisterSysregXmlParam param = {cs, s};
cpu->dyn_xml.num_cpregs = 0;
- cpu->dyn_xml.cpregs_keys = g_malloc(sizeof(uint32_t *) *
- g_hash_table_size(cpu->cp_regs));
+ cpu->dyn_xml.cpregs_keys = g_new(uint32_t, g_hash_table_size(cpu->cp_regs));
g_string_printf(s, "<?xml version=\"1.0\"?>");
g_string_append_printf(s, "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">");
g_string_append_printf(s, "<feature name=\"org.qemu.gdb.arm.sys.regs\">");
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (6 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores Peter Maydell
` (18 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Francisco Iglesias <frasse.iglesias@gmail.com>
Coverity found that the string return by 'object_get_canonical_path' was not
being freed at two locations in the model (CID 1391294 and CID 1391293) and
also that a memset was being called with a value greater than the max of a byte
on the second argument (CID 1391286). This patch corrects this by adding the
freeing of the strings and also changing to memset to zero instead on
descriptor unaligned errors.
Signed-off-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-id: 20180528184859.3530-1-frasse.iglesias@gmail.com
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/dma/xlnx-zdma.c | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c
index 14d86c254b..8eea757aff 100644
--- a/hw/dma/xlnx-zdma.c
+++ b/hw/dma/xlnx-zdma.c
@@ -302,7 +302,7 @@ static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf)
qemu_log_mask(LOG_GUEST_ERROR,
"zdma: unaligned descriptor at %" PRIx64,
addr);
- memset(buf, 0xdeadbeef, sizeof(XlnxZDMADescr));
+ memset(buf, 0x0, sizeof(XlnxZDMADescr));
s->error = true;
return false;
}
@@ -707,9 +707,11 @@ static uint64_t zdma_read(void *opaque, hwaddr addr, unsigned size)
RegisterInfo *r = &s->regs_info[addr / 4];
if (!r->data) {
+ gchar *path = object_get_canonical_path(OBJECT(s));
qemu_log("%s: Decode error: read from %" HWADDR_PRIx "\n",
- object_get_canonical_path(OBJECT(s)),
+ path,
addr);
+ g_free(path);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
zdma_ch_imr_update_irq(s);
return 0;
@@ -724,9 +726,11 @@ static void zdma_write(void *opaque, hwaddr addr, uint64_t value,
RegisterInfo *r = &s->regs_info[addr / 4];
if (!r->data) {
+ gchar *path = object_get_canonical_path(OBJECT(s));
qemu_log("%s: Decode error: write to %" HWADDR_PRIx "=%" PRIx64 "\n",
- object_get_canonical_path(OBJECT(s)),
+ path,
addr, value);
+ g_free(path);
ARRAY_FIELD_DP32(s->regs, ZDMA_CH_ISR, INV_APB, true);
zdma_ch_imr_update_irq(s);
return;
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (7 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation Peter Maydell
` (17 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
In commit f0aff255700 we made cpacr_write() enforce that some CPACR
bits are RAZ/WI and some are RAO/WI for ARMv7 cores. Unfortunately
we forgot to also update the register's reset value. The effect
was that (a) a guest that read CPACR on reset would not see ones in
the RAO bits, and (b) if you did a migration before the guest did
a write to the CPACR then the migration would fail because the
destination would enforce the RAO bits and then complain that they
didn't match the zero value from the source.
Implement reset for the CPACR using a custom reset function
that just calls cpacr_write(), to avoid having to duplicate
the logic for which bits are RAO.
This bug would affect migration for TCG CPUs which are ARMv7
with VFP but without one of Neon or VFPv3.
Reported-by: Cédric Le Goater <clg@kaod.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Cédric Le Goater <clg@kaod.org>
Message-id: 20180522173713.26282-1-peter.maydell@linaro.org
---
target/arm/helper.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a4bfac3932..f75aa6e9ca 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -863,6 +863,14 @@ static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
env->cp15.cpacr_el1 = value;
}
+static void cpacr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ /* Call cpacr_write() so that we reset with the correct RAO bits set
+ * for our CPU features.
+ */
+ cpacr_write(env, ri, 0);
+}
+
static CPAccessResult cpacr_access(CPUARMState *env, const ARMCPRegInfo *ri,
bool isread)
{
@@ -920,7 +928,7 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
{ .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
.crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2, .accessfn = cpacr_access,
.access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.cpacr_el1),
- .resetvalue = 0, .writefn = cpacr_write },
+ .resetfn = cpacr_reset, .writefn = cpacr_write },
REGINFO_SENTINEL
};
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (8 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Peter Maydell
` (16 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
Add more detail to the documentation for memory_region_init_iommu()
and other IOMMU-related functions and data structures.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 20180521140402.23318-2-peter.maydell@linaro.org
---
include/exec/memory.h | 105 ++++++++++++++++++++++++++++++++++++++----
1 file changed, 95 insertions(+), 10 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 525619a5f4..267aa5fca4 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -194,29 +194,100 @@ enum IOMMUMemoryRegionAttr {
IOMMU_ATTR_SPAPR_TCE_FD
};
+/**
+ * IOMMUMemoryRegionClass:
+ *
+ * All IOMMU implementations need to subclass TYPE_IOMMU_MEMORY_REGION
+ * and provide an implementation of at least the @translate method here
+ * to handle requests to the memory region. Other methods are optional.
+ *
+ * The IOMMU implementation must use the IOMMU notifier infrastructure
+ * to report whenever mappings are changed, by calling
+ * memory_region_notify_iommu() (or, if necessary, by calling
+ * memory_region_notify_one() for each registered notifier).
+ */
typedef struct IOMMUMemoryRegionClass {
/* private */
struct DeviceClass parent_class;
/*
- * Return a TLB entry that contains a given address. Flag should
- * be the access permission of this translation operation. We can
- * set flag to IOMMU_NONE to mean that we don't need any
- * read/write permission checks, like, when for region replay.
+ * Return a TLB entry that contains a given address.
+ *
+ * The IOMMUAccessFlags indicated via @flag are optional and may
+ * be specified as IOMMU_NONE to indicate that the caller needs
+ * the full translation information for both reads and writes. If
+ * the access flags are specified then the IOMMU implementation
+ * may use this as an optimization, to stop doing a page table
+ * walk as soon as it knows that the requested permissions are not
+ * allowed. If IOMMU_NONE is passed then the IOMMU must do the
+ * full page table walk and report the permissions in the returned
+ * IOMMUTLBEntry. (Note that this implies that an IOMMU may not
+ * return different mappings for reads and writes.)
+ *
+ * The returned information remains valid while the caller is
+ * holding the big QEMU lock or is inside an RCU critical section;
+ * if the caller wishes to cache the mapping beyond that it must
+ * register an IOMMU notifier so it can invalidate its cached
+ * information when the IOMMU mapping changes.
+ *
+ * @iommu: the IOMMUMemoryRegion
+ * @hwaddr: address to be translated within the memory region
+ * @flag: requested access permissions
*/
IOMMUTLBEntry (*translate)(IOMMUMemoryRegion *iommu, hwaddr addr,
IOMMUAccessFlags flag);
- /* Returns minimum supported page size */
+ /* Returns minimum supported page size in bytes.
+ * If this method is not provided then the minimum is assumed to
+ * be TARGET_PAGE_SIZE.
+ *
+ * @iommu: the IOMMUMemoryRegion
+ */
uint64_t (*get_min_page_size)(IOMMUMemoryRegion *iommu);
- /* Called when IOMMU Notifier flag changed */
+ /* Called when IOMMU Notifier flag changes (ie when the set of
+ * events which IOMMU users are requesting notification for changes).
+ * Optional method -- need not be provided if the IOMMU does not
+ * need to know exactly which events must be notified.
+ *
+ * @iommu: the IOMMUMemoryRegion
+ * @old_flags: events which previously needed to be notified
+ * @new_flags: events which now need to be notified
+ */
void (*notify_flag_changed)(IOMMUMemoryRegion *iommu,
IOMMUNotifierFlag old_flags,
IOMMUNotifierFlag new_flags);
- /* Set this up to provide customized IOMMU replay function */
+ /* Called to handle memory_region_iommu_replay().
+ *
+ * The default implementation of memory_region_iommu_replay() is to
+ * call the IOMMU translate method for every page in the address space
+ * with flag == IOMMU_NONE and then call the notifier if translate
+ * returns a valid mapping. If this method is implemented then it
+ * overrides the default behaviour, and must provide the full semantics
+ * of memory_region_iommu_replay(), by calling @notifier for every
+ * translation present in the IOMMU.
+ *
+ * Optional method -- an IOMMU only needs to provide this method
+ * if the default is inefficient or produces undesirable side effects.
+ *
+ * Note: this is not related to record-and-replay functionality.
+ */
void (*replay)(IOMMUMemoryRegion *iommu, IOMMUNotifier *notifier);
- /* Get IOMMU misc attributes */
- int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr,
+ /* Get IOMMU misc attributes. This is an optional method that
+ * can be used to allow users of the IOMMU to get implementation-specific
+ * information. The IOMMU implements this method to handle calls
+ * by IOMMU users to memory_region_iommu_get_attr() by filling in
+ * the arbitrary data pointer for any IOMMUMemoryRegionAttr values that
+ * the IOMMU supports. If the method is unimplemented then
+ * memory_region_iommu_get_attr() will always return -EINVAL.
+ *
+ * @iommu: the IOMMUMemoryRegion
+ * @attr: attribute being queried
+ * @data: memory to fill in with the attribute data
+ *
+ * Returns 0 on success, or a negative errno; in particular
+ * returns -EINVAL for unrecognized or unimplemented attribute types.
+ */
+ int (*get_attr)(IOMMUMemoryRegion *iommu, enum IOMMUMemoryRegionAttr attr,
void *data);
} IOMMUMemoryRegionClass;
@@ -705,6 +776,14 @@ static inline void memory_region_init_reservation(MemoryRegion *mr,
* An IOMMU region translates addresses and forwards accesses to a target
* memory region.
*
+ * The IOMMU implementation must define a subclass of TYPE_IOMMU_MEMORY_REGION.
+ * @_iommu_mr should be a pointer to enough memory for an instance of
+ * that subclass, @instance_size is the size of that subclass, and
+ * @mrtypename is its name. This function will initialize @_iommu_mr as an
+ * instance of the subclass, and its methods will then be called to handle
+ * accesses to the memory region. See the documentation of
+ * #IOMMUMemoryRegionClass for further details.
+ *
* @_iommu_mr: the #IOMMUMemoryRegion to be initialized
* @instance_size: the IOMMUMemoryRegion subclass instance size
* @mrtypename: the type name of the #IOMMUMemoryRegion
@@ -953,6 +1032,8 @@ void memory_region_register_iommu_notifier(MemoryRegion *mr,
* a notifier with the minimum page granularity returned by
* mr->iommu_ops->get_page_size().
*
+ * Note: this is not related to record-and-replay functionality.
+ *
* @iommu_mr: the memory region to observe
* @n: the notifier to which to replay iommu mappings
*/
@@ -962,6 +1043,8 @@ void memory_region_iommu_replay(IOMMUMemoryRegion *iommu_mr, IOMMUNotifier *n);
* memory_region_iommu_replay_all: replay existing IOMMU translations
* to all the notifiers registered.
*
+ * Note: this is not related to record-and-replay functionality.
+ *
* @iommu_mr: the memory region to observe
*/
void memory_region_iommu_replay_all(IOMMUMemoryRegion *iommu_mr);
@@ -981,7 +1064,9 @@ void memory_region_unregister_iommu_notifier(MemoryRegion *mr,
* memory_region_iommu_get_attr: return an IOMMU attr if get_attr() is
* defined on the IOMMU.
*
- * Returns 0 if succeded, error code otherwise.
+ * Returns 0 on success, or a negative errno otherwise. In particular,
+ * -EINVAL indicates that the IOMMU does not support the requested
+ * attribute.
*
* @iommu_mr: the memory region
* @attr: the requested attribute
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (9 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() " Peter Maydell
` (15 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to tb_invalidate_phys_addr().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-3-peter.maydell@linaro.org
---
include/exec/exec-all.h | 5 +++--
accel/tcg/translate-all.c | 2 +-
exec.c | 2 +-
target/xtensa/op_helper.c | 3 ++-
4 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h
index bd68328ed9..4d09eaba72 100644
--- a/include/exec/exec-all.h
+++ b/include/exec/exec-all.h
@@ -255,7 +255,7 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_ulong vaddr,
void tlb_set_page(CPUState *cpu, target_ulong vaddr,
hwaddr paddr, int prot,
int mmu_idx, target_ulong size);
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr);
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs);
void probe_write(CPUArchState *env, target_ulong addr, int size, int mmu_idx,
uintptr_t retaddr);
#else
@@ -303,7 +303,8 @@ static inline void tlb_flush_by_mmuidx_all_cpus_synced(CPUState *cpu,
uint16_t idxmap)
{
}
-static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+static inline void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr,
+ MemTxAttrs attrs)
{
}
#endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 732c919629..18ce24a94d 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1669,7 +1669,7 @@ static TranslationBlock *tb_find_pc(uintptr_t tc_ptr)
}
#if !defined(CONFIG_USER_ONLY)
-void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr)
+void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
{
ram_addr_t ram_addr;
MemoryRegion *mr;
diff --git a/exec.c b/exec.c
index ffa1099547..c3a197e67b 100644
--- a/exec.c
+++ b/exec.c
@@ -898,7 +898,7 @@ static void breakpoint_invalidate(CPUState *cpu, target_ulong pc)
if (phys != -1) {
/* Locks grabbed by tb_invalidate_phys_addr */
tb_invalidate_phys_addr(cpu->cpu_ases[asidx].as,
- phys | (pc & ~TARGET_PAGE_MASK));
+ phys | (pc & ~TARGET_PAGE_MASK), attrs);
}
}
#endif
diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c
index e3bcbe10d6..8a8c763c63 100644
--- a/target/xtensa/op_helper.c
+++ b/target/xtensa/op_helper.c
@@ -105,7 +105,8 @@ static void tb_invalidate_virtual_addr(CPUXtensaState *env, uint32_t vaddr)
int ret = xtensa_get_physical_addr(env, false, vaddr, 2, 0,
&paddr, &page_size, &access);
if (ret == 0) {
- tb_invalidate_phys_addr(&address_space_memory, paddr);
+ tb_invalidate_phys_addr(&address_space_memory, paddr,
+ MEMTXATTRS_UNSPECIFIED);
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (10 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 13/25] Make address_space_map() " Peter Maydell
` (14 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate()
and address_space_translate_cached(). Callers either have an
attrs value to hand, or don't care and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-4-peter.maydell@linaro.org
---
include/exec/memory.h | 4 +++-
accel/tcg/translate-all.c | 2 +-
exec.c | 14 +++++++++-----
hw/vfio/common.c | 3 ++-
memory_ldst.inc.c | 18 +++++++++---------
target/riscv/helper.c | 2 +-
6 files changed, 25 insertions(+), 18 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 267aa5fca4..b95ceb272b 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1908,6 +1908,7 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
* #MemoryRegion.
* @len: pointer to length
* @is_write: indicates the transfer direction
+ * @attrs: memory attributes
*/
MemoryRegion *flatview_translate(FlatView *fv,
hwaddr addr, hwaddr *xlat,
@@ -1915,7 +1916,8 @@ MemoryRegion *flatview_translate(FlatView *fv,
static inline MemoryRegion *address_space_translate(AddressSpace *as,
hwaddr addr, hwaddr *xlat,
- hwaddr *len, bool is_write)
+ hwaddr *len, bool is_write,
+ MemTxAttrs attrs)
{
return flatview_translate(address_space_to_flatview(as),
addr, xlat, len, is_write);
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index 18ce24a94d..d48b56ca38 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -1676,7 +1676,7 @@ void tb_invalidate_phys_addr(AddressSpace *as, hwaddr addr, MemTxAttrs attrs)
hwaddr l = 1;
rcu_read_lock();
- mr = address_space_translate(as, addr, &addr, &l, false);
+ mr = address_space_translate(as, addr, &addr, &l, false, attrs);
if (!(memory_region_is_ram(mr)
|| memory_region_is_romd(mr))) {
rcu_read_unlock();
diff --git a/exec.c b/exec.c
index c3a197e67b..d314c7cc39 100644
--- a/exec.c
+++ b/exec.c
@@ -3322,7 +3322,8 @@ static inline void cpu_physical_memory_write_rom_internal(AddressSpace *as,
rcu_read_lock();
while (len > 0) {
l = len;
- mr = address_space_translate(as, addr, &addr1, &l, true);
+ mr = address_space_translate(as, addr, &addr1, &l, true,
+ MEMTXATTRS_UNSPECIFIED);
if (!(memory_region_is_ram(mr) ||
memory_region_is_romd(mr))) {
@@ -3699,7 +3700,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache)
*/
static inline MemoryRegion *address_space_translate_cached(
MemoryRegionCache *cache, hwaddr addr, hwaddr *xlat,
- hwaddr *plen, bool is_write)
+ hwaddr *plen, bool is_write, MemTxAttrs attrs)
{
MemoryRegionSection section;
MemoryRegion *mr;
@@ -3733,7 +3734,8 @@ address_space_read_cached_slow(MemoryRegionCache *cache, hwaddr addr,
MemoryRegion *mr;
l = len;
- mr = address_space_translate_cached(cache, addr, &addr1, &l, false);
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, false,
+ MEMTXATTRS_UNSPECIFIED);
flatview_read_continue(cache->fv,
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
addr1, l, mr);
@@ -3750,7 +3752,8 @@ address_space_write_cached_slow(MemoryRegionCache *cache, hwaddr addr,
MemoryRegion *mr;
l = len;
- mr = address_space_translate_cached(cache, addr, &addr1, &l, true);
+ mr = address_space_translate_cached(cache, addr, &addr1, &l, true,
+ MEMTXATTRS_UNSPECIFIED);
flatview_write_continue(cache->fv,
addr, MEMTXATTRS_UNSPECIFIED, buf, len,
addr1, l, mr);
@@ -3848,7 +3851,8 @@ bool cpu_physical_memory_is_io(hwaddr phys_addr)
rcu_read_lock();
mr = address_space_translate(&address_space_memory,
- phys_addr, &phys_addr, &l, false);
+ phys_addr, &phys_addr, &l, false,
+ MEMTXATTRS_UNSPECIFIED);
res = !(memory_region_is_ram(mr) || memory_region_is_romd(mr));
rcu_read_unlock();
diff --git a/hw/vfio/common.c b/hw/vfio/common.c
index 07ffa0ba10..8e57265edf 100644
--- a/hw/vfio/common.c
+++ b/hw/vfio/common.c
@@ -324,7 +324,8 @@ static bool vfio_get_vaddr(IOMMUTLBEntry *iotlb, void **vaddr,
*/
mr = address_space_translate(&address_space_memory,
iotlb->translated_addr,
- &xlat, &len, writable);
+ &xlat, &len, writable,
+ MEMTXATTRS_UNSPECIFIED);
if (!memory_region_is_ram(mr)) {
error_report("iommu map to non memory area %"HWADDR_PRIx"",
xlat);
diff --git a/memory_ldst.inc.c b/memory_ldst.inc.c
index 25d6125747..15483987fe 100644
--- a/memory_ldst.inc.c
+++ b/memory_ldst.inc.c
@@ -33,7 +33,7 @@ static inline uint32_t glue(address_space_ldl_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false);
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
if (l < 4 || !IS_DIRECT(mr, false)) {
release_lock |= prepare_mmio_access(mr);
@@ -109,7 +109,7 @@ static inline uint64_t glue(address_space_ldq_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false);
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
if (l < 8 || !IS_DIRECT(mr, false)) {
release_lock |= prepare_mmio_access(mr);
@@ -183,7 +183,7 @@ uint32_t glue(address_space_ldub, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false);
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
if (!IS_DIRECT(mr, false)) {
release_lock |= prepare_mmio_access(mr);
@@ -219,7 +219,7 @@ static inline uint32_t glue(address_space_lduw_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, false);
+ mr = TRANSLATE(addr, &addr1, &l, false, attrs);
if (l < 2 || !IS_DIRECT(mr, false)) {
release_lock |= prepare_mmio_access(mr);
@@ -296,7 +296,7 @@ void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true);
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 4 || !IS_DIRECT(mr, true)) {
release_lock |= prepare_mmio_access(mr);
@@ -333,7 +333,7 @@ static inline void glue(address_space_stl_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true);
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 4 || !IS_DIRECT(mr, true)) {
release_lock |= prepare_mmio_access(mr);
@@ -405,7 +405,7 @@ void glue(address_space_stb, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true);
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (!IS_DIRECT(mr, true)) {
release_lock |= prepare_mmio_access(mr);
r = memory_region_dispatch_write(mr, addr1, val, 1, attrs);
@@ -438,7 +438,7 @@ static inline void glue(address_space_stw_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true);
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 2 || !IS_DIRECT(mr, true)) {
release_lock |= prepare_mmio_access(mr);
@@ -511,7 +511,7 @@ static void glue(address_space_stq_internal, SUFFIX)(ARG1_DECL,
bool release_lock = false;
RCU_READ_LOCK();
- mr = TRANSLATE(addr, &addr1, &l, true);
+ mr = TRANSLATE(addr, &addr1, &l, true, attrs);
if (l < 8 || !IS_DIRECT(mr, true)) {
release_lock |= prepare_mmio_access(mr);
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 95889f23b9..29e1a603dc 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -210,7 +210,7 @@ restart:
MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1;
mr = address_space_translate(cs->as, pte_addr,
- &addr1, &l, false);
+ &addr1, &l, false, MEMTXATTRS_UNSPECIFIED);
if (memory_access_is_direct(mr, true)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (11 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 14/25] Make address_space_access_valid() " Peter Maydell
` (13 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_map().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-5-peter.maydell@linaro.org
---
include/exec/memory.h | 3 ++-
include/sysemu/dma.h | 3 ++-
exec.c | 6 ++++--
target/ppc/mmu-hash64.c | 3 ++-
4 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index b95ceb272b..d594639d7c 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1952,9 +1952,10 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_
* @addr: address within that address space
* @plen: pointer to length of buffer; updated on return
* @is_write: indicates the transfer direction
+ * @attrs: memory attributes
*/
void *address_space_map(AddressSpace *as, hwaddr addr,
- hwaddr *plen, bool is_write);
+ hwaddr *plen, bool is_write, MemTxAttrs attrs);
/* address_space_unmap: Unmaps a memory region previously mapped by address_space_map()
*
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index c228c66513..0d73902634 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -132,7 +132,8 @@ static inline void *dma_memory_map(AddressSpace *as,
hwaddr xlen = *len;
void *p;
- p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE);
+ p = address_space_map(as, addr, &xlen, dir == DMA_DIRECTION_FROM_DEVICE,
+ MEMTXATTRS_UNSPECIFIED);
*len = xlen;
return p;
}
diff --git a/exec.c b/exec.c
index d314c7cc39..1dc81cfe4a 100644
--- a/exec.c
+++ b/exec.c
@@ -3529,7 +3529,8 @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
void *address_space_map(AddressSpace *as,
hwaddr addr,
hwaddr *plen,
- bool is_write)
+ bool is_write,
+ MemTxAttrs attrs)
{
hwaddr len = *plen;
hwaddr l, xlat;
@@ -3616,7 +3617,8 @@ void *cpu_physical_memory_map(hwaddr addr,
hwaddr *plen,
int is_write)
{
- return address_space_map(&address_space_memory, addr, plen, is_write);
+ return address_space_map(&address_space_memory, addr, plen, is_write,
+ MEMTXATTRS_UNSPECIFIED);
}
void cpu_physical_memory_unmap(void *buffer, hwaddr len,
diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c
index a1db20e3a8..aa200cba4c 100644
--- a/target/ppc/mmu-hash64.c
+++ b/target/ppc/mmu-hash64.c
@@ -431,7 +431,8 @@ const ppc_hash_pte64_t *ppc_hash64_map_hptes(PowerPCCPU *cpu,
return NULL;
}
- hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false);
+ hptes = address_space_map(CPU(cpu)->as, base + pte_offset, &plen, false,
+ MEMTXATTRS_UNSPECIFIED);
if (plen < (n * HASH_PTE_SIZE_64)) {
hw_error("%s: Unable to map all requested HPTEs\n", __func__);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 14/25] Make address_space_access_valid() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (12 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 13/25] Make address_space_map() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 15/25] Make flatview_extend_translation() " Peter Maydell
` (12 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-6-peter.maydell@linaro.org
---
include/exec/memory.h | 4 +++-
include/sysemu/dma.h | 3 ++-
exec.c | 3 ++-
target/s390x/diag.c | 6 ++++--
target/s390x/excp_helper.c | 3 ++-
target/s390x/mmu_helper.c | 3 ++-
target/s390x/sigp.c | 3 ++-
7 files changed, 17 insertions(+), 8 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index d594639d7c..3f2671f332 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1937,8 +1937,10 @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
* @addr: address within that address space
* @len: length of the area to be checked
* @is_write: indicates the transfer direction
+ * @attrs: memory attributes
*/
-bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len, bool is_write);
+bool address_space_access_valid(AddressSpace *as, hwaddr addr, int len,
+ bool is_write, MemTxAttrs attrs);
/* address_space_map: map a physical memory region into a host virtual address
*
diff --git a/include/sysemu/dma.h b/include/sysemu/dma.h
index 0d73902634..5da3c4e3c5 100644
--- a/include/sysemu/dma.h
+++ b/include/sysemu/dma.h
@@ -77,7 +77,8 @@ static inline bool dma_memory_valid(AddressSpace *as,
DMADirection dir)
{
return address_space_access_valid(as, addr, len,
- dir == DMA_DIRECTION_FROM_DEVICE);
+ dir == DMA_DIRECTION_FROM_DEVICE,
+ MEMTXATTRS_UNSPECIFIED);
}
static inline int dma_memory_rw_relaxed(AddressSpace *as, dma_addr_t addr,
diff --git a/exec.c b/exec.c
index 1dc81cfe4a..22af4e8cb9 100644
--- a/exec.c
+++ b/exec.c
@@ -3480,7 +3480,8 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
}
bool address_space_access_valid(AddressSpace *as, hwaddr addr,
- int len, bool is_write)
+ int len, bool is_write,
+ MemTxAttrs attrs)
{
FlatView *fv;
bool result;
diff --git a/target/s390x/diag.c b/target/s390x/diag.c
index ac2c40f363..d1d3433aa7 100644
--- a/target/s390x/diag.c
+++ b/target/s390x/diag.c
@@ -87,7 +87,8 @@ void handle_diag_308(CPUS390XState *env, uint64_t r1, uint64_t r3, uintptr_t ra)
return;
}
if (!address_space_access_valid(&address_space_memory, addr,
- sizeof(IplParameterBlock), false)) {
+ sizeof(IplParameterBlock), false,
+ MEMTXATTRS_UNSPECIFIED)) {
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
return;
}
@@ -116,7 +117,8 @@ out:
return;
}
if (!address_space_access_valid(&address_space_memory, addr,
- sizeof(IplParameterBlock), true)) {
+ sizeof(IplParameterBlock), true,
+ MEMTXATTRS_UNSPECIFIED)) {
s390_program_interrupt(env, PGM_ADDRESSING, ILEN_AUTO, ra);
return;
}
diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c
index dfee221111..f0ce60cff2 100644
--- a/target/s390x/excp_helper.c
+++ b/target/s390x/excp_helper.c
@@ -120,7 +120,8 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr, int size,
/* check out of RAM access */
if (!address_space_access_valid(&address_space_memory, raddr,
- TARGET_PAGE_SIZE, rw)) {
+ TARGET_PAGE_SIZE, rw,
+ MEMTXATTRS_UNSPECIFIED)) {
DPRINTF("%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", __func__,
(uint64_t)raddr, (uint64_t)ram_size);
trigger_pgm_exception(env, PGM_ADDRESSING, ILEN_AUTO);
diff --git a/target/s390x/mmu_helper.c b/target/s390x/mmu_helper.c
index a25deef5dd..145b62a7ef 100644
--- a/target/s390x/mmu_helper.c
+++ b/target/s390x/mmu_helper.c
@@ -461,7 +461,8 @@ static int translate_pages(S390CPU *cpu, vaddr addr, int nr_pages,
return ret;
}
if (!address_space_access_valid(&address_space_memory, pages[i],
- TARGET_PAGE_SIZE, is_write)) {
+ TARGET_PAGE_SIZE, is_write,
+ MEMTXATTRS_UNSPECIFIED)) {
trigger_access_exception(env, PGM_ADDRESSING, ILEN_AUTO, 0);
return -EFAULT;
}
diff --git a/target/s390x/sigp.c b/target/s390x/sigp.c
index aff1530c82..c1f9245797 100644
--- a/target/s390x/sigp.c
+++ b/target/s390x/sigp.c
@@ -280,7 +280,8 @@ static void sigp_set_prefix(CPUState *cs, run_on_cpu_data arg)
cpu_synchronize_state(cs);
if (!address_space_access_valid(&address_space_memory, addr,
- sizeof(struct LowCore), false)) {
+ sizeof(struct LowCore), false,
+ MEMTXATTRS_UNSPECIFIED)) {
set_sigp_status(si, SIGP_STAT_INVALID_PARAMETER);
return;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (13 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 14/25] Make address_space_access_valid() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 16/25] Make memory_region_access_valid() " Peter Maydell
` (11 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_extend_translation().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-7-peter.maydell@linaro.org
---
exec.c | 15 ++++++++++-----
1 file changed, 10 insertions(+), 5 deletions(-)
diff --git a/exec.c b/exec.c
index 22af4e8cb9..718b33921b 100644
--- a/exec.c
+++ b/exec.c
@@ -3495,9 +3495,9 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
static hwaddr
flatview_extend_translation(FlatView *fv, hwaddr addr,
- hwaddr target_len,
- MemoryRegion *mr, hwaddr base, hwaddr len,
- bool is_write)
+ hwaddr target_len,
+ MemoryRegion *mr, hwaddr base, hwaddr len,
+ bool is_write, MemTxAttrs attrs)
{
hwaddr done = 0;
hwaddr xlat;
@@ -3574,7 +3574,7 @@ void *address_space_map(AddressSpace *as,
memory_region_ref(mr);
*plen = flatview_extend_translation(fv, addr, len, mr, xlat,
- l, is_write);
+ l, is_write, attrs);
ptr = qemu_ram_ptr_length(mr->ram_block, xlat, plen, true);
rcu_read_unlock();
@@ -3659,8 +3659,13 @@ int64_t address_space_cache_init(MemoryRegionCache *cache,
mr = cache->mrs.mr;
memory_region_ref(mr);
if (memory_access_is_direct(mr, is_write)) {
+ /* We don't care about the memory attributes here as we're only
+ * doing this if we found actual RAM, which behaves the same
+ * regardless of attributes; so UNSPECIFIED is fine.
+ */
l = flatview_extend_translation(cache->fv, addr, len, mr,
- cache->xlat, l, is_write);
+ cache->xlat, l, is_write,
+ MEMTXATTRS_UNSPECIFIED);
cache->ptr = qemu_ram_ptr_length(mr->ram_block, cache->xlat, &l, true);
} else {
cache->ptr = NULL;
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (14 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 15/25] Make flatview_extend_translation() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback " Peter Maydell
` (10 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to memory_region_access_valid().
Its callers either have an attrs value to hand, or don't care
and can use MEMTXATTRS_UNSPECIFIED.
The callsite in flatview_access_valid() is part of a recursive
loop flatview_access_valid() -> memory_region_access_valid() ->
subpage_accepts() -> flatview_access_valid(); we make it pass
MEMTXATTRS_UNSPECIFIED for now, until the next several commits
have plumbed an attrs parameter through the rest of the loop
and we can add an attrs parameter to flatview_access_valid().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-8-peter.maydell@linaro.org
---
include/exec/memory-internal.h | 3 ++-
exec.c | 4 +++-
hw/s390x/s390-pci-inst.c | 3 ++-
memory.c | 7 ++++---
4 files changed, 11 insertions(+), 6 deletions(-)
diff --git a/include/exec/memory-internal.h b/include/exec/memory-internal.h
index 58399b9318..56c25c0ef7 100644
--- a/include/exec/memory-internal.h
+++ b/include/exec/memory-internal.h
@@ -37,7 +37,8 @@ void flatview_unref(FlatView *view);
extern const MemoryRegionOps unassigned_mem_ops;
bool memory_region_access_valid(MemoryRegion *mr, hwaddr addr,
- unsigned size, bool is_write);
+ unsigned size, bool is_write,
+ MemTxAttrs attrs);
void flatview_add_to_dispatch(FlatView *fv, MemoryRegionSection *section);
AddressSpaceDispatch *address_space_dispatch_new(FlatView *fv);
diff --git a/exec.c b/exec.c
index 718b33921b..6cf97b5d28 100644
--- a/exec.c
+++ b/exec.c
@@ -3468,7 +3468,9 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
if (!memory_access_is_direct(mr, is_write)) {
l = memory_access_size(mr, l, addr);
- if (!memory_region_access_valid(mr, xlat, l, is_write)) {
+ /* When our callers all have attrs we'll pass them through here */
+ if (!memory_region_access_valid(mr, xlat, l, is_write,
+ MEMTXATTRS_UNSPECIFIED)) {
return false;
}
}
diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c
index 02a815fd31..d1a5f79678 100644
--- a/hw/s390x/s390-pci-inst.c
+++ b/hw/s390x/s390-pci-inst.c
@@ -762,7 +762,8 @@ int pcistb_service_call(S390CPU *cpu, uint8_t r1, uint8_t r3, uint64_t gaddr,
mr = s390_get_subregion(mr, offset, len);
offset -= mr->addr;
- if (!memory_region_access_valid(mr, offset, len, true)) {
+ if (!memory_region_access_valid(mr, offset, len, true,
+ MEMTXATTRS_UNSPECIFIED)) {
s390_program_interrupt(env, PGM_OPERAND, 6, ra);
return 0;
}
diff --git a/memory.c b/memory.c
index fc7f9b782b..279f7c9b4a 100644
--- a/memory.c
+++ b/memory.c
@@ -1347,7 +1347,8 @@ static const MemoryRegionOps ram_device_mem_ops = {
bool memory_region_access_valid(MemoryRegion *mr,
hwaddr addr,
unsigned size,
- bool is_write)
+ bool is_write,
+ MemTxAttrs attrs)
{
int access_size_min, access_size_max;
int access_size, i;
@@ -1416,7 +1417,7 @@ MemTxResult memory_region_dispatch_read(MemoryRegion *mr,
{
MemTxResult r;
- if (!memory_region_access_valid(mr, addr, size, false)) {
+ if (!memory_region_access_valid(mr, addr, size, false, attrs)) {
*pval = unassigned_mem_read(mr, addr, size);
return MEMTX_DECODE_ERROR;
}
@@ -1458,7 +1459,7 @@ MemTxResult memory_region_dispatch_write(MemoryRegion *mr,
unsigned size,
MemTxAttrs attrs)
{
- if (!memory_region_access_valid(mr, addr, size, true)) {
+ if (!memory_region_access_valid(mr, addr, size, true, attrs)) {
unassigned_mem_write(mr, addr, data, size);
return MEMTX_DECODE_ERROR;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (15 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 16/25] Make memory_region_access_valid() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 18/25] Make flatview_access_valid() " Peter Maydell
` (9 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to the MemoryRegion valid.accepts
callback. We'll need this for subpage_accepts().
We could take the approach we used with the read and write
callbacks and add new a new _with_attrs version, but since there
are so few implementations of the accepts hook we just change
them all.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-9-peter.maydell@linaro.org
---
include/exec/memory.h | 3 ++-
exec.c | 9 ++++++---
hw/hppa/dino.c | 3 ++-
hw/nvram/fw_cfg.c | 12 ++++++++----
hw/scsi/esp.c | 3 ++-
hw/xen/xen_pt_msi.c | 3 ++-
memory.c | 5 +++--
7 files changed, 25 insertions(+), 13 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 3f2671f332..76a2dd3878 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -166,7 +166,8 @@ struct MemoryRegionOps {
* as a machine check exception).
*/
bool (*accepts)(void *opaque, hwaddr addr,
- unsigned size, bool is_write);
+ unsigned size, bool is_write,
+ MemTxAttrs attrs);
} valid;
/* Internal implementation constraints: */
struct {
diff --git a/exec.c b/exec.c
index 6cf97b5d28..b58eb0fedd 100644
--- a/exec.c
+++ b/exec.c
@@ -2539,7 +2539,8 @@ static void notdirty_mem_write(void *opaque, hwaddr ram_addr,
}
static bool notdirty_mem_accepts(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return is_write;
}
@@ -2762,7 +2763,8 @@ static MemTxResult subpage_write(void *opaque, hwaddr addr,
}
static bool subpage_accepts(void *opaque, hwaddr addr,
- unsigned len, bool is_write)
+ unsigned len, bool is_write,
+ MemTxAttrs attrs)
{
subpage_t *subpage = opaque;
#if defined(DEBUG_SUBPAGE)
@@ -2845,7 +2847,8 @@ static void readonly_mem_write(void *opaque, hwaddr addr,
}
static bool readonly_mem_accepts(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return is_write;
}
diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c
index c5dcf3104d..26f2704cd5 100644
--- a/hw/hppa/dino.c
+++ b/hw/hppa/dino.c
@@ -137,7 +137,8 @@ static void gsc_to_pci_forwarding(DinoState *s)
}
static bool dino_chip_mem_valid(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
switch (addr) {
case DINO_IAR0:
diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c
index 2a0739d0e9..b23e7f64a8 100644
--- a/hw/nvram/fw_cfg.c
+++ b/hw/nvram/fw_cfg.c
@@ -420,14 +420,16 @@ static void fw_cfg_dma_mem_write(void *opaque, hwaddr addr,
}
static bool fw_cfg_dma_mem_valid(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return !is_write || ((size == 4 && (addr == 0 || addr == 4)) ||
(size == 8 && addr == 0));
}
static bool fw_cfg_data_mem_valid(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return addr == 0;
}
@@ -439,7 +441,8 @@ static void fw_cfg_ctl_mem_write(void *opaque, hwaddr addr,
}
static bool fw_cfg_ctl_mem_valid(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return is_write && size == 2;
}
@@ -458,7 +461,8 @@ static void fw_cfg_comb_write(void *opaque, hwaddr addr,
}
static bool fw_cfg_comb_valid(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return (size == 1) || (is_write && size == 2);
}
diff --git a/hw/scsi/esp.c b/hw/scsi/esp.c
index 64ec285826..9ed9727744 100644
--- a/hw/scsi/esp.c
+++ b/hw/scsi/esp.c
@@ -564,7 +564,8 @@ void esp_reg_write(ESPState *s, uint32_t saddr, uint64_t val)
}
static bool esp_mem_accepts(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return (size == 1) || (is_write && size == 4);
}
diff --git a/hw/xen/xen_pt_msi.c b/hw/xen/xen_pt_msi.c
index 6d1e3bdeb4..cc514f9157 100644
--- a/hw/xen/xen_pt_msi.c
+++ b/hw/xen/xen_pt_msi.c
@@ -498,7 +498,8 @@ static uint64_t pci_msix_read(void *opaque, hwaddr addr,
}
static bool pci_msix_accepts(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return !(addr & (size - 1));
}
diff --git a/memory.c b/memory.c
index 279f7c9b4a..10fa2ddd31 100644
--- a/memory.c
+++ b/memory.c
@@ -1269,7 +1269,8 @@ static void unassigned_mem_write(void *opaque, hwaddr addr,
}
static bool unassigned_mem_accepts(void *opaque, hwaddr addr,
- unsigned size, bool is_write)
+ unsigned size, bool is_write,
+ MemTxAttrs attrs)
{
return false;
}
@@ -1374,7 +1375,7 @@ bool memory_region_access_valid(MemoryRegion *mr,
access_size = MAX(MIN(size, access_size_max), access_size_min);
for (i = 0; i < size; i += access_size) {
if (!mr->ops->valid.accepts(mr->opaque, addr + i, access_size,
- is_write)) {
+ is_write, attrs)) {
return false;
}
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (16 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 19/25] Make flatview_translate() " Peter Maydell
` (8 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_access_valid().
Its callers now all have an attrs value to hand, so we can
correct our earlier temporary use of MEMTXATTRS_UNSPECIFIED.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-10-peter.maydell@linaro.org
---
exec.c | 12 +++++-------
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git a/exec.c b/exec.c
index b58eb0fedd..33e0a4f153 100644
--- a/exec.c
+++ b/exec.c
@@ -2697,7 +2697,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
const uint8_t *buf, int len);
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
- bool is_write);
+ bool is_write, MemTxAttrs attrs);
static MemTxResult subpage_read(void *opaque, hwaddr addr, uint64_t *data,
unsigned len, MemTxAttrs attrs)
@@ -2773,7 +2773,7 @@ static bool subpage_accepts(void *opaque, hwaddr addr,
#endif
return flatview_access_valid(subpage->fv, addr + subpage->base,
- len, is_write);
+ len, is_write, attrs);
}
static const MemoryRegionOps subpage_ops = {
@@ -3461,7 +3461,7 @@ static void cpu_notify_map_clients(void)
}
static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
- bool is_write)
+ bool is_write, MemTxAttrs attrs)
{
MemoryRegion *mr;
hwaddr l, xlat;
@@ -3471,9 +3471,7 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
mr = flatview_translate(fv, addr, &xlat, &l, is_write);
if (!memory_access_is_direct(mr, is_write)) {
l = memory_access_size(mr, l, addr);
- /* When our callers all have attrs we'll pass them through here */
- if (!memory_region_access_valid(mr, xlat, l, is_write,
- MEMTXATTRS_UNSPECIFIED)) {
+ if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
return false;
}
}
@@ -3493,7 +3491,7 @@ bool address_space_access_valid(AddressSpace *as, hwaddr addr,
rcu_read_lock();
fv = address_space_to_flatview(as);
- result = flatview_access_valid(fv, addr, len, is_write);
+ result = flatview_access_valid(fv, addr, len, is_write, attrs);
rcu_read_unlock();
return result;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 19/25] Make flatview_translate() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (17 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 18/25] Make flatview_access_valid() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() " Peter Maydell
` (7 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_translate(); all its
callers now have attrs available.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-11-peter.maydell@linaro.org
---
include/exec/memory.h | 7 ++++---
exec.c | 17 +++++++++--------
2 files changed, 13 insertions(+), 11 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 76a2dd3878..28a694970a 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1913,7 +1913,8 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
*/
MemoryRegion *flatview_translate(FlatView *fv,
hwaddr addr, hwaddr *xlat,
- hwaddr *len, bool is_write);
+ hwaddr *len, bool is_write,
+ MemTxAttrs attrs);
static inline MemoryRegion *address_space_translate(AddressSpace *as,
hwaddr addr, hwaddr *xlat,
@@ -1921,7 +1922,7 @@ static inline MemoryRegion *address_space_translate(AddressSpace *as,
MemTxAttrs attrs)
{
return flatview_translate(address_space_to_flatview(as),
- addr, xlat, len, is_write);
+ addr, xlat, len, is_write, attrs);
}
/* address_space_access_valid: check for validity of accessing an address
@@ -2030,7 +2031,7 @@ MemTxResult address_space_read(AddressSpace *as, hwaddr addr,
rcu_read_lock();
fv = address_space_to_flatview(as);
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, false);
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
if (len == l && memory_access_is_direct(mr, false)) {
ptr = qemu_map_ram_ptr(mr->ram_block, addr1);
memcpy(buf, ptr, len);
diff --git a/exec.c b/exec.c
index 33e0a4f153..d54a56fefa 100644
--- a/exec.c
+++ b/exec.c
@@ -618,7 +618,8 @@ iotlb_fail:
/* Called from RCU critical section */
MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
- hwaddr *plen, bool is_write)
+ hwaddr *plen, bool is_write,
+ MemTxAttrs attrs)
{
MemoryRegion *mr;
MemoryRegionSection section;
@@ -3152,7 +3153,7 @@ static MemTxResult flatview_write_continue(FlatView *fv, hwaddr addr,
}
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, true);
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
}
return result;
@@ -3168,7 +3169,7 @@ static MemTxResult flatview_write(FlatView *fv, hwaddr addr, MemTxAttrs attrs,
MemTxResult result = MEMTX_OK;
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, true);
+ mr = flatview_translate(fv, addr, &addr1, &l, true, attrs);
result = flatview_write_continue(fv, addr, attrs, buf, len,
addr1, l, mr);
@@ -3239,7 +3240,7 @@ MemTxResult flatview_read_continue(FlatView *fv, hwaddr addr,
}
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, false);
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
}
return result;
@@ -3254,7 +3255,7 @@ static MemTxResult flatview_read(FlatView *fv, hwaddr addr,
MemoryRegion *mr;
l = len;
- mr = flatview_translate(fv, addr, &addr1, &l, false);
+ mr = flatview_translate(fv, addr, &addr1, &l, false, attrs);
return flatview_read_continue(fv, addr, attrs, buf, len,
addr1, l, mr);
}
@@ -3468,7 +3469,7 @@ static bool flatview_access_valid(FlatView *fv, hwaddr addr, int len,
while (len > 0) {
l = len;
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
if (!memory_access_is_direct(mr, is_write)) {
l = memory_access_size(mr, l, addr);
if (!memory_region_access_valid(mr, xlat, l, is_write, attrs)) {
@@ -3516,7 +3517,7 @@ flatview_extend_translation(FlatView *fv, hwaddr addr,
len = target_len;
this_mr = flatview_translate(fv, addr, &xlat,
- &len, is_write);
+ &len, is_write, attrs);
if (this_mr != mr || xlat != base + done) {
return done;
}
@@ -3549,7 +3550,7 @@ void *address_space_map(AddressSpace *as,
l = len;
rcu_read_lock();
fv = address_space_to_flatview(as);
- mr = flatview_translate(fv, addr, &xlat, &l, is_write);
+ mr = flatview_translate(fv, addr, &xlat, &l, is_write, attrs);
if (!memory_access_is_direct(mr, is_write)) {
if (atomic_xchg(&bounce.in_use, true)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (18 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 19/25] Make flatview_translate() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 21/25] Make flatview_do_translate() " Peter Maydell
` (6 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_get_iotlb_entry().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-12-peter.maydell@linaro.org
---
include/exec/memory.h | 2 +-
exec.c | 2 +-
hw/virtio/vhost.c | 3 ++-
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/include/exec/memory.h b/include/exec/memory.h
index 28a694970a..67ea7fe1ee 100644
--- a/include/exec/memory.h
+++ b/include/exec/memory.h
@@ -1896,7 +1896,7 @@ void address_space_cache_destroy(MemoryRegionCache *cache);
* entry. Should be called from an RCU critical section.
*/
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
- bool is_write);
+ bool is_write, MemTxAttrs attrs);
/* address_space_translate: translate an address range into an address space
* into a MemoryRegion and an address range into that section. Should be
diff --git a/exec.c b/exec.c
index d54a56fefa..57c64c6c13 100644
--- a/exec.c
+++ b/exec.c
@@ -582,7 +582,7 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
/* Called from RCU critical section */
IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
- bool is_write)
+ bool is_write, MemTxAttrs attrs)
{
MemoryRegionSection section;
hwaddr xlat, page_mask;
diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c
index b08290036d..4565b69f83 100644
--- a/hw/virtio/vhost.c
+++ b/hw/virtio/vhost.c
@@ -897,7 +897,8 @@ int vhost_device_iotlb_miss(struct vhost_dev *dev, uint64_t iova, int write)
trace_vhost_iotlb_miss(dev, 1);
iotlb = address_space_get_iotlb_entry(dev->vdev->dma_as,
- iova, write);
+ iova, write,
+ MEMTXATTRS_UNSPECIFIED);
if (iotlb.target_as != NULL) {
ret = vhost_memory_region_lookup(dev, iotlb.translated_addr,
&uaddr, &len);
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (19 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 22/25] Make address_space_translate_iommu " Peter Maydell
` (5 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to flatview_do_translate().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-13-peter.maydell@linaro.org
---
exec.c | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index 57c64c6c13..e84e0d8c58 100644
--- a/exec.c
+++ b/exec.c
@@ -541,6 +541,7 @@ unassigned:
* @is_write: whether the translation operation is for write
* @is_mmio: whether this can be MMIO, set true if it can
* @target_as: the address space targeted by the IOMMU
+ * @attrs: memory transaction attributes
*
* This function is called from RCU critical section
*/
@@ -551,7 +552,8 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
hwaddr *page_mask_out,
bool is_write,
bool is_mmio,
- AddressSpace **target_as)
+ AddressSpace **target_as,
+ MemTxAttrs attrs)
{
MemoryRegionSection *section;
IOMMUMemoryRegion *iommu_mr;
@@ -592,7 +594,8 @@ IOMMUTLBEntry address_space_get_iotlb_entry(AddressSpace *as, hwaddr addr,
* but page mask.
*/
section = flatview_do_translate(address_space_to_flatview(as), addr, &xlat,
- NULL, &page_mask, is_write, false, &as);
+ NULL, &page_mask, is_write, false, &as,
+ attrs);
/* Illegal translation */
if (section.mr == &io_mem_unassigned) {
@@ -627,7 +630,7 @@ MemoryRegion *flatview_translate(FlatView *fv, hwaddr addr, hwaddr *xlat,
/* This can be MMIO, so setup MMIO bit. */
section = flatview_do_translate(fv, addr, xlat, plen, NULL,
- is_write, true, &as);
+ is_write, true, &as, attrs);
mr = section.mr;
if (xen_enabled() && memory_access_is_direct(mr, is_write)) {
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 22/25] Make address_space_translate_iommu take a MemTxAttrs argument
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (20 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 21/25] Make flatview_do_translate() " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY Peter Maydell
` (4 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
As part of plumbing MemTxAttrs down to the IOMMU translate method,
add MemTxAttrs as an argument to address_space_translate_iommu().
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20180521140402.23318-14-peter.maydell@linaro.org
---
exec.c | 8 +++++---
1 file changed, 5 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index e84e0d8c58..c30f905598 100644
--- a/exec.c
+++ b/exec.c
@@ -478,6 +478,7 @@ address_space_translate_internal(AddressSpaceDispatch *d, hwaddr addr, hwaddr *x
* @is_write: whether the translation operation is for write
* @is_mmio: whether this can be MMIO, set true if it can
* @target_as: the address space targeted by the IOMMU
+ * @attrs: transaction attributes
*
* This function is called from RCU critical section. It is the common
* part of flatview_do_translate and address_space_translate_cached.
@@ -488,7 +489,8 @@ static MemoryRegionSection address_space_translate_iommu(IOMMUMemoryRegion *iomm
hwaddr *page_mask_out,
bool is_write,
bool is_mmio,
- AddressSpace **target_as)
+ AddressSpace **target_as,
+ MemTxAttrs attrs)
{
MemoryRegionSection *section;
hwaddr page_mask = (hwaddr)-1;
@@ -572,7 +574,7 @@ static MemoryRegionSection flatview_do_translate(FlatView *fv,
return address_space_translate_iommu(iommu_mr, xlat,
plen_out, page_mask_out,
is_write, is_mmio,
- target_as);
+ target_as, attrs);
}
if (page_mask_out) {
/* Not behind an IOMMU, use default page size. */
@@ -3734,7 +3736,7 @@ static inline MemoryRegion *address_space_translate_cached(
section = address_space_translate_iommu(iommu_mr, xlat, plen,
NULL, is_write, true,
- &target_as);
+ &target_as, attrs);
return section.mr;
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (21 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 22/25] Make address_space_translate_iommu " Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc Peter Maydell
` (3 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
Provide a VMSTATE_BOOL_SUB_ARRAY to go with VMSTATE_UINT8_SUB_ARRAY
and friends.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180521140402.23318-23-peter.maydell@linaro.org
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index df463fd33d..59fc75e418 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -870,6 +870,9 @@ extern const VMStateInfo vmstate_info_qtailq;
#define VMSTATE_BOOL_ARRAY(_f, _s, _n) \
VMSTATE_BOOL_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_BOOL_SUB_ARRAY(_f, _s, _start, _num) \
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_bool, bool)
+
#define VMSTATE_UINT16_ARRAY_V(_f, _s, _n, _v) \
VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_uint16, uint16_t)
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (22 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice Peter Maydell
` (2 subsequent siblings)
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Shannon Zhao <zhaoshenglong@huawei.com>
acpi_data_push uses g_array_set_size to resize the memory size. If there
is no enough contiguous memory, the address will be changed. So previous
pointer could not be used any more. It must update the pointer and use
the new one.
Also, previous codes wrongly use le32 conversion of iort->node_offset
for subsequent computations that will result incorrect value if host is
not litlle endian. So use the non-converted one instead.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527663951-14552-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/arm/virt-acpi-build.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 92ceee9c0f..74f5744e87 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -400,7 +400,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
AcpiIortItsGroup *its;
AcpiIortTable *iort;
AcpiIortSmmu3 *smmu;
- size_t node_size, iort_length, smmu_offset = 0;
+ size_t node_size, iort_node_offset, iort_length, smmu_offset = 0;
AcpiIortRC *rc;
iort = acpi_data_push(table_data, sizeof(*iort));
@@ -413,7 +413,12 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
iort_length = sizeof(*iort);
iort->node_count = cpu_to_le32(nb_nodes);
- iort->node_offset = cpu_to_le32(sizeof(*iort));
+ /*
+ * Use a copy in case table_data->data moves during acpi_data_push
+ * operations.
+ */
+ iort_node_offset = sizeof(*iort);
+ iort->node_offset = cpu_to_le32(iort_node_offset);
/* ITS group node */
node_size = sizeof(*its) + sizeof(uint32_t);
@@ -429,7 +434,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
int irq = vms->irqmap[VIRT_SMMU];
/* SMMUv3 node */
- smmu_offset = iort->node_offset + node_size;
+ smmu_offset = iort_node_offset + node_size;
node_size = sizeof(*smmu) + sizeof(*idmap);
iort_length += node_size;
smmu = acpi_data_push(table_data, node_size);
@@ -450,7 +455,7 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
idmap->id_count = cpu_to_le32(0xFFFF);
idmap->output_base = 0;
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort->node_offset);
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
}
/* Root Complex Node */
@@ -479,9 +484,14 @@ build_iort(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
idmap->output_reference = cpu_to_le32(smmu_offset);
} else {
/* output IORT node is the ITS group node (the first node) */
- idmap->output_reference = cpu_to_le32(iort->node_offset);
+ idmap->output_reference = cpu_to_le32(iort_node_offset);
}
+ /*
+ * Update the pointer address in case table_data->data moves during above
+ * acpi_data_push operations.
+ */
+ iort = (AcpiIortTable *)(table_data->data + iort_start);
iort->length = cpu_to_le32(iort_length);
build_header(linker, table_data, (void *)(table_data->data + iort_start),
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (23 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc Peter Maydell
@ 2018-05-31 14:23 ` Peter Maydell
2018-05-31 15:32 ` [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-05-31 15:38 ` no-reply
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 14:23 UTC (permalink / raw)
To: qemu-devel
From: Shannon Zhao <zhaoshenglong@huawei.com>
kvm_irqchip_create called by kvm_init will call kvm_init_irq_routing to
initialize global capability variables. If we call kvm_init_irq_routing in
GIC realize function, previous allocated memory will leak.
Fix this by deleting the unnecessary call.
Signed-off-by: Shannon Zhao <zhaoshenglong@huawei.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Message-id: 1527750994-14360-1-git-send-email-zhaoshenglong@huawei.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic_kvm.c | 1 -
hw/intc/arm_gicv3_kvm.c | 1 -
2 files changed, 2 deletions(-)
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 6f467e68a8..204369d0e2 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -572,7 +572,6 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
if (kvm_has_gsi_routing()) {
/* set up irq routing */
- kvm_init_irq_routing(kvm_state);
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
}
diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c
index 3536795501..0279b86cd9 100644
--- a/hw/intc/arm_gicv3_kvm.c
+++ b/hw/intc/arm_gicv3_kvm.c
@@ -761,7 +761,6 @@ static void kvm_arm_gicv3_realize(DeviceState *dev, Error **errp)
if (kvm_has_gsi_routing()) {
/* set up irq routing */
- kvm_init_irq_routing(kvm_state);
for (i = 0; i < s->num_irq - GIC_INTERNAL; ++i) {
kvm_irqchip_add_irq_route(kvm_state, i, 0, i);
}
--
2.17.1
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PULL 00/25] target-arm queue
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (24 preceding siblings ...)
2018-05-31 14:23 ` [Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice Peter Maydell
@ 2018-05-31 15:32 ` Peter Maydell
2018-05-31 15:38 ` no-reply
26 siblings, 0 replies; 28+ messages in thread
From: Peter Maydell @ 2018-05-31 15:32 UTC (permalink / raw)
To: QEMU Developers
On 31 May 2018 at 15:23, Peter Maydell <peter.maydell@linaro.org> wrote:
> target-arm queue. This has the "plumb txattrs through various
> bits of exec.c" patches, and a collection of bug fixes from
> various people.
>
> thanks
> -- PMM
>
>
>
> The following changes since commit a3ac12fba028df90f7b3dbec924995c126c41022:
>
> Merge remote-tracking branch 'remotes/ehabkost/tags/numa-next-pull-request' into staging (2018-05-31 11:12:36 +0100)
>
> are available in the Git repository at:
>
> git://git.linaro.org/people/pmaydell/qemu-arm.git tags/pull-target-arm-20180531
>
> for you to fetch changes up to 49d1dca0520ea71bc21867fab6647f474fcf857b:
>
> KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice (2018-05-31 14:52:53 +0100)
>
Patch "Make address_space_translate{, _cached}() take a MemTxAttrs argument"
needs this squashed into it:
--- a/target/arm/kvm.c
+++ b/target/arm/kvm.c
@@ -664,7 +664,8 @@ int kvm_arch_fixup_msi_route(struct
kvm_irq_routing_entry *route,
/* MSI doorbell address is translated by an IOMMU */
rcu_read_lock();
- mr = address_space_translate(as, address, &xlat, &len, true);
+ mr = address_space_translate(as, address, &xlat, &len, true,
+ MEMTXATTRS_UNSPECIFIED);
if (!mr) {
goto unlock;
}
to avoid a compile failure on arm hosts.
-- PMM
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [Qemu-devel] [PULL 00/25] target-arm queue
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
` (25 preceding siblings ...)
2018-05-31 15:32 ` [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
@ 2018-05-31 15:38 ` no-reply
26 siblings, 0 replies; 28+ messages in thread
From: no-reply @ 2018-05-31 15:38 UTC (permalink / raw)
To: peter.maydell; +Cc: famz, qemu-devel
Hi,
This series seems to have some coding style problems. See output below for
more information:
Type: series
Message-id: 20180531142357.904-1-peter.maydell@linaro.org
Subject: [Qemu-devel] [PULL 00/25] target-arm queue
=== TEST SCRIPT BEGIN ===
#!/bin/bash
BASE=base
n=1
total=$(git log --oneline $BASE.. | wc -l)
failed=0
git config --local diff.renamelimit 0
git config --local diff.renames True
git config --local diff.algorithm histogram
commits="$(git log --format=%H --reverse $BASE..)"
for c in $commits; do
echo "Checking PATCH $n/$total: $(git log -n 1 --format=%s $c)..."
if ! git show $c --format=email | ./scripts/checkpatch.pl --mailback -; then
failed=1
echo
fi
n=$((n+1))
done
exit $failed
=== TEST SCRIPT END ===
Updating 3c8cf5a9c21ff8782164d1def7f44bd888713384
From https://github.com/patchew-project/qemu
fe817a8a0d..a3ac12fba0 master -> master
t [tag update] patchew/1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com -> patchew/1527736557-11084-1-git-send-email-zhaoshenglong@huawei.com
* [new tag] patchew/20180531142357.904-1-peter.maydell@linaro.org -> patchew/20180531142357.904-1-peter.maydell@linaro.org
Switched to a new branch 'test'
a487bba092 KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice
5a3bf5043e ARM: ACPI: Fix use-after-free due to memory realloc
676e28bdf5 vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY
d7aae0ee61 Make address_space_translate_iommu take a MemTxAttrs argument
12bb5f653d Make flatview_do_translate() take a MemTxAttrs argument
8a6e14496d Make address_space_get_iotlb_entry() take a MemTxAttrs argument
9cac582143 Make flatview_translate() take a MemTxAttrs argument
55db02aca6 Make flatview_access_valid() take a MemTxAttrs argument
f87f897086 Make MemoryRegion valid.accepts callback take a MemTxAttrs argument
9aa53aa0d4 Make memory_region_access_valid() take a MemTxAttrs argument
7b418bb6cf Make flatview_extend_translation() take a MemTxAttrs argument
377f13129d Make address_space_access_valid() take a MemTxAttrs argument
0649977ea0 Make address_space_map() take a MemTxAttrs argument
aa2f49abf1 Make address_space_translate{, _cached}() take a MemTxAttrs argument
105bf37846 Make tb_invalidate_phys_addr() take a MemTxAttrs argument
73b69cf0cd memory.h: Improve IOMMU related documentation
0031fdaa47 Correct CPACR reset value for v7 cores
0926c82acb xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors
48374ca065 arm: fix malloc type mismatch
427a2da078 arm: fix qemu crash on startup with -bios option
fe5e7fe927 tcg: Fix helper function vs host abi for float16
726e508937 arm_gicv3_kvm: increase clroffset accordingly
b6fb16391d hw/intc/arm_gicv3: Fix APxR<n> register dispatching
420d87bf34 MAINTAINERS: Add entries for newer MPS2 boards and devices
101898757f target/arm: Honour FPCR.FZ in FRECPX
=== OUTPUT BEGIN ===
Checking PATCH 1/25: target/arm: Honour FPCR.FZ in FRECPX...
Checking PATCH 2/25: MAINTAINERS: Add entries for newer MPS2 boards and devices...
Checking PATCH 3/25: hw/intc/arm_gicv3: Fix APxR<n> register dispatching...
Checking PATCH 4/25: arm_gicv3_kvm: increase clroffset accordingly...
Checking PATCH 5/25: tcg: Fix helper function vs host abi for float16...
ERROR: space prohibited before that close parenthesis ')'
#242: FILE: target/arm/helper.c:11367:
+ CONV_FTOI(vfp_to##name##p, ftype, fsz, sign, ) \
ERROR: space prohibited before that close parenthesis ')'
#251: FILE: target/arm/helper.c:11370:
+FLOAT_CONVS(si, h, uint32_t, 16, )
ERROR: space prohibited before that close parenthesis ')'
#252: FILE: target/arm/helper.c:11371:
+FLOAT_CONVS(si, s, float32, 32, )
ERROR: space prohibited before that close parenthesis ')'
#253: FILE: target/arm/helper.c:11372:
+FLOAT_CONVS(si, d, float64, 64, )
total: 4 errors, 0 warnings, 312 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 6/25: arm: fix qemu crash on startup with -bios option...
Checking PATCH 7/25: arm: fix malloc type mismatch...
Checking PATCH 8/25: xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors...
Checking PATCH 9/25: Correct CPACR reset value for v7 cores...
Checking PATCH 10/25: memory.h: Improve IOMMU related documentation...
Checking PATCH 11/25: Make tb_invalidate_phys_addr() take a MemTxAttrs argument...
Checking PATCH 12/25: Make address_space_translate{, _cached}() take a MemTxAttrs argument...
Checking PATCH 13/25: Make address_space_map() take a MemTxAttrs argument...
Checking PATCH 14/25: Make address_space_access_valid() take a MemTxAttrs argument...
Checking PATCH 15/25: Make flatview_extend_translation() take a MemTxAttrs argument...
Checking PATCH 16/25: Make memory_region_access_valid() take a MemTxAttrs argument...
Checking PATCH 17/25: Make MemoryRegion valid.accepts callback take a MemTxAttrs argument...
Checking PATCH 18/25: Make flatview_access_valid() take a MemTxAttrs argument...
Checking PATCH 19/25: Make flatview_translate() take a MemTxAttrs argument...
Checking PATCH 20/25: Make address_space_get_iotlb_entry() take a MemTxAttrs argument...
Checking PATCH 21/25: Make flatview_do_translate() take a MemTxAttrs argument...
Checking PATCH 22/25: Make address_space_translate_iommu take a MemTxAttrs argument...
WARNING: line over 80 characters
#35: FILE: exec.c:492:
+ AddressSpace **target_as,
total: 0 errors, 1 warnings, 32 lines checked
Your patch has style problems, please review. If any of these errors
are false positives report them to the maintainer, see
CHECKPATCH in MAINTAINERS.
Checking PATCH 23/25: vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY...
Checking PATCH 24/25: ARM: ACPI: Fix use-after-free due to memory realloc...
Checking PATCH 25/25: KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice...
=== OUTPUT END ===
Test command exited with code: 1
---
Email generated automatically by Patchew [http://patchew.org/].
Please send your feedback to patchew-devel@redhat.com
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2018-05-31 15:39 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-05-31 14:23 [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 01/25] target/arm: Honour FPCR.FZ in FRECPX Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 05/25] tcg: Fix helper function vs host abi for float16 Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 13/25] Make address_space_map() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 14/25] Make address_space_access_valid() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 15/25] Make flatview_extend_translation() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 16/25] Make memory_region_access_valid() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 17/25] Make MemoryRegion valid.accepts callback " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 18/25] Make flatview_access_valid() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 19/25] Make flatview_translate() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 21/25] Make flatview_do_translate() " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 22/25] Make address_space_translate_iommu " Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 23/25] vmstate.h: Provide VMSTATE_BOOL_SUB_ARRAY Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 24/25] ARM: ACPI: Fix use-after-free due to memory realloc Peter Maydell
2018-05-31 14:23 ` [Qemu-devel] [PULL 25/25] KVM: GIC: Fix memory leak due to calling kvm_init_irq_routing twice Peter Maydell
2018-05-31 15:32 ` [Qemu-devel] [PULL 00/25] target-arm queue Peter Maydell
2018-05-31 15:38 ` no-reply
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