* [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9
@ 2018-06-04 17:20 Cédric Le Goater
2018-06-04 23:10 ` David Gibson
0 siblings, 1 reply; 4+ messages in thread
From: Cédric Le Goater @ 2018-06-04 17:20 UTC (permalink / raw)
To: qemu-ppc
Cc: qemu-devel, David Gibson, Michael Ellerman, Cédric Le Goater
POWER9 introduced a new variant of the eieio instruction using bit 6
as a hint to tell the CPU it is a store-forwarding barrier.
The usage of this eieio extension was recently added in Linux 4.17
which activated the "support for a store forwarding barrier at kernel
entry/exit".
This loosen the QEMU eieio instruction mask to boot newer kernel but I
think we should be adding a new *eieio* instruction specific to POWER9
instead. I just don't know how to define an instruction variant with
the same op code for an ISA version. Any idea ?
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
target/ppc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Index: qemu-powernv-2.13.git/target/ppc/translate.c
===================================================================
--- qemu-powernv-2.13.git.orig/target/ppc/translate.c
+++ qemu-powernv-2.13.git/target/ppc/translate.c
@@ -6496,7 +6496,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
-GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
+GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9
2018-06-04 17:20 [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9 Cédric Le Goater
@ 2018-06-04 23:10 ` David Gibson
2018-06-05 8:14 ` Cédric Le Goater
0 siblings, 1 reply; 4+ messages in thread
From: David Gibson @ 2018-06-04 23:10 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Michael Ellerman
[-- Attachment #1: Type: text/plain, Size: 2198 bytes --]
On Mon, Jun 04, 2018 at 07:20:39PM +0200, Cédric Le Goater wrote:
> POWER9 introduced a new variant of the eieio instruction using bit 6
> as a hint to tell the CPU it is a store-forwarding barrier.
>
> The usage of this eieio extension was recently added in Linux 4.17
> which activated the "support for a store forwarding barrier at kernel
> entry/exit".
>
> This loosen the QEMU eieio instruction mask to boot newer kernel but I
> think we should be adding a new *eieio* instruction specific to POWER9
> instead. I just don't know how to define an instruction variant with
> the same op code for an ISA version. Any idea ?
I think you're right that this should be done slightly differently.
I think you can do that by adding a new instruction mask bit; say
PPC2_MEM_EIEIO2 or whatever. You leave the existing GEN_HANDLER as
is, add another GEN_HANDLER_E with the new mask dependent on the new
bit, then make sure POWER9 has the new bit set, but not the old one.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>
> target/ppc/translate.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> Index: qemu-powernv-2.13.git/target/ppc/translate.c
> ===================================================================
> --- qemu-powernv-2.13.git.orig/target/ppc/translate.c
> +++ qemu-powernv-2.13.git/target/ppc/translate.c
> @@ -6496,7 +6496,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00
> GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
> -GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
> +GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
> GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
>
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9
2018-06-04 23:10 ` David Gibson
@ 2018-06-05 8:14 ` Cédric Le Goater
2018-06-05 23:51 ` David Gibson
0 siblings, 1 reply; 4+ messages in thread
From: Cédric Le Goater @ 2018-06-05 8:14 UTC (permalink / raw)
To: David Gibson; +Cc: qemu-ppc, qemu-devel, Michael Ellerman
On 06/05/2018 01:10 AM, David Gibson wrote:
> On Mon, Jun 04, 2018 at 07:20:39PM +0200, Cédric Le Goater wrote:
>> POWER9 introduced a new variant of the eieio instruction using bit 6
>> as a hint to tell the CPU it is a store-forwarding barrier.
>>
>> The usage of this eieio extension was recently added in Linux 4.17
>> which activated the "support for a store forwarding barrier at kernel
>> entry/exit".
>>
>> This loosen the QEMU eieio instruction mask to boot newer kernel but I
>> think we should be adding a new *eieio* instruction specific to POWER9
>> instead. I just don't know how to define an instruction variant with
>> the same op code for an ISA version. Any idea ?
>
> I think you're right that this should be done slightly differently.
> I think you can do that by adding a new instruction mask bit; say
> PPC2_MEM_EIEIO2 or whatever. You leave the existing GEN_HANDLER as
> is, add another GEN_HANDLER_E with the new mask dependent on the new
> bit, then make sure POWER9 has the new bit set, but not the old one.
Unfortunately this doesn't work :/ QEMU considers the opcode is already
defined. May be we could test bit6 in gen_eieio ?
C.
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9
2018-06-05 8:14 ` Cédric Le Goater
@ 2018-06-05 23:51 ` David Gibson
0 siblings, 0 replies; 4+ messages in thread
From: David Gibson @ 2018-06-05 23:51 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Michael Ellerman
[-- Attachment #1: Type: text/plain, Size: 1521 bytes --]
On Tue, Jun 05, 2018 at 10:14:13AM +0200, Cédric Le Goater wrote:
> On 06/05/2018 01:10 AM, David Gibson wrote:
> > On Mon, Jun 04, 2018 at 07:20:39PM +0200, Cédric Le Goater wrote:
> >> POWER9 introduced a new variant of the eieio instruction using bit 6
> >> as a hint to tell the CPU it is a store-forwarding barrier.
> >>
> >> The usage of this eieio extension was recently added in Linux 4.17
> >> which activated the "support for a store forwarding barrier at kernel
> >> entry/exit".
> >>
> >> This loosen the QEMU eieio instruction mask to boot newer kernel but I
> >> think we should be adding a new *eieio* instruction specific to POWER9
> >> instead. I just don't know how to define an instruction variant with
> >> the same op code for an ISA version. Any idea ?
> >
> > I think you're right that this should be done slightly differently.
> > I think you can do that by adding a new instruction mask bit; say
> > PPC2_MEM_EIEIO2 or whatever. You leave the existing GEN_HANDLER as
> > is, add another GEN_HANDLER_E with the new mask dependent on the new
> > bit, then make sure POWER9 has the new bit set, but not the old one.
>
> Unfortunately this doesn't work :/ QEMU considers the opcode is already
> defined. May be we could test bit6 in gen_eieio ?
Yeah, I guess we'll have to.
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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^ permalink raw reply [flat|nested] 4+ messages in thread
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2018-06-04 17:20 [Qemu-devel] [RFC PATCH] target/ppc: extend eieio for POWER9 Cédric Le Goater
2018-06-04 23:10 ` David Gibson
2018-06-05 8:14 ` Cédric Le Goater
2018-06-05 23:51 ` David Gibson
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