* [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
@ 2018-06-04 21:40 Michel Thierry
2018-06-04 21:40 ` [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift Michel Thierry
` (3 more replies)
0 siblings, 4 replies; 7+ messages in thread
From: Michel Thierry @ 2018-06-04 21:40 UTC (permalink / raw)
To: intel-gfx
The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
context hw id in GEN8-10, so use them and have one less thing to
maintain in the unlikely case we change the descriptor sw fields.
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_perf.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index a6c8d61add0c..36b6d64d6018 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1279,7 +1279,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
i915->perf.oa.specific_ctx_id_mask =
(1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
} else {
- i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
+ i915->perf.oa.specific_ctx_id =
+ upper_32_bits(ce->lrc_desc);
i915->perf.oa.specific_ctx_id_mask =
(1U << GEN8_CTX_ID_WIDTH) - 1;
}
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift
2018-06-04 21:40 [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Michel Thierry
@ 2018-06-04 21:40 ` Michel Thierry
2018-06-04 22:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 7+ messages in thread
From: Michel Thierry @ 2018-06-04 21:40 UTC (permalink / raw)
To: intel-gfx
Use the correct engine class shift value while storing the ctx hw id.
Fixes the copy+paste error from commit 61d5676b5561 ("drm/i915/perf: fix
ctx_id read with GuC & ICL").
Apologies for not spotting this in the original review, the
specific_ctx_id_mask is correct, only the specific_ctx_id had this
problem.
v2: Just use the upper 32 bits of lrc_desc (Chris)
Fixes: 61d5676b5561 ("drm/i915/perf: fix ctx_id read with GuC & ICL")
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_perf.c | 7 +------
1 file changed, 1 insertion(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
index 36b6d64d6018..d049fde46dec 100644
--- a/drivers/gpu/drm/i915/i915_perf.c
+++ b/drivers/gpu/drm/i915/i915_perf.c
@@ -1287,12 +1287,7 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
break;
case 11: {
- struct intel_engine_cs *engine = i915->engine[RCS];
-
- i915->perf.oa.specific_ctx_id =
- stream->ctx->hw_id << (GEN11_SW_CTX_ID_SHIFT - 32) |
- engine->instance << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
- engine->class << (GEN11_ENGINE_INSTANCE_SHIFT - 32);
+ i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc);
i915->perf.oa.specific_ctx_id_mask =
((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32) |
((1U << GEN11_ENGINE_INSTANCE_WIDTH) - 1) << (GEN11_ENGINE_INSTANCE_SHIFT - 32) |
--
2.17.1
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^ permalink raw reply related [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
2018-06-04 21:40 [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Michel Thierry
2018-06-04 21:40 ` [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift Michel Thierry
@ 2018-06-04 22:05 ` Patchwork
2018-06-04 23:11 ` [PATCH 1/2] " Lionel Landwerlin
2018-06-05 0:30 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-06-04 22:05 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
URL : https://patchwork.freedesktop.org/series/44230/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4277 -> Patchwork_9189 =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9189 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9189, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/44230/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9189:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_gttfill@basic:
fi-pnv-d510: SKIP -> PASS
== Known issues ==
Here are the changes found in Patchwork_9189 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_busy@basic-hang-default:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719)
igt@kms_flip@basic-flip-vs-modeset:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097)
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-j4005: PASS -> FAIL (fdo#103928)
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
== Participating hosts (42 -> 37) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4277 -> Patchwork_9189
CI_DRM_4277: 2309ca0c3ab113e1e760045e230576e0ab4a88e2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4505: 8a8f0271a71e2e0d2a2caa4d41f4ad1d9c89670e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9189: 2f234df4f9fd147df56175ba9a942b7b6e09260d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
2f234df4f9fd drm/i915/perf: fix gen11 engine class shift
10b03b88aff9 drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9189/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
2018-06-04 21:40 [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Michel Thierry
2018-06-04 21:40 ` [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift Michel Thierry
2018-06-04 22:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Patchwork
@ 2018-06-04 23:11 ` Lionel Landwerlin
2018-06-04 23:18 ` Michel Thierry
2018-06-05 0:30 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
3 siblings, 1 reply; 7+ messages in thread
From: Lionel Landwerlin @ 2018-06-04 23:11 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
On 04/06/18 22:40, Michel Thierry wrote:
> The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
> context hw id in GEN8-10, so use them and have one less thing to
> maintain in the unlikely case we change the descriptor sw fields.
>
> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_perf.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c
> index a6c8d61add0c..36b6d64d6018 100644
> --- a/drivers/gpu/drm/i915/i915_perf.c
> +++ b/drivers/gpu/drm/i915/i915_perf.c
> @@ -1279,7 +1279,8 @@ static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
> i915->perf.oa.specific_ctx_id_mask =
> (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
> } else {
> - i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
> + i915->perf.oa.specific_ctx_id =
> + upper_32_bits(ce->lrc_desc);
> i915->perf.oa.specific_ctx_id_mask =
> (1U << GEN8_CTX_ID_WIDTH) - 1;
> }
I would do this :
i915->perf.oa.specific_ctx_id_mask = (1U << GEN8_CTX_ID_WIDTH) - 1;
i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc) &
i915->perf.oa.specific_ctx_id_mask;
Same for Gen11.
I'm concerned otherwise we might get incorrect comparison in the
gen8_append_oa_reports on the "reserved" bits.
Thanks,
-
Lionel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
2018-06-04 23:11 ` [PATCH 1/2] " Lionel Landwerlin
@ 2018-06-04 23:18 ` Michel Thierry
2018-06-04 23:54 ` Lionel Landwerlin
0 siblings, 1 reply; 7+ messages in thread
From: Michel Thierry @ 2018-06-04 23:18 UTC (permalink / raw)
To: Lionel Landwerlin, intel-gfx
On 6/4/2018 4:11 PM, Lionel Landwerlin wrote:
> On 04/06/18 22:40, Michel Thierry wrote:
>> The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
>> context hw id in GEN8-10, so use them and have one less thing to
>> maintain in the unlikely case we change the descriptor sw fields.
>>
>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> ---
>> drivers/gpu/drm/i915/i915_perf.c | 3 ++-
>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>> b/drivers/gpu/drm/i915/i915_perf.c
>> index a6c8d61add0c..36b6d64d6018 100644
>> --- a/drivers/gpu/drm/i915/i915_perf.c
>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>> @@ -1279,7 +1279,8 @@ static int oa_get_render_ctx_id(struct
>> i915_perf_stream *stream)
>> i915->perf.oa.specific_ctx_id_mask =
>> (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>> } else {
>> - i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
>> + i915->perf.oa.specific_ctx_id =
>> + upper_32_bits(ce->lrc_desc);
>> i915->perf.oa.specific_ctx_id_mask =
>> (1U << GEN8_CTX_ID_WIDTH) - 1;
>> }
>
> I would do this :
>
> i915->perf.oa.specific_ctx_id_mask = (1U << GEN8_CTX_ID_WIDTH) - 1;
> i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc) &
> i915->perf.oa.specific_ctx_id_mask;
>
> Same for Gen11.
> I'm concerned otherwise we might get incorrect comparison in the
> gen8_append_oa_reports on the "reserved" bits.
>
For some reason I thought specific_ctx_id_mask was already being applied
to this ctx_id... but no, you're right, otherwise the oa.specific_ctx_id
== ctx_id check in gen8_append_oa_reports may fail.
> Thanks,
>
> -
> Lionel
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
2018-06-04 23:18 ` Michel Thierry
@ 2018-06-04 23:54 ` Lionel Landwerlin
0 siblings, 0 replies; 7+ messages in thread
From: Lionel Landwerlin @ 2018-06-04 23:54 UTC (permalink / raw)
To: Michel Thierry, intel-gfx
On 05/06/18 00:18, Michel Thierry wrote:
> On 6/4/2018 4:11 PM, Lionel Landwerlin wrote:
>> On 04/06/18 22:40, Michel Thierry wrote:
>>> The upper 32 bits of the lrc_desc (bits 52-32 to be precise) are the
>>> context hw id in GEN8-10, so use them and have one less thing to
>>> maintain in the unlikely case we change the descriptor sw fields.
>>>
>>> Signed-off-by: Michel Thierry <michel.thierry@intel.com>
>>> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
>>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>>> ---
>>> drivers/gpu/drm/i915/i915_perf.c | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/i915_perf.c
>>> b/drivers/gpu/drm/i915/i915_perf.c
>>> index a6c8d61add0c..36b6d64d6018 100644
>>> --- a/drivers/gpu/drm/i915/i915_perf.c
>>> +++ b/drivers/gpu/drm/i915/i915_perf.c
>>> @@ -1279,7 +1279,8 @@ static int oa_get_render_ctx_id(struct
>>> i915_perf_stream *stream)
>>> i915->perf.oa.specific_ctx_id_mask =
>>> (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
>>> } else {
>>> - i915->perf.oa.specific_ctx_id = stream->ctx->hw_id;
>>> + i915->perf.oa.specific_ctx_id =
>>> + upper_32_bits(ce->lrc_desc);
>>> i915->perf.oa.specific_ctx_id_mask =
>>> (1U << GEN8_CTX_ID_WIDTH) - 1;
>>> }
>>
>> I would do this :
>>
>> i915->perf.oa.specific_ctx_id_mask = (1U << GEN8_CTX_ID_WIDTH) - 1;
>> i915->perf.oa.specific_ctx_id = upper_32_bits(ce->lrc_desc) &
>> i915->perf.oa.specific_ctx_id_mask;
>>
>> Same for Gen11.
>> I'm concerned otherwise we might get incorrect comparison in the
>> gen8_append_oa_reports on the "reserved" bits.
>>
>
> For some reason I thought specific_ctx_id_mask was already being
> applied to this ctx_id... but no, you're right, otherwise the
> oa.specific_ctx_id == ctx_id check in gen8_append_oa_reports may fail.
Yeah, only applied on the OA report side :(
>
>> Thanks,
>>
>> -
>> Lionel
>>
>
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
2018-06-04 21:40 [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Michel Thierry
` (2 preceding siblings ...)
2018-06-04 23:11 ` [PATCH 1/2] " Lionel Landwerlin
@ 2018-06-05 0:30 ` Patchwork
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-06-05 0:30 UTC (permalink / raw)
To: Michel Thierry; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10
URL : https://patchwork.freedesktop.org/series/44230/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4277_full -> Patchwork_9189_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9189_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9189_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/44230/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9189_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-bsd2:
shard-kbl: SKIP -> PASS
igt@gem_mocs_settings@mocs-rc6-render:
shard-kbl: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_9189_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
shard-kbl: PASS -> DMESG-FAIL (fdo#106560)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-hsw: PASS -> FAIL (fdo#102887, fdo#105363)
igt@kms_flip@plain-flip-ts-check:
shard-hsw: PASS -> FAIL (fdo#103928)
igt@kms_flip_tiling@flip-to-x-tiled:
shard-glk: PASS -> FAIL (fdo#104724, fdo#103822)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-pgflip-blt:
shard-glk: PASS -> FAIL (fdo#104724, fdo#103167)
igt@kms_vblank@pipe-a-wait-forked-busy-hang:
shard-glk: PASS -> DMESG-WARN (fdo#105763) +1
==== Possible fixes ====
igt@drv_selftest@live_gtt:
shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@gem_eio@hibernate:
shard-snb: INCOMPLETE (fdo#105411) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: FAIL (fdo#102887, fdo#105363) -> PASS
igt@kms_flip@plain-flip-fb-recreate-interruptible:
shard-glk: FAIL (fdo#100368) -> PASS +1
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4277 -> Patchwork_9189
CI_DRM_4277: 2309ca0c3ab113e1e760045e230576e0ab4a88e2 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4505: 8a8f0271a71e2e0d2a2caa4d41f4ad1d9c89670e @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9189: 2f234df4f9fd147df56175ba9a942b7b6e09260d @ git://anongit.freedesktop.org/gfx-ci/linux
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9189/shards.html
_______________________________________________
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^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2018-06-05 0:30 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-04 21:40 [PATCH 1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Michel Thierry
2018-06-04 21:40 ` [PATCH v2 2/2] drm/i915/perf: fix gen11 engine class shift Michel Thierry
2018-06-04 22:05 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/perf: use the lrc_desc to get the ctx hw id in gen8-10 Patchwork
2018-06-04 23:11 ` [PATCH 1/2] " Lionel Landwerlin
2018-06-04 23:18 ` Michel Thierry
2018-06-04 23:54 ` Lionel Landwerlin
2018-06-05 0:30 ` ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
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