* [PATCH i-g-t 1/2] scripts/trace.pl: Support class:instance engine tracepoints @ 2018-06-05 16:50 ` Tvrtko Ursulin 0 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-05 16:50 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> New way of describing engines needs the tool to be adapted to understand it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- scripts/trace.pl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/trace.pl b/scripts/trace.pl index 068eee68b30c..ea6c667696f4 100755 --- a/scripts/trace.pl +++ b/scripts/trace.pl @@ -378,6 +378,8 @@ while (<>) { $k = 'global' if $k eq 'global_seqno'; chop $v if substr($v, -1, 1) eq ','; $tp{$k} = $v; + + $tp{'ring'} = $tp{'engine'} if $k eq 'engine'; } next if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}}; @@ -631,7 +633,7 @@ foreach my $gid (sort keys %rings) { # Extract all GPU busy intervals and sort them. foreach my $key (@sorted_keys) { - next unless $db{$key}->{'ring'} == $ring; + next unless $db{$key}->{'ring'} eq $ring; push @s_, $db{$key}->{'start'}; push @e_, $db{$key}->{'end'}; die if $db{$key}->{'start'} > $db{$key}->{'end'}; -- 2.17.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH i-g-t 1/2] scripts/trace.pl: Support class:instance engine tracepoints @ 2018-06-05 16:50 ` Tvrtko Ursulin 0 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-05 16:50 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> New way of describing engines needs the tool to be adapted to understand it. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> --- scripts/trace.pl | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/trace.pl b/scripts/trace.pl index 068eee68b30c..ea6c667696f4 100755 --- a/scripts/trace.pl +++ b/scripts/trace.pl @@ -378,6 +378,8 @@ while (<>) { $k = 'global' if $k eq 'global_seqno'; chop $v if substr($v, -1, 1) eq ','; $tp{$k} = $v; + + $tp{'ring'} = $tp{'engine'} if $k eq 'engine'; } next if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}}; @@ -631,7 +633,7 @@ foreach my $gid (sort keys %rings) { # Extract all GPU busy intervals and sort them. foreach my $key (@sorted_keys) { - next unless $db{$key}->{'ring'} == $ring; + next unless $db{$key}->{'ring'} eq $ring; push @s_, $db{$key}->{'start'}; push @e_, $db{$key}->{'end'}; die if $db{$key}->{'start'} > $db{$key}->{'end'}; -- 2.17.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin @ 2018-06-05 16:50 ` Tvrtko Ursulin -1 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-05 16:50 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A miminal hack to parse the new tracepoint format and invent new "ring id's" based on engine class and instance. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> --- overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c index ea3480050ab9..e77125672088 100644 --- a/overlay/gpu-perf.c +++ b/overlay/gpu-perf.c @@ -85,7 +85,8 @@ struct tracepoint { int device_field; int ctx_field; - int ring_field; + int class_field; + int instance_field; int seqno_field; int global_seqno_field; int plane_field; @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) tp->device_field = f; } else if (!strcmp(tp->fields[f].name, "ctx")) { tp->ctx_field = f; - } else if (!strcmp(tp->fields[f].name, "ring")) { - tp->ring_field = f; + } else if (!strcmp(tp->fields[f].name, "class")) { + tp->class_field = f; + } else if (!strcmp(tp->fields[f].name, "instance")) { + tp->instance_field = f; } else if (!strcmp(tp->fields[f].name, "seqno")) { tp->seqno_field = f; } else if (!strcmp(tp->fields[f].name, "global_seqno")) { @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) tracepoints[tp_id].fields[ \ tracepoints[tp_id].field_name##_field].offset)) +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ + (*(const uint16_t *)((sample)->tracepoint_data + \ + tracepoints[tp_id].fields[ \ + tracepoints[tp_id].field_name##_field].offset)) + +#define GET_RING_ID(sample, tp_id) \ +({ \ + unsigned char class, instance, ring; \ +\ + class = READ_TP_FIELD_U16(sample, tp_id, class); \ + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ +\ + ring = class * 2 + instance; \ +\ + ring; \ +}) + static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, int (*func)(struct gpu_perf *, const void *)) { @@ -313,7 +333,7 @@ static int request_add(struct gpu_perf *gp, const void *event) if (comm == NULL) return 0; - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; return 1; } @@ -329,7 +349,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; return 1; } @@ -367,8 +387,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); wait->time = sample->time; - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; return 0; } @@ -377,7 +397,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; struct gpu_perf_time *wait, **prev; - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); -- 2.17.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-05 16:50 ` Tvrtko Ursulin 0 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-05 16:50 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A miminal hack to parse the new tracepoint format and invent new "ring id's" based on engine class and instance. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> --- overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c index ea3480050ab9..e77125672088 100644 --- a/overlay/gpu-perf.c +++ b/overlay/gpu-perf.c @@ -85,7 +85,8 @@ struct tracepoint { int device_field; int ctx_field; - int ring_field; + int class_field; + int instance_field; int seqno_field; int global_seqno_field; int plane_field; @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) tp->device_field = f; } else if (!strcmp(tp->fields[f].name, "ctx")) { tp->ctx_field = f; - } else if (!strcmp(tp->fields[f].name, "ring")) { - tp->ring_field = f; + } else if (!strcmp(tp->fields[f].name, "class")) { + tp->class_field = f; + } else if (!strcmp(tp->fields[f].name, "instance")) { + tp->instance_field = f; } else if (!strcmp(tp->fields[f].name, "seqno")) { tp->seqno_field = f; } else if (!strcmp(tp->fields[f].name, "global_seqno")) { @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) tracepoints[tp_id].fields[ \ tracepoints[tp_id].field_name##_field].offset)) +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ + (*(const uint16_t *)((sample)->tracepoint_data + \ + tracepoints[tp_id].fields[ \ + tracepoints[tp_id].field_name##_field].offset)) + +#define GET_RING_ID(sample, tp_id) \ +({ \ + unsigned char class, instance, ring; \ +\ + class = READ_TP_FIELD_U16(sample, tp_id, class); \ + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ +\ + ring = class * 2 + instance; \ +\ + ring; \ +}) + static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, int (*func)(struct gpu_perf *, const void *)) { @@ -313,7 +333,7 @@ static int request_add(struct gpu_perf *gp, const void *event) if (comm == NULL) return 0; - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; return 1; } @@ -329,7 +349,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; return 1; } @@ -367,8 +387,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); wait->time = sample->time; - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; return 0; } @@ -377,7 +397,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; struct gpu_perf_time *wait, **prev; - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); -- 2.17.0 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin @ 2018-06-05 17:14 ` Lionel Landwerlin -1 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-05 17:14 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx On 05/06/18 17:50, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A miminal hack to parse the new tracepoint format and invent new "ring > id's" based on engine class and instance. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 8 deletions(-) > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > index ea3480050ab9..e77125672088 100644 > --- a/overlay/gpu-perf.c > +++ b/overlay/gpu-perf.c > @@ -85,7 +85,8 @@ struct tracepoint { > > int device_field; > int ctx_field; > - int ring_field; > + int class_field; > + int instance_field; > int seqno_field; > int global_seqno_field; > int plane_field; > @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) > tp->device_field = f; > } else if (!strcmp(tp->fields[f].name, "ctx")) { > tp->ctx_field = f; > - } else if (!strcmp(tp->fields[f].name, "ring")) { > - tp->ring_field = f; > + } else if (!strcmp(tp->fields[f].name, "class")) { > + tp->class_field = f; > + } else if (!strcmp(tp->fields[f].name, "instance")) { > + tp->instance_field = f; That looks good to me. We only support the most recent kernel? > } else if (!strcmp(tp->fields[f].name, "seqno")) { > tp->seqno_field = f; > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) > tracepoints[tp_id].fields[ \ > tracepoints[tp_id].field_name##_field].offset)) > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > + (*(const uint16_t *)((sample)->tracepoint_data + \ > + tracepoints[tp_id].fields[ \ > + tracepoints[tp_id].field_name##_field].offset)) > + > +#define GET_RING_ID(sample, tp_id) \ > +({ \ > + unsigned char class, instance, ring; \ > +\ > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > +\ > + ring = class * 2 + instance; \ Do you want to make it clear that we cannot have more than 2 instances per class? > +\ > + ring; \ > +}) > + > static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, > int (*func)(struct gpu_perf *, const void *)) > { > @@ -313,7 +333,7 @@ static int request_add(struct gpu_perf *gp, const void *event) > if (comm == NULL) > return 0; > > - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; > + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; > return 1; > } > > @@ -329,7 +349,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > > - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; > + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; > return 1; > } > > @@ -367,8 +387,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) > wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); > wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); > wait->time = sample->time; > - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; > - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; > + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; > + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; > > return 0; > } > @@ -377,7 +397,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > struct gpu_perf_time *wait, **prev; > - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); > + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); > uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); > uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-05 17:14 ` Lionel Landwerlin 0 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-05 17:14 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx, Tvrtko Ursulin On 05/06/18 17:50, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A miminal hack to parse the new tracepoint format and invent new "ring > id's" based on engine class and instance. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- > 1 file changed, 28 insertions(+), 8 deletions(-) > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > index ea3480050ab9..e77125672088 100644 > --- a/overlay/gpu-perf.c > +++ b/overlay/gpu-perf.c > @@ -85,7 +85,8 @@ struct tracepoint { > > int device_field; > int ctx_field; > - int ring_field; > + int class_field; > + int instance_field; > int seqno_field; > int global_seqno_field; > int plane_field; > @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) > tp->device_field = f; > } else if (!strcmp(tp->fields[f].name, "ctx")) { > tp->ctx_field = f; > - } else if (!strcmp(tp->fields[f].name, "ring")) { > - tp->ring_field = f; > + } else if (!strcmp(tp->fields[f].name, "class")) { > + tp->class_field = f; > + } else if (!strcmp(tp->fields[f].name, "instance")) { > + tp->instance_field = f; That looks good to me. We only support the most recent kernel? > } else if (!strcmp(tp->fields[f].name, "seqno")) { > tp->seqno_field = f; > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) > tracepoints[tp_id].fields[ \ > tracepoints[tp_id].field_name##_field].offset)) > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > + (*(const uint16_t *)((sample)->tracepoint_data + \ > + tracepoints[tp_id].fields[ \ > + tracepoints[tp_id].field_name##_field].offset)) > + > +#define GET_RING_ID(sample, tp_id) \ > +({ \ > + unsigned char class, instance, ring; \ > +\ > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > +\ > + ring = class * 2 + instance; \ Do you want to make it clear that we cannot have more than 2 instances per class? > +\ > + ring; \ > +}) > + > static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, > int (*func)(struct gpu_perf *, const void *)) > { > @@ -313,7 +333,7 @@ static int request_add(struct gpu_perf *gp, const void *event) > if (comm == NULL) > return 0; > > - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; > + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; > return 1; > } > > @@ -329,7 +349,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > > - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; > + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; > return 1; > } > > @@ -367,8 +387,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) > wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); > wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); > wait->time = sample->time; > - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; > - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; > + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; > + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; > > return 0; > } > @@ -377,7 +397,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > struct gpu_perf_time *wait, **prev; > - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); > + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); > uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); > uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); > _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-05 17:14 ` [igt-dev] " Lionel Landwerlin @ 2018-06-05 19:40 ` Chris Wilson -1 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2018-06-05 19:40 UTC (permalink / raw) To: Lionel Landwerlin, Tvrtko Ursulin, igt-dev; +Cc: intel-gfx Quoting Lionel Landwerlin (2018-06-05 18:14:58) > On 05/06/18 17:50, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > A miminal hack to parse the new tracepoint format and invent new "ring > > id's" based on engine class and instance. > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > --- > > overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- > > 1 file changed, 28 insertions(+), 8 deletions(-) > > > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > > index ea3480050ab9..e77125672088 100644 > > --- a/overlay/gpu-perf.c > > +++ b/overlay/gpu-perf.c > > @@ -85,7 +85,8 @@ struct tracepoint { > > > > int device_field; > > int ctx_field; > > - int ring_field; > > + int class_field; > > + int instance_field; > > int seqno_field; > > int global_seqno_field; > > int plane_field; > > @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) > > tp->device_field = f; > > } else if (!strcmp(tp->fields[f].name, "ctx")) { > > tp->ctx_field = f; > > - } else if (!strcmp(tp->fields[f].name, "ring")) { > > - tp->ring_field = f; > > + } else if (!strcmp(tp->fields[f].name, "class")) { > > + tp->class_field = f; > > + } else if (!strcmp(tp->fields[f].name, "instance")) { > > + tp->instance_field = f; > > That looks good to me. We only support the most recent kernel? Yes. It's a devtool using a dev interface. It's sole purpose is for debugging the current kernel, or userspace in conjunction with drm-tip. It's a temporary hack... > > } else if (!strcmp(tp->fields[f].name, "seqno")) { > > tp->seqno_field = f; > > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > > @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) > > tracepoints[tp_id].fields[ \ > > tracepoints[tp_id].field_name##_field].offset)) > > > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > > + (*(const uint16_t *)((sample)->tracepoint_data + \ > > + tracepoints[tp_id].fields[ \ > > + tracepoints[tp_id].field_name##_field].offset)) > > + > > +#define GET_RING_ID(sample, tp_id) \ > > +({ \ > > + unsigned char class, instance, ring; \ > > +\ > > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > > +\ > > + ring = class * 2 + instance; \ > > Do you want to make it clear that we cannot have more than 2 instances > per class? Or make it easier to spot and expand in future. -Chris _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-05 19:40 ` Chris Wilson 0 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2018-06-05 19:40 UTC (permalink / raw) To: Lionel Landwerlin, Tvrtko Ursulin, igt-dev; +Cc: intel-gfx, Tvrtko Ursulin Quoting Lionel Landwerlin (2018-06-05 18:14:58) > On 05/06/18 17:50, Tvrtko Ursulin wrote: > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > > > A miminal hack to parse the new tracepoint format and invent new "ring > > id's" based on engine class and instance. > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > > --- > > overlay/gpu-perf.c | 36 ++++++++++++++++++++++++++++-------- > > 1 file changed, 28 insertions(+), 8 deletions(-) > > > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > > index ea3480050ab9..e77125672088 100644 > > --- a/overlay/gpu-perf.c > > +++ b/overlay/gpu-perf.c > > @@ -85,7 +85,8 @@ struct tracepoint { > > > > int device_field; > > int ctx_field; > > - int ring_field; > > + int class_field; > > + int instance_field; > > int seqno_field; > > int global_seqno_field; > > int plane_field; > > @@ -151,8 +152,10 @@ tracepoint_id(int tp_id) > > tp->device_field = f; > > } else if (!strcmp(tp->fields[f].name, "ctx")) { > > tp->ctx_field = f; > > - } else if (!strcmp(tp->fields[f].name, "ring")) { > > - tp->ring_field = f; > > + } else if (!strcmp(tp->fields[f].name, "class")) { > > + tp->class_field = f; > > + } else if (!strcmp(tp->fields[f].name, "instance")) { > > + tp->instance_field = f; > > That looks good to me. We only support the most recent kernel? Yes. It's a devtool using a dev interface. It's sole purpose is for debugging the current kernel, or userspace in conjunction with drm-tip. It's a temporary hack... > > } else if (!strcmp(tp->fields[f].name, "seqno")) { > > tp->seqno_field = f; > > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > > @@ -175,6 +178,23 @@ tracepoint_id(int tp_id) > > tracepoints[tp_id].fields[ \ > > tracepoints[tp_id].field_name##_field].offset)) > > > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > > + (*(const uint16_t *)((sample)->tracepoint_data + \ > > + tracepoints[tp_id].fields[ \ > > + tracepoints[tp_id].field_name##_field].offset)) > > + > > +#define GET_RING_ID(sample, tp_id) \ > > +({ \ > > + unsigned char class, instance, ring; \ > > +\ > > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > > +\ > > + ring = class * 2 + instance; \ > > Do you want to make it clear that we cannot have more than 2 instances > per class? Or make it easier to spot and expand in future. -Chris _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-05 19:40 ` Chris Wilson @ 2018-06-06 9:02 ` Tvrtko Ursulin -1 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-06 9:02 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A miminal hack to parse the new tracepoint format and invent new "ring id's" based on engine class and instance. v2: * Make it a bit more future proof. (Lionel, Chris) * Some assorted fixups to show forgotten engines. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> --- overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- overlay/overlay.c | 17 +++++++++-------- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c index ea3480050ab9..5629f826765e 100644 --- a/overlay/gpu-perf.c +++ b/overlay/gpu-perf.c @@ -33,6 +33,7 @@ #include <string.h> #include <fcntl.h> #include <errno.h> +#include <assert.h> #include "igt_perf.h" @@ -85,7 +86,8 @@ struct tracepoint { int device_field; int ctx_field; - int ring_field; + int class_field; + int instance_field; int seqno_field; int global_seqno_field; int plane_field; @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) tp->device_field = f; } else if (!strcmp(tp->fields[f].name, "ctx")) { tp->ctx_field = f; - } else if (!strcmp(tp->fields[f].name, "ring")) { - tp->ring_field = f; + } else if (!strcmp(tp->fields[f].name, "class")) { + tp->class_field = f; + } else if (!strcmp(tp->fields[f].name, "instance")) { + tp->instance_field = f; } else if (!strcmp(tp->fields[f].name, "seqno")) { tp->seqno_field = f; } else if (!strcmp(tp->fields[f].name, "global_seqno")) { @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) tracepoints[tp_id].fields[ \ tracepoints[tp_id].field_name##_field].offset)) +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ + (*(const uint16_t *)((sample)->tracepoint_data + \ + tracepoints[tp_id].fields[ \ + tracepoints[tp_id].field_name##_field].offset)) + +#define GET_RING_ID(sample, tp_id) \ +({ \ + unsigned char class, instance, ring; \ +\ + class = READ_TP_FIELD_U16(sample, tp_id, class); \ + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ +\ + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ + assert(instance <= 4); \ +\ + ring = class * 4 + instance; \ +\ + ring; \ +}) + static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, int (*func)(struct gpu_perf *, const void *)) { @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const void *event) if (comm == NULL) return 0; - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; return 1; } @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; return 1; } @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); wait->time = sample->time; - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; return 0; } @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; struct gpu_perf_time *wait, **prev; - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); diff --git a/overlay/overlay.c b/overlay/overlay.c index 545af7bcb2f5..eae5ddfa8823 100644 --- a/overlay/overlay.c +++ b/overlay/overlay.c @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, { 0.25, 1, 0.25, 1 }, { 0.25, 0.25, 1, 1 }, { 1, 1, 1, 1 }, + { 1, 1, 0.25, 1 }, }; int n; @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * { 1, 1, 1, 1 }, }; struct gpu_perf_comm *comm, **prev; - const char *ring_name[] = { - "R", - "B", - "V0", - "V1", + const char *ring_name[MAX_RINGS] = { + "R", "?", "?", "?", + "B", "?", "?", "?", + "V0", "V1", "?", "?", + "VE0", "?", "?", "?", }; double range[2]; char buf[1024]; @@ -326,7 +327,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * gpu_perf_update(&gp->gpu_perf); - for (n = 0; n < 4; n++) { + for (n = 0; n < MAX_RINGS; n++) { if (gp->gpu_perf.ctx_switch[n]) has_ctx = n + 1; if (gp->gpu_perf.flip_complete[n]) @@ -389,7 +390,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * } total = 0; - for (n = 0; n < 3; n++) + for (n = 0; n < MAX_RINGS; n++) total += comm->nr_requests[n]; chart_add_sample(comm->user_data, total); } @@ -433,7 +434,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * goto skip_comm; len = sprintf(buf, "%s:", comm->name); - for (n = 0; n < sizeof(ring_name)/sizeof(ring_name[0]); n++) { + for (n = 0; n < MAX_RINGS; n++) { if (comm->nr_requests[n] == 0) continue; len += sprintf(buf + len, "%s %d%s", need_comma ? "," : "", comm->nr_requests[n], ring_name[n]); -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [Intel-gfx] [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-06 9:02 ` Tvrtko Ursulin 0 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-06 9:02 UTC (permalink / raw) To: igt-dev; +Cc: intel-gfx From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> A miminal hack to parse the new tracepoint format and invent new "ring id's" based on engine class and instance. v2: * Make it a bit more future proof. (Lionel, Chris) * Some assorted fixups to show forgotten engines. Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> --- overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- overlay/overlay.c | 17 +++++++++-------- 2 files changed, 41 insertions(+), 16 deletions(-) diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c index ea3480050ab9..5629f826765e 100644 --- a/overlay/gpu-perf.c +++ b/overlay/gpu-perf.c @@ -33,6 +33,7 @@ #include <string.h> #include <fcntl.h> #include <errno.h> +#include <assert.h> #include "igt_perf.h" @@ -85,7 +86,8 @@ struct tracepoint { int device_field; int ctx_field; - int ring_field; + int class_field; + int instance_field; int seqno_field; int global_seqno_field; int plane_field; @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) tp->device_field = f; } else if (!strcmp(tp->fields[f].name, "ctx")) { tp->ctx_field = f; - } else if (!strcmp(tp->fields[f].name, "ring")) { - tp->ring_field = f; + } else if (!strcmp(tp->fields[f].name, "class")) { + tp->class_field = f; + } else if (!strcmp(tp->fields[f].name, "instance")) { + tp->instance_field = f; } else if (!strcmp(tp->fields[f].name, "seqno")) { tp->seqno_field = f; } else if (!strcmp(tp->fields[f].name, "global_seqno")) { @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) tracepoints[tp_id].fields[ \ tracepoints[tp_id].field_name##_field].offset)) +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ + (*(const uint16_t *)((sample)->tracepoint_data + \ + tracepoints[tp_id].fields[ \ + tracepoints[tp_id].field_name##_field].offset)) + +#define GET_RING_ID(sample, tp_id) \ +({ \ + unsigned char class, instance, ring; \ +\ + class = READ_TP_FIELD_U16(sample, tp_id, class); \ + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ +\ + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ + assert(instance <= 4); \ +\ + ring = class * 4 + instance; \ +\ + ring; \ +}) + static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, int (*func)(struct gpu_perf *, const void *)) { @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const void *event) if (comm == NULL) return 0; - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; return 1; } @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; return 1; } @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); wait->time = sample->time; - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; return 0; } @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) { const struct sample_event *sample = event; struct gpu_perf_time *wait, **prev; - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); diff --git a/overlay/overlay.c b/overlay/overlay.c index 545af7bcb2f5..eae5ddfa8823 100644 --- a/overlay/overlay.c +++ b/overlay/overlay.c @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, { 0.25, 1, 0.25, 1 }, { 0.25, 0.25, 1, 1 }, { 1, 1, 1, 1 }, + { 1, 1, 0.25, 1 }, }; int n; @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * { 1, 1, 1, 1 }, }; struct gpu_perf_comm *comm, **prev; - const char *ring_name[] = { - "R", - "B", - "V0", - "V1", + const char *ring_name[MAX_RINGS] = { + "R", "?", "?", "?", + "B", "?", "?", "?", + "V0", "V1", "?", "?", + "VE0", "?", "?", "?", }; double range[2]; char buf[1024]; @@ -326,7 +327,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * gpu_perf_update(&gp->gpu_perf); - for (n = 0; n < 4; n++) { + for (n = 0; n < MAX_RINGS; n++) { if (gp->gpu_perf.ctx_switch[n]) has_ctx = n + 1; if (gp->gpu_perf.flip_complete[n]) @@ -389,7 +390,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * } total = 0; - for (n = 0; n < 3; n++) + for (n = 0; n < MAX_RINGS; n++) total += comm->nr_requests[n]; chart_add_sample(comm->user_data, total); } @@ -433,7 +434,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * goto skip_comm; len = sprintf(buf, "%s:", comm->name); - for (n = 0; n < sizeof(ring_name)/sizeof(ring_name[0]); n++) { + for (n = 0; n < MAX_RINGS; n++) { if (comm->nr_requests[n] == 0) continue; len += sprintf(buf + len, "%s %d%s", need_comma ? "," : "", comm->nr_requests[n], ring_name[n]); -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-06 9:02 ` [Intel-gfx] " Tvrtko Ursulin @ 2018-06-06 10:29 ` Lionel Landwerlin -1 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-06 10:29 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx On 06/06/18 10:02, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A miminal hack to parse the new tracepoint format and invent new "ring > id's" based on engine class and instance. > > v2: > * Make it a bit more future proof. (Lionel, Chris) > * Some assorted fixups to show forgotten engines. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- > overlay/overlay.c | 17 +++++++++-------- > 2 files changed, 41 insertions(+), 16 deletions(-) > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > index ea3480050ab9..5629f826765e 100644 > --- a/overlay/gpu-perf.c > +++ b/overlay/gpu-perf.c > @@ -33,6 +33,7 @@ > #include <string.h> > #include <fcntl.h> > #include <errno.h> > +#include <assert.h> > > #include "igt_perf.h" > > @@ -85,7 +86,8 @@ struct tracepoint { > > int device_field; > int ctx_field; > - int ring_field; > + int class_field; > + int instance_field; > int seqno_field; > int global_seqno_field; > int plane_field; > @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) > tp->device_field = f; > } else if (!strcmp(tp->fields[f].name, "ctx")) { > tp->ctx_field = f; > - } else if (!strcmp(tp->fields[f].name, "ring")) { > - tp->ring_field = f; > + } else if (!strcmp(tp->fields[f].name, "class")) { > + tp->class_field = f; > + } else if (!strcmp(tp->fields[f].name, "instance")) { > + tp->instance_field = f; > } else if (!strcmp(tp->fields[f].name, "seqno")) { > tp->seqno_field = f; > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) > tracepoints[tp_id].fields[ \ > tracepoints[tp_id].field_name##_field].offset)) > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > + (*(const uint16_t *)((sample)->tracepoint_data + \ > + tracepoints[tp_id].fields[ \ > + tracepoints[tp_id].field_name##_field].offset)) > + > +#define GET_RING_ID(sample, tp_id) \ > +({ \ > + unsigned char class, instance, ring; \ > +\ > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > +\ > + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ > + assert(instance <= 4); \ > +\ > + ring = class * 4 + instance; \ > +\ > + ring; \ > +}) > + > static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, > int (*func)(struct gpu_perf *, const void *)) > { > @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const void *event) > if (comm == NULL) > return 0; > > - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; > + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; > return 1; > } > > @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > > - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; > + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; > return 1; > } > > @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) > wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); > wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); > wait->time = sample->time; > - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; > - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; > + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; > + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; > > return 0; > } > @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > struct gpu_perf_time *wait, **prev; > - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); > + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); > uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); > uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); > > diff --git a/overlay/overlay.c b/overlay/overlay.c > index 545af7bcb2f5..eae5ddfa8823 100644 > --- a/overlay/overlay.c > +++ b/overlay/overlay.c > @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, > { 0.25, 1, 0.25, 1 }, > { 0.25, 0.25, 1, 1 }, > { 1, 1, 1, 1 }, > + { 1, 1, 0.25, 1 }, > }; > int n; > > @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > { 1, 1, 1, 1 }, > }; > struct gpu_perf_comm *comm, **prev; > - const char *ring_name[] = { > - "R", > - "B", > - "V0", > - "V1", > + const char *ring_name[MAX_RINGS] = { > + "R", "?", "?", "?", > + "B", "?", "?", "?", > + "V0", "V1", "?", "?", > + "VE0", "?", "?", "?", > }; I guess if you defined a MAX_ENGINE_INSTANCES somewhere, you could just have an array of class names and then generate ring_name off the n variable further below. class = n / MAX_ENGINE_INSTANCES instance = n % MAX_ENGINE_INSTANCES snprintf(ring_name, sizeof(ring_name), "%s%i", class_names[class], instance); Just a suggestion, regardless : Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > double range[2]; > char buf[1024]; > @@ -326,7 +327,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > > gpu_perf_update(&gp->gpu_perf); > > - for (n = 0; n < 4; n++) { > + for (n = 0; n < MAX_RINGS; n++) { > if (gp->gpu_perf.ctx_switch[n]) > has_ctx = n + 1; > if (gp->gpu_perf.flip_complete[n]) > @@ -389,7 +390,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > } > > total = 0; > - for (n = 0; n < 3; n++) > + for (n = 0; n < MAX_RINGS; n++) > total += comm->nr_requests[n]; > chart_add_sample(comm->user_data, total); > } > @@ -433,7 +434,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > goto skip_comm; > > len = sprintf(buf, "%s:", comm->name); > - for (n = 0; n < sizeof(ring_name)/sizeof(ring_name[0]); n++) { > + for (n = 0; n < MAX_RINGS; n++) { > if (comm->nr_requests[n] == 0) > continue; > len += sprintf(buf + len, "%s %d%s", need_comma ? "," : "", comm->nr_requests[n], ring_name[n]); _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-06 10:29 ` Lionel Landwerlin 0 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-06 10:29 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx, Tvrtko Ursulin On 06/06/18 10:02, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > A miminal hack to parse the new tracepoint format and invent new "ring > id's" based on engine class and instance. > > v2: > * Make it a bit more future proof. (Lionel, Chris) > * Some assorted fixups to show forgotten engines. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > --- > overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- > overlay/overlay.c | 17 +++++++++-------- > 2 files changed, 41 insertions(+), 16 deletions(-) > > diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c > index ea3480050ab9..5629f826765e 100644 > --- a/overlay/gpu-perf.c > +++ b/overlay/gpu-perf.c > @@ -33,6 +33,7 @@ > #include <string.h> > #include <fcntl.h> > #include <errno.h> > +#include <assert.h> > > #include "igt_perf.h" > > @@ -85,7 +86,8 @@ struct tracepoint { > > int device_field; > int ctx_field; > - int ring_field; > + int class_field; > + int instance_field; > int seqno_field; > int global_seqno_field; > int plane_field; > @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) > tp->device_field = f; > } else if (!strcmp(tp->fields[f].name, "ctx")) { > tp->ctx_field = f; > - } else if (!strcmp(tp->fields[f].name, "ring")) { > - tp->ring_field = f; > + } else if (!strcmp(tp->fields[f].name, "class")) { > + tp->class_field = f; > + } else if (!strcmp(tp->fields[f].name, "instance")) { > + tp->instance_field = f; > } else if (!strcmp(tp->fields[f].name, "seqno")) { > tp->seqno_field = f; > } else if (!strcmp(tp->fields[f].name, "global_seqno")) { > @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) > tracepoints[tp_id].fields[ \ > tracepoints[tp_id].field_name##_field].offset)) > > +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ > + (*(const uint16_t *)((sample)->tracepoint_data + \ > + tracepoints[tp_id].fields[ \ > + tracepoints[tp_id].field_name##_field].offset)) > + > +#define GET_RING_ID(sample, tp_id) \ > +({ \ > + unsigned char class, instance, ring; \ > +\ > + class = READ_TP_FIELD_U16(sample, tp_id, class); \ > + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ > +\ > + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ > + assert(instance <= 4); \ > +\ > + ring = class * 4 + instance; \ > +\ > + ring; \ > +}) > + > static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, > int (*func)(struct gpu_perf *, const void *)) > { > @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const void *event) > if (comm == NULL) > return 0; > > - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, ring)]++; > + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; > return 1; > } > > @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > > - gp->ctx_switch[READ_TP_FIELD_U32(sample, TP_GEM_RING_SWITCH_CONTEXT, ring)]++; > + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; > return 1; > } > > @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const void *event) > wait->context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ctx); > wait->seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, seqno); > wait->time = sample->time; > - wait->next = gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)]; > - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, ring)] = wait; > + wait->next = gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)]; > + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; > > return 0; > } > @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const void *event) > { > const struct sample_event *sample = event; > struct gpu_perf_time *wait, **prev; > - uint32_t engine = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ring); > + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); > uint32_t context = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, ctx); > uint32_t seqno = READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_END, seqno); > > diff --git a/overlay/overlay.c b/overlay/overlay.c > index 545af7bcb2f5..eae5ddfa8823 100644 > --- a/overlay/overlay.c > +++ b/overlay/overlay.c > @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, > { 0.25, 1, 0.25, 1 }, > { 0.25, 0.25, 1, 1 }, > { 1, 1, 1, 1 }, > + { 1, 1, 0.25, 1 }, > }; > int n; > > @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > { 1, 1, 1, 1 }, > }; > struct gpu_perf_comm *comm, **prev; > - const char *ring_name[] = { > - "R", > - "B", > - "V0", > - "V1", > + const char *ring_name[MAX_RINGS] = { > + "R", "?", "?", "?", > + "B", "?", "?", "?", > + "V0", "V1", "?", "?", > + "VE0", "?", "?", "?", > }; I guess if you defined a MAX_ENGINE_INSTANCES somewhere, you could just have an array of class names and then generate ring_name off the n variable further below. class = n / MAX_ENGINE_INSTANCES instance = n % MAX_ENGINE_INSTANCES snprintf(ring_name, sizeof(ring_name), "%s%i", class_names[class], instance); Just a suggestion, regardless : Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> > double range[2]; > char buf[1024]; > @@ -326,7 +327,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > > gpu_perf_update(&gp->gpu_perf); > > - for (n = 0; n < 4; n++) { > + for (n = 0; n < MAX_RINGS; n++) { > if (gp->gpu_perf.ctx_switch[n]) > has_ctx = n + 1; > if (gp->gpu_perf.flip_complete[n]) > @@ -389,7 +390,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > } > > total = 0; > - for (n = 0; n < 3; n++) > + for (n = 0; n < MAX_RINGS; n++) > total += comm->nr_requests[n]; > chart_add_sample(comm->user_data, total); > } > @@ -433,7 +434,7 @@ static void show_gpu_perf(struct overlay_context *ctx, struct overlay_gpu_perf * > goto skip_comm; > > len = sprintf(buf, "%s:", comm->name); > - for (n = 0; n < sizeof(ring_name)/sizeof(ring_name[0]); n++) { > + for (n = 0; n < MAX_RINGS; n++) { > if (comm->nr_requests[n] == 0) > continue; > len += sprintf(buf + len, "%s %d%s", need_comma ? "," : "", comm->nr_requests[n], ring_name[n]); _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints 2018-06-06 10:29 ` [igt-dev] " Lionel Landwerlin @ 2018-06-06 11:01 ` Tvrtko Ursulin -1 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-06 11:01 UTC (permalink / raw) To: Lionel Landwerlin, Tvrtko Ursulin, igt-dev; +Cc: intel-gfx On 06/06/2018 11:29, Lionel Landwerlin wrote: > On 06/06/18 10:02, Tvrtko Ursulin wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> A miminal hack to parse the new tracepoint format and invent new "ring >> id's" based on engine class and instance. >> >> v2: >> * Make it a bit more future proof. (Lionel, Chris) >> * Some assorted fixups to show forgotten engines. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> >> --- >> overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- >> overlay/overlay.c | 17 +++++++++-------- >> 2 files changed, 41 insertions(+), 16 deletions(-) >> >> diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c >> index ea3480050ab9..5629f826765e 100644 >> --- a/overlay/gpu-perf.c >> +++ b/overlay/gpu-perf.c >> @@ -33,6 +33,7 @@ >> #include <string.h> >> #include <fcntl.h> >> #include <errno.h> >> +#include <assert.h> >> #include "igt_perf.h" >> @@ -85,7 +86,8 @@ struct tracepoint { >> int device_field; >> int ctx_field; >> - int ring_field; >> + int class_field; >> + int instance_field; >> int seqno_field; >> int global_seqno_field; >> int plane_field; >> @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) >> tp->device_field = f; >> } else if (!strcmp(tp->fields[f].name, "ctx")) { >> tp->ctx_field = f; >> - } else if (!strcmp(tp->fields[f].name, "ring")) { >> - tp->ring_field = f; >> + } else if (!strcmp(tp->fields[f].name, "class")) { >> + tp->class_field = f; >> + } else if (!strcmp(tp->fields[f].name, "instance")) { >> + tp->instance_field = f; >> } else if (!strcmp(tp->fields[f].name, "seqno")) { >> tp->seqno_field = f; >> } else if (!strcmp(tp->fields[f].name, "global_seqno")) { >> @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) >> tracepoints[tp_id].fields[ \ >> tracepoints[tp_id].field_name##_field].offset)) >> +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ >> + (*(const uint16_t *)((sample)->tracepoint_data + \ >> + tracepoints[tp_id].fields[ \ >> + tracepoints[tp_id].field_name##_field].offset)) >> + >> +#define GET_RING_ID(sample, tp_id) \ >> +({ \ >> + unsigned char class, instance, ring; \ >> +\ >> + class = READ_TP_FIELD_U16(sample, tp_id, class); \ >> + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ >> +\ >> + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ >> + assert(instance <= 4); \ >> +\ >> + ring = class * 4 + instance; \ >> +\ >> + ring; \ >> +}) >> + >> static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, >> int (*func)(struct gpu_perf *, const void *)) >> { >> @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const >> void *event) >> if (comm == NULL) >> return 0; >> - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, >> ring)]++; >> + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; >> return 1; >> } >> @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const >> void *event) >> { >> const struct sample_event *sample = event; >> - gp->ctx_switch[READ_TP_FIELD_U32(sample, >> TP_GEM_RING_SWITCH_CONTEXT, ring)]++; >> + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; >> return 1; >> } >> @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const >> void *event) >> wait->context = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, ctx); >> wait->seqno = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, seqno); >> wait->time = sample->time; >> - wait->next = gp->wait[READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, ring)]; >> - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, >> ring)] = wait; >> + wait->next = gp->wait[GET_RING_ID(sample, >> TP_GEM_REQUEST_WAIT_BEGIN)]; >> + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; >> return 0; >> } >> @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const >> void *event) >> { >> const struct sample_event *sample = event; >> struct gpu_perf_time *wait, **prev; >> - uint32_t engine = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, ring); >> + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); >> uint32_t context = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, ctx); >> uint32_t seqno = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, seqno); >> diff --git a/overlay/overlay.c b/overlay/overlay.c >> index 545af7bcb2f5..eae5ddfa8823 100644 >> --- a/overlay/overlay.c >> +++ b/overlay/overlay.c >> @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, >> { 0.25, 1, 0.25, 1 }, >> { 0.25, 0.25, 1, 1 }, >> { 1, 1, 1, 1 }, >> + { 1, 1, 0.25, 1 }, >> }; >> int n; >> @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context >> *ctx, struct overlay_gpu_perf * >> { 1, 1, 1, 1 }, >> }; >> struct gpu_perf_comm *comm, **prev; >> - const char *ring_name[] = { >> - "R", >> - "B", >> - "V0", >> - "V1", >> + const char *ring_name[MAX_RINGS] = { >> + "R", "?", "?", "?", >> + "B", "?", "?", "?", >> + "V0", "V1", "?", "?", >> + "VE0", "?", "?", "?", >> }; > > I guess if you defined a MAX_ENGINE_INSTANCES somewhere, you could just > have an array of class names and then generate ring_name off the n > variable further below. > > class = n / MAX_ENGINE_INSTANCES > instance = n % MAX_ENGINE_INSTANCES > > snprintf(ring_name, sizeof(ring_name), "%s%i", class_names[class], > instance); > > > Just a suggestion, regardless : > > Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Thanks! Above is a completely reasonable suggestion but I have pushed this for now just so the tool doesn't segfault for now. I suspect there are more issues lurking in there if it is to be made really future proof. Regards, Tvrtko _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [Intel-gfx] [PATCH i-g-t v2 2/2] intel_gpu_overlay: Update for class:instance engine tracepoints @ 2018-06-06 11:01 ` Tvrtko Ursulin 0 siblings, 0 replies; 20+ messages in thread From: Tvrtko Ursulin @ 2018-06-06 11:01 UTC (permalink / raw) To: Lionel Landwerlin, Tvrtko Ursulin, igt-dev; +Cc: intel-gfx On 06/06/2018 11:29, Lionel Landwerlin wrote: > On 06/06/18 10:02, Tvrtko Ursulin wrote: >> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> >> A miminal hack to parse the new tracepoint format and invent new "ring >> id's" based on engine class and instance. >> >> v2: >> * Make it a bit more future proof. (Lionel, Chris) >> * Some assorted fixups to show forgotten engines. >> >> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> >> Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> >> --- >> overlay/gpu-perf.c | 40 ++++++++++++++++++++++++++++++++-------- >> overlay/overlay.c | 17 +++++++++-------- >> 2 files changed, 41 insertions(+), 16 deletions(-) >> >> diff --git a/overlay/gpu-perf.c b/overlay/gpu-perf.c >> index ea3480050ab9..5629f826765e 100644 >> --- a/overlay/gpu-perf.c >> +++ b/overlay/gpu-perf.c >> @@ -33,6 +33,7 @@ >> #include <string.h> >> #include <fcntl.h> >> #include <errno.h> >> +#include <assert.h> >> #include "igt_perf.h" >> @@ -85,7 +86,8 @@ struct tracepoint { >> int device_field; >> int ctx_field; >> - int ring_field; >> + int class_field; >> + int instance_field; >> int seqno_field; >> int global_seqno_field; >> int plane_field; >> @@ -151,8 +153,10 @@ tracepoint_id(int tp_id) >> tp->device_field = f; >> } else if (!strcmp(tp->fields[f].name, "ctx")) { >> tp->ctx_field = f; >> - } else if (!strcmp(tp->fields[f].name, "ring")) { >> - tp->ring_field = f; >> + } else if (!strcmp(tp->fields[f].name, "class")) { >> + tp->class_field = f; >> + } else if (!strcmp(tp->fields[f].name, "instance")) { >> + tp->instance_field = f; >> } else if (!strcmp(tp->fields[f].name, "seqno")) { >> tp->seqno_field = f; >> } else if (!strcmp(tp->fields[f].name, "global_seqno")) { >> @@ -175,6 +179,26 @@ tracepoint_id(int tp_id) >> tracepoints[tp_id].fields[ \ >> tracepoints[tp_id].field_name##_field].offset)) >> +#define READ_TP_FIELD_U16(sample, tp_id, field_name) \ >> + (*(const uint16_t *)((sample)->tracepoint_data + \ >> + tracepoints[tp_id].fields[ \ >> + tracepoints[tp_id].field_name##_field].offset)) >> + >> +#define GET_RING_ID(sample, tp_id) \ >> +({ \ >> + unsigned char class, instance, ring; \ >> +\ >> + class = READ_TP_FIELD_U16(sample, tp_id, class); \ >> + instance = READ_TP_FIELD_U16(sample, tp_id, instance); \ >> +\ >> + assert(class <= I915_ENGINE_CLASS_VIDEO_ENHANCE); \ >> + assert(instance <= 4); \ >> +\ >> + ring = class * 4 + instance; \ >> +\ >> + ring; \ >> +}) >> + >> static int perf_tracepoint_open(struct gpu_perf *gp, int tp_id, >> int (*func)(struct gpu_perf *, const void *)) >> { >> @@ -313,7 +337,7 @@ static int request_add(struct gpu_perf *gp, const >> void *event) >> if (comm == NULL) >> return 0; >> - comm->nr_requests[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_ADD, >> ring)]++; >> + comm->nr_requests[GET_RING_ID(sample, TP_GEM_REQUEST_ADD)]++; >> return 1; >> } >> @@ -329,7 +353,7 @@ static int ctx_switch(struct gpu_perf *gp, const >> void *event) >> { >> const struct sample_event *sample = event; >> - gp->ctx_switch[READ_TP_FIELD_U32(sample, >> TP_GEM_RING_SWITCH_CONTEXT, ring)]++; >> + gp->ctx_switch[GET_RING_ID(sample, TP_GEM_RING_SWITCH_CONTEXT)]++; >> return 1; >> } >> @@ -367,8 +391,8 @@ static int wait_begin(struct gpu_perf *gp, const >> void *event) >> wait->context = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, ctx); >> wait->seqno = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, seqno); >> wait->time = sample->time; >> - wait->next = gp->wait[READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_BEGIN, ring)]; >> - gp->wait[READ_TP_FIELD_U32(sample, TP_GEM_REQUEST_WAIT_BEGIN, >> ring)] = wait; >> + wait->next = gp->wait[GET_RING_ID(sample, >> TP_GEM_REQUEST_WAIT_BEGIN)]; >> + gp->wait[GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_BEGIN)] = wait; >> return 0; >> } >> @@ -377,7 +401,7 @@ static int wait_end(struct gpu_perf *gp, const >> void *event) >> { >> const struct sample_event *sample = event; >> struct gpu_perf_time *wait, **prev; >> - uint32_t engine = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, ring); >> + uint32_t engine = GET_RING_ID(sample, TP_GEM_REQUEST_WAIT_END); >> uint32_t context = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, ctx); >> uint32_t seqno = READ_TP_FIELD_U32(sample, >> TP_GEM_REQUEST_WAIT_END, seqno); >> diff --git a/overlay/overlay.c b/overlay/overlay.c >> index 545af7bcb2f5..eae5ddfa8823 100644 >> --- a/overlay/overlay.c >> +++ b/overlay/overlay.c >> @@ -148,6 +148,7 @@ static void init_gpu_top(struct overlay_context *ctx, >> { 0.25, 1, 0.25, 1 }, >> { 0.25, 0.25, 1, 1 }, >> { 1, 1, 1, 1 }, >> + { 1, 1, 0.25, 1 }, >> }; >> int n; >> @@ -311,11 +312,11 @@ static void show_gpu_perf(struct overlay_context >> *ctx, struct overlay_gpu_perf * >> { 1, 1, 1, 1 }, >> }; >> struct gpu_perf_comm *comm, **prev; >> - const char *ring_name[] = { >> - "R", >> - "B", >> - "V0", >> - "V1", >> + const char *ring_name[MAX_RINGS] = { >> + "R", "?", "?", "?", >> + "B", "?", "?", "?", >> + "V0", "V1", "?", "?", >> + "VE0", "?", "?", "?", >> }; > > I guess if you defined a MAX_ENGINE_INSTANCES somewhere, you could just > have an array of class names and then generate ring_name off the n > variable further below. > > class = n / MAX_ENGINE_INSTANCES > instance = n % MAX_ENGINE_INSTANCES > > snprintf(ring_name, sizeof(ring_name), "%s%i", class_names[class], > instance); > > > Just a suggestion, regardless : > > Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Thanks! Above is a completely reasonable suggestion but I have pushed this for now just so the tool doesn't segfault for now. I suspect there are more issues lurking in there if it is to be made really future proof. Regards, Tvrtko _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] scripts/trace.pl: Support class:instance engine tracepoints 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin @ 2018-06-05 17:15 ` Lionel Landwerlin -1 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-05 17:15 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> On 05/06/18 17:50, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > New way of describing engines needs the tool to be adapted to understand it. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > scripts/trace.pl | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/scripts/trace.pl b/scripts/trace.pl > index 068eee68b30c..ea6c667696f4 100755 > --- a/scripts/trace.pl > +++ b/scripts/trace.pl > @@ -378,6 +378,8 @@ while (<>) { > $k = 'global' if $k eq 'global_seqno'; > chop $v if substr($v, -1, 1) eq ','; > $tp{$k} = $v; > + > + $tp{'ring'} = $tp{'engine'} if $k eq 'engine'; > } > > next if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}}; > @@ -631,7 +633,7 @@ foreach my $gid (sort keys %rings) { > > # Extract all GPU busy intervals and sort them. > foreach my $key (@sorted_keys) { > - next unless $db{$key}->{'ring'} == $ring; > + next unless $db{$key}->{'ring'} eq $ring; > push @s_, $db{$key}->{'start'}; > push @e_, $db{$key}->{'end'}; > die if $db{$key}->{'start'} > $db{$key}->{'end'}; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [igt-dev] [PATCH i-g-t 1/2] scripts/trace.pl: Support class:instance engine tracepoints @ 2018-06-05 17:15 ` Lionel Landwerlin 0 siblings, 0 replies; 20+ messages in thread From: Lionel Landwerlin @ 2018-06-05 17:15 UTC (permalink / raw) To: Tvrtko Ursulin, igt-dev; +Cc: intel-gfx, Tvrtko Ursulin Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> On 05/06/18 17:50, Tvrtko Ursulin wrote: > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > > New way of describing engines needs the tool to be adapted to understand it. > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com> > --- > scripts/trace.pl | 4 +++- > 1 file changed, 3 insertions(+), 1 deletion(-) > > diff --git a/scripts/trace.pl b/scripts/trace.pl > index 068eee68b30c..ea6c667696f4 100755 > --- a/scripts/trace.pl > +++ b/scripts/trace.pl > @@ -378,6 +378,8 @@ while (<>) { > $k = 'global' if $k eq 'global_seqno'; > chop $v if substr($v, -1, 1) eq ','; > $tp{$k} = $v; > + > + $tp{'ring'} = $tp{'engine'} if $k eq 'engine'; > } > > next if exists $tp{'ring'} and exists $ignore_ring{$tp{'ring'}}; > @@ -631,7 +633,7 @@ foreach my $gid (sort keys %rings) { > > # Extract all GPU busy intervals and sort them. > foreach my $key (@sorted_keys) { > - next unless $db{$key}->{'ring'} == $ring; > + next unless $db{$key}->{'ring'} eq $ring; > push @s_, $db{$key}->{'start'}; > push @e_, $db{$key}->{'end'}; > die if $db{$key}->{'start'} > $db{$key}->{'end'}; _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin ` (2 preceding siblings ...) (?) @ 2018-06-05 19:25 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-05 19:25 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints URL : https://patchwork.freedesktop.org/series/44295/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4280 -> IGTPW_1415 = == Summary - WARNING == Minor unknown changes coming with IGTPW_1415 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_1415, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44295/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in IGTPW_1415: === IGT changes === ==== Warnings ==== igt@gem_exec_gttfill@basic: fi-pnv-d510: SKIP -> PASS == Known issues == Here are the changes found in IGTPW_1415 that come from known issues: === IGT changes === ==== Issues hit ==== igt@gvt_basic@invalid-placeholder-test: fi-glk-j4005: SKIP -> INCOMPLETE (k.org#198133, fdo#103359) igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) ==== Possible fixes ==== igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: FAIL (fdo#103841) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (41 -> 37) == Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * IGT: IGT_4507 -> IGTPW_1415 CI_DRM_4280: 967aa2f22752af3adc629b50e7d2ed2b7e061e44 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1415: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1415/ IGT_4507: 938135f033d7fd79c04a7a042d40f9d074489ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1415/issues.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin ` (3 preceding siblings ...) (?) @ 2018-06-06 5:17 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-06 5:17 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints URL : https://patchwork.freedesktop.org/series/44295/ State : success == Summary == = CI Bug Log - changes from IGT_4507_full -> IGTPW_1415_full = == Summary - WARNING == Minor unknown changes coming with IGTPW_1415_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_1415_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44295/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in IGTPW_1415_full: === IGT changes === ==== Warnings ==== igt@gem_exec_schedule@deep-vebox: shard-kbl: PASS -> SKIP +2 igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in IGTPW_1415_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: PASS -> FAIL (fdo#105703) +1 igt@kms_cursor_legacy@2x-long-cursor-vs-flip-legacy: shard-hsw: PASS -> FAIL (fdo#105767) igt@kms_flip@2x-plain-flip-ts-check: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip@2x-plain-flip-ts-check-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-render: shard-glk: PASS -> FAIL (fdo#104724, fdo#103167) igt@kms_setmode@basic: shard-hsw: PASS -> FAIL (fdo#99912) igt@perf_pmu@other-read-4: shard-snb: PASS -> INCOMPLETE (fdo#105411) +1 igt@pm_rps@reset: shard-apl: PASS -> FAIL (fdo#102250) igt@testdisplay: shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359) ==== Possible fixes ==== igt@drv_selftest@live_gtt: shard-kbl: INCOMPLETE (fdo#103665) -> PASS shard-glk: INCOMPLETE (k.org#198133, fdo#103359) -> PASS igt@gem_eio@suspend: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@gem_softpin@noreloc-s3: shard-kbl: DMESG-WARN (fdo#103313) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#106509, fdo#105454) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: FAIL (fdo#102887) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#105189) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-shrfb-draw-mmap-wc: shard-glk: FAIL (fdo#104724, fdo#103167) -> PASS +1 igt@kms_rotation_crc@sprite-rotation-180: shard-snb: FAIL (fdo#103925, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102250 https://bugs.freedesktop.org/show_bug.cgi?id=102250 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#105767 https://bugs.freedesktop.org/show_bug.cgi?id=105767 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * IGT: IGT_4507 -> IGTPW_1415 * Linux: CI_DRM_4278 -> CI_DRM_4280 CI_DRM_4278: 6832f9f1d1d74ea696ae703d6ce9aa195be663f2 @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_4280: 967aa2f22752af3adc629b50e7d2ed2b7e061e44 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1415: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1415/ IGT_4507: 938135f033d7fd79c04a7a042d40f9d074489ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1415/shards.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints (rev2) 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin ` (4 preceding siblings ...) (?) @ 2018-06-06 9:37 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-06 9:37 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints (rev2) URL : https://patchwork.freedesktop.org/series/44295/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4280 -> IGTPW_1417 = == Summary - WARNING == Minor unknown changes coming with IGTPW_1417 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_1417, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44295/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in IGTPW_1417: === IGT changes === ==== Warnings ==== igt@gem_exec_gttfill@basic: fi-pnv-d510: SKIP -> PASS == Known issues == Here are the changes found in IGTPW_1417 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-no-display: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725) igt@gem_sync@basic-all: fi-cnl-y3: PASS -> INCOMPLETE (fdo#105086) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) ==== Possible fixes ==== igt@gem_mmap_gtt@basic-small-bo-tiledx: fi-gdg-551: FAIL (fdo#102575) -> PASS igt@kms_chamelium@dp-edid-read: fi-kbl-7500u: FAIL (fdo#103841) -> PASS igt@prime_vgem@basic-fence-flip: fi-ilk-650: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102575 https://bugs.freedesktop.org/show_bug.cgi?id=102575 fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 == Participating hosts (41 -> 37) == Missing (4): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-skl-6700hq == Build changes == * IGT: IGT_4507 -> IGTPW_1417 CI_DRM_4280: 967aa2f22752af3adc629b50e7d2ed2b7e061e44 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1417: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1417/ IGT_4507: 938135f033d7fd79c04a7a042d40f9d074489ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1417/issues.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints (rev2) 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin ` (5 preceding siblings ...) (?) @ 2018-06-06 10:30 ` Patchwork -1 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-06 10:30 UTC (permalink / raw) To: Tvrtko Ursulin; +Cc: igt-dev == Series Details == Series: series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints (rev2) URL : https://patchwork.freedesktop.org/series/44295/ State : success == Summary == = CI Bug Log - changes from IGT_4507_full -> IGTPW_1417_full = == Summary - WARNING == Minor unknown changes coming with IGTPW_1417_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in IGTPW_1417_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44295/revisions/2/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in IGTPW_1417_full: === IGT changes === ==== Warnings ==== igt@gem_mocs_settings@mocs-rc6-ctx-dirty-render: shard-kbl: SKIP -> PASS +1 == Known issues == Here are the changes found in IGTPW_1417_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_gtt: shard-apl: PASS -> INCOMPLETE (fdo#103927) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_cursor_legacy@cursor-vs-flip-legacy: shard-hsw: PASS -> FAIL (fdo#103355) igt@kms_flip@2x-flip-vs-expired-vblank: shard-hsw: PASS -> FAIL (fdo#105189) igt@kms_flip@dpms-vs-vblank-race: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip@flip-vs-absolute-wf_vblank-interruptible: shard-hsw: PASS -> FAIL (fdo#100368) igt@kms_flip@flip-vs-expired-vblank: shard-kbl: PASS -> FAIL (fdo#102887, fdo#105363) shard-glk: PASS -> FAIL (fdo#105189) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_setmode@basic: shard-apl: PASS -> FAIL (fdo#99912) shard-hsw: PASS -> FAIL (fdo#99912) igt@perf_pmu@multi-client-rcs0: shard-snb: PASS -> INCOMPLETE (fdo#105411) ==== Possible fixes ==== igt@drv_selftest@live_gtt: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@gem_eio@suspend: shard-snb: INCOMPLETE (fdo#105411) -> PASS igt@gem_ppgtt@blt-vs-render-ctxn: shard-kbl: INCOMPLETE (fdo#106023, fdo#103665) -> PASS igt@gem_softpin@noreloc-s3: shard-kbl: DMESG-WARN (fdo#103313) -> PASS igt@kms_flip@2x-dpms-vs-vblank-race: shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank: shard-glk: FAIL (fdo#102887) -> PASS igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#105189) -> PASS igt@kms_flip_tiling@flip-y-tiled: shard-glk: FAIL (fdo#104724) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-render: shard-glk: FAIL (fdo#104724, fdo#103167) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-snb: FAIL (fdo#103925, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105189 https://bugs.freedesktop.org/show_bug.cgi?id=105189 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * IGT: IGT_4507 -> IGTPW_1417 * Linux: CI_DRM_4278 -> CI_DRM_4280 CI_DRM_4278: 6832f9f1d1d74ea696ae703d6ce9aa195be663f2 @ git://anongit.freedesktop.org/gfx-ci/linux CI_DRM_4280: 967aa2f22752af3adc629b50e7d2ed2b7e061e44 @ git://anongit.freedesktop.org/gfx-ci/linux IGTPW_1417: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1417/ IGT_4507: 938135f033d7fd79c04a7a042d40f9d074489ffd @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1417/shards.html _______________________________________________ igt-dev mailing list igt-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/igt-dev ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2018-06-06 11:01 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-06-05 16:50 [PATCH i-g-t 1/2] scripts/trace.pl: Support class:instance engine tracepoints Tvrtko Ursulin 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin 2018-06-05 16:50 ` [PATCH i-g-t 2/2] intel_gpu_overlay: Update for " Tvrtko Ursulin 2018-06-05 16:50 ` [Intel-gfx] " Tvrtko Ursulin 2018-06-05 17:14 ` Lionel Landwerlin 2018-06-05 17:14 ` [igt-dev] " Lionel Landwerlin 2018-06-05 19:40 ` Chris Wilson 2018-06-05 19:40 ` Chris Wilson 2018-06-06 9:02 ` [PATCH i-g-t v2 " Tvrtko Ursulin 2018-06-06 9:02 ` [Intel-gfx] " Tvrtko Ursulin 2018-06-06 10:29 ` Lionel Landwerlin 2018-06-06 10:29 ` [igt-dev] " Lionel Landwerlin 2018-06-06 11:01 ` Tvrtko Ursulin 2018-06-06 11:01 ` [igt-dev] [Intel-gfx] " Tvrtko Ursulin 2018-06-05 17:15 ` [igt-dev] [PATCH i-g-t 1/2] scripts/trace.pl: Support " Lionel Landwerlin 2018-06-05 17:15 ` Lionel Landwerlin 2018-06-05 19:25 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] " Patchwork 2018-06-06 5:17 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork 2018-06-06 9:37 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,1/2] scripts/trace.pl: Support class:instance engine tracepoints (rev2) Patchwork 2018-06-06 10:30 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
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