* [Qemu-devel] [PATCH v2] target/ppc: extend eieio for POWER9
@ 2018-06-06 7:33 Cédric Le Goater
2018-06-08 3:06 ` David Gibson
0 siblings, 1 reply; 2+ messages in thread
From: Cédric Le Goater @ 2018-06-06 7:33 UTC (permalink / raw)
To: qemu-ppc
Cc: qemu-devel, David Gibson, Michael Ellerman, Cédric Le Goater
POWER9 introduced a new variant of the eieio instruction using bit 6
as a hint to tell the CPU it is a store-forwarding barrier.
The usage of this eieio extension was recently added in Linux 4.17
which activated the "support for a store forwarding barrier at kernel
entry/exit".
Unfortunately, it is not possible to insert this new eieio instruction
without considerable change in ppc_tr_translate_insn(). So instead we
loosen the QEMU eieio instruction mask and modify the gen_eieio()
helper to test for bit6. On non-POWER9 CPUs, the bit6 is just ignored
but a warning is emitted as this is not an instruction software should
be using.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
---
Changes since v1:
- removed specific PPC2_MEM_EIEIO2 flag
- ignore bit6 on non-POWER9 CPU
target/ppc/translate.c | 25 +++++++++++++++++++++++--
1 file changed, 23 insertions(+), 2 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 8ba8f67dc513..5fe1ba655599 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -2967,7 +2967,28 @@ static void gen_stswx(DisasContext *ctx)
/* eieio */
static void gen_eieio(DisasContext *ctx)
{
- tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
+ TCGBar bar = TCG_MO_LD_ST;
+
+ /*
+ * POWER9 has a eieio instruction variant using bit 6 as a hint to
+ * tell the CPU it is a store-forwarding barrier.
+ */
+ if (ctx->opcode & 0x2000000) {
+ /*
+ * ISA says that "Reserved fields in instructions are ignored
+ * by the processor". So ignore the bit 6 on non-POWER9 CPU but
+ * as this is not an instruction software should be using,
+ * complain to the user.
+ */
+ if (!(ctx->insns_flags2 & PPC2_ISA300)) {
+ qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
+ TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
+ } else {
+ bar = TCG_MO_ST_LD;
+ }
+ }
+
+ tcg_gen_mb(bar | TCG_BAR_SC);
}
#if !defined(CONFIG_USER_ONLY)
@@ -6483,7 +6504,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
-GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
+GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
--
2.13.6
^ permalink raw reply related [flat|nested] 2+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target/ppc: extend eieio for POWER9
2018-06-06 7:33 [Qemu-devel] [PATCH v2] target/ppc: extend eieio for POWER9 Cédric Le Goater
@ 2018-06-08 3:06 ` David Gibson
0 siblings, 0 replies; 2+ messages in thread
From: David Gibson @ 2018-06-08 3:06 UTC (permalink / raw)
To: Cédric Le Goater; +Cc: qemu-ppc, qemu-devel, Michael Ellerman
[-- Attachment #1: Type: text/plain, Size: 3152 bytes --]
On Wed, Jun 06, 2018 at 09:33:53AM +0200, Cédric Le Goater wrote:
> POWER9 introduced a new variant of the eieio instruction using bit 6
> as a hint to tell the CPU it is a store-forwarding barrier.
>
> The usage of this eieio extension was recently added in Linux 4.17
> which activated the "support for a store forwarding barrier at kernel
> entry/exit".
>
> Unfortunately, it is not possible to insert this new eieio instruction
> without considerable change in ppc_tr_translate_insn(). So instead we
> loosen the QEMU eieio instruction mask and modify the gen_eieio()
> helper to test for bit6. On non-POWER9 CPUs, the bit6 is just ignored
> but a warning is emitted as this is not an instruction software should
> be using.
>
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
Applied to ppc-for-3.0.
> ---
>
> Changes since v1:
>
> - removed specific PPC2_MEM_EIEIO2 flag
> - ignore bit6 on non-POWER9 CPU
>
> target/ppc/translate.c | 25 +++++++++++++++++++++++--
> 1 file changed, 23 insertions(+), 2 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 8ba8f67dc513..5fe1ba655599 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -2967,7 +2967,28 @@ static void gen_stswx(DisasContext *ctx)
> /* eieio */
> static void gen_eieio(DisasContext *ctx)
> {
> - tcg_gen_mb(TCG_MO_LD_ST | TCG_BAR_SC);
> + TCGBar bar = TCG_MO_LD_ST;
> +
> + /*
> + * POWER9 has a eieio instruction variant using bit 6 as a hint to
> + * tell the CPU it is a store-forwarding barrier.
> + */
> + if (ctx->opcode & 0x2000000) {
> + /*
> + * ISA says that "Reserved fields in instructions are ignored
> + * by the processor". So ignore the bit 6 on non-POWER9 CPU but
> + * as this is not an instruction software should be using,
> + * complain to the user.
> + */
> + if (!(ctx->insns_flags2 & PPC2_ISA300)) {
> + qemu_log_mask(LOG_GUEST_ERROR, "invalid eieio using bit 6 at @"
> + TARGET_FMT_lx "\n", ctx->base.pc_next - 4);
> + } else {
> + bar = TCG_MO_ST_LD;
> + }
> + }
> +
> + tcg_gen_mb(bar | TCG_BAR_SC);
> }
>
> #if !defined(CONFIG_USER_ONLY)
> @@ -6483,7 +6504,7 @@ GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
> GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
> -GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
> +GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x01FFF801, PPC_MEM_EIEIO),
> GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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