[PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h

[PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Mika Kuoppala]

Carve out chipset definitions into new intel_chipset.h

Cc: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.h      | 194 +------------------------
 drivers/gpu/drm/i915/intel_chipset.h | 202 +++++++++++++++++++++++++++
 2 files changed, 203 insertions(+), 193 deletions(-)
 create mode 100644 drivers/gpu/drm/i915/intel_chipset.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index c4073666f1ca..e659c89198d2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -58,6 +58,7 @@
 #include "i915_utils.h"
 
 #include "intel_bios.h"
+#include "intel_chipset.h"
 #include "intel_device_info.h"
 #include "intel_display.h"
 #include "intel_dpll_mgr.h"
@@ -2309,199 +2310,6 @@ intel_info(const struct drm_i915_private *dev_priv)
 
 #define INTEL_INFO(dev_priv)	intel_info((dev_priv))
 
-#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
-#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
-
-#define REVID_FOREVER		0xff
-#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
-
-#define GEN_FOREVER (0)
-
-#define INTEL_GEN_MASK(s, e) ( \
-	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
-	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
-	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
-		(s) != GEN_FOREVER ? (s) - 1 : 0) \
-)
-
-/*
- * Returns true if Gen is in inclusive range [Start, End].
- *
- * Use GEN_FOREVER for unbound start and or end.
- */
-#define IS_GEN(dev_priv, s, e) \
-	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
-
-/*
- * Return true if revision is in range [since,until] inclusive.
- *
- * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
- */
-#define IS_REVID(p, since, until) \
-	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
-
-#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
-
-#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
-#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
-#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
-#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
-#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
-#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
-#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
-#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
-#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
-#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
-#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
-#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
-#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
-#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
-#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
-#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
-#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
-#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
-#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
-				 (dev_priv)->info.gt == 1)
-#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
-#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
-#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
-#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
-#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
-#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
-#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
-#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
-#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
-#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
-#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
-#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
-#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
-				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
-#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
-/* ULX machines are also considered ULT. */
-#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
-#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
-#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
-#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
-/* ULX machines are also considered ULT. */
-#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
-				 INTEL_DEVID(dev_priv) == 0x0A1E)
-#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
-				 INTEL_DEVID(dev_priv) == 0x1913 || \
-				 INTEL_DEVID(dev_priv) == 0x1916 || \
-				 INTEL_DEVID(dev_priv) == 0x1921 || \
-				 INTEL_DEVID(dev_priv) == 0x1926)
-#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
-				 INTEL_DEVID(dev_priv) == 0x1915 || \
-				 INTEL_DEVID(dev_priv) == 0x191E)
-#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
-				 INTEL_DEVID(dev_priv) == 0x5913 || \
-				 INTEL_DEVID(dev_priv) == 0x5916 || \
-				 INTEL_DEVID(dev_priv) == 0x5921 || \
-				 INTEL_DEVID(dev_priv) == 0x5926)
-#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
-				 INTEL_DEVID(dev_priv) == 0x5915 || \
-				 INTEL_DEVID(dev_priv) == 0x591E)
-#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
-#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
-#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 4)
-#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
-#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
-#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
-#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 2)
-#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
-				 (dev_priv)->info.gt == 3)
-#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
-					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
-
-#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
-
-#define SKL_REVID_A0		0x0
-#define SKL_REVID_B0		0x1
-#define SKL_REVID_C0		0x2
-#define SKL_REVID_D0		0x3
-#define SKL_REVID_E0		0x4
-#define SKL_REVID_F0		0x5
-#define SKL_REVID_G0		0x6
-#define SKL_REVID_H0		0x7
-
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
-
-#define BXT_REVID_A0		0x0
-#define BXT_REVID_A1		0x1
-#define BXT_REVID_B0		0x3
-#define BXT_REVID_B_LAST	0x8
-#define BXT_REVID_C0		0x9
-
-#define IS_BXT_REVID(dev_priv, since, until) \
-	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
-
-#define KBL_REVID_A0		0x0
-#define KBL_REVID_B0		0x1
-#define KBL_REVID_C0		0x2
-#define KBL_REVID_D0		0x3
-#define KBL_REVID_E0		0x4
-
-#define IS_KBL_REVID(dev_priv, since, until) \
-	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
-
-#define GLK_REVID_A0		0x0
-#define GLK_REVID_A1		0x1
-
-#define IS_GLK_REVID(dev_priv, since, until) \
-	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
-
-#define CNL_REVID_A0		0x0
-#define CNL_REVID_B0		0x1
-#define CNL_REVID_C0		0x2
-
-#define IS_CNL_REVID(p, since, until) \
-	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
-
-#define ICL_REVID_A0		0x0
-#define ICL_REVID_A2		0x1
-#define ICL_REVID_B0		0x3
-#define ICL_REVID_B2		0x4
-#define ICL_REVID_C0		0x5
-
-#define IS_ICL_REVID(p, since, until) \
-	(IS_ICELAKE(p) && IS_REVID(p, since, until))
-
-/*
- * The genX designation typically refers to the render engine, so render
- * capability related checks should use IS_GEN, while display and other checks
- * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
- * chips, etc.).
- */
-#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
-#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
-#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
-#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
-#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
-#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
-#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
-#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
-#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
-#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
-
-#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
-#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
-#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
-
 #define ENGINE_MASK(id)	BIT(id)
 #define RENDER_RING	ENGINE_MASK(RCS)
 #define BSD_RING	ENGINE_MASK(VCS)
diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
new file mode 100644
index 000000000000..0e71571fb4c1
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -0,0 +1,202 @@
+/* SPDX-License-Identifier: MIT
+ *
+ * Copyright © 2018 Intel Corporation
+ */
+
+#ifndef _INTEL_CHIPSET_H_
+#define _INTEL_CHIPSET_H_
+
+#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
+#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
+
+#define REVID_FOREVER		0xff
+#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
+
+#define GEN_FOREVER (0)
+
+#define INTEL_GEN_MASK(s, e) ( \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
+	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
+		(s) != GEN_FOREVER ? (s) - 1 : 0) \
+)
+
+/*
+ * Returns true if Gen is in inclusive range [Start, End].
+ *
+ * Use GEN_FOREVER for unbound start and or end.
+ */
+#define IS_GEN(dev_priv, s, e) \
+	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
+
+/*
+ * Return true if revision is in range [since,until] inclusive.
+ *
+ * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
+ */
+#define IS_REVID(p, since, until) \
+	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
+
+#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & BIT(p))
+
+#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
+#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
+#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
+#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
+#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
+#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
+#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
+#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
+#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
+#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
+#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
+#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
+#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
+#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
+#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
+#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
+#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
+#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
+#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
+#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
+				 (dev_priv)->info.gt == 1)
+#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
+#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
+#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
+#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
+#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
+#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
+#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
+#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
+#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
+#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
+#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
+#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
+#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
+				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
+#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
+/* ULX machines are also considered ULT. */
+#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
+#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 (dev_priv)->info.gt == 3)
+#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
+#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
+				 (dev_priv)->info.gt == 3)
+/* ULX machines are also considered ULT. */
+#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
+				 INTEL_DEVID(dev_priv) == 0x0A1E)
+#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
+				 INTEL_DEVID(dev_priv) == 0x1913 || \
+				 INTEL_DEVID(dev_priv) == 0x1916 || \
+				 INTEL_DEVID(dev_priv) == 0x1921 || \
+				 INTEL_DEVID(dev_priv) == 0x1926)
+#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
+				 INTEL_DEVID(dev_priv) == 0x1915 || \
+				 INTEL_DEVID(dev_priv) == 0x191E)
+#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
+				 INTEL_DEVID(dev_priv) == 0x5913 || \
+				 INTEL_DEVID(dev_priv) == 0x5916 || \
+				 INTEL_DEVID(dev_priv) == 0x5921 || \
+				 INTEL_DEVID(dev_priv) == 0x5926)
+#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
+				 INTEL_DEVID(dev_priv) == 0x5915 || \
+				 INTEL_DEVID(dev_priv) == 0x591E)
+#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)
+#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)
+#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 4)
+#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)
+#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)
+#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
+#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)
+#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)
+#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
+					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
+
+#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
+
+#define SKL_REVID_A0		0x0
+#define SKL_REVID_B0		0x1
+#define SKL_REVID_C0		0x2
+#define SKL_REVID_D0		0x3
+#define SKL_REVID_E0		0x4
+#define SKL_REVID_F0		0x5
+#define SKL_REVID_G0		0x6
+#define SKL_REVID_H0		0x7
+
+#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+
+#define BXT_REVID_A0		0x0
+#define BXT_REVID_A1		0x1
+#define BXT_REVID_B0		0x3
+#define BXT_REVID_B_LAST	0x8
+#define BXT_REVID_C0		0x9
+
+#define IS_BXT_REVID(dev_priv, since, until) \
+	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
+
+#define KBL_REVID_A0		0x0
+#define KBL_REVID_B0		0x1
+#define KBL_REVID_C0		0x2
+#define KBL_REVID_D0		0x3
+#define KBL_REVID_E0		0x4
+
+#define IS_KBL_REVID(dev_priv, since, until) \
+	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+
+#define GLK_REVID_A0		0x0
+#define GLK_REVID_A1		0x1
+
+#define IS_GLK_REVID(dev_priv, since, until) \
+	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+
+#define CNL_REVID_A0		0x0
+#define CNL_REVID_B0		0x1
+#define CNL_REVID_C0		0x2
+
+#define IS_CNL_REVID(p, since, until) \
+	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+
+#define ICL_REVID_A0		0x0
+#define ICL_REVID_A2		0x1
+#define ICL_REVID_B0		0x3
+#define ICL_REVID_B2		0x4
+#define ICL_REVID_C0		0x5
+
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+
+/*
+ * The genX designation typically refers to the render engine, so render
+ * capability related checks should use IS_GEN, while display and other checks
+ * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for particular
+ * chips, etc.).
+ */
+#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
+#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
+#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
+#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
+#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
+#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
+#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
+#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
+#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
+#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
+
+#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
+#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
+#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
+
+#endif
-- 
2.17.0

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[PATCH 2/5] drm/i915: Store first production revid into device info

[Mika Kuoppala]

Store first known production revid into the device info.

This enables us to easily see if we are running on
a preproduction hardware.

Uninitialized (zero) product revision id means that
there are no known preliminary hardware for this platform,
or that the platform is of gen that we don't care.
This is all pre gen9 platforms.

Unknown product revision maps to REVID_FOREVER on a
gen9+ platforms on default. When the platform
gets the first production revision and our testing
infra is cleaned from preproduction hardware, we can
set a first production revid. At that point we start
to complain about running driver on preliminary hardware.

v2: initialize GEN9_FEATURES too (CI)
v3: comment, eyesore fix (Chris), cfl fix, squash

Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c          |  6 +++---
 drivers/gpu/drm/i915/i915_pci.c          | 10 ++++++++--
 drivers/gpu/drm/i915/intel_chipset.h     |  7 +++++++
 drivers/gpu/drm/i915/intel_device_info.h | 10 ++++++++++
 4 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index be71fdf8d92e..86725c272251 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -852,13 +852,13 @@ static void i915_workqueues_cleanup(struct drm_i915_private *dev_priv)
  */
 static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 {
+	const struct intel_device_info *info = INTEL_INFO(dev_priv);
 	bool pre = false;
 
 	pre |= IS_HSW_EARLY_SDV(dev_priv);
-	pre |= IS_SKL_REVID(dev_priv, 0, SKL_REVID_F0);
-	pre |= IS_BXT_REVID(dev_priv, 0, BXT_REVID_B_LAST);
+	pre |= IS_PREPRODUCTION_HW(dev_priv);
 
-	if (pre) {
+	if (pre && FIRST_PRODUCT_REVID(info) != PRODUCT_REVID_UNKNOWN) {
 		DRM_ERROR("This is a pre-production stepping. "
 			  "It may not be fully functional.\n");
 		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 97a91e6af7e3..60a02082055c 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -461,10 +461,12 @@ static const struct intel_device_info intel_cherryview_info = {
 	.has_csr = 1, \
 	.has_guc = 1, \
 	.has_ipc = 1, \
+	.first_product_revid = PRODUCT_REVID_UNKNOWN, \
 	.ddb_size = 896
 
 #define SKL_PLATFORM \
 	GEN9_FEATURES, \
+	.first_product_revid = SKL_REVID_PRODUCT, \
 	PLATFORM(INTEL_SKYLAKE)
 
 static const struct intel_device_info intel_skylake_gt1_info = {
@@ -518,6 +520,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 	.has_reset_engine = 1, \
 	.has_snoop = true, \
 	.has_ipc = 1, \
+	.first_product_revid = PRODUCT_REVID_UNKNOWN, \
 	GEN9_DEFAULT_PAGE_SIZES, \
 	GEN_DEFAULT_PIPEOFFSETS, \
 	IVB_CURSOR_OFFSETS, \
@@ -526,6 +529,7 @@ static const struct intel_device_info intel_skylake_gt4_info = {
 static const struct intel_device_info intel_broxton_info = {
 	GEN9_LP_FEATURES,
 	PLATFORM(INTEL_BROXTON),
+	.first_product_revid = BXT_REVID_PRODUCT,
 	.ddb_size = 512,
 };
 
@@ -538,7 +542,8 @@ static const struct intel_device_info intel_geminilake_info = {
 
 #define KBL_PLATFORM \
 	GEN9_FEATURES, \
-	PLATFORM(INTEL_KABYLAKE)
+	PLATFORM(INTEL_KABYLAKE), \
+	.first_product_revid = KBL_REVID_PRODUCT
 
 static const struct intel_device_info intel_kabylake_gt1_info = {
 	KBL_PLATFORM,
@@ -558,7 +563,8 @@ static const struct intel_device_info intel_kabylake_gt3_info = {
 
 #define CFL_PLATFORM \
 	GEN9_FEATURES, \
-	PLATFORM(INTEL_COFFEELAKE)
+	PLATFORM(INTEL_COFFEELAKE), \
+	.first_product_revid = 0x00 /* cfl doesn't use revids */
 
 static const struct intel_device_info intel_coffeelake_gt1_info = {
 	CFL_PLATFORM,
diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
index 0e71571fb4c1..a917ab40f857 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -127,6 +127,10 @@
 
 #define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
+#define PRODUCT_REVID_UNKNOWN	REVID_FOREVER
+#define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
+#define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+
 #define SKL_REVID_A0		0x0
 #define SKL_REVID_B0		0x1
 #define SKL_REVID_C0		0x2
@@ -134,6 +138,7 @@
 #define SKL_REVID_E0		0x4
 #define SKL_REVID_F0		0x5
 #define SKL_REVID_G0		0x6
+#define SKL_REVID_PRODUCT	SKL_REVID_G0
 #define SKL_REVID_H0		0x7
 
 #define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
@@ -143,12 +148,14 @@
 #define BXT_REVID_B0		0x3
 #define BXT_REVID_B_LAST	0x8
 #define BXT_REVID_C0		0x9
+#define BXT_REVID_PRODUCT	BXT_REVID_C0
 
 #define IS_BXT_REVID(dev_priv, since, until) \
 	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
 
 #define KBL_REVID_A0		0x0
 #define KBL_REVID_B0		0x1
+#define KBL_REVID_PRODUCT	KBL_REVID_B0
 #define KBL_REVID_C0		0x2
 #define KBL_REVID_D0		0x3
 #define KBL_REVID_E0		0x4
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 933e31669557..64ec283003dd 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -146,6 +146,16 @@ struct intel_device_info {
 	u16 device_id;
 	u16 gen_mask;
 
+	/*
+	 * First known production hardware pci revision id, or:
+	 * - uninitialized (0x00):         no known preliminary hw, (gen < 9)
+	 * - PRODUCT_REVID_UNKNOWN (0xff): no known production hw yet (gen >= 9)
+	 *
+	 * Do not set first product revid unless you are certain that testing
+	 * infrastructure is already on top of production revid machines.
+	 */
+	u8 first_product_revid;
+
 	u8 gen;
 	u8 gt; /* GT number, 0 if undefined */
 	u8 num_rings;
-- 
2.17.0

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[PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag

[Mika Kuoppala]

We don't need to have distinct flag for alpha quality if
we agree that setting the first production revid to be the
epoch for stepping out from alpha quality on that platform.

v2: rebase, comment beautification

Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c          | 2 +-
 drivers/gpu/drm/i915/i915_pci.c          | 3 +--
 drivers/gpu/drm/i915/intel_chipset.h     | 2 +-
 drivers/gpu/drm/i915/intel_device_info.h | 1 -
 4 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 86725c272251..74d3cccca905 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -858,7 +858,7 @@ static void intel_detect_preproduction_hw(struct drm_i915_private *dev_priv)
 	pre |= IS_HSW_EARLY_SDV(dev_priv);
 	pre |= IS_PREPRODUCTION_HW(dev_priv);
 
-	if (pre && FIRST_PRODUCT_REVID(info) != PRODUCT_REVID_UNKNOWN) {
+	if (pre && !IS_PLATFORM_SUPPORT_ALPHA(info)) {
 		DRM_ERROR("This is a pre-production stepping. "
 			  "It may not be fully functional.\n");
 		add_taint(TAINT_MACHINE_CHECK, LOCKDEP_STILL_OK);
diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index 60a02082055c..4a5a4f8778ad 100644
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -604,7 +604,6 @@ static const struct intel_device_info intel_cannonlake_info = {
 static const struct intel_device_info intel_icelake_11_info = {
 	GEN11_FEATURES,
 	PLATFORM(INTEL_ICELAKE),
-	.is_alpha_support = 1,
 	.has_resource_streamer = 0,
 	.ring_mask = RENDER_RING | BLT_RING | VEBOX_RING | BSD_RING | BSD3_RING,
 };
@@ -689,7 +688,7 @@ static int i915_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
 		(struct intel_device_info *) ent->driver_data;
 	int err;
 
-	if (IS_ALPHA_SUPPORT(intel_info) && !i915_modparams.alpha_support) {
+	if (IS_PLATFORM_SUPPORT_ALPHA(intel_info) && !i915_modparams.alpha_support) {
 		DRM_INFO("The driver support for your hardware in this kernel version is alpha quality\n"
 			 "See CONFIG_DRM_I915_ALPHA_SUPPORT or i915.alpha_support module parameter\n"
 			 "to enable support in this kernel version, or check for kernel updates.\n");
diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
index a917ab40f857..946c889c0118 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -125,11 +125,11 @@
 #define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
 					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
 
-#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
 
 #define PRODUCT_REVID_UNKNOWN	REVID_FOREVER
 #define FIRST_PRODUCT_REVID(intel_info) ((intel_info)->first_product_revid)
 #define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
+#define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)
 
 #define SKL_REVID_A0		0x0
 #define SKL_REVID_B0		0x1
diff --git a/drivers/gpu/drm/i915/intel_device_info.h b/drivers/gpu/drm/i915/intel_device_info.h
index 64ec283003dd..a66837db341b 100644
--- a/drivers/gpu/drm/i915/intel_device_info.h
+++ b/drivers/gpu/drm/i915/intel_device_info.h
@@ -77,7 +77,6 @@ enum intel_platform {
 #define DEV_INFO_FOR_EACH_FLAG(func) \
 	func(is_mobile); \
 	func(is_lp); \
-	func(is_alpha_support); \
 	/* Keep has_* in alphabetical order */ \
 	func(has_64bit_reloc); \
 	func(has_aliasing_ppgtt); \
-- 
2.17.0

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[PATCH 4/5] drm/i915: Remove kbl preproduction workarounds

[Mika Kuoppala]

We don't need kbl preprod workarounds anymore.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_lrc.c         | 12 ------------
 drivers/gpu/drm/i915/intel_workarounds.c |  5 -----
 2 files changed, 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c
index 091e28f0e024..ffec91cdb1b4 100644
--- a/drivers/gpu/drm/i915/intel_lrc.c
+++ b/drivers/gpu/drm/i915/intel_lrc.c
@@ -1581,18 +1581,6 @@ static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
 			GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE);
 	*batch++ = MI_NOOP;
 
-	/* WaClearSlmSpaceAtContextSwitch:kbl */
-	/* Actual scratch location is at 128 bytes offset */
-	if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) {
-		batch = gen8_emit_pipe_control(batch,
-					       PIPE_CONTROL_FLUSH_L3 |
-					       PIPE_CONTROL_GLOBAL_GTT_IVB |
-					       PIPE_CONTROL_CS_STALL |
-					       PIPE_CONTROL_QW_WRITE,
-					       i915_ggtt_offset(engine->scratch)
-					       + 2 * CACHELINE_BYTES);
-	}
-
 	/* WaMediaPoolStateCmdInWABB:bxt,glk */
 	if (HAS_POOLED_EU(engine->i915)) {
 		/*
diff --git a/drivers/gpu/drm/i915/intel_workarounds.c b/drivers/gpu/drm/i915/intel_workarounds.c
index 24b929ce3341..cdeb7abc14bf 100644
--- a/drivers/gpu/drm/i915/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/intel_workarounds.c
@@ -355,11 +355,6 @@ static int kbl_ctx_workarounds_init(struct drm_i915_private *dev_priv)
 	if (ret)
 		return ret;
 
-	/* WaDisableFenceDestinationToSLM:kbl (pre-prod) */
-	if (IS_KBL_REVID(dev_priv, KBL_REVID_A0, KBL_REVID_A0))
-		WA_SET_BIT_MASKED(HDC_CHICKEN0,
-				  HDC_FENCE_DEST_SLM_DISABLE);
-
 	/* WaToEnableHwFixForPushConstHWBug:kbl */
 	if (IS_KBL_REVID(dev_priv, KBL_REVID_C0, REVID_FOREVER))
 		WA_SET_BIT_MASKED(COMMON_SLICE_CHICKEN2,
-- 
2.17.0

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[PATCH 5/5] drm/i915: Warn on obsolete revision checks

[Mika Kuoppala]

If we are doing revision checks against a preproduction
range, when there is already a product, it is a sign
that there is code to be removed.

Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_chipset.h | 30 +++++++++++++++++++++-------
 1 file changed, 23 insertions(+), 7 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
index 946c889c0118..bc9ff02dc8df 100644
--- a/drivers/gpu/drm/i915/intel_chipset.h
+++ b/drivers/gpu/drm/i915/intel_chipset.h
@@ -131,6 +131,12 @@
 #define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
 #define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)
 
+#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
+		BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
+			     (revid) < (production_revid)); \
+		1; \
+	})
+
 #define SKL_REVID_A0		0x0
 #define SKL_REVID_B0		0x1
 #define SKL_REVID_C0		0x2
@@ -141,7 +147,9 @@
 #define SKL_REVID_PRODUCT	SKL_REVID_G0
 #define SKL_REVID_H0		0x7
 
-#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
+#define IS_SKL_REVID(p, since, until) \
+	(BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
+	 IS_SKYLAKE(p) && IS_REVID(p, since, until))
 
 #define BXT_REVID_A0		0x0
 #define BXT_REVID_A1		0x1
@@ -151,7 +159,8 @@
 #define BXT_REVID_PRODUCT	BXT_REVID_C0
 
 #define IS_BXT_REVID(dev_priv, since, until) \
-	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
+	(BUILD_BUG_ON_REVID_LT(until, BXT_REVID_PRODUCT) && \
+	 IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
 
 #define KBL_REVID_A0		0x0
 #define KBL_REVID_B0		0x1
@@ -161,29 +170,36 @@
 #define KBL_REVID_E0		0x4
 
 #define IS_KBL_REVID(dev_priv, since, until) \
-	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+	(BUILD_BUG_ON_REVID_LT(until, KBL_REVID_PRODUCT) && \
+	 IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
 
 #define GLK_REVID_A0		0x0
 #define GLK_REVID_A1		0x1
+#define GLK_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
 
-#define IS_GLK_REVID(dev_priv, since, until) \
-	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
+#define IS_GLK_REVID(dev_priv, since, until)		    \
+	(BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
+	 IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
 
 #define CNL_REVID_A0		0x0
 #define CNL_REVID_B0		0x1
 #define CNL_REVID_C0		0x2
+#define CNL_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
 
 #define IS_CNL_REVID(p, since, until) \
-	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
+	(BUILD_BUG_ON_REVID_LT(until, CNL_REVID_PRODUCT) && \
+	 IS_CANNONLAKE(p) && IS_REVID(p, since, until))
 
 #define ICL_REVID_A0		0x0
 #define ICL_REVID_A2		0x1
 #define ICL_REVID_B0		0x3
 #define ICL_REVID_B2		0x4
 #define ICL_REVID_C0		0x5
+#define ICL_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
 
 #define IS_ICL_REVID(p, since, until) \
-	(IS_ICELAKE(p) && IS_REVID(p, since, until))
+	(BUILD_BUG_ON_REVID_LT(until, ICL_REVID_PRODUCT) && \
+	IS_ICELAKE(p) && IS_REVID(p, since, until))
 
 /*
  * The genX designation typically refers to the render engine, so render
-- 
2.17.0

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Re: [PATCH 5/5] drm/i915: Warn on obsolete revision checks

[Chris Wilson]

Quoting Mika Kuoppala (2018-06-08 14:42:05)
> If we are doing revision checks against a preproduction
> range, when there is already a product, it is a sign
> that there is code to be removed.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_chipset.h | 30 +++++++++++++++++++++-------
>  1 file changed, 23 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
> index 946c889c0118..bc9ff02dc8df 100644
> --- a/drivers/gpu/drm/i915/intel_chipset.h
> +++ b/drivers/gpu/drm/i915/intel_chipset.h
> @@ -131,6 +131,12 @@
>  #define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
>  #define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)
>  
> +#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \

BUILD_BUG_ON_PREPRODUCTION()

It doesn't look that general, or widely useful to say REVID_LT. Sort of
implies we will have REVID_GTE etc later.

> +               BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
> +                            (revid) < (production_revid)); \

I'd prefer (!BUILD_BUG_ON_ZERO()) (Or push the
!BUILD_BUG_ON_PREPRODUCTION to the caller as that's easier to read).

That avoids the ({block}) making it less likely to cause problems.
-Chris
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Re: [PATCH 4/5] drm/i915: Remove kbl preproduction workarounds

[Chris Wilson]

Quoting Mika Kuoppala (2018-06-08 14:42:04)
> We don't need kbl preprod workarounds anymore.
> 
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>

As we now consider cnl stable, and icl the new development branch, we
can rid ourselves of preproduction w/a for anything older than cnl. (By
my understanding of our process rules.)

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag

[Chris Wilson]

Quoting Mika Kuoppala (2018-06-08 14:42:03)
> We don't need to have distinct flag for alpha quality if
> we agree that setting the first production revid to be the
> epoch for stepping out from alpha quality on that platform.
> 
> v2: rebase, comment beautification
> 
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Though not my domain, so please do get maintainer buy in.
-Chris
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Re: [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Chris Wilson]

Quoting Mika Kuoppala (2018-06-08 14:42:01)
> Carve out chipset definitions into new intel_chipset.h
> 
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Please check with Jani and Rodrigo that this fits in with our new/old
platform strategy.

> diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
> new file mode 100644
> index 000000000000..0e71571fb4c1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_chipset.h
> @@ -0,0 +1,202 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2018 Intel Corporation
> + */
> +
> +#ifndef _INTEL_CHIPSET_H_
> +#define _INTEL_CHIPSET_H_
> +
> +#define INTEL_GEN(dev_priv)    ((dev_priv)->info.gen)
> +#define INTEL_DEVID(dev_priv)  ((dev_priv)->info.device_id)

dev_priv. Will make this much harder to become standalone. Oh well.
-Chris
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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
URL   : https://patchwork.freedesktop.org/series/44488/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b04c01486105 drm/i915: Move chipset definitions to intel_chipset.h
-:225: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#225: 
new file mode 100644

-:246: CHECK:MACRO_ARG_REUSE: Macro argument reuse 's' - possible side-effects?
#246: FILE: drivers/gpu/drm/i915/intel_chipset.h:17:
+#define INTEL_GEN_MASK(s, e) ( \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
+	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
+		(s) != GEN_FOREVER ? (s) - 1 : 0) \
+)

-:246: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'e' - possible side-effects?
#246: FILE: drivers/gpu/drm/i915/intel_chipset.h:17:
+#define INTEL_GEN_MASK(s, e) ( \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
+	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
+	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
+		(s) != GEN_FOREVER ? (s) - 1 : 0) \
+)

-:266: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#266: FILE: drivers/gpu/drm/i915/intel_chipset.h:37:
+#define IS_REVID(p, since, until) \
+	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))

-:283: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#283: FILE: drivers/gpu/drm/i915/intel_chipset.h:54:
+#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))

-:290: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#290: FILE: drivers/gpu/drm/i915/intel_chipset.h:61:
+#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
+				 (dev_priv)->info.gt == 1)

-:304: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#304: FILE: drivers/gpu/drm/i915/intel_chipset.h:75:
+#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
+				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)

-:306: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#306: FILE: drivers/gpu/drm/i915/intel_chipset.h:77:
+#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))

-:311: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#311: FILE: drivers/gpu/drm/i915/intel_chipset.h:82:
+#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)

-:313: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#313: FILE: drivers/gpu/drm/i915/intel_chipset.h:84:
+#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
+				 (dev_priv)->info.gt == 3)

-:315: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#315: FILE: drivers/gpu/drm/i915/intel_chipset.h:86:
+#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)

-:317: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#317: FILE: drivers/gpu/drm/i915/intel_chipset.h:88:
+#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
+				 (dev_priv)->info.gt == 3)

-:320: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#320: FILE: drivers/gpu/drm/i915/intel_chipset.h:91:
+#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
+				 INTEL_DEVID(dev_priv) == 0x0A1E)

-:322: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#322: FILE: drivers/gpu/drm/i915/intel_chipset.h:93:
+#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
+				 INTEL_DEVID(dev_priv) == 0x1913 || \
+				 INTEL_DEVID(dev_priv) == 0x1916 || \
+				 INTEL_DEVID(dev_priv) == 0x1921 || \
+				 INTEL_DEVID(dev_priv) == 0x1926)

-:327: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#327: FILE: drivers/gpu/drm/i915/intel_chipset.h:98:
+#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
+				 INTEL_DEVID(dev_priv) == 0x1915 || \
+				 INTEL_DEVID(dev_priv) == 0x191E)

-:330: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#330: FILE: drivers/gpu/drm/i915/intel_chipset.h:101:
+#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
+				 INTEL_DEVID(dev_priv) == 0x5913 || \
+				 INTEL_DEVID(dev_priv) == 0x5916 || \
+				 INTEL_DEVID(dev_priv) == 0x5921 || \
+				 INTEL_DEVID(dev_priv) == 0x5926)

-:335: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#335: FILE: drivers/gpu/drm/i915/intel_chipset.h:106:
+#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
+				 INTEL_DEVID(dev_priv) == 0x5915 || \
+				 INTEL_DEVID(dev_priv) == 0x591E)

-:338: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#338: FILE: drivers/gpu/drm/i915/intel_chipset.h:109:
+#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)

-:340: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#340: FILE: drivers/gpu/drm/i915/intel_chipset.h:111:
+#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)

-:342: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#342: FILE: drivers/gpu/drm/i915/intel_chipset.h:113:
+#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 4)

-:344: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#344: FILE: drivers/gpu/drm/i915/intel_chipset.h:115:
+#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)

-:346: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#346: FILE: drivers/gpu/drm/i915/intel_chipset.h:117:
+#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)

-:348: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#348: FILE: drivers/gpu/drm/i915/intel_chipset.h:119:
+#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)

-:350: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#350: FILE: drivers/gpu/drm/i915/intel_chipset.h:121:
+#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 2)

-:352: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#352: FILE: drivers/gpu/drm/i915/intel_chipset.h:123:
+#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
+				 (dev_priv)->info.gt == 3)

-:354: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#354: FILE: drivers/gpu/drm/i915/intel_chipset.h:125:
+#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
+					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)

-:368: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#368: FILE: drivers/gpu/drm/i915/intel_chipset.h:139:
+#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))

-:376: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#376: FILE: drivers/gpu/drm/i915/intel_chipset.h:147:
+#define IS_BXT_REVID(dev_priv, since, until) \
+	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))

-:385: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#385: FILE: drivers/gpu/drm/i915/intel_chipset.h:156:
+#define IS_KBL_REVID(dev_priv, since, until) \
+	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))

-:391: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#391: FILE: drivers/gpu/drm/i915/intel_chipset.h:162:
+#define IS_GLK_REVID(dev_priv, since, until) \
+	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

-:398: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#398: FILE: drivers/gpu/drm/i915/intel_chipset.h:169:
+#define IS_CNL_REVID(p, since, until) \
+	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))

-:407: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#407: FILE: drivers/gpu/drm/i915/intel_chipset.h:178:
+#define IS_ICL_REVID(p, since, until) \
+	(IS_ICELAKE(p) && IS_REVID(p, since, until))

-:428: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#428: FILE: drivers/gpu/drm/i915/intel_chipset.h:199:
+#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))

-:429: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#429: FILE: drivers/gpu/drm/i915/intel_chipset.h:200:
+#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))

total: 0 errors, 1 warnings, 33 checks, 408 lines checked
b8d2b1ec3867 drm/i915: Store first production revid into device info
-:117: WARNING:LONG_LINE: line over 100 characters
#117: FILE: drivers/gpu/drm/i915/intel_chipset.h:132:
+#define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))

-:117: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#117: FILE: drivers/gpu/drm/i915/intel_chipset.h:132:
+#define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))

total: 0 errors, 1 warnings, 1 checks, 107 lines checked
9ef4f2cb2515 drm/i915: Use unknown production revid as alpha quality flag
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/intel_chipset.h:132:
+#define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)

total: 0 errors, 1 warnings, 0 checks, 42 lines checked
941d3c77de1d drm/i915: Remove kbl preproduction workarounds
503bc7e600b1 drm/i915: Warn on obsolete revision checks
-:20: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'production_revid' - possible side-effects?
#20: FILE: drivers/gpu/drm/i915/intel_chipset.h:134:
+#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
+		BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
+			     (revid) < (production_revid)); \
+		1; \
+	})

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'p' - possible side-effects?
#34: FILE: drivers/gpu/drm/i915/intel_chipset.h:150:
+#define IS_SKL_REVID(p, since, until) \
+	(BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
+	 IS_SKYLAKE(p) && IS_REVID(p, since, until))

-:34: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'until' - possible side-effects?
#34: FILE: drivers/gpu/drm/i915/intel_chipset.h:150:
+#define IS_SKL_REVID(p, since, until) \
+	(BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
+	 IS_SKYLAKE(p) && IS_REVID(p, since, until))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'dev_priv' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/intel_chipset.h:180:
+#define IS_GLK_REVID(dev_priv, since, until)		    \
+	(BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
+	 IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

-:64: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'until' - possible side-effects?
#64: FILE: drivers/gpu/drm/i915/intel_chipset.h:180:
+#define IS_GLK_REVID(dev_priv, since, until)		    \
+	(BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
+	 IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))

total: 0 errors, 0 warnings, 5 checks, 72 lines checked

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✗ Fi.CI.SPARSE: warning for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
URL   : https://patchwork.freedesktop.org/series/44488/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915: Move chipset definitions to intel_chipset.h
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3669:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3477:16: warning: expression using sizeof(void)

Commit: drm/i915: Store first production revid into device info
Okay!

Commit: drm/i915: Use unknown production revid as alpha quality flag
Okay!

Commit: drm/i915: Remove kbl preproduction workarounds
Okay!

Commit: drm/i915: Warn on obsolete revision checks
Okay!

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✓ Fi.CI.BAT: success for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
URL   : https://patchwork.freedesktop.org/series/44488/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4294 -> Patchwork_9242 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9242 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9242, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44488/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9242:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9242 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@gem_sync@basic-many-each:
      fi-cnl-y3:          INCOMPLETE (fdo#105086) -> PASS

    igt@kms_chamelium@dp-crc-fast:
      fi-kbl-7500u:       DMESG-FAIL (fdo#103841) -> PASS

    igt@kms_flip@basic-flip-vs-modeset:
      fi-glk-j4005:       DMESG-WARN (fdo#106097, fdo#106000) -> PASS

    
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105086 https://bugs.freedesktop.org/show_bug.cgi?id=105086
  fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
  fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097


== Participating hosts (41 -> 37) ==

  Additional (1): fi-bxt-dsi 
  Missing    (5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-skl-gvtdvm fi-skl-6700hq 


== Build changes ==

    * Linux: CI_DRM_4294 -> Patchwork_9242

  CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9242: 503bc7e600b180a943cb72eed79622d45fd5f516 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

503bc7e600b1 drm/i915: Warn on obsolete revision checks
941d3c77de1d drm/i915: Remove kbl preproduction workarounds
9ef4f2cb2515 drm/i915: Use unknown production revid as alpha quality flag
b8d2b1ec3867 drm/i915: Store first production revid into device info
b04c01486105 drm/i915: Move chipset definitions to intel_chipset.h

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9242/issues.html
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Re: [PATCH 2/5] drm/i915: Store first production revid into device info

[Chris Wilson]

Quoting Mika Kuoppala (2018-06-08 14:42:02)
> Store first known production revid into the device info.
> 
> This enables us to easily see if we are running on
> a preproduction hardware.
> 
> Uninitialized (zero) product revision id means that
> there are no known preliminary hardware for this platform,
> or that the platform is of gen that we don't care.
> This is all pre gen9 platforms.
> 
> Unknown product revision maps to REVID_FOREVER on a
> gen9+ platforms on default. When the platform
> gets the first production revision and our testing
> infra is cleaned from preproduction hardware, we can
> set a first production revid. At that point we start
> to complain about running driver on preliminary hardware.
> 
> v2: initialize GEN9_FEATURES too (CI)
> v3: comment, eyesore fix (Chris), cfl fix, squash
> 
> Suggested-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tomi Sarvela <tomi.p.sarvela@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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Re: [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Michal Wajdeczko]

On Fri, 08 Jun 2018 15:42:01 +0200, Mika Kuoppala  
<mika.kuoppala@linux.intel.com> wrote:

> Carve out chipset definitions into new intel_chipset.h
>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.h      | 194 +------------------------
>  drivers/gpu/drm/i915/intel_chipset.h | 202 +++++++++++++++++++++++++++
>  2 files changed, 203 insertions(+), 193 deletions(-)
>  create mode 100644 drivers/gpu/drm/i915/intel_chipset.h
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h  
> b/drivers/gpu/drm/i915/i915_drv.h
> index c4073666f1ca..e659c89198d2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -58,6 +58,7 @@
>  #include "i915_utils.h"
> #include "intel_bios.h"
> +#include "intel_chipset.h"
>  #include "intel_device_info.h"
>  #include "intel_display.h"
>  #include "intel_dpll_mgr.h"
> @@ -2309,199 +2310,6 @@ intel_info(const struct drm_i915_private  
> *dev_priv)
> #define INTEL_INFO(dev_priv)	intel_info((dev_priv))
> -#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
> -#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
> -
> -#define REVID_FOREVER		0xff
> -#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
> -
> -#define GEN_FOREVER (0)
> -
> -#define INTEL_GEN_MASK(s, e) ( \
> -	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
> -	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
> -	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
> -		(s) != GEN_FOREVER ? (s) - 1 : 0) \
> -)
> -
> -/*
> - * Returns true if Gen is in inclusive range [Start, End].
> - *
> - * Use GEN_FOREVER for unbound start and or end.
> - */
> -#define IS_GEN(dev_priv, s, e) \
> -	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
> -
> -/*
> - * Return true if revision is in range [since,until] inclusive.
> - *
> - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
> - */
> -#define IS_REVID(p, since, until) \
> -	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
> -
> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask &  
> BIT(p))
> -
> -#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
> -#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
> -#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
> -#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
> -#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
> -#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
> -#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
> -#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
> -#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
> -#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
> -#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
> -#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
> -#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
> -#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
> -#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
> -#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
> -#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
> -#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
> -#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> -#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
> -				 (dev_priv)->info.gt == 1)
> -#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
> -#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
> -#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
> -#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
> -#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
> -#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
> -#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
> -#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
> -#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> -#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> -#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> -#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
> -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> -				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> -#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> -/* ULX machines are also considered ULT. */
> -#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> -#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
> -				 (dev_priv)->info.gt == 3)
> -#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> -#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
> -				 (dev_priv)->info.gt == 3)
> -/* ULX machines are also considered ULT. */
> -#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
> -				 INTEL_DEVID(dev_priv) == 0x0A1E)
> -#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
> -				 INTEL_DEVID(dev_priv) == 0x1913 || \
> -				 INTEL_DEVID(dev_priv) == 0x1916 || \
> -				 INTEL_DEVID(dev_priv) == 0x1921 || \
> -				 INTEL_DEVID(dev_priv) == 0x1926)
> -#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
> -				 INTEL_DEVID(dev_priv) == 0x1915 || \
> -				 INTEL_DEVID(dev_priv) == 0x191E)
> -#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
> -				 INTEL_DEVID(dev_priv) == 0x5913 || \
> -				 INTEL_DEVID(dev_priv) == 0x5916 || \
> -				 INTEL_DEVID(dev_priv) == 0x5921 || \
> -				 INTEL_DEVID(dev_priv) == 0x5926)
> -#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
> -				 INTEL_DEVID(dev_priv) == 0x5915 || \
> -				 INTEL_DEVID(dev_priv) == 0x591E)
> -#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 2)
> -#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 3)
> -#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 4)
> -#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 2)
> -#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 3)
> -#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> -#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 2)
> -#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> -				 (dev_priv)->info.gt == 3)
> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
> -					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
> -
> -#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
> -
> -#define SKL_REVID_A0		0x0
> -#define SKL_REVID_B0		0x1
> -#define SKL_REVID_C0		0x2
> -#define SKL_REVID_D0		0x3
> -#define SKL_REVID_E0		0x4
> -#define SKL_REVID_F0		0x5
> -#define SKL_REVID_G0		0x6
> -#define SKL_REVID_H0		0x7
> -
> -#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p,  
> since, until))
> -
> -#define BXT_REVID_A0		0x0
> -#define BXT_REVID_A1		0x1
> -#define BXT_REVID_B0		0x3
> -#define BXT_REVID_B_LAST	0x8
> -#define BXT_REVID_C0		0x9
> -
> -#define IS_BXT_REVID(dev_priv, since, until) \
> -	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> -#define KBL_REVID_A0		0x0
> -#define KBL_REVID_B0		0x1
> -#define KBL_REVID_C0		0x2
> -#define KBL_REVID_D0		0x3
> -#define KBL_REVID_E0		0x4
> -
> -#define IS_KBL_REVID(dev_priv, since, until) \
> -	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> -#define GLK_REVID_A0		0x0
> -#define GLK_REVID_A1		0x1
> -
> -#define IS_GLK_REVID(dev_priv, since, until) \
> -	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> -
> -#define CNL_REVID_A0		0x0
> -#define CNL_REVID_B0		0x1
> -#define CNL_REVID_C0		0x2
> -
> -#define IS_CNL_REVID(p, since, until) \
> -	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> -
> -#define ICL_REVID_A0		0x0
> -#define ICL_REVID_A2		0x1
> -#define ICL_REVID_B0		0x3
> -#define ICL_REVID_B2		0x4
> -#define ICL_REVID_C0		0x5
> -
> -#define IS_ICL_REVID(p, since, until) \
> -	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> -
> -/*
> - * The genX designation typically refers to the render engine, so render
> - * capability related checks should use IS_GEN, while display and other  
> checks
> - * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for  
> particular
> - * chips, etc.).
> - */
> -#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
> -#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
> -#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
> -#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
> -#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
> -#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
> -#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
> -#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
> -#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
> -#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
> -
> -#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
> -#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
> -#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> -
>  #define ENGINE_MASK(id)	BIT(id)
>  #define RENDER_RING	ENGINE_MASK(RCS)
>  #define BSD_RING	ENGINE_MASK(VCS)
> diff --git a/drivers/gpu/drm/i915/intel_chipset.h  
> b/drivers/gpu/drm/i915/intel_chipset.h
> new file mode 100644
> index 000000000000..0e71571fb4c1
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_chipset.h
> @@ -0,0 +1,202 @@
> +/* SPDX-License-Identifier: MIT
> + *
> + * Copyright © 2018 Intel Corporation
> + */
> +
> +#ifndef _INTEL_CHIPSET_H_
> +#define _INTEL_CHIPSET_H_
> +
> +#define INTEL_GEN(dev_priv)	((dev_priv)->info.gen)
> +#define INTEL_DEVID(dev_priv)	((dev_priv)->info.device_id)
> +
> +#define REVID_FOREVER		0xff
> +#define INTEL_REVID(dev_priv)	((dev_priv)->drm.pdev->revision)
> +
> +#define GEN_FOREVER (0)
> +
> +#define INTEL_GEN_MASK(s, e) ( \
> +	BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
> +	BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
> +	GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
> +		(s) != GEN_FOREVER ? (s) - 1 : 0) \
> +)
> +
> +/*
> + * Returns true if Gen is in inclusive range [Start, End].
> + *
> + * Use GEN_FOREVER for unbound start and or end.
> + */
> +#define IS_GEN(dev_priv, s, e) \
> +	(!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
> +
> +/*
> + * Return true if revision is in range [since,until] inclusive.
> + *
> + * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
> + */
> +#define IS_REVID(p, since, until) \
> +	(INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
> +
> +#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask &  
> BIT(p))
> +
> +#define IS_I830(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I830)
> +#define IS_I845G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I845G)
> +#define IS_I85X(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I85X)
> +#define IS_I865G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I865G)
> +#define IS_I915G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915G)
> +#define IS_I915GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I915GM)
> +#define IS_I945G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945G)
> +#define IS_I945GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I945GM)
> +#define IS_I965G(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965G)
> +#define IS_I965GM(dev_priv)	IS_PLATFORM(dev_priv, INTEL_I965GM)
> +#define IS_G45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G45)
> +#define IS_GM45(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GM45)
> +#define IS_G4X(dev_priv)	(IS_G45(dev_priv) || IS_GM45(dev_priv))
> +#define IS_PINEVIEW_G(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa001)
> +#define IS_PINEVIEW_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0xa011)
> +#define IS_PINEVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
> +#define IS_G33(dev_priv)	IS_PLATFORM(dev_priv, INTEL_G33)
> +#define IS_IRONLAKE_M(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0046)
> +#define IS_IVYBRIDGE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
> +#define IS_IVB_GT1(dev_priv)	(IS_IVYBRIDGE(dev_priv) && \
> +				 (dev_priv)->info.gt == 1)
> +#define IS_VALLEYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_VALLEYVIEW)
> +#define IS_CHERRYVIEW(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CHERRYVIEW)
> +#define IS_HASWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_HASWELL)
> +#define IS_BROADWELL(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROADWELL)
> +#define IS_SKYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
> +#define IS_BROXTON(dev_priv)	IS_PLATFORM(dev_priv, INTEL_BROXTON)
> +#define IS_KABYLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
> +#define IS_GEMINILAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_GEMINILAKE)
> +#define IS_COFFEELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_COFFEELAKE)
> +#define IS_CANNONLAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_CANNONLAKE)
> +#define IS_ICELAKE(dev_priv)	IS_PLATFORM(dev_priv, INTEL_ICELAKE)

hmm, enum intel_platform is defined in "intel_device_info.h"
so maybe we should keep these macros there too?


> +#define IS_MOBILE(dev_priv)	((dev_priv)->info.is_mobile)
> +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
> +				    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
> +#define IS_BDW_ULT(dev_priv)	(IS_BROADWELL(dev_priv) && \
> +				 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||	\
> +				 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||	\
> +				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
> +/* ULX machines are also considered ULT. */
> +#define IS_BDW_ULX(dev_priv)	(IS_BROADWELL(dev_priv) && \
> +				 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
> +#define IS_BDW_GT3(dev_priv)	(IS_BROADWELL(dev_priv) && \
> +				 (dev_priv)->info.gt == 3)
> +#define IS_HSW_ULT(dev_priv)	(IS_HASWELL(dev_priv) && \
> +				 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
> +#define IS_HSW_GT3(dev_priv)	(IS_HASWELL(dev_priv) && \
> +				 (dev_priv)->info.gt == 3)
> +/* ULX machines are also considered ULT. */
> +#define IS_HSW_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x0A0E || \
> +				 INTEL_DEVID(dev_priv) == 0x0A1E)
> +#define IS_SKL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x1906 || \
> +				 INTEL_DEVID(dev_priv) == 0x1913 || \
> +				 INTEL_DEVID(dev_priv) == 0x1916 || \
> +				 INTEL_DEVID(dev_priv) == 0x1921 || \
> +				 INTEL_DEVID(dev_priv) == 0x1926)
> +#define IS_SKL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x190E || \
> +				 INTEL_DEVID(dev_priv) == 0x1915 || \
> +				 INTEL_DEVID(dev_priv) == 0x191E)
> +#define IS_KBL_ULT(dev_priv)	(INTEL_DEVID(dev_priv) == 0x5906 || \
> +				 INTEL_DEVID(dev_priv) == 0x5913 || \
> +				 INTEL_DEVID(dev_priv) == 0x5916 || \
> +				 INTEL_DEVID(dev_priv) == 0x5921 || \
> +				 INTEL_DEVID(dev_priv) == 0x5926)
> +#define IS_KBL_ULX(dev_priv)	(INTEL_DEVID(dev_priv) == 0x590E || \
> +				 INTEL_DEVID(dev_priv) == 0x5915 || \
> +				 INTEL_DEVID(dev_priv) == 0x591E)

for me, intel_chipset.h (or similar separate public header) should consist
only plain defines with devid and revid like:


#define INTEL_DEVID_KBL_ULX_GT2   0x591E
#define INTEL_DEVID_KBL_ULX_GT1_5 0x5915
#define INTEL_REVID_KBL_A0        0x0

then in i915_pciid.h:

	INTEL_VGA_DEVICE(INTEL_DEVID_KBL_ULX_GT2, info), \

and in some other place we can construct more complex macros:

#define __IS_KABYLAKE(devid) \
	((devid) == INTEL_DEVID_KBL_ULX_GT2 || \
...

#define __IS_KBL_REVID(devid, revid, since, until) \
	(__IS_KABYLAKE(devid) && \
	 __IS_REVID(revid, since, until))

#define IS_KBL_REVID(dev_priv, since, until) \
	__IS_KBL_REVID(INTEL_DEVID(dev_priv), \
	               INTEL_REVID(dev_priv), \
	               INTEL_REVID_KBL_##since, \
	               INTEL_REVID_KBL_##until))

> +#define IS_SKL_GT2(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 2)
> +#define IS_SKL_GT3(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 3)
> +#define IS_SKL_GT4(dev_priv)	(IS_SKYLAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 4)
> +#define IS_KBL_GT2(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 2)
> +#define IS_KBL_GT3(dev_priv)	(IS_KABYLAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 3)
> +#define IS_CFL_ULT(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> +				 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
> +#define IS_CFL_GT2(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 2)
> +#define IS_CFL_GT3(dev_priv)	(IS_COFFEELAKE(dev_priv) && \
> +				 (dev_priv)->info.gt == 3)
> +#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
> +					(INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
> +
> +#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
> +
> +#define SKL_REVID_A0		0x0
> +#define SKL_REVID_B0		0x1
> +#define SKL_REVID_C0		0x2
> +#define SKL_REVID_D0		0x3
> +#define SKL_REVID_E0		0x4
> +#define SKL_REVID_F0		0x5
> +#define SKL_REVID_G0		0x6
> +#define SKL_REVID_H0		0x7
> +
> +#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p,  
> since, until))
> +
> +#define BXT_REVID_A0		0x0
> +#define BXT_REVID_A1		0x1
> +#define BXT_REVID_B0		0x3
> +#define BXT_REVID_B_LAST	0x8
> +#define BXT_REVID_C0		0x9
> +
> +#define IS_BXT_REVID(dev_priv, since, until) \
> +	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> +
> +#define KBL_REVID_A0		0x0
> +#define KBL_REVID_B0		0x1
> +#define KBL_REVID_C0		0x2
> +#define KBL_REVID_D0		0x3
> +#define KBL_REVID_E0		0x4
> +
> +#define IS_KBL_REVID(dev_priv, since, until) \
> +	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> +
> +#define GLK_REVID_A0		0x0
> +#define GLK_REVID_A1		0x1
> +
> +#define IS_GLK_REVID(dev_priv, since, until) \
> +	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> +
> +#define CNL_REVID_A0		0x0
> +#define CNL_REVID_B0		0x1
> +#define CNL_REVID_C0		0x2
> +
> +#define IS_CNL_REVID(p, since, until) \
> +	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> +
> +#define ICL_REVID_A0		0x0
> +#define ICL_REVID_A2		0x1
> +#define ICL_REVID_B0		0x3
> +#define ICL_REVID_B2		0x4
> +#define ICL_REVID_C0		0x5
> +
> +#define IS_ICL_REVID(p, since, until) \
> +	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> +
> +/*
> + * The genX designation typically refers to the render engine, so render
> + * capability related checks should use IS_GEN, while display and other  
> checks
> + * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for  
> particular
> + * chips, etc.).
> + */
> +#define IS_GEN2(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(1)))
> +#define IS_GEN3(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(2)))
> +#define IS_GEN4(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(3)))
> +#define IS_GEN5(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(4)))
> +#define IS_GEN6(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(5)))
> +#define IS_GEN7(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(6)))
> +#define IS_GEN8(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(7)))
> +#define IS_GEN9(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(8)))
> +#define IS_GEN10(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(9)))
> +#define IS_GEN11(dev_priv)	(!!((dev_priv)->info.gen_mask & BIT(10)))
> +
> +#define IS_LP(dev_priv)	(INTEL_INFO(dev_priv)->is_lp)
> +#define IS_GEN9_LP(dev_priv)	(IS_GEN9(dev_priv) && IS_LP(dev_priv))
> +#define IS_GEN9_BC(dev_priv)	(IS_GEN9(dev_priv) && !IS_LP(dev_priv))
> +
> +#endif
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✓ Fi.CI.IGT: success for series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Patchwork]

== Series Details ==

Series: series starting with [1/5] drm/i915: Move chipset definitions to intel_chipset.h
URL   : https://patchwork.freedesktop.org/series/44488/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4294_full -> Patchwork_9242_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9242_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9242_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9242_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-vebox:
      shard-kbl:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_9242_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_exec_big:
      shard-hsw:          PASS -> INCOMPLETE (fdo#103540)

    igt@gem_exec_suspend@basic-s3:
      shard-snb:          PASS -> INCOMPLETE (fdo#105411)

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking:
      shard-glk:          PASS -> FAIL (fdo#105703)

    igt@kms_cursor_crc@cursor-64x64-random:
      shard-kbl:          PASS -> DMESG-WARN (fdo#105602, fdo#103558) +2

    igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#103822, fdo#104724)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@prime_vgem@basic-fence-flip:
      shard-glk:          PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_gtt:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS
      shard-apl:          FAIL (fdo#105347) -> PASS

    igt@drv_selftest@live_hangcheck:
      shard-kbl:          DMESG-FAIL (fdo#106560) -> PASS

    igt@gem_eio@suspend:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS +1

    igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing:
      shard-glk:          FAIL (fdo#105703) -> PASS

    igt@kms_flip@2x-plain-flip-fb-recreate:
      shard-hsw:          FAIL (fdo#100368) -> PASS +1

    igt@kms_flip@modeset-vs-vblank-race-interruptible:
      shard-hsw:          FAIL (fdo#103060) -> PASS +1

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          FAIL (fdo#104724) -> PASS

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-pri-indfb-draw-mmap-cpu:
      shard-snb:          FAIL (fdo#103167, fdo#104724) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4294 -> Patchwork_9242

  CI_DRM_4294: af0889384edc6de2f91494325d571c66dffea83f @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4512: 093fa482371795c3aa246509994eb21907f501b9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9242: 503bc7e600b180a943cb72eed79622d45fd5f516 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9242/shards.html
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Re: [PATCH 1/5] drm/i915: Move chipset definitions to intel_chipset.h

[Tvrtko Ursulin]

On 08/06/2018 16:04, Michal Wajdeczko wrote:
> On Fri, 08 Jun 2018 15:42:01 +0200, Mika Kuoppala 
> <mika.kuoppala@linux.intel.com> wrote:
> 
>> Carve out chipset definitions into new intel_chipset.h
>>
>> Cc: Chris Wilson <chris@chris-wilson.co.uk>
>> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
>> ---
>>  drivers/gpu/drm/i915/i915_drv.h      | 194 +------------------------
>>  drivers/gpu/drm/i915/intel_chipset.h | 202 +++++++++++++++++++++++++++
>>  2 files changed, 203 insertions(+), 193 deletions(-)
>>  create mode 100644 drivers/gpu/drm/i915/intel_chipset.h
>>
>> diff --git a/drivers/gpu/drm/i915/i915_drv.h 
>> b/drivers/gpu/drm/i915/i915_drv.h
>> index c4073666f1ca..e659c89198d2 100644
>> --- a/drivers/gpu/drm/i915/i915_drv.h
>> +++ b/drivers/gpu/drm/i915/i915_drv.h
>> @@ -58,6 +58,7 @@
>>  #include "i915_utils.h"
>> #include "intel_bios.h"
>> +#include "intel_chipset.h"
>>  #include "intel_device_info.h"
>>  #include "intel_display.h"
>>  #include "intel_dpll_mgr.h"
>> @@ -2309,199 +2310,6 @@ intel_info(const struct drm_i915_private 
>> *dev_priv)
>> #define INTEL_INFO(dev_priv)    intel_info((dev_priv))
>> -#define INTEL_GEN(dev_priv)    ((dev_priv)->info.gen)
>> -#define INTEL_DEVID(dev_priv)    ((dev_priv)->info.device_id)
>> -
>> -#define REVID_FOREVER        0xff
>> -#define INTEL_REVID(dev_priv)    ((dev_priv)->drm.pdev->revision)
>> -
>> -#define GEN_FOREVER (0)
>> -
>> -#define INTEL_GEN_MASK(s, e) ( \
>> -    BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
>> -    BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
>> -    GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
>> -        (s) != GEN_FOREVER ? (s) - 1 : 0) \
>> -)
>> -
>> -/*
>> - * Returns true if Gen is in inclusive range [Start, End].
>> - *
>> - * Use GEN_FOREVER for unbound start and or end.
>> - */
>> -#define IS_GEN(dev_priv, s, e) \
>> -    (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>> -
>> -/*
>> - * Return true if revision is in range [since,until] inclusive.
>> - *
>> - * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
>> - */
>> -#define IS_REVID(p, since, until) \
>> -    (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>> -
>> -#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & 
>> BIT(p))
>> -
>> -#define IS_I830(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I830)
>> -#define IS_I845G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I845G)
>> -#define IS_I85X(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I85X)
>> -#define IS_I865G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I865G)
>> -#define IS_I915G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I915G)
>> -#define IS_I915GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I915GM)
>> -#define IS_I945G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I945G)
>> -#define IS_I945GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I945GM)
>> -#define IS_I965G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I965G)
>> -#define IS_I965GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I965GM)
>> -#define IS_G45(dev_priv)    IS_PLATFORM(dev_priv, INTEL_G45)
>> -#define IS_GM45(dev_priv)    IS_PLATFORM(dev_priv, INTEL_GM45)
>> -#define IS_G4X(dev_priv)    (IS_G45(dev_priv) || IS_GM45(dev_priv))
>> -#define IS_PINEVIEW_G(dev_priv)    (INTEL_DEVID(dev_priv) == 0xa001)
>> -#define IS_PINEVIEW_M(dev_priv)    (INTEL_DEVID(dev_priv) == 0xa011)
>> -#define IS_PINEVIEW(dev_priv)    IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
>> -#define IS_G33(dev_priv)    IS_PLATFORM(dev_priv, INTEL_G33)
>> -#define IS_IRONLAKE_M(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0046)
>> -#define IS_IVYBRIDGE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
>> -#define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 1)
>> -#define IS_VALLEYVIEW(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_VALLEYVIEW)
>> -#define IS_CHERRYVIEW(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_CHERRYVIEW)
>> -#define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
>> -#define IS_BROADWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROADWELL)
>> -#define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
>> -#define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
>> -#define IS_KABYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
>> -#define IS_GEMINILAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_GEMINILAKE)
>> -#define IS_COFFEELAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_COFFEELAKE)
>> -#define IS_CANNONLAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_CANNONLAKE)
>> -#define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
>> -#define IS_MOBILE(dev_priv)    ((dev_priv)->info.is_mobile)
>> -#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> -                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> -#define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> -                 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||    \
>> -                 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||    \
>> -                 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
>> -/* ULX machines are also considered ULT. */
>> -#define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> -                 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> -#define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> -                 (dev_priv)->info.gt == 3)
>> -#define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
>> -                 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> -#define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
>> -                 (dev_priv)->info.gt == 3)
>> -/* ULX machines are also considered ULT. */
>> -#define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
>> -                 INTEL_DEVID(dev_priv) == 0x0A1E)
>> -#define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
>> -                 INTEL_DEVID(dev_priv) == 0x1913 || \
>> -                 INTEL_DEVID(dev_priv) == 0x1916 || \
>> -                 INTEL_DEVID(dev_priv) == 0x1921 || \
>> -                 INTEL_DEVID(dev_priv) == 0x1926)
>> -#define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
>> -                 INTEL_DEVID(dev_priv) == 0x1915 || \
>> -                 INTEL_DEVID(dev_priv) == 0x191E)
>> -#define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
>> -                 INTEL_DEVID(dev_priv) == 0x5913 || \
>> -                 INTEL_DEVID(dev_priv) == 0x5916 || \
>> -                 INTEL_DEVID(dev_priv) == 0x5921 || \
>> -                 INTEL_DEVID(dev_priv) == 0x5926)
>> -#define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
>> -                 INTEL_DEVID(dev_priv) == 0x5915 || \
>> -                 INTEL_DEVID(dev_priv) == 0x591E)
>> -#define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 2)
>> -#define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 3)
>> -#define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 4)
>> -#define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 2)
>> -#define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 3)
>> -#define IS_CFL_ULT(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> -                 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> -#define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 2)
>> -#define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> -                 (dev_priv)->info.gt == 3)
>> -#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
>> -                    (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>> -
>> -#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>> -
>> -#define SKL_REVID_A0        0x0
>> -#define SKL_REVID_B0        0x1
>> -#define SKL_REVID_C0        0x2
>> -#define SKL_REVID_D0        0x3
>> -#define SKL_REVID_E0        0x4
>> -#define SKL_REVID_F0        0x5
>> -#define SKL_REVID_G0        0x6
>> -#define SKL_REVID_H0        0x7
>> -
>> -#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, 
>> since, until))
>> -
>> -#define BXT_REVID_A0        0x0
>> -#define BXT_REVID_A1        0x1
>> -#define BXT_REVID_B0        0x3
>> -#define BXT_REVID_B_LAST    0x8
>> -#define BXT_REVID_C0        0x9
>> -
>> -#define IS_BXT_REVID(dev_priv, since, until) \
>> -    (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>> -
>> -#define KBL_REVID_A0        0x0
>> -#define KBL_REVID_B0        0x1
>> -#define KBL_REVID_C0        0x2
>> -#define KBL_REVID_D0        0x3
>> -#define KBL_REVID_E0        0x4
>> -
>> -#define IS_KBL_REVID(dev_priv, since, until) \
>> -    (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>> -
>> -#define GLK_REVID_A0        0x0
>> -#define GLK_REVID_A1        0x1
>> -
>> -#define IS_GLK_REVID(dev_priv, since, until) \
>> -    (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>> -
>> -#define CNL_REVID_A0        0x0
>> -#define CNL_REVID_B0        0x1
>> -#define CNL_REVID_C0        0x2
>> -
>> -#define IS_CNL_REVID(p, since, until) \
>> -    (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>> -
>> -#define ICL_REVID_A0        0x0
>> -#define ICL_REVID_A2        0x1
>> -#define ICL_REVID_B0        0x3
>> -#define ICL_REVID_B2        0x4
>> -#define ICL_REVID_C0        0x5
>> -
>> -#define IS_ICL_REVID(p, since, until) \
>> -    (IS_ICELAKE(p) && IS_REVID(p, since, until))
>> -
>> -/*
>> - * The genX designation typically refers to the render engine, so render
>> - * capability related checks should use IS_GEN, while display and 
>> other checks
>> - * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for 
>> particular
>> - * chips, etc.).
>> - */
>> -#define IS_GEN2(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(1)))
>> -#define IS_GEN3(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(2)))
>> -#define IS_GEN4(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(3)))
>> -#define IS_GEN5(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(4)))
>> -#define IS_GEN6(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(5)))
>> -#define IS_GEN7(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(6)))
>> -#define IS_GEN8(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(7)))
>> -#define IS_GEN9(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(8)))
>> -#define IS_GEN10(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(9)))
>> -#define IS_GEN11(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(10)))
>> -
>> -#define IS_LP(dev_priv)    (INTEL_INFO(dev_priv)->is_lp)
>> -#define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && IS_LP(dev_priv))
>> -#define IS_GEN9_BC(dev_priv)    (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
>> -
>>  #define ENGINE_MASK(id)    BIT(id)
>>  #define RENDER_RING    ENGINE_MASK(RCS)
>>  #define BSD_RING    ENGINE_MASK(VCS)
>> diff --git a/drivers/gpu/drm/i915/intel_chipset.h 
>> b/drivers/gpu/drm/i915/intel_chipset.h
>> new file mode 100644
>> index 000000000000..0e71571fb4c1
>> --- /dev/null
>> +++ b/drivers/gpu/drm/i915/intel_chipset.h
>> @@ -0,0 +1,202 @@
>> +/* SPDX-License-Identifier: MIT
>> + *
>> + * Copyright © 2018 Intel Corporation
>> + */
>> +
>> +#ifndef _INTEL_CHIPSET_H_
>> +#define _INTEL_CHIPSET_H_
>> +
>> +#define INTEL_GEN(dev_priv)    ((dev_priv)->info.gen)
>> +#define INTEL_DEVID(dev_priv)    ((dev_priv)->info.device_id)
>> +
>> +#define REVID_FOREVER        0xff
>> +#define INTEL_REVID(dev_priv)    ((dev_priv)->drm.pdev->revision)
>> +
>> +#define GEN_FOREVER (0)
>> +
>> +#define INTEL_GEN_MASK(s, e) ( \
>> +    BUILD_BUG_ON_ZERO(!__builtin_constant_p(s)) + \
>> +    BUILD_BUG_ON_ZERO(!__builtin_constant_p(e)) + \
>> +    GENMASK((e) != GEN_FOREVER ? (e) - 1 : BITS_PER_LONG - 1, \
>> +        (s) != GEN_FOREVER ? (s) - 1 : 0) \
>> +)
>> +
>> +/*
>> + * Returns true if Gen is in inclusive range [Start, End].
>> + *
>> + * Use GEN_FOREVER for unbound start and or end.
>> + */
>> +#define IS_GEN(dev_priv, s, e) \
>> +    (!!((dev_priv)->info.gen_mask & INTEL_GEN_MASK((s), (e))))
>> +
>> +/*
>> + * Return true if revision is in range [since,until] inclusive.
>> + *
>> + * Use 0 for open-ended since, and REVID_FOREVER for open-ended until.
>> + */
>> +#define IS_REVID(p, since, until) \
>> +    (INTEL_REVID(p) >= (since) && INTEL_REVID(p) <= (until))
>> +
>> +#define IS_PLATFORM(dev_priv, p) ((dev_priv)->info.platform_mask & 
>> BIT(p))
>> +
>> +#define IS_I830(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I830)
>> +#define IS_I845G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I845G)
>> +#define IS_I85X(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I85X)
>> +#define IS_I865G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I865G)
>> +#define IS_I915G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I915G)
>> +#define IS_I915GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I915GM)
>> +#define IS_I945G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I945G)
>> +#define IS_I945GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I945GM)
>> +#define IS_I965G(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I965G)
>> +#define IS_I965GM(dev_priv)    IS_PLATFORM(dev_priv, INTEL_I965GM)
>> +#define IS_G45(dev_priv)    IS_PLATFORM(dev_priv, INTEL_G45)
>> +#define IS_GM45(dev_priv)    IS_PLATFORM(dev_priv, INTEL_GM45)
>> +#define IS_G4X(dev_priv)    (IS_G45(dev_priv) || IS_GM45(dev_priv))
>> +#define IS_PINEVIEW_G(dev_priv)    (INTEL_DEVID(dev_priv) == 0xa001)
>> +#define IS_PINEVIEW_M(dev_priv)    (INTEL_DEVID(dev_priv) == 0xa011)
>> +#define IS_PINEVIEW(dev_priv)    IS_PLATFORM(dev_priv, INTEL_PINEVIEW)
>> +#define IS_G33(dev_priv)    IS_PLATFORM(dev_priv, INTEL_G33)
>> +#define IS_IRONLAKE_M(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0046)
>> +#define IS_IVYBRIDGE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_IVYBRIDGE)
>> +#define IS_IVB_GT1(dev_priv)    (IS_IVYBRIDGE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 1)
>> +#define IS_VALLEYVIEW(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_VALLEYVIEW)
>> +#define IS_CHERRYVIEW(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_CHERRYVIEW)
>> +#define IS_HASWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_HASWELL)
>> +#define IS_BROADWELL(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROADWELL)
>> +#define IS_SKYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_SKYLAKE)
>> +#define IS_BROXTON(dev_priv)    IS_PLATFORM(dev_priv, INTEL_BROXTON)
>> +#define IS_KABYLAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_KABYLAKE)
>> +#define IS_GEMINILAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_GEMINILAKE)
>> +#define IS_COFFEELAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_COFFEELAKE)
>> +#define IS_CANNONLAKE(dev_priv)    IS_PLATFORM(dev_priv, 
>> INTEL_CANNONLAKE)
>> +#define IS_ICELAKE(dev_priv)    IS_PLATFORM(dev_priv, INTEL_ICELAKE)
> 
> hmm, enum intel_platform is defined in "intel_device_info.h"
> so maybe we should keep these macros there too?
> 
> 
>> +#define IS_MOBILE(dev_priv)    ((dev_priv)->info.is_mobile)
>> +#define IS_HSW_EARLY_SDV(dev_priv) (IS_HASWELL(dev_priv) && \
>> +                    (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0C00)
>> +#define IS_BDW_ULT(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> +                 ((INTEL_DEVID(dev_priv) & 0xf) == 0x6 ||    \
>> +                 (INTEL_DEVID(dev_priv) & 0xf) == 0xb ||    \
>> +                 (INTEL_DEVID(dev_priv) & 0xf) == 0xe))
>> +/* ULX machines are also considered ULT. */
>> +#define IS_BDW_ULX(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> +                 (INTEL_DEVID(dev_priv) & 0xf) == 0xe)
>> +#define IS_BDW_GT3(dev_priv)    (IS_BROADWELL(dev_priv) && \
>> +                 (dev_priv)->info.gt == 3)
>> +#define IS_HSW_ULT(dev_priv)    (IS_HASWELL(dev_priv) && \
>> +                 (INTEL_DEVID(dev_priv) & 0xFF00) == 0x0A00)
>> +#define IS_HSW_GT3(dev_priv)    (IS_HASWELL(dev_priv) && \
>> +                 (dev_priv)->info.gt == 3)
>> +/* ULX machines are also considered ULT. */
>> +#define IS_HSW_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x0A0E || \
>> +                 INTEL_DEVID(dev_priv) == 0x0A1E)
>> +#define IS_SKL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x1906 || \
>> +                 INTEL_DEVID(dev_priv) == 0x1913 || \
>> +                 INTEL_DEVID(dev_priv) == 0x1916 || \
>> +                 INTEL_DEVID(dev_priv) == 0x1921 || \
>> +                 INTEL_DEVID(dev_priv) == 0x1926)
>> +#define IS_SKL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x190E || \
>> +                 INTEL_DEVID(dev_priv) == 0x1915 || \
>> +                 INTEL_DEVID(dev_priv) == 0x191E)
>> +#define IS_KBL_ULT(dev_priv)    (INTEL_DEVID(dev_priv) == 0x5906 || \
>> +                 INTEL_DEVID(dev_priv) == 0x5913 || \
>> +                 INTEL_DEVID(dev_priv) == 0x5916 || \
>> +                 INTEL_DEVID(dev_priv) == 0x5921 || \
>> +                 INTEL_DEVID(dev_priv) == 0x5926)
>> +#define IS_KBL_ULX(dev_priv)    (INTEL_DEVID(dev_priv) == 0x590E || \
>> +                 INTEL_DEVID(dev_priv) == 0x5915 || \
>> +                 INTEL_DEVID(dev_priv) == 0x591E)
> 
> for me, intel_chipset.h (or similar separate public header) should consist
> only plain defines with devid and revid like:
> 
> 
> #define INTEL_DEVID_KBL_ULX_GT2   0x591E
> #define INTEL_DEVID_KBL_ULX_GT1_5 0x5915
> #define INTEL_REVID_KBL_A0        0x0
> 
> then in i915_pciid.h:
> 
>      INTEL_VGA_DEVICE(INTEL_DEVID_KBL_ULX_GT2, info), \
> 
> and in some other place we can construct more complex macros:
> 
> #define __IS_KABYLAKE(devid) \
>      ((devid) == INTEL_DEVID_KBL_ULX_GT2 || \
> ...
> 
> #define __IS_KBL_REVID(devid, revid, since, until) \
>      (__IS_KABYLAKE(devid) && \
>       __IS_REVID(revid, since, until))
> 
> #define IS_KBL_REVID(dev_priv, since, until) \
>      __IS_KBL_REVID(INTEL_DEVID(dev_priv), \
>                     INTEL_REVID(dev_priv), \
>                     INTEL_REVID_KBL_##since, \
>                     INTEL_REVID_KBL_##until))

I agree with Michal here, when I read intel_chipset.h I expect purely 
hardware data (as much as possible) and no, or as little as possible, 
interfacing with i915 structures/concepts.

Would it work for this series to just move revision ids to 
intel_chipset.h and leave the rest in i915_drv.h? Or we would need to 
find a new place for everything?

Regards,

Tvrtko

>> +#define IS_SKL_GT2(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 2)
>> +#define IS_SKL_GT3(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 3)
>> +#define IS_SKL_GT4(dev_priv)    (IS_SKYLAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 4)
>> +#define IS_KBL_GT2(dev_priv)    (IS_KABYLAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 2)
>> +#define IS_KBL_GT3(dev_priv)    (IS_KABYLAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 3)
>> +#define IS_CFL_ULT(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> +                 (INTEL_DEVID(dev_priv) & 0x00F0) == 0x00A0)
>> +#define IS_CFL_GT2(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 2)
>> +#define IS_CFL_GT3(dev_priv)    (IS_COFFEELAKE(dev_priv) && \
>> +                 (dev_priv)->info.gt == 3)
>> +#define IS_CNL_WITH_PORT_F(dev_priv)   (IS_CANNONLAKE(dev_priv) && \
>> +                    (INTEL_DEVID(dev_priv) & 0x0004) == 0x0004)
>> +
>> +#define IS_ALPHA_SUPPORT(intel_info) ((intel_info)->is_alpha_support)
>> +
>> +#define SKL_REVID_A0        0x0
>> +#define SKL_REVID_B0        0x1
>> +#define SKL_REVID_C0        0x2
>> +#define SKL_REVID_D0        0x3
>> +#define SKL_REVID_E0        0x4
>> +#define SKL_REVID_F0        0x5
>> +#define SKL_REVID_G0        0x6
>> +#define SKL_REVID_H0        0x7
>> +
>> +#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, 
>> since, until))
>> +
>> +#define BXT_REVID_A0        0x0
>> +#define BXT_REVID_A1        0x1
>> +#define BXT_REVID_B0        0x3
>> +#define BXT_REVID_B_LAST    0x8
>> +#define BXT_REVID_C0        0x9
>> +
>> +#define IS_BXT_REVID(dev_priv, since, until) \
>> +    (IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>> +
>> +#define KBL_REVID_A0        0x0
>> +#define KBL_REVID_B0        0x1
>> +#define KBL_REVID_C0        0x2
>> +#define KBL_REVID_D0        0x3
>> +#define KBL_REVID_E0        0x4
>> +
>> +#define IS_KBL_REVID(dev_priv, since, until) \
>> +    (IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>> +
>> +#define GLK_REVID_A0        0x0
>> +#define GLK_REVID_A1        0x1
>> +
>> +#define IS_GLK_REVID(dev_priv, since, until) \
>> +    (IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>> +
>> +#define CNL_REVID_A0        0x0
>> +#define CNL_REVID_B0        0x1
>> +#define CNL_REVID_C0        0x2
>> +
>> +#define IS_CNL_REVID(p, since, until) \
>> +    (IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>> +
>> +#define ICL_REVID_A0        0x0
>> +#define ICL_REVID_A2        0x1
>> +#define ICL_REVID_B0        0x3
>> +#define ICL_REVID_B2        0x4
>> +#define ICL_REVID_C0        0x5
>> +
>> +#define IS_ICL_REVID(p, since, until) \
>> +    (IS_ICELAKE(p) && IS_REVID(p, since, until))
>> +
>> +/*
>> + * The genX designation typically refers to the render engine, so render
>> + * capability related checks should use IS_GEN, while display and 
>> other checks
>> + * have their own (e.g. HAS_PCH_SPLIT for ILK+ display, IS_foo for 
>> particular
>> + * chips, etc.).
>> + */
>> +#define IS_GEN2(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(1)))
>> +#define IS_GEN3(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(2)))
>> +#define IS_GEN4(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(3)))
>> +#define IS_GEN5(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(4)))
>> +#define IS_GEN6(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(5)))
>> +#define IS_GEN7(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(6)))
>> +#define IS_GEN8(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(7)))
>> +#define IS_GEN9(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(8)))
>> +#define IS_GEN10(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(9)))
>> +#define IS_GEN11(dev_priv)    (!!((dev_priv)->info.gen_mask & BIT(10)))
>> +
>> +#define IS_LP(dev_priv)    (INTEL_INFO(dev_priv)->is_lp)
>> +#define IS_GEN9_LP(dev_priv)    (IS_GEN9(dev_priv) && IS_LP(dev_priv))
>> +#define IS_GEN9_BC(dev_priv)    (IS_GEN9(dev_priv) && !IS_LP(dev_priv))
>> +
>> +#endif
> _______________________________________________
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Re: [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag

[Joonas Lahtinen]

Quoting Mika Kuoppala (2018-06-08 16:42:03)
> We don't need to have distinct flag for alpha quality if
> we agree that setting the first production revid to be the
> epoch for stepping out from alpha quality on that platform.

Well, I'm hoping we won't be at the phase when the product is shipping
and the field gets populated, but the driver quality is still alpha
where we would need two fields. But this indeed happened with Skylake,
so I would not remove the separation of the fields just in case.

Regards, Joonas
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Re: [PATCH 3/5] drm/i915: Use unknown production revid as alpha quality flag

[Jani Nikula]

On Mon, 11 Jun 2018, Joonas Lahtinen <joonas.lahtinen@linux.intel.com> wrote:
> Quoting Mika Kuoppala (2018-06-08 16:42:03)
>> We don't need to have distinct flag for alpha quality if
>> we agree that setting the first production revid to be the
>> epoch for stepping out from alpha quality on that platform.
>
> Well, I'm hoping we won't be at the phase when the product is shipping
> and the field gets populated, but the driver quality is still alpha
> where we would need two fields. But this indeed happened with Skylake,
> so I would not remove the separation of the fields just in case.

Yeah, please keep them separated, and please keep the name as
IS_ALPHA_SUPPORT. Let's not rename it too often and let's not conflate
this stuff in the interest of letting it sink in what all of these mean.

BR,
Jani.

-- 
Jani Nikula, Intel Open Source Graphics Center
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Re: [PATCH 5/5] drm/i915: Warn on obsolete revision checks

[Jani Nikula]

On Fri, 08 Jun 2018, Mika Kuoppala <mika.kuoppala@linux.intel.com> wrote:
> If we are doing revision checks against a preproduction
> range, when there is already a product, it is a sign
> that there is code to be removed.
>
> Signed-off-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_chipset.h | 30 +++++++++++++++++++++-------
>  1 file changed, 23 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_chipset.h b/drivers/gpu/drm/i915/intel_chipset.h
> index 946c889c0118..bc9ff02dc8df 100644
> --- a/drivers/gpu/drm/i915/intel_chipset.h
> +++ b/drivers/gpu/drm/i915/intel_chipset.h
> @@ -131,6 +131,12 @@
>  #define IS_PREPRODUCTION_HW(dev_priv)   (INTEL_REVID(dev_priv) < FIRST_PRODUCT_REVID(INTEL_INFO(dev_priv)))
>  #define IS_PLATFORM_SUPPORT_ALPHA(intel_info) (FIRST_PRODUCT_REVID(intel_info) == PRODUCT_REVID_UNKNOWN)
>  
> +#define BUILD_BUG_ON_REVID_LT(revid, production_revid) ({ \
> +		BUILD_BUG_ON((production_revid) != PRODUCT_REVID_UNKNOWN && \
> +			     (revid) < (production_revid)); \
> +		1; \
> +	})
> +
>  #define SKL_REVID_A0		0x0
>  #define SKL_REVID_B0		0x1
>  #define SKL_REVID_C0		0x2
> @@ -141,7 +147,9 @@
>  #define SKL_REVID_PRODUCT	SKL_REVID_G0
>  #define SKL_REVID_H0		0x7
>  
> -#define IS_SKL_REVID(p, since, until) (IS_SKYLAKE(p) && IS_REVID(p, since, until))
> +#define IS_SKL_REVID(p, since, until) \
> +	(BUILD_BUG_ON_REVID_LT(until, SKL_REVID_PRODUCT) && \
> +	 IS_SKYLAKE(p) && IS_REVID(p, since, until))
>  
>  #define BXT_REVID_A0		0x0
>  #define BXT_REVID_A1		0x1
> @@ -151,7 +159,8 @@
>  #define BXT_REVID_PRODUCT	BXT_REVID_C0
>  
>  #define IS_BXT_REVID(dev_priv, since, until) \
> -	(IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
> +	(BUILD_BUG_ON_REVID_LT(until, BXT_REVID_PRODUCT) && \
> +	 IS_BROXTON(dev_priv) && IS_REVID(dev_priv, since, until))
>  
>  #define KBL_REVID_A0		0x0
>  #define KBL_REVID_B0		0x1
> @@ -161,29 +170,36 @@
>  #define KBL_REVID_E0		0x4
>  
>  #define IS_KBL_REVID(dev_priv, since, until) \
> -	(IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> +	(BUILD_BUG_ON_REVID_LT(until, KBL_REVID_PRODUCT) && \
> +	 IS_KABYLAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>  
>  #define GLK_REVID_A0		0x0
>  #define GLK_REVID_A1		0x1
> +#define GLK_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
>  
> -#define IS_GLK_REVID(dev_priv, since, until) \
> -	(IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
> +#define IS_GLK_REVID(dev_priv, since, until)		    \
> +	(BUILD_BUG_ON_REVID_LT(until, GLK_REVID_PRODUCT) && \
> +	 IS_GEMINILAKE(dev_priv) && IS_REVID(dev_priv, since, until))
>  
>  #define CNL_REVID_A0		0x0
>  #define CNL_REVID_B0		0x1
>  #define CNL_REVID_C0		0x2
> +#define CNL_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
>  
>  #define IS_CNL_REVID(p, since, until) \
> -	(IS_CANNONLAKE(p) && IS_REVID(p, since, until))
> +	(BUILD_BUG_ON_REVID_LT(until, CNL_REVID_PRODUCT) && \
> +	 IS_CANNONLAKE(p) && IS_REVID(p, since, until))
>  
>  #define ICL_REVID_A0		0x0
>  #define ICL_REVID_A2		0x1
>  #define ICL_REVID_B0		0x3
>  #define ICL_REVID_B2		0x4
>  #define ICL_REVID_C0		0x5
> +#define ICL_REVID_PRODUCT	PRODUCT_REVID_UNKNOWN
>  
>  #define IS_ICL_REVID(p, since, until) \
> -	(IS_ICELAKE(p) && IS_REVID(p, since, until))
> +	(BUILD_BUG_ON_REVID_LT(until, ICL_REVID_PRODUCT) && \
> +	IS_ICELAKE(p) && IS_REVID(p, since, until))

The trouble with this is that it ties the macros *_REVID_PRODUCT to
having to get rid of all the pre-production revid checks. We'll
typically know the product revid *before* we can drop all the
checks. And we can't drop all the checks because there'll be plenty of
hardware to phase out and replace, and it doesn't happen overnight. But
we'd still like to start complaining about the pre-pro hardware use as
soon as possible.

BR,
Jani.

>  
>  /*
>   * The genX designation typically refers to the render engine, so render

-- 
Jani Nikula, Intel Open Source Graphics Center
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