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From: Chris Wilson <chris@chris-wilson.co.uk>
To: intel-gfx@lists.freedesktop.org
Subject: [PATCH 06/17] drm/i915/ringbuffer: Serialize load of PD_DIR
Date: Sun, 10 Jun 2018 20:43:14 +0100	[thread overview]
Message-ID: <20180610194325.13467-7-chris@chris-wilson.co.uk> (raw)
In-Reply-To: <20180610194325.13467-1-chris@chris-wilson.co.uk>

After triggering the mm switch with a load of PD_DIR, which may be
deferred unto the MI_SET_CONTEXT on rcs, serialise the next commands
with that load by posting a read of PD_DIR (or else those subsequent
commands may access the stale page tables).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Matthew Auld <matthew.william.auld@gmail.com>
---
 drivers/gpu/drm/i915/intel_engine_cs.c  |  5 +--
 drivers/gpu/drm/i915/intel_ringbuffer.c | 48 ++++++++++++++++++-------
 drivers/gpu/drm/i915/intel_ringbuffer.h |  5 ++-
 3 files changed, 43 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_engine_cs.c b/drivers/gpu/drm/i915/intel_engine_cs.c
index d1cf8b4926ab..d278fed8cb31 100644
--- a/drivers/gpu/drm/i915/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/intel_engine_cs.c
@@ -499,7 +499,8 @@ void intel_engine_setup_common(struct intel_engine_cs *engine)
 	intel_engine_init_cmd_parser(engine);
 }
 
-int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
+int intel_engine_create_scratch(struct intel_engine_cs *engine,
+				unsigned int size)
 {
 	struct drm_i915_gem_object *obj;
 	struct i915_vma *vma;
@@ -533,7 +534,7 @@ int intel_engine_create_scratch(struct intel_engine_cs *engine, int size)
 	return ret;
 }
 
-static void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
+void intel_engine_cleanup_scratch(struct intel_engine_cs *engine)
 {
 	i915_vma_unpin_and_release(&engine->scratch);
 }
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 7970ecb199e2..66183eb3c102 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -1362,8 +1362,9 @@ intel_ring_context_pin(struct intel_engine_cs *engine,
 
 static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 {
-	struct intel_ring *ring;
 	struct i915_timeline *timeline;
+	struct intel_ring *ring;
+	unsigned int size;
 	int err;
 
 	intel_engine_setup_common(engine);
@@ -1389,12 +1390,21 @@ static int intel_init_ring_buffer(struct intel_engine_cs *engine)
 	GEM_BUG_ON(engine->buffer);
 	engine->buffer = ring;
 
-	err = intel_engine_init_common(engine);
+	size = PAGE_SIZE;
+	if (HAS_BROKEN_CS_TLB(engine->i915))
+		size = I830_WA_SIZE;
+	err = intel_engine_create_scratch(engine, size);
 	if (err)
 		goto err_unpin;
 
+	err = intel_engine_init_common(engine);
+	if (err)
+		goto err_scratch;
+
 	return 0;
 
+err_scratch:
+	intel_engine_cleanup_scratch(engine);
 err_unpin:
 	intel_ring_unpin(ring);
 err_ring:
@@ -1456,6 +1466,24 @@ static int load_pd_dir(struct i915_request *rq,
 	return 0;
 }
 
+static int flush_pd_dir(struct i915_request *rq)
+{
+	const struct intel_engine_cs * const engine = rq->engine;
+	u32 *cs;
+
+	cs = intel_ring_begin(rq, 4);
+	if (IS_ERR(cs))
+		return PTR_ERR(cs);
+
+	*cs++ = MI_STORE_REGISTER_MEM | MI_SRM_LRM_GLOBAL_GTT;
+	*cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine));
+	*cs++ = i915_ggtt_offset(engine->scratch);
+	*cs++ = MI_NOOP;
+
+	intel_ring_advance(rq, cs);
+	return 0;
+}
+
 static inline int mi_set_context(struct i915_request *rq, u32 flags)
 {
 	struct drm_i915_private *i915 = rq->i915;
@@ -1634,6 +1662,12 @@ static int switch_context(struct i915_request *rq)
 			goto err_mm;
 	}
 
+	if (ppgtt) {
+		ret = flush_pd_dir(rq);
+		if (ret)
+			goto err_mm;
+	}
+
 	if (ctx->remap_slice) {
 		for (i = 0; i < MAX_L3_SLICES; i++) {
 			if (!(ctx->remap_slice & BIT(i)))
@@ -2154,16 +2188,6 @@ int intel_init_render_ring_buffer(struct intel_engine_cs *engine)
 	if (ret)
 		return ret;
 
-	if (INTEL_GEN(dev_priv) >= 6) {
-		ret = intel_engine_create_scratch(engine, PAGE_SIZE);
-		if (ret)
-			return ret;
-	} else if (HAS_BROKEN_CS_TLB(dev_priv)) {
-		ret = intel_engine_create_scratch(engine, I830_WA_SIZE);
-		if (ret)
-			return ret;
-	}
-
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h
index 1d8140ac2016..eba271e74c25 100644
--- a/drivers/gpu/drm/i915/intel_ringbuffer.h
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.h
@@ -873,9 +873,12 @@ void intel_engine_init_global_seqno(struct intel_engine_cs *engine, u32 seqno);
 
 void intel_engine_setup_common(struct intel_engine_cs *engine);
 int intel_engine_init_common(struct intel_engine_cs *engine);
-int intel_engine_create_scratch(struct intel_engine_cs *engine, int size);
 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
 
+int intel_engine_create_scratch(struct intel_engine_cs *engine,
+				unsigned int size);
+void intel_engine_cleanup_scratch(struct intel_engine_cs *engine);
+
 int intel_init_render_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine);
 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine);
-- 
2.17.1

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  parent reply	other threads:[~2018-06-10 19:43 UTC|newest]

Thread overview: 44+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-06-10 19:43 Haswell full-ppgtt Chris Wilson
2018-06-10 19:43 ` [PATCH 01/17] drm/i915: Apply batch location restrictions before pinning Chris Wilson
2018-06-11  9:57   ` Joonas Lahtinen
2018-06-11 10:08     ` Chris Wilson
2018-06-10 19:43 ` [PATCH 02/17] drm/i915/ringbuffer: Brute force context restore Chris Wilson
2018-06-11 10:00   ` Tvrtko Ursulin
2018-06-11 10:04     ` Chris Wilson
2018-06-11 10:23       ` Tvrtko Ursulin
2018-06-11 10:33         ` Chris Wilson
2018-06-11 10:07   ` Mika Kuoppala
2018-06-11 10:11   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 03/17] drm/i915/ringbuffer: Fix context restore upon reset Chris Wilson
2018-06-11 10:28   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 04/17] drm/i915: Wrap around the tail offset before setting ring->tail Chris Wilson
2018-06-11 10:16   ` Mika Kuoppala
2018-06-11 10:26     ` Chris Wilson
2018-06-11 10:40       ` Mika Kuoppala
2018-06-11 10:30   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 05/17] drm/i915/gtt: Invalidate GGTT caches after writing the gen6 page directories Chris Wilson
2018-06-11 10:37   ` Joonas Lahtinen
2018-06-10 19:43 ` Chris Wilson [this message]
2018-06-11 10:12   ` [PATCH 06/17] drm/i915/ringbuffer: Serialize load of PD_DIR Chris Wilson
2018-06-11 10:43   ` Joonas Lahtinen
2018-06-11 10:47     ` Chris Wilson
2018-06-10 19:43 ` [PATCH 07/17] drm/i915/gtt: Subclass gen6_hw_ppgtt Chris Wilson
2018-06-10 19:43 ` [PATCH 08/17] drm/i915/gtt: Onionify error handling for gen6_ppgtt_create Chris Wilson
2018-06-11 10:48   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 09/17] drm/i915/gtt: Make gen6 page directories evictable Chris Wilson
2018-06-11 10:56   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 10/17] drm/i915/gtt: Only keep gen6 page directories pinned while active Chris Wilson
2018-06-10 19:43 ` [PATCH 11/17] drm/i915/gtt: Lazily allocate page directories for gen7 Chris Wilson
2018-06-11 11:03   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 12/17] drm/i915/gtt: Free unused page tables on unbind the context Chris Wilson
2018-06-11 11:09   ` Joonas Lahtinen
2018-06-10 19:43 ` [PATCH 13/17] drm/i915/gtt: Skip initializing PT with scratch if full Chris Wilson
2018-06-10 19:43 ` [PATCH 14/17] drm/i915/gtt: Cache the PTE encoding of the scratch page Chris Wilson
2018-06-10 19:43 ` [PATCH 15/17] drm/i915/gtt: Reduce a pair of runtime asserts Chris Wilson
2018-06-10 19:43 ` [PATCH 16/17] drm/i915/gtt: Skip clearing the GGTT under gen6+ full-ppgtt Chris Wilson
2018-06-11  9:28   ` Matthew Auld
2018-06-10 19:43 ` [PATCH 17/17] drm/i915/gtt: Enable full-ppgtt by default everywhere Chris Wilson
2018-06-10 20:00 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/17] drm/i915: Apply batch location restrictions before pinning Patchwork
2018-06-10 20:05 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-06-10 20:18 ` ✓ Fi.CI.BAT: success " Patchwork
2018-06-10 21:10 ` ✓ Fi.CI.IGT: " Patchwork

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