* [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96
@ 2018-06-11 4:42 Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family Manivannan Sadhasivam
` (8 more replies)
0 siblings, 9 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:42 UTC (permalink / raw)
To: u-boot
This patchset adds SoC support for Actions Semi S900 SoC and ucRobotics
Bubblegum-96 board along with UART and Clock drivers.
S900 SoC consists of 4 ARM Cortex-A53 cores up to 1.8GHz with
Imagination Power VR G6230 GPU. More information on this SoC can be
found in Actions Semi product page:
http://www.actions-semi.com/en/productview.aspx?id=204
Bubblegum-96 board is one of the 96Boards Consumer Edition platform
based on S900 SoC. This board has 2GB LPDDR3 operating at 533 MHz and
8GB eMMC along with other peripherals required by 96Boards Consumer
Edition Specification. More information on this board can be found in
96Boards product page.
https://www.96boards.org/product/bubblegum-96/
Most of the code is based on Actions tree found here:
https://github.com/96boards-bubblegum/u-boot/
With this patchset, Bubblegum-96 board can boot into U-Boot shell.
Thanks,
Mani
Manivannan Sadhasivam (9):
arm: Add support for Actions Semi OWL SoC family
board: Add uCRobotics Bubblegum-96 board support
dt-bindings: clock: Add S900 CMU register definitions
arm: dts: s900: Add Clock Management Unit (CMU) nodes
clk: Add Actions Semi OWL clock support
arm: dts: s900: Add UART node
arm: dts: bubblegum_96: Enable UART5 for serial console
serial: Add Actions Semi OWL UART support
MAINTAINERS: Add entries for Actions Semi OWL family
MAINTAINERS | 9 ++
arch/arm/Kconfig | 10 ++
arch/arm/Makefile | 1 +
arch/arm/dts/bubblegum_96.dts | 31 +++++
arch/arm/dts/s900.dtsi | 53 ++++++++
arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++
arch/arm/include/asm/arch-owl/regs_s900.h | 64 +++++++++
arch/arm/mach-owl/Kconfig | 27 ++++
arch/arm/mach-owl/Makefile | 3 +
arch/arm/mach-owl/sysmap-s900.c | 32 +++++
board/ucRobotics/bubblegum_96/Kconfig | 15 ++
board/ucRobotics/bubblegum_96/MAINTAINERS | 6 +
board/ucRobotics/bubblegum_96/Makefile | 3 +
board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 ++++++++
configs/bubblegum_96_defconfig | 22 +++
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/owl/Kconfig | 12 ++
drivers/clk/owl/Makefile | 4 +
drivers/clk/owl/clk_owl.c | 60 ++++++++
drivers/clk/owl/clk_s900.c | 104 ++++++++++++++
drivers/serial/Kconfig | 8 ++
drivers/serial/Makefile | 1 +
drivers/serial/serial_owl.c | 136 +++++++++++++++++++
include/configs/bubblegum_96.h | 43 ++++++
include/dt-bindings/clock/s900_cmu.h | 77 +++++++++++
26 files changed, 840 insertions(+)
create mode 100644 arch/arm/dts/bubblegum_96.dts
create mode 100644 arch/arm/dts/s900.dtsi
create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h
create mode 100644 arch/arm/include/asm/arch-owl/regs_s900.h
create mode 100644 arch/arm/mach-owl/Kconfig
create mode 100644 arch/arm/mach-owl/Makefile
create mode 100644 arch/arm/mach-owl/sysmap-s900.c
create mode 100644 board/ucRobotics/bubblegum_96/Kconfig
create mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS
create mode 100644 board/ucRobotics/bubblegum_96/Makefile
create mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c
create mode 100644 configs/bubblegum_96_defconfig
create mode 100644 drivers/clk/owl/Kconfig
create mode 100644 drivers/clk/owl/Makefile
create mode 100644 drivers/clk/owl/clk_owl.c
create mode 100644 drivers/clk/owl/clk_s900.c
create mode 100644 drivers/serial/serial_owl.c
create mode 100644 include/configs/bubblegum_96.h
create mode 100644 include/dt-bindings/clock/s900_cmu.h
--
2.17.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
@ 2018-06-11 4:42 ` Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 2/9] board: Add uCRobotics Bubblegum-96 board support Manivannan Sadhasivam
` (7 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:42 UTC (permalink / raw)
To: u-boot
This commit adds Actions Semi OWL SoC family support with S900 as the
first target SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/Kconfig | 9 +++++++++
arch/arm/Makefile | 1 +
arch/arm/dts/s900.dtsi | 23 +++++++++++++++++++++++
arch/arm/mach-owl/Kconfig | 6 ++++++
arch/arm/mach-owl/Makefile | 3 +++
arch/arm/mach-owl/sysmap-s900.c | 32 ++++++++++++++++++++++++++++++++
6 files changed, 74 insertions(+)
create mode 100644 arch/arm/dts/s900.dtsi
create mode 100644 arch/arm/mach-owl/Kconfig
create mode 100644 arch/arm/mach-owl/Makefile
create mode 100644 arch/arm/mach-owl/sysmap-s900.c
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index dde422bc5d..ec0bb5a42b 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -699,6 +699,13 @@ config ARCH_MX5
select BOARD_EARLY_INIT_F
imply MXC_GPIO
+config ARCH_OWL
+ bool "Actions Semi OWL SoCs"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ select OF_CONTROL
+
config ARCH_QEMU
bool "QEMU Virtual Platform"
select DM
@@ -1335,6 +1342,8 @@ source "arch/arm/cpu/armv8/fsl-layerscape/Kconfig"
source "arch/arm/mach-orion5x/Kconfig"
+source "arch/arm/mach-owl/Kconfig"
+
source "arch/arm/mach-rmobile/Kconfig"
source "arch/arm/mach-meson/Kconfig"
diff --git a/arch/arm/Makefile b/arch/arm/Makefile
index 680c6e8516..f15b2287df 100644
--- a/arch/arm/Makefile
+++ b/arch/arm/Makefile
@@ -66,6 +66,7 @@ machine-$(CONFIG_ARCH_MVEBU) += mvebu
# TODO: rename CONFIG_ORION5X -> CONFIG_ARCH_ORION5X
machine-$(CONFIG_ORION5X) += orion5x
machine-$(CONFIG_ARCH_OMAP2PLUS) += omap2
+machine-$(CONFIG_ARCH_OWL) += owl
machine-$(CONFIG_ARCH_S5PC1XX) += s5pc1xx
machine-$(CONFIG_ARCH_SUNXI) += sunxi
machine-$(CONFIG_ARCH_SNAPDRAGON) += snapdragon
diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi
new file mode 100644
index 0000000000..3bd14b82d4
--- /dev/null
+++ b/arch/arm/dts/s900.dtsi
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree Source for Actions Semi S900 SoC
+//
+// Copyright (C) 2015 Actions Semi Co., Ltd.
+// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+/dts-v1/;
+
+/ {
+ compatible = "actions,s900";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+
+ soc {
+ u-boot,dm-pre-reloc;
+ compatible = "simple-bus";
+ #address-cells = <0x2>;
+ #size-cells = <0x2>;
+ ranges;
+ };
+};
+
diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
new file mode 100644
index 0000000000..f695c16d1e
--- /dev/null
+++ b/arch/arm/mach-owl/Kconfig
@@ -0,0 +1,6 @@
+if ARCH_OWL
+
+config SYS_SOC
+ default "owl"
+
+endif
diff --git a/arch/arm/mach-owl/Makefile b/arch/arm/mach-owl/Makefile
new file mode 100644
index 0000000000..1b43dc2921
--- /dev/null
+++ b/arch/arm/mach-owl/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y += sysmap-s900.o
diff --git a/arch/arm/mach-owl/sysmap-s900.c b/arch/arm/mach-owl/sysmap-s900.c
new file mode 100644
index 0000000000..f78b639740
--- /dev/null
+++ b/arch/arm/mach-owl/sysmap-s900.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi S900 Memory map
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region s900_mem_map[] = {
+ {
+ .virt = 0x0UL, /* DDR */
+ .phys = 0x0UL, /* DDR */
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xE0000000UL, /* Peripheral block */
+ .phys = 0xE0000000UL, /* Peripheral block */
+ .size = 0x08000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = s900_mem_map;
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 2/9] board: Add uCRobotics Bubblegum-96 board support
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family Manivannan Sadhasivam
@ 2018-06-11 4:42 ` Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 3/9] dt-bindings: clock: Add S900 CMU register definitions Manivannan Sadhasivam
` (6 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:42 UTC (permalink / raw)
To: u-boot
This commit adds uCRobotics Bubblegum-96 board support. This board is
one of the 96Boards Consumer Edition platform based on Actions Semi
S900 SoC.
Features:
- Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
- 2GiB RAM
- 8GiB eMMC, uSD slot
- WiFi, Bluetooth and GPS module
- 2x Host, 1x Device USB port
- HDMI
- 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
U-Boot will be loaded by ATF at EL2 execution level. Relevant driver
support will be added in further commits.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/Kconfig | 1 +
arch/arm/dts/bubblegum_96.dts | 19 +++++++
arch/arm/mach-owl/Kconfig | 21 ++++++++
board/ucRobotics/bubblegum_96/Kconfig | 15 ++++++
board/ucRobotics/bubblegum_96/MAINTAINERS | 6 +++
board/ucRobotics/bubblegum_96/Makefile | 3 ++
board/ucRobotics/bubblegum_96/bubblegum_96.c | 56 ++++++++++++++++++++
configs/bubblegum_96_defconfig | 22 ++++++++
include/configs/bubblegum_96.h | 43 +++++++++++++++
9 files changed, 186 insertions(+)
create mode 100644 arch/arm/dts/bubblegum_96.dts
create mode 100644 board/ucRobotics/bubblegum_96/Kconfig
create mode 100644 board/ucRobotics/bubblegum_96/MAINTAINERS
create mode 100644 board/ucRobotics/bubblegum_96/Makefile
create mode 100644 board/ucRobotics/bubblegum_96/bubblegum_96.c
create mode 100644 configs/bubblegum_96_defconfig
create mode 100644 include/configs/bubblegum_96.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index ec0bb5a42b..6e203f96aa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -1431,6 +1431,7 @@ source "board/spear/spear600/Kconfig"
source "board/spear/x600/Kconfig"
source "board/st/stv0991/Kconfig"
source "board/tcl/sl50/Kconfig"
+source "board/ucRobotics/bubblegum_96/Kconfig"
source "board/birdland/bav335x/Kconfig"
source "board/timll/devkit3250/Kconfig"
source "board/toradex/colibri_pxa270/Kconfig"
diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts
new file mode 100644
index 0000000000..4e34ebaa49
--- /dev/null
+++ b/arch/arm/dts/bubblegum_96.dts
@@ -0,0 +1,19 @@
+// SPDX-License-Identifier: GPL-2.0+
+//
+// Device Tree Source for Bubblegum-96
+//
+// Copyright (C) 2015 Actions Semi Co., Ltd.
+// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+
+/dts-v1/;
+#include "s900.dtsi"
+
+/ {
+ model = "Bubblegum-96";
+ compatible = "ucrobotics,bubblegum-96", "actions,s900";
+
+ memory at 0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+};
diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index f695c16d1e..b0b506dbb4 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -3,4 +3,25 @@ if ARCH_OWL
config SYS_SOC
default "owl"
+choice
+ prompt "Actions OWL SoCs board select"
+ optional
+
+config TARGET_BUBBLEGUM_96
+ bool "96Boards Bubblegum-96"
+ help
+ Support for 96Boards Bubblegum-96. This board complies with
+ 96Board Consumer Edition Specification. Features:
+ - Actions Semi S900 SoC (4xCortex A53, Power VR G6230 GPU)
+ - 2GiB RAM
+ - 8GiB eMMC, uSD slot
+ - WiFi, Bluetooth and GPS module
+ - 2x Host, 1x Device USB port
+ - HDMI
+ - 20-pin low speed and 40-pin high speed expanders, 6 LED, 3 buttons
+
+endchoice
+
+source "board/ucRobotics/bubblegum_96/Kconfig"
+
endif
diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig
new file mode 100644
index 0000000000..2dd40d9b6a
--- /dev/null
+++ b/board/ucRobotics/bubblegum_96/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_BUBBLEGUM_96
+
+config SYS_BOARD
+ default "bubblegum_96"
+
+config SYS_VENDOR
+ default "ucRobotics"
+
+config SYS_SOC
+ default "s900"
+
+config SYS_CONFIG_NAME
+ default "bubblegum_96"
+
+endif
diff --git a/board/ucRobotics/bubblegum_96/MAINTAINERS b/board/ucRobotics/bubblegum_96/MAINTAINERS
new file mode 100644
index 0000000000..d0cb7278c6
--- /dev/null
+++ b/board/ucRobotics/bubblegum_96/MAINTAINERS
@@ -0,0 +1,6 @@
+BUBBLEGUM_96 BOARD
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: board/ucRobotics/bubblegum_96/
+F: include/configs/bubblegum_96.h
+F: configs/bubblegum_96_defconfig
diff --git a/board/ucRobotics/bubblegum_96/Makefile b/board/ucRobotics/bubblegum_96/Makefile
new file mode 100644
index 0000000000..c4b524def2
--- /dev/null
+++ b/board/ucRobotics/bubblegum_96/Makefile
@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-y := bubblegum_96.o
diff --git a/board/ucRobotics/bubblegum_96/bubblegum_96.c b/board/ucRobotics/bubblegum_96/bubblegum_96.c
new file mode 100644
index 0000000000..a4c202da19
--- /dev/null
+++ b/board/ucRobotics/bubblegum_96/bubblegum_96.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Bubblegum-96 Boards Support
+ *
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <linux/arm-smccc.h>
+#include <linux/psci.h>
+#include <common.h>
+#include <asm/io.h>
+#include <asm/mach-types.h>
+#include <asm/psci.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+/*
+ * dram_init - sets uboots idea of sdram size
+ */
+int dram_init(void)
+{
+ gd->ram_size = CONFIG_SYS_SDRAM_SIZE;
+ return 0;
+}
+
+/* This is called after dram_init() so use get_ram_size result */
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+ gd->bd->bi_dram[0].size = gd->ram_size;
+
+ return 0;
+}
+
+static void show_psci_version(void)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
+
+ printf("PSCI: v%ld.%ld\n",
+ PSCI_VERSION_MAJOR(res.a0),
+ PSCI_VERSION_MINOR(res.a0));
+}
+
+int board_init(void)
+{
+ show_psci_version();
+
+ return 0;
+}
+
+void reset_cpu(ulong addr)
+{
+ psci_system_reset();
+}
diff --git a/configs/bubblegum_96_defconfig b/configs/bubblegum_96_defconfig
new file mode 100644
index 0000000000..a2bd7e80e2
--- /dev/null
+++ b/configs/bubblegum_96_defconfig
@@ -0,0 +1,22 @@
+CONFIG_ARM=y
+CONFIG_ARCH_OWL=y
+CONFIG_TARGET_BUBBLEGUM_96=y
+CONFIG_SYS_TEXT_BASE=0x11000000
+CONFIG_IDENT_STRING="\nBubblegum-96"
+CONFIG_DEFAULT_DEVICE_TREE="bubblegum_96"
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_USE_BOOTARGS=y
+CONFIG_ARM_SMCCC=y
+CONFIG_BOOTARGS="console=ttyOWL5,115200n8"
+CONFIG_BOOTDELAY=5
+CONFIG_SYS_PROMPT="U-Boot => "
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_CMD_MD5SUM=y
+CONFIG_CMD_MEMINFO=y
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_TIMER=y
+CONFIG_CLK=y
+CONFIG_CLK_OWL=y
+CONFIG_CLK_S900=y
+CONFIG_OWL_SERIAL=y
diff --git a/include/configs/bubblegum_96.h b/include/configs/bubblegum_96.h
new file mode 100644
index 0000000000..a8f38a23f9
--- /dev/null
+++ b/include/configs/bubblegum_96.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Board configuration file for Bubblegum-96
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _BUBBLEGUM_96_H_
+#define _BUGGLEGUM_96_H_
+
+/* SDRAM Definitions */
+#define CONFIG_SYS_SDRAM_BASE 0x0
+#define CONFIG_NR_DRAM_BANKS 1
+#define CONFIG_SYS_SDRAM_SIZE 0x80000000
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (24000000) /* 24MHz */
+
+#define CONFIG_SYS_MALLOC_LEN (32 * 1024 * 1024)
+
+/* Some commands use this as the default load address */
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x7ffc0)
+
+/*
+ * This is the initial SP which is used only briefly for relocating the u-boot
+ * image to the top of SDRAM. After relocation u-boot moves the stack to the
+ * proper place.
+ */
+#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x7ff00)
+
+/* UART Definitions */
+#define CONFIG_BAUDRATE 115200
+
+#define CONFIG_ENV_SIZE 0x2000
+
+/* Console configuration */
+#define CONFIG_SYS_CBSIZE 1024 /* Console buffer size */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 3/9] dt-bindings: clock: Add S900 CMU register definitions
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 2/9] board: Add uCRobotics Bubblegum-96 board support Manivannan Sadhasivam
@ 2018-06-11 4:42 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes Manivannan Sadhasivam
` (5 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:42 UTC (permalink / raw)
To: u-boot
This commit adds Actions Semi S900 CMU register definitions to clock
bindings.
---
include/dt-bindings/clock/s900_cmu.h | 77 ++++++++++++++++++++++++++++
1 file changed, 77 insertions(+)
create mode 100644 include/dt-bindings/clock/s900_cmu.h
diff --git a/include/dt-bindings/clock/s900_cmu.h b/include/dt-bindings/clock/s900_cmu.h
new file mode 100644
index 0000000000..2685a6df4a
--- /dev/null
+++ b/include/dt-bindings/clock/s900_cmu.h
@@ -0,0 +1,77 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_S900_CMU_H_
+#define _DT_BINDINGS_CLOCK_S900_CMU_H_
+
+/* Module Clock ID */
+#define CLOCK_DDRCH1 0
+#define CLOCK_DMAC 1
+#define CLOCK_DDRCH0 2
+#define CLOCK_BROM 3
+#define CLOCK_NANDC0 4
+#define CLOCK_SD0 5
+#define CLOCK_SD1 6
+#define CLOCK_SD2 7
+#define CLOCK_DE 8
+#define CLOCK_LVDS 9
+#define CLOCK_EDP 10
+#define CLOCK_NANDC1 11
+#define CLOCK_DSI 12
+#define CLOCK_CSI0 13
+#define CLOCK_BISP 14
+#define CLOCK_CSI1 15
+#define CLOCK_SD3 16
+#define CLOCK_I2C4 17
+#define CLOCK_GPIO 18
+#define CLOCK_DMM 19
+#define CLOCK_I2STX 20
+#define CLOCK_I2SRX 21
+#define CLOCK_HDMIA 22
+#define CLOCK_SPDIF 23
+#define CLOCK_PCM0 24
+#define CLOCK_VDE 25
+#define CLOCK_VCE 26
+#define CLOCK_HDE 27
+#define CLOCK_SHARESRAM 28
+#define CLOCK_CMU_DDR1 29
+#define CLOCK_GPU3D 30
+#define CLOCK_CMUDDR0 31
+#define CLOCK_SPEED 32
+#define CLOCK_I2C5 33
+#define CLOCK_THERMAL 34
+#define CLOCK_HDMI 35
+#define CLOCK_PWM4 36
+#define CLOCK_PWM5 37
+#define CLOCK_UART0 38
+#define CLOCK_UART1 39
+#define CLOCK_UART2 40
+#define CLOCK_IRC 41
+#define CLOCK_SPI0 42
+#define CLOCK_SPI1 43
+#define CLOCK_SPI2 44
+#define CLOCK_SPI3 45
+#define CLOCK_I2C0 46
+#define CLOCK_I2C1 47
+#define CLOCK_PCM1 48
+#define CLOCK_IMX 49
+#define CLOCK_UART6 50
+#define CLOCK_UART3 51
+#define CLOCK_UART4 52
+#define CLOCK_UART5 53
+#define CLOCK_ETHERNET 54
+#define CLOCK_PWM0 55
+#define CLOCK_PWM1 56
+#define CLOCK_PWM2 57
+#define CLOCK_PWM3 58
+#define CLOCK_TIMER 59
+#define CLOCK_SE 60
+#define CLOCK_HDCP2TX 61
+#define CLOCK_I2C2 62
+#define CLOCK_I2C3 63
+
+#endif
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (2 preceding siblings ...)
2018-06-11 4:42 ` [U-Boot] [PATCH 3/9] dt-bindings: clock: Add S900 CMU register definitions Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 5/9] clk: Add Actions Semi OWL clock support Manivannan Sadhasivam
` (4 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
This commit adds Clock Management Unit (CMU) nodes for Actions Semi
S900 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/dts/s900.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi
index 3bd14b82d4..e9d47b1ff1 100644
--- a/arch/arm/dts/s900.dtsi
+++ b/arch/arm/dts/s900.dtsi
@@ -6,18 +6,40 @@
// Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
/dts-v1/;
+#include <dt-bindings/clock/s900_cmu.h>
/ {
compatible = "actions,s900";
#address-cells = <0x2>;
#size-cells = <0x2>;
+ losc: losc {
+ compatible = "fixed-clock";
+ clock-frequency = <32768>;
+ #clock-cells = <0>;
+ };
+
+ diff24M: diff24M {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ #clock-cells = <0>;
+ };
+
soc {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
+
+ cmu: clock-controller at e0160000 {
+ u-boot,dm-pre-reloc;
+ compatible = "actions,s900-cmu";
+ reg = <0x0 0xe0160000 0x0 0x1000>;
+ clocks = <&losc>, <&diff24M>;
+ clock-names = "losc", "diff24M";
+ #clock-cells = <1>;
+ };
};
};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 5/9] clk: Add Actions Semi OWL clock support
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (3 preceding siblings ...)
2018-06-11 4:43 ` [U-Boot] [PATCH 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 6/9] arm: dts: s900: Add UART node Manivannan Sadhasivam
` (3 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
This commit adds Actions Semi OWL family base clock and S900 SoC specific
clock support. For S900 peripheral clock support, only UART clock has been
added for now.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/include/asm/arch-owl/clk_owl.h | 61 +++++++++++++
arch/arm/include/asm/arch-owl/regs_s900.h | 64 +++++++++++++
arch/arm/mach-owl/Kconfig | 2 +-
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/owl/Kconfig | 12 +++
drivers/clk/owl/Makefile | 4 +
drivers/clk/owl/clk_owl.c | 60 +++++++++++++
drivers/clk/owl/clk_s900.c | 104 ++++++++++++++++++++++
9 files changed, 308 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/include/asm/arch-owl/clk_owl.h
create mode 100644 arch/arm/include/asm/arch-owl/regs_s900.h
create mode 100644 drivers/clk/owl/Kconfig
create mode 100644 drivers/clk/owl/Makefile
create mode 100644 drivers/clk/owl/clk_owl.c
create mode 100644 drivers/clk/owl/clk_s900.c
diff --git a/arch/arm/include/asm/arch-owl/clk_owl.h b/arch/arm/include/asm/arch-owl/clk_owl.h
new file mode 100644
index 0000000000..1ad8e80e28
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/clk_owl.h
@@ -0,0 +1,61 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi OWL Clock Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_CLK_OWL_H_
+#define _OWL_CLK_OWL_H_
+
+#include <clk-uclass.h>
+
+struct owl_clk_priv {
+ phys_addr_t base;
+};
+
+/* BUSCLK register definitions */
+#define CMU_PDBGDIV_8 7
+#define CMU_PDBGDIV_SHIFT 26
+#define CMU_PDBGDIV_DIV (CMU_PDBGDIV_8 << CMU_PDBGDIV_SHIFT)
+#define CMU_PERDIV_8 7
+#define CMU_PERDIV_SHIFT 20
+#define CMU_PERDIV_DIV (CMU_PERDIV_8 << CMU_PERDIV_SHIFT)
+#define CMU_NOCDIV_2 1
+#define CMU_NOCDIV_SHIFT 19
+#define CMU_NOCDIV_DIV (CMU_NOCDIV_2 << CMU_NOCDIV_SHIFT)
+#define CMU_DMMCLK_SRC_APLL 2
+#define CMU_DMMCLK_SRC_SHIFT 10
+#define CMU_DMMCLK_SRC (CMU_DMMCLK_SRC_APLL << CMU_DMMCLK_SRC_SHIFT)
+#define CMU_APBCLK_DIV BIT(8)
+#define CMU_NOCCLK_SRC BIT(7)
+#define CMU_AHBCLK_DIV BIT(4)
+#define CMU_CORECLK_MASK 3
+#define CMU_CORECLK_CPLL BIT(1)
+#define CMU_CORECLK_HOSC BIT(0)
+
+/* COREPLL register definitions */
+#define CMU_COREPLL_EN BIT(9)
+#define CMU_COREPLL_HOSC_EN BIT(8)
+#define CMU_COREPLL_OUT (1104 / 24)
+
+/* DEVPLL register definitions */
+#define CMU_DEVPLL_CLK BIT(12)
+#define CMU_DEVPLL_EN BIT(8)
+#define CMU_DEVPLL_OUT (660 / 6)
+
+/* UARTCLK register definitions */
+#define CMU_UARTCLK_SRC_DEVPLL BIT(16)
+
+/* DEVCLKEN1 register definitions */
+#define CMU_DEVCLKEN1_UART5 BIT(21)
+
+#define PLL_STABILITY_WAIT_US 50
+
+void owl_clk_init(struct owl_clk_priv *priv);
+int owl_periph_clk_enable(struct clk *clk);
+int owl_periph_clk_disable(struct clk *clk);
+
+#endif
diff --git a/arch/arm/include/asm/arch-owl/regs_s900.h b/arch/arm/include/asm/arch-owl/regs_s900.h
new file mode 100644
index 0000000000..9e9106ddaa
--- /dev/null
+++ b/arch/arm/include/asm/arch-owl/regs_s900.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Actions Semi S900 Register Definitions
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ *
+ */
+
+#ifndef _OWL_REGS_S900_H_
+#define _OWL_REGS_S900_H_
+
+/* CMU registers */
+#define CMU_COREPLL (0x0000)
+#define CMU_DEVPLL (0x0004)
+#define CMU_DDRPLL (0x0008)
+#define CMU_NANDPLL (0x000C)
+#define CMU_DISPLAYPLL (0x0010)
+#define CMU_AUDIOPLL (0x0014)
+#define CMU_TVOUTPLL (0x0018)
+#define CMU_BUSCLK (0x001C)
+#define CMU_SENSORCLK (0x0020)
+#define CMU_LCDCLK (0x0024)
+#define CMU_DSICLK (0x0028)
+#define CMU_CSICLK (0x002C)
+#define CMU_DECLK (0x0030)
+#define CMU_BISPCLK (0x0034)
+#define CMU_IMXCLK (0x0038)
+#define CMU_HDECLK (0x003C)
+#define CMU_VDECLK (0x0040)
+#define CMU_VCECLK (0x0044)
+#define CMU_NANDCCLK (0x004C)
+#define CMU_SD0CLK (0x0050)
+#define CMU_SD1CLK (0x0054)
+#define CMU_SD2CLK (0x0058)
+#define CMU_UART0CLK (0x005C)
+#define CMU_UART1CLK (0x0060)
+#define CMU_UART2CLK (0x0064)
+#define CMU_PWM0CLK (0x0070)
+#define CMU_PWM1CLK (0x0074)
+#define CMU_PWM2CLK (0x0078)
+#define CMU_PWM3CLK (0x007C)
+#define CMU_USBPLL (0x0080)
+#define CMU_ASSISTPLL (0x0084)
+#define CMU_EDPCLK (0x0088)
+#define CMU_GPU3DCLK (0x0090)
+#define CMU_CORECTL (0x009C)
+#define CMU_DEVCLKEN0 (0x00A0)
+#define CMU_DEVCLKEN1 (0x00A4)
+#define CMU_DEVRST0 (0x00A8)
+#define CMU_DEVRST1 (0x00AC)
+#define CMU_UART3CLK (0x00B0)
+#define CMU_UART4CLK (0x00B4)
+#define CMU_UART5CLK (0x00B8)
+#define CMU_UART6CLK (0x00BC)
+#define CMU_TLSCLK (0x00C0)
+#define CMU_SD3CLK (0x00C4)
+#define CMU_PWM4CLK (0x00C8)
+#define CMU_PWM5CLK (0x00CC)
+#define CMU_ANALOGDEBUG (0x00D4)
+#define CMU_TVOUTPLLDEBUG0 (0x00EC)
+#define CMU_TVOUTPLLDEBUG1 (0x00FC)
+
+#endif
diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index b0b506dbb4..199e772988 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -4,7 +4,7 @@ config SYS_SOC
default "owl"
choice
- prompt "Actions OWL SoCs board select"
+ prompt "Actions Semi OWL SoCs board select"
optional
config TARGET_BUBBLEGUM_96
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index edb4ca58ea..18bf8a6d28 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -89,6 +89,7 @@ source "drivers/clk/exynos/Kconfig"
source "drivers/clk/at91/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/mvebu/Kconfig"
+source "drivers/clk/owl/Kconfig"
config ICS8N3QV01
bool "Enable ICS8N3QV01 VCXO driver"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 58139b13a8..078f8d7ae1 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -16,6 +16,7 @@ obj-$(CONFIG_CLK_BCM6345) += clk_bcm6345.o
obj-$(CONFIG_CLK_BOSTON) += clk_boston.o
obj-$(CONFIG_CLK_EXYNOS) += exynos/
obj-$(CONFIG_CLK_HSDK) += clk-hsdk-cgu.o
+obj-$(CONFIG_CLK_OWL) += owl/
obj-$(CONFIG_CLK_RENESAS) += renesas/
obj-$(CONFIG_CLK_STM32F) += clk_stm32f.o
obj-$(CONFIG_CLK_STM32MP1) += clk_stm32mp1.o
diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig
new file mode 100644
index 0000000000..661f1981b9
--- /dev/null
+++ b/drivers/clk/owl/Kconfig
@@ -0,0 +1,12 @@
+config CLK_OWL
+ bool "Actions Semi OWL clock drivers"
+ depends on CLK && ARCH_OWL
+ help
+ Enable support for clock managemet unit present in Actions Semi
+ OWL SoCs.
+
+config CLK_S900
+ bool "Actions Semi S900 clock driver"
+ depends on CLK_OWL && ARM64
+ help
+ Enable support for the clocks in Actions Semi S900 SoC.
diff --git a/drivers/clk/owl/Makefile b/drivers/clk/owl/Makefile
new file mode 100644
index 0000000000..b21f23002d
--- /dev/null
+++ b/drivers/clk/owl/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+obj-$(CONFIG_CLK_OWL) += clk_owl.o
+obj-$(CONFIG_CLK_S900) += clk_s900.o
diff --git a/drivers/clk/owl/clk_owl.c b/drivers/clk/owl/clk_owl.c
new file mode 100644
index 0000000000..c289825dab
--- /dev/null
+++ b/drivers/clk/owl/clk_owl.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi OWL SoCs Clock driver
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <asm/arch-owl/clk_owl.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+static int owl_clk_probe(struct udevice *dev)
+{
+ struct owl_clk_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ /* setup necessary clocks */
+ owl_clk_init(priv);
+
+ return 0;
+}
+
+static int owl_clk_enable(struct clk *clk)
+{
+ return owl_periph_clk_enable(clk);
+}
+
+static int owl_clk_disable(struct clk *clk)
+{
+ return owl_periph_clk_disable(clk);
+}
+
+static struct clk_ops owl_clk_ops = {
+ .enable = owl_clk_enable,
+ .disable = owl_clk_disable,
+};
+
+static const struct udevice_id owl_clk_ids[] = {
+ { .compatible = "actions,s900-cmu" },
+ { }
+};
+
+U_BOOT_DRIVER(clk_owl) = {
+ .name = "clk_owl",
+ .id = UCLASS_CLK,
+ .of_match = owl_clk_ids,
+ .ops = &owl_clk_ops,
+ .priv_auto_alloc_size = sizeof(struct owl_clk_priv),
+ .probe = owl_clk_probe,
+ .flags = DM_FLAG_PRE_RELOC,
+};
diff --git a/drivers/clk/owl/clk_s900.c b/drivers/clk/owl/clk_s900.c
new file mode 100644
index 0000000000..8fe225b0de
--- /dev/null
+++ b/drivers/clk/owl/clk_s900.c
@@ -0,0 +1,104 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi S900 clock driver
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/arch-owl/clk_owl.h>
+#include <asm/arch-owl/regs_s900.h>
+#include <asm/io.h>
+
+#include <dt-bindings/clock/s900_cmu.h>
+
+void owl_clk_init(struct owl_clk_priv *priv)
+{
+ u32 bus_clk = 0, core_pll, dev_pll;
+
+ /* Enable ASSIST_PLL */
+ setbits_le32(priv->base + CMU_ASSISTPLL, BIT(0));
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Source HOSC to DEV_CLK */
+ clrbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+ /* Configure BUS_CLK */
+ bus_clk |= (CMU_PDBGDIV_DIV | CMU_PERDIV_DIV | CMU_NOCDIV_DIV |
+ CMU_DMMCLK_SRC | CMU_APBCLK_DIV | CMU_AHBCLK_DIV |
+ CMU_NOCCLK_SRC | CMU_CORECLK_HOSC);
+ writel(bus_clk, priv->base + CMU_BUSCLK);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Configure CORE_PLL */
+ core_pll = readl(priv->base + CMU_COREPLL);
+ core_pll |= (CMU_COREPLL_EN | CMU_COREPLL_HOSC_EN | CMU_COREPLL_OUT);
+ writel(core_pll, priv->base + CMU_COREPLL);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Configure DEV_PLL */
+ dev_pll = readl(priv->base + CMU_DEVPLL);
+ dev_pll |= (CMU_DEVPLL_EN | CMU_DEVPLL_OUT);
+ writel(dev_pll, priv->base + CMU_DEVPLL);
+
+ udelay(PLL_STABILITY_WAIT_US);
+
+ /* Source CORE_PLL for CORE_CLK */
+ clrsetbits_le32(priv->base + CMU_BUSCLK, CMU_CORECLK_MASK,
+ CMU_CORECLK_CPLL);
+
+ /* Source DEV_PLL for DEV_CLK */
+ setbits_le32(priv->base + CMU_DEVPLL, CMU_DEVPLL_CLK);
+
+ udelay(PLL_STABILITY_WAIT_US);
+}
+
+void owl_uart_clk_enable(struct owl_clk_priv *priv)
+{
+ /* Source HOSC for UART5 interface */
+ clrbits_le32(priv->base + CMU_UART5CLK, CMU_UARTCLK_SRC_DEVPLL);
+
+ /* Enable UART5 interface clock */
+ setbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+}
+
+void owl_uart_clk_disable(struct owl_clk_priv *priv)
+{
+ /* Disable UART5 interface clock */
+ clrbits_le32(priv->base + CMU_DEVCLKEN1, CMU_DEVCLKEN1_UART5);
+}
+
+int owl_periph_clk_enable(struct clk *clk)
+{
+ struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLOCK_UART5:
+ owl_uart_clk_enable(priv);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
+
+int owl_periph_clk_disable(struct clk *clk)
+{
+ struct owl_clk_priv *priv = dev_get_priv(clk->dev);
+
+ switch (clk->id) {
+ case CLOCK_UART5:
+ owl_uart_clk_disable(priv);
+ break;
+ default:
+ return 0;
+ }
+
+ return 0;
+}
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 6/9] arm: dts: s900: Add UART node
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (4 preceding siblings ...)
2018-06-11 4:43 ` [U-Boot] [PATCH 5/9] clk: Add Actions Semi OWL clock support Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console Manivannan Sadhasivam
` (2 subsequent siblings)
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
This commit adds UART node for Actions Semi S900 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/dts/s900.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/s900.dtsi b/arch/arm/dts/s900.dtsi
index e9d47b1ff1..2bbb30a5a8 100644
--- a/arch/arm/dts/s900.dtsi
+++ b/arch/arm/dts/s900.dtsi
@@ -32,6 +32,14 @@
#size-cells = <0x2>;
ranges;
+ uart5: serial at e012a000 {
+ u-boot,dm-pre-reloc;
+ compatible = "actions,s900-serial";
+ reg = <0x0 0xe012a000 0x0 0x1000>;
+ clocks = <&cmu CLOCK_UART5>;
+ status = "disabled";
+ };
+
cmu: clock-controller at e0160000 {
u-boot,dm-pre-reloc;
compatible = "actions,s900-cmu";
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (5 preceding siblings ...)
2018-06-11 4:43 ` [U-Boot] [PATCH 6/9] arm: dts: s900: Add UART node Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 8/9] serial: Add Actions Semi OWL UART support Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 9/9] MAINTAINERS: Add entries for Actions Semi OWL family Manivannan Sadhasivam
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
This commit enables UART5 found in S900 SoC for serial console support.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
arch/arm/dts/bubblegum_96.dts | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/bubblegum_96.dts b/arch/arm/dts/bubblegum_96.dts
index 4e34ebaa49..5b58d15594 100644
--- a/arch/arm/dts/bubblegum_96.dts
+++ b/arch/arm/dts/bubblegum_96.dts
@@ -12,8 +12,20 @@
model = "Bubblegum-96";
compatible = "ucrobotics,bubblegum-96", "actions,s900";
+ aliases {
+ serial5 = &uart5;
+ };
+
+ chosen {
+ stdout-path = "serial5:115200n8";
+ };
+
memory at 0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x80000000>;
};
};
+
+&uart5 {
+ status = "okay";
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 8/9] serial: Add Actions Semi OWL UART support
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (6 preceding siblings ...)
2018-06-11 4:43 ` [U-Boot] [PATCH 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 9/9] MAINTAINERS: Add entries for Actions Semi OWL family Manivannan Sadhasivam
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
This commit adds Actions Semi OWL family UART support. This driver
relies on baudrate configured by primary bootloaders.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
drivers/serial/Kconfig | 8 +++
drivers/serial/Makefile | 1 +
drivers/serial/serial_owl.c | 136 ++++++++++++++++++++++++++++++++++++
3 files changed, 145 insertions(+)
create mode 100644 drivers/serial/serial_owl.c
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 2940bd05dc..766e5ced03 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -625,6 +625,14 @@ config MSM_SERIAL
for example APQ8016 and MSM8916.
Single baudrate is supported in current implementation (115200).
+config OWL_SERIAL
+ bool "Actions Semi OWL UART"
+ depends on DM_SERIAL && ARCH_OWL
+ help
+ If you have a Actions Semi OWL based board and want to use the on-chip
+ serial port, say Y to this option. If unsure, say N.
+ Single baudrate is supported in current implementation (115200).
+
config PXA_SERIAL
bool "PXA serial port support"
help
diff --git a/drivers/serial/Makefile b/drivers/serial/Makefile
index e66899489e..9fa81d855d 100644
--- a/drivers/serial/Makefile
+++ b/drivers/serial/Makefile
@@ -64,6 +64,7 @@ obj-$(CONFIG_MSM_SERIAL) += serial_msm.o
obj-$(CONFIG_MVEBU_A3700_UART) += serial_mvebu_a3700.o
obj-$(CONFIG_MPC8XX_CONS) += serial_mpc8xx.o
obj-$(CONFIG_NULLDEV_SERIAL) += serial_nulldev.o
+obj-$(CONFIG_OWL_SERIAL) += serial_owl.o
ifndef CONFIG_SPL_BUILD
obj-$(CONFIG_USB_TTY) += usbtty.o
diff --git a/drivers/serial/serial_owl.c b/drivers/serial/serial_owl.c
new file mode 100644
index 0000000000..6fd97e2502
--- /dev/null
+++ b/drivers/serial/serial_owl.c
@@ -0,0 +1,136 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Actions Semi OWL SoCs UART driver
+ *
+ * Copyright (C) 2015 Actions Semi Co., Ltd.
+ * Copyright (C) 2018 Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+ */
+
+#include <common.h>
+#include <clk.h>
+#include <dm.h>
+#include <errno.h>
+#include <fdtdec.h>
+#include <serial.h>
+#include <asm/io.h>
+#include <asm/types.h>
+
+/* UART Registers */
+#define OWL_UART_CTL (0x0000)
+#define OWL_UART_RXDAT (0x0004)
+#define OWL_UART_TXDAT (0x0008)
+#define OWL_UART_STAT (0x000C)
+
+/* UART_CTL Register Definitions */
+#define OWL_UART_CTL_PRS_NONE GENMASK(6, 4)
+#define OWL_UART_CTL_STPS BIT(2)
+#define OWL_UART_CTL_DWLS 3
+
+/* UART_STAT Register Definitions */
+#define OWL_UART_STAT_TFES BIT(10) /* TX FIFO Empty Status */
+#define OWL_UART_STAT_RFFS BIT(9) /* RX FIFO full Status */
+#define OWL_UART_STAT_TFFU BIT(6) /* TX FIFO full Status */
+#define OWL_UART_STAT_RFEM BIT(5) /* RX FIFO Empty Status */
+
+struct owl_serial_priv {
+ phys_addr_t base;
+};
+
+int owl_serial_setbrg(struct udevice *dev, int baudrate)
+{
+ /* Driver supports only fixed baudrate */
+ return 0;
+}
+
+static int owl_serial_getc(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_RFEM)
+ return -EAGAIN;
+
+ return (int)(readl(priv->base + OWL_UART_RXDAT));
+}
+
+static int owl_serial_putc(struct udevice *dev, const char ch)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ if (readl(priv->base + OWL_UART_STAT) & OWL_UART_STAT_TFFU)
+ return -EAGAIN;
+
+ writel(ch, priv->base + OWL_UART_TXDAT);
+
+ return 0;
+}
+
+static int owl_serial_pending(struct udevice *dev, bool input)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+ unsigned int stat = readl(priv->base + OWL_UART_STAT);
+
+ if (input)
+ return !(stat & OWL_UART_STAT_RFEM);
+ else
+ return !(stat & OWL_UART_STAT_TFES);
+}
+
+static int owl_serial_probe(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+ struct clk clk;
+ u32 uart_ctl;
+ int ret;
+
+ /* Set data, parity and stop bits */
+ uart_ctl = readl(priv->base + OWL_UART_CTL);
+ uart_ctl &= ~(OWL_UART_CTL_PRS_NONE);
+ uart_ctl &= ~(OWL_UART_CTL_STPS);
+ uart_ctl |= OWL_UART_CTL_DWLS;
+ writel(uart_ctl, priv->base + OWL_UART_CTL);
+
+ /* Enable UART clock */
+ ret = clk_get_by_index(dev, 0, &clk);
+ if (ret < 0)
+ return ret;
+
+ ret = clk_enable(&clk);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int owl_serial_ofdata_to_platdata(struct udevice *dev)
+{
+ struct owl_serial_priv *priv = dev_get_priv(dev);
+
+ priv->base = dev_read_addr(dev);
+ if (priv->base == FDT_ADDR_T_NONE)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct dm_serial_ops owl_serial_ops = {
+ .putc = owl_serial_putc,
+ .pending = owl_serial_pending,
+ .getc = owl_serial_getc,
+ .setbrg = owl_serial_setbrg,
+};
+
+static const struct udevice_id owl_serial_ids[] = {
+ { .compatible = "actions,s900-serial" },
+ { }
+};
+
+U_BOOT_DRIVER(serial_owl) = {
+ .name = "serial_owl",
+ .id = UCLASS_SERIAL,
+ .of_match = owl_serial_ids,
+ .ofdata_to_platdata = owl_serial_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct owl_serial_priv),
+ .probe = owl_serial_probe,
+ .ops = &owl_serial_ops,
+ .flags = DM_FLAG_PRE_RELOC,
+};
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [U-Boot] [PATCH 9/9] MAINTAINERS: Add entries for Actions Semi OWL family
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
` (7 preceding siblings ...)
2018-06-11 4:43 ` [U-Boot] [PATCH 8/9] serial: Add Actions Semi OWL UART support Manivannan Sadhasivam
@ 2018-06-11 4:43 ` Manivannan Sadhasivam
8 siblings, 0 replies; 10+ messages in thread
From: Manivannan Sadhasivam @ 2018-06-11 4:43 UTC (permalink / raw)
To: u-boot
Add myself as the Maintainer for Actions Semi OWL family and its
relevant board, drivers.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
---
MAINTAINERS | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 642c448093..0f70cb04fe 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -145,6 +145,15 @@ T: git git://git.denx.de/u-boot-pxa.git
F: arch/arm/cpu/pxa/
F: arch/arm/include/asm/arch-pxa/
+ARM OWL
+M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
+S: Maintained
+F: arch/arm/include/asm/arch-owl/
+F: arch/arm/mach-owl/
+F: board/ucRobotics/
+F: drivers/clk/owl/
+F: drivers/serial/serial_owl.c
+
ARM RENESAS RMOBILE/R-CAR
M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
M: Marek Vasut <marek.vasut+renesas@gmail.com>
--
2.17.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
end of thread, other threads:[~2018-06-11 4:43 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-11 4:42 [U-Boot] [PATCH 0/9] Add SoC and Board support for Bubblegum-96 Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 1/9] arm: Add support for Actions Semi OWL SoC family Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 2/9] board: Add uCRobotics Bubblegum-96 board support Manivannan Sadhasivam
2018-06-11 4:42 ` [U-Boot] [PATCH 3/9] dt-bindings: clock: Add S900 CMU register definitions Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 4/9] arm: dts: s900: Add Clock Management Unit (CMU) nodes Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 5/9] clk: Add Actions Semi OWL clock support Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 6/9] arm: dts: s900: Add UART node Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 7/9] arm: dts: bubblegum_96: Enable UART5 for serial console Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 8/9] serial: Add Actions Semi OWL UART support Manivannan Sadhasivam
2018-06-11 4:43 ` [U-Boot] [PATCH 9/9] MAINTAINERS: Add entries for Actions Semi OWL family Manivannan Sadhasivam
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