* [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x @ 2018-06-11 20:02 Ville Syrjala 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala ` (7 more replies) 0 siblings, 8 replies; 20+ messages in thread From: Ville Syrjala @ 2018-06-11 20:02 UTC (permalink / raw) To: intel-gfx; +Cc: stable From: Ville Syrjälä <ville.syrjala@linux.intel.com> On i965/g4x IIR is edge triggered. So in order for IIR to notice that there is still a pending interrupt we have to force and edge in ISR. For the ISR/IIR pipe event bits we can do that by temporarily clearing all the PIPESTAT enable bits when we ack the status bits. This will force the ISR pipe event bit low, and it can then go back high when we restore the PIPESTAT enable bits. This avoids the following race: 1. stat = read(PIPESTAT) 2. an enabled PIPESTAT status bit goes high 3. write(PIPESTAT, enable|stat); 4. write(IIR, PIPE_EVENT) The end result is IIR==0 and ISR!=0. This can lead to nasty vblank wait/flip_done timeouts if another interrupt source doesn't trick us into looking at the PIPESTAT status bits despite the IIR PIPE_EVENT bit being low. Before i965 IIR was level triggered so this problem can't actually happen there. And curiously VLV/CHV went back to the level triggered scheme as well. But for simplicity we'll use the same i965/g4x compatible code for all platforms. Cc: stable@vger.kernel.org Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 2fd92a886789..364e1c85315e 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1893,9 +1893,17 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, /* * Clear the PIPE*STAT regs before the IIR + * + * Toggle the enable bits to make sure we get an + * edge in the ISR pipe event bit if we don't clear + * all the enabled status bits. Otherwise the edge + * triggered IIR on i965/g4x wouldn't notice that + * an interrupt is still pending. */ - if (pipe_stats[pipe]) - I915_WRITE(reg, enable_mask | pipe_stats[pipe]); + if (pipe_stats[pipe]) { + I915_WRITE(reg, pipe_stats[pipe]); + I915_WRITE(reg, enable_mask); + } } spin_unlock(&dev_priv->irq_lock); } -- 2.16.4 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala @ 2018-06-11 20:02 ` Ville Syrjala 2018-06-11 20:58 ` [Intel-gfx] " Chris Wilson ` (2 more replies) 2018-06-11 20:02 ` [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack Ville Syrjala ` (6 subsequent siblings) 7 siblings, 3 replies; 20+ messages in thread From: Ville Syrjala @ 2018-06-11 20:02 UTC (permalink / raw) To: intel-gfx; +Cc: stable From: Ville Syrjälä <ville.syrjala@linux.intel.com> Just like with PIPESTAT, the edge triggered IIR on i965/g4x also causes problems for hotplug interrupts. To make sure we don't get the IIR port interrupt bit stuck low with the ISR bit high we must force an edge in ISR. We do that by clearing PORT_HOTPLUG_EN temporaryly when we ack PORT_HOTPLUG_STAT. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++--- 1 file changed, 28 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 364e1c85315e..59250ecbd0d9 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1998,10 +1998,35 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) { - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); + u32 hotplug_status, hotplug_en; - if (hotplug_status) - I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); + hotplug_status = I915_READ(PORT_HOTPLUG_STAT); + + if (IS_G4X(dev_priv) || + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + hotplug_status &= HOTPLUG_INT_STATUS_G4X | + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; + else + hotplug_status &= HOTPLUG_INT_STATUS_I915; + + if (hotplug_status == 0) + return 0; + + spin_lock(&dev_priv->irq_lock); + + /* + * Toggle all PORT_HOTPLUG_EN bits to make sure we + * get an edge in the ISR port interrupt bit if we + * don't clear all the enabled status bits. Otherwise + * the edge triggered IIR on i965/g4x wouldn't notice + * that an interrupt is still pending. + */ + hotplug_en = I915_READ(PORT_HOTPLUG_EN); + I915_WRITE(PORT_HOTPLUG_EN, 0); + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); + I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); + + spin_unlock(&dev_priv->irq_lock); return hotplug_status; } -- 2.16.4 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala @ 2018-06-11 20:58 ` Chris Wilson 2018-06-14 16:27 ` Ville Syrjälä 2018-06-14 17:56 ` [PATCH v2 " Ville Syrjala 2 siblings, 0 replies; 20+ messages in thread From: Chris Wilson @ 2018-06-11 20:58 UTC (permalink / raw) To: Ville Syrjala, intel-gfx; +Cc: stable Quoting Ville Syrjala (2018-06-11 21:02:56) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Just like with PIPESTAT, the edge triggered IIR on i965/g4x > also causes problems for hotplug interrupts. To make sure > we don't get the IIR port interrupt bit stuck low with the > ISR bit high we must force an edge in ISR. We do that by > clearing PORT_HOTPLUG_EN temporaryly when we ack > PORT_HOTPLUG_STAT. > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Having accepted the first, Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala @ 2018-06-14 16:27 ` Ville Syrjälä 2018-06-14 16:27 ` Ville Syrjälä 2018-06-14 17:56 ` [PATCH v2 " Ville Syrjala 2 siblings, 0 replies; 20+ messages in thread From: Ville Syrjälä @ 2018-06-14 16:27 UTC (permalink / raw) To: intel-gfx; +Cc: stable On Mon, Jun 11, 2018 at 11:02:56PM +0300, Ville Syrjala wrote: > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > Just like with PIPESTAT, the edge triggered IIR on i965/g4x > also causes problems for hotplug interrupts. To make sure > we don't get the IIR port interrupt bit stuck low with the > ISR bit high we must force an edge in ISR. We do that by > clearing PORT_HOTPLUG_EN temporaryly when we ack > PORT_HOTPLUG_STAT. > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++--- > 1 file changed, 28 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 364e1c85315e..59250ecbd0d9 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1998,10 +1998,35 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, > > static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) > { > - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + u32 hotplug_status, hotplug_en; > > - if (hotplug_status) > - I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + > + if (IS_G4X(dev_priv) || > + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + hotplug_status &= HOTPLUG_INT_STATUS_G4X | > + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; > + else > + hotplug_status &= HOTPLUG_INT_STATUS_I915; > + > + if (hotplug_status == 0) > + return 0; > + > + spin_lock(&dev_priv->irq_lock); > + > + /* > + * Toggle all PORT_HOTPLUG_EN bits to make sure we > + * get an edge in the ISR port interrupt bit if we > + * don't clear all the enabled status bits. Otherwise > + * the edge triggered IIR on i965/g4x wouldn't notice > + * that an interrupt is still pending. > + */ > + hotplug_en = I915_READ(PORT_HOTPLUG_EN); > + I915_WRITE(PORT_HOTPLUG_EN, 0); > + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); Actually this seems to be a bad idea. At least one elk here likes to signal a long pulse on disconnected ports every time I toggle the enable bit in PORT_HOTPLUG_EN. The spec even warns that something like this could happen. Not sure why it specifically happens for ports where nothing is connected. Feels like it should be the other way around. So looks like I'll need to come up with some other way to guarantee the ISR edge. Can't immediately think of any way apart from clearing PORT_HOTPLUG_STAT in a loop :( > + > + spin_unlock(&dev_priv->irq_lock); > > return hotplug_status; > } > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrj�l� Intel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [PATCH 2/4] drm/i915: Fix hotplug irq ack on i965/g4x @ 2018-06-14 16:27 ` Ville Syrjälä 0 siblings, 0 replies; 20+ messages in thread From: Ville Syrjälä @ 2018-06-14 16:27 UTC (permalink / raw) To: intel-gfx; +Cc: stable On Mon, Jun 11, 2018 at 11:02:56PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Just like with PIPESTAT, the edge triggered IIR on i965/g4x > also causes problems for hotplug interrupts. To make sure > we don't get the IIR port interrupt bit stuck low with the > ISR bit high we must force an edge in ISR. We do that by > clearing PORT_HOTPLUG_EN temporaryly when we ack > PORT_HOTPLUG_STAT. > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 31 ++++++++++++++++++++++++++++--- > 1 file changed, 28 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 364e1c85315e..59250ecbd0d9 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1998,10 +1998,35 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, > > static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) > { > - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + u32 hotplug_status, hotplug_en; > > - if (hotplug_status) > - I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + > + if (IS_G4X(dev_priv) || > + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + hotplug_status &= HOTPLUG_INT_STATUS_G4X | > + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; > + else > + hotplug_status &= HOTPLUG_INT_STATUS_I915; > + > + if (hotplug_status == 0) > + return 0; > + > + spin_lock(&dev_priv->irq_lock); > + > + /* > + * Toggle all PORT_HOTPLUG_EN bits to make sure we > + * get an edge in the ISR port interrupt bit if we > + * don't clear all the enabled status bits. Otherwise > + * the edge triggered IIR on i965/g4x wouldn't notice > + * that an interrupt is still pending. > + */ > + hotplug_en = I915_READ(PORT_HOTPLUG_EN); > + I915_WRITE(PORT_HOTPLUG_EN, 0); > + I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + I915_WRITE(PORT_HOTPLUG_EN, hotplug_en); Actually this seems to be a bad idea. At least one elk here likes to signal a long pulse on disconnected ports every time I toggle the enable bit in PORT_HOTPLUG_EN. The spec even warns that something like this could happen. Not sure why it specifically happens for ports where nothing is connected. Feels like it should be the other way around. So looks like I'll need to come up with some other way to guarantee the ISR edge. Can't immediately think of any way apart from clearing PORT_HOTPLUG_STAT in a loop :( > + > + spin_unlock(&dev_priv->irq_lock); > > return hotplug_status; > } > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Ville Syrjälä Intel _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH v2 2/4] drm/i915: Fix hotplug irq ack on i965/g4x 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala 2018-06-11 20:58 ` [Intel-gfx] " Chris Wilson 2018-06-14 16:27 ` Ville Syrjälä @ 2018-06-14 17:56 ` Ville Syrjala 2018-07-03 9:56 ` Imre Deak 2 siblings, 1 reply; 20+ messages in thread From: Ville Syrjala @ 2018-06-14 17:56 UTC (permalink / raw) To: intel-gfx; +Cc: stable From: Ville Syrjälä <ville.syrjala@linux.intel.com> Just like with PIPESTAT, the edge triggered IIR on i965/g4x also causes problems for hotplug interrupts. To make sure we don't get the IIR port interrupt bit stuck low with the ISR bit high we must force an edge in ISR. Unfortunately we can't borrow the PIPESTAT trick and toggle the enable bits in PORT_HOTPLUG_EN as that act itself generates hotplug interrupts. Instead we just have to loop until we've cleared PORT_HOTPLUG_STAT, or we just give up and WARN. v2: Don't frob with PORT_HOTPLUG_EN Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 32 ++++++++++++++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index d5aee0b74f4b..55a4d4f3fbb2 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -1998,10 +1998,38 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) { - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); + u32 hotplug_status = 0, hotplug_status_mask; + int i; + + if (IS_G4X(dev_priv) || + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) + hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; + else + hotplug_status_mask = HOTPLUG_INT_STATUS_I915; - if (hotplug_status) + /* + * We absolutely have to clear all the pending interrupt + * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port + * interrupt bit won't have an edge, and the i965/g4x + * edge triggered IIR will not notice that an interrupt + * is still pending. We can't use PORT_HOTPLUG_EN to + * guarantee the edge as the act of toggling the enable + * bits can itself generate a new hotplug interrupt :( + */ + for (i = 0; i < 10; i++) { + u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask; + + if (tmp == 0) + return hotplug_status; + + hotplug_status |= tmp; I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); + } + + WARN_ONCE(1, + "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", + I915_READ(PORT_HOTPLUG_STAT)); return hotplug_status; } -- 2.16.4 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Fix hotplug irq ack on i965/g4x 2018-06-14 17:56 ` [PATCH v2 " Ville Syrjala @ 2018-07-03 9:56 ` Imre Deak 0 siblings, 0 replies; 20+ messages in thread From: Imre Deak @ 2018-07-03 9:56 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, stable On Thu, Jun 14, 2018 at 08:56:25PM +0300, Ville Syrjala wrote: > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > Just like with PIPESTAT, the edge triggered IIR on i965/g4x > also causes problems for hotplug interrupts. To make sure > we don't get the IIR port interrupt bit stuck low with the > ISR bit high we must force an edge in ISR. Unfortunately > we can't borrow the PIPESTAT trick and toggle the enable > bits in PORT_HOTPLUG_EN as that act itself generates hotplug > interrupts. Instead we just have to loop until we've cleared > PORT_HOTPLUG_STAT, or we just give up and WARN. > > v2: Don't frob with PORT_HOTPLUG_EN > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> Ok, not so great that we have to loop, but looks like there's no better way to go about it. Good that the problem was root caused: Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 32 ++++++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index d5aee0b74f4b..55a4d4f3fbb2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1998,10 +1998,38 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, > > static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) > { > - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + u32 hotplug_status = 0, hotplug_status_mask; > + int i; > + > + if (IS_G4X(dev_priv) || > + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | > + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; > + else > + hotplug_status_mask = HOTPLUG_INT_STATUS_I915; > > - if (hotplug_status) > + /* > + * We absolutely have to clear all the pending interrupt > + * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port > + * interrupt bit won't have an edge, and the i965/g4x > + * edge triggered IIR will not notice that an interrupt > + * is still pending. We can't use PORT_HOTPLUG_EN to > + * guarantee the edge as the act of toggling the enable > + * bits can itself generate a new hotplug interrupt :( > + */ > + for (i = 0; i < 10; i++) { > + u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask; > + > + if (tmp == 0) > + return hotplug_status; > + > + hotplug_status |= tmp; > I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + } > + > + WARN_ONCE(1, > + "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", > + I915_READ(PORT_HOTPLUG_STAT)); > > return hotplug_status; > } > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH v2 2/4] drm/i915: Fix hotplug irq ack on i965/g4x @ 2018-07-03 9:56 ` Imre Deak 0 siblings, 0 replies; 20+ messages in thread From: Imre Deak @ 2018-07-03 9:56 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, stable On Thu, Jun 14, 2018 at 08:56:25PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Just like with PIPESTAT, the edge triggered IIR on i965/g4x > also causes problems for hotplug interrupts. To make sure > we don't get the IIR port interrupt bit stuck low with the > ISR bit high we must force an edge in ISR. Unfortunately > we can't borrow the PIPESTAT trick and toggle the enable > bits in PORT_HOTPLUG_EN as that act itself generates hotplug > interrupts. Instead we just have to loop until we've cleared > PORT_HOTPLUG_STAT, or we just give up and WARN. > > v2: Don't frob with PORT_HOTPLUG_EN > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Ok, not so great that we have to loop, but looks like there's no better way to go about it. Good that the problem was root caused: Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 32 ++++++++++++++++++++++++++++++-- > 1 file changed, 30 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index d5aee0b74f4b..55a4d4f3fbb2 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1998,10 +1998,38 @@ static void valleyview_pipestat_irq_handler(struct drm_i915_private *dev_priv, > > static u32 i9xx_hpd_irq_ack(struct drm_i915_private *dev_priv) > { > - u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT); > + u32 hotplug_status = 0, hotplug_status_mask; > + int i; > + > + if (IS_G4X(dev_priv) || > + IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) > + hotplug_status_mask = HOTPLUG_INT_STATUS_G4X | > + DP_AUX_CHANNEL_MASK_INT_STATUS_G4X; > + else > + hotplug_status_mask = HOTPLUG_INT_STATUS_I915; > > - if (hotplug_status) > + /* > + * We absolutely have to clear all the pending interrupt > + * bits in PORT_HOTPLUG_STAT. Otherwise the ISR port > + * interrupt bit won't have an edge, and the i965/g4x > + * edge triggered IIR will not notice that an interrupt > + * is still pending. We can't use PORT_HOTPLUG_EN to > + * guarantee the edge as the act of toggling the enable > + * bits can itself generate a new hotplug interrupt :( > + */ > + for (i = 0; i < 10; i++) { > + u32 tmp = I915_READ(PORT_HOTPLUG_STAT) & hotplug_status_mask; > + > + if (tmp == 0) > + return hotplug_status; > + > + hotplug_status |= tmp; > I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status); > + } > + > + WARN_ONCE(1, > + "PORT_HOTPLUG_STAT did not clear (0x%08x)\n", > + I915_READ(PORT_HOTPLUG_STAT)); > > return hotplug_status; > } > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala @ 2018-06-11 20:02 ` Ville Syrjala 2018-07-03 11:58 ` Imre Deak 2018-06-11 20:02 ` [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 Ville Syrjala ` (5 subsequent siblings) 7 siblings, 1 reply; 20+ messages in thread From: Ville Syrjala @ 2018-06-11 20:02 UTC (permalink / raw) To: intel-gfx; +Cc: stable From: Ville Syrjälä <ville.syrjala@linux.intel.com> Adjust the EIR clearing to cope with the edge triggered IIR on i965/g4x. To guarantee an edge in the ISR master error bit we temporarily mask everything in EMR. As some of the EIR bits can't even be directly cleared we also borrow a trick from i915_clear_error_registers() and permanently mask any bit that remains high. No real thought given to how we might unmask them again once the cause for the error has been clered. I suppose on pre-g4x GPU reset will reinitialize EMR from scratch. Cc: stable@vger.kernel.org Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 105 ++++++++++++++++++++++++++++++++++++---- drivers/gpu/drm/i915/i915_reg.h | 1 - 2 files changed, 96 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 59250ecbd0d9..985a137901fb 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -3087,7 +3087,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) */ DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); I915_WRITE(EMR, I915_READ(EMR) | eir); - I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); + I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT); } } @@ -4107,6 +4107,81 @@ static int i8xx_irq_postinstall(struct drm_device *dev) return 0; } +static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv, + u16 *eir, u16 *eir_stuck) +{ + u16 emr; + + *eir = I915_READ16(EIR); + + if (*eir) + I915_WRITE16(EIR, *eir); + + *eir_stuck = I915_READ16(EIR); + if (*eir_stuck == 0) + return; + + /* + * Toggle all EMR bits to make sure we get an edge + * in the ISR master error bit if we don't clear + * all the EIR bits. Otherwise the edge triggered + * IIR on i965/g4x wouldn't notice that an interrupt + * is still pending. Also some EIR bits can't be + * cleared except by handling the underlying error + * (or by a GPU reset) so we mask any bit that + * remains set. + */ + emr = I915_READ16(EMR); + I915_WRITE16(EMR, 0xffff); + I915_WRITE16(EMR, emr | *eir_stuck); +} + +static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, + u16 eir, u16 eir_stuck) +{ + DRM_DEBUG("Master Error: EIR 0x%04x\n", eir); + + if (eir_stuck) + DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck); +} + +static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, + u32 *eir, u32 *eir_stuck) +{ + u32 emr; + + *eir = I915_READ(EIR); + + I915_WRITE(EIR, *eir); + + *eir_stuck = I915_READ(EIR); + if (*eir_stuck == 0) + return; + + /* + * Toggle all EMR bits to make sure we get an edge + * in the ISR master error bit if we don't clear + * all the EIR bits. Otherwise the edge triggered + * IIR on i965/g4x wouldn't notice that an interrupt + * is still pending. Also some EIR bits can't be + * cleared except by handling the underlying error + * (or by a GPU reset) so we mask any bit that + * remains set. + */ + emr = I915_READ(EMR); + I915_WRITE(EMR, 0xffffffff); + I915_WRITE(EMR, emr | *eir_stuck); +} + +static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, + u32 eir, u32 eir_stuck) +{ + DRM_DEBUG("Master Error, EIR 0x%08x\n", eir); + + if (eir_stuck) + DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck); +} + static irqreturn_t i8xx_irq_handler(int irq, void *arg) { struct drm_device *dev = arg; @@ -4121,6 +4196,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) do { u32 pipe_stats[I915_MAX_PIPES] = {}; + u16 eir = 0, eir_stuck = 0; u16 iir; iir = I915_READ16(IIR); @@ -4133,13 +4209,16 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) * signalled in iir */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); + I915_WRITE16(IIR, iir); if (iir & I915_USER_INTERRUPT) notify_ring(dev_priv->engine[RCS]); - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i8xx_error_irq_handler(dev_priv, eir, eir_stuck); i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); } while (0); @@ -4220,6 +4299,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) do { u32 pipe_stats[I915_MAX_PIPES] = {}; + u32 eir = 0, eir_stuck = 0; u32 hotplug_status = 0; u32 iir; @@ -4237,13 +4317,16 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) * signalled in iir */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); + I915_WRITE(IIR, iir); if (iir & I915_USER_INTERRUPT) notify_ring(dev_priv->engine[RCS]); - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); @@ -4297,14 +4380,14 @@ static int i965_irq_postinstall(struct drm_device *dev) I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); + I915_MASTER_ERROR_INTERRUPT); enable_mask = I915_ASLE_INTERRUPT | I915_DISPLAY_PORT_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT; if (IS_G4X(dev_priv)) @@ -4364,6 +4447,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) do { u32 pipe_stats[I915_MAX_PIPES] = {}; + u32 eir = 0, eir_stuck = 0; u32 hotplug_status = 0; u32 iir; @@ -4380,6 +4464,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) * signalled in iir */ i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); + I915_WRITE(IIR, iir); if (iir & I915_USER_INTERRUPT) @@ -4388,8 +4475,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) if (iir & I915_BSD_USER_INTERRUPT) notify_ring(dev_priv->engine[VCS]); - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); + if (iir & I915_MASTER_ERROR_INTERRUPT) + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); if (hotplug_status) i9xx_hpd_irq_handler(dev_priv, hotplug_status); diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 987def26ce82..50a47753014b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2805,7 +2805,6 @@ enum i915_power_well_id { #define I915_DISPLAY_PORT_INTERRUPT (1<<17) #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) #define I915_MASTER_ERROR_INTERRUPT (1<<15) -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) -- 2.16.4 ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack 2018-06-11 20:02 ` [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack Ville Syrjala @ 2018-07-03 11:58 ` Imre Deak 0 siblings, 0 replies; 20+ messages in thread From: Imre Deak @ 2018-07-03 11:58 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, stable On Mon, Jun 11, 2018 at 11:02:57PM +0300, Ville Syrjala wrote: > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > Adjust the EIR clearing to cope with the edge triggered IIR > on i965/g4x. To guarantee an edge in the ISR master error bit > we temporarily mask everything in EMR. As some of the EIR bits > can't even be directly cleared we also borrow a trick from > i915_clear_error_registers() and permanently mask any bit that > remains high. No real thought given to how we might unmask them > again once the cause for the error has been clered. I suppose > on pre-g4x GPU reset will reinitialize EMR from scratch. > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 105 ++++++++++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 1 - > 2 files changed, 96 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 59250ecbd0d9..985a137901fb 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3087,7 +3087,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) > */ > DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); > I915_WRITE(EMR, I915_READ(EMR) | eir); > - I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); > + I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT); > } > } > > @@ -4107,6 +4107,81 @@ static int i8xx_irq_postinstall(struct drm_device *dev) > return 0; > } > > +static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv, > + u16 *eir, u16 *eir_stuck) > +{ > + u16 emr; > + > + *eir = I915_READ16(EIR); > + > + if (*eir) > + I915_WRITE16(EIR, *eir); > + > + *eir_stuck = I915_READ16(EIR); Nit: this could store a new error interrupt after the above read to eir_stuck instead of eir, but we won't lose the event in any case, so: Reviewed-by: Imre Deak <imre.deak@intel.com> > + if (*eir_stuck == 0) > + return; > + > + /* > + * Toggle all EMR bits to make sure we get an edge > + * in the ISR master error bit if we don't clear > + * all the EIR bits. Otherwise the edge triggered > + * IIR on i965/g4x wouldn't notice that an interrupt > + * is still pending. Also some EIR bits can't be > + * cleared except by handling the underlying error > + * (or by a GPU reset) so we mask any bit that > + * remains set. > + */ > + emr = I915_READ16(EMR); > + I915_WRITE16(EMR, 0xffff); > + I915_WRITE16(EMR, emr | *eir_stuck); > +} > + > +static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, > + u16 eir, u16 eir_stuck) > +{ > + DRM_DEBUG("Master Error: EIR 0x%04x\n", eir); > + > + if (eir_stuck) > + DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck); > +} > + > +static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, > + u32 *eir, u32 *eir_stuck) > +{ > + u32 emr; > + > + *eir = I915_READ(EIR); > + > + I915_WRITE(EIR, *eir); > + > + *eir_stuck = I915_READ(EIR); > + if (*eir_stuck == 0) > + return; > + > + /* > + * Toggle all EMR bits to make sure we get an edge > + * in the ISR master error bit if we don't clear > + * all the EIR bits. Otherwise the edge triggered > + * IIR on i965/g4x wouldn't notice that an interrupt > + * is still pending. Also some EIR bits can't be > + * cleared except by handling the underlying error > + * (or by a GPU reset) so we mask any bit that > + * remains set. > + */ > + emr = I915_READ(EMR); > + I915_WRITE(EMR, 0xffffffff); > + I915_WRITE(EMR, emr | *eir_stuck); > +} > + > +static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, > + u32 eir, u32 eir_stuck) > +{ > + DRM_DEBUG("Master Error, EIR 0x%08x\n", eir); > + > + if (eir_stuck) > + DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck); > +} > + > static irqreturn_t i8xx_irq_handler(int irq, void *arg) > { > struct drm_device *dev = arg; > @@ -4121,6 +4196,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u16 eir = 0, eir_stuck = 0; > u16 iir; > > iir = I915_READ16(IIR); > @@ -4133,13 +4209,16 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE16(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > notify_ring(dev_priv->engine[RCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i8xx_error_irq_handler(dev_priv, eir, eir_stuck); > > i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); > } while (0); > @@ -4220,6 +4299,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u32 eir = 0, eir_stuck = 0; > u32 hotplug_status = 0; > u32 iir; > > @@ -4237,13 +4317,16 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > notify_ring(dev_priv->engine[RCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > > if (hotplug_status) > i9xx_hpd_irq_handler(dev_priv, hotplug_status); > @@ -4297,14 +4380,14 @@ static int i965_irq_postinstall(struct drm_device *dev) > I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); > + I915_MASTER_ERROR_INTERRUPT); > > enable_mask = > I915_ASLE_INTERRUPT | > I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT | > I915_USER_INTERRUPT; > > if (IS_G4X(dev_priv)) > @@ -4364,6 +4447,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u32 eir = 0, eir_stuck = 0; > u32 hotplug_status = 0; > u32 iir; > > @@ -4380,6 +4464,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > @@ -4388,8 +4475,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > if (iir & I915_BSD_USER_INTERRUPT) > notify_ring(dev_priv->engine[VCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > > if (hotplug_status) > i9xx_hpd_irq_handler(dev_priv, hotplug_status); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 987def26ce82..50a47753014b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2805,7 +2805,6 @@ enum i915_power_well_id { > #define I915_DISPLAY_PORT_INTERRUPT (1<<17) > #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) > #define I915_MASTER_ERROR_INTERRUPT (1<<15) > -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) > #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) > #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ > #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack @ 2018-07-03 11:58 ` Imre Deak 0 siblings, 0 replies; 20+ messages in thread From: Imre Deak @ 2018-07-03 11:58 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx, stable On Mon, Jun 11, 2018 at 11:02:57PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > Adjust the EIR clearing to cope with the edge triggered IIR > on i965/g4x. To guarantee an edge in the ISR master error bit > we temporarily mask everything in EMR. As some of the EIR bits > can't even be directly cleared we also borrow a trick from > i915_clear_error_registers() and permanently mask any bit that > remains high. No real thought given to how we might unmask them > again once the cause for the error has been clered. I suppose > on pre-g4x GPU reset will reinitialize EMR from scratch. > > Cc: stable@vger.kernel.org > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 105 ++++++++++++++++++++++++++++++++++++---- > drivers/gpu/drm/i915/i915_reg.h | 1 - > 2 files changed, 96 insertions(+), 10 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 59250ecbd0d9..985a137901fb 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -3087,7 +3087,7 @@ static void i915_clear_error_registers(struct drm_i915_private *dev_priv) > */ > DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masking\n", eir); > I915_WRITE(EMR, I915_READ(EMR) | eir); > - I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); > + I915_WRITE(IIR, I915_MASTER_ERROR_INTERRUPT); > } > } > > @@ -4107,6 +4107,81 @@ static int i8xx_irq_postinstall(struct drm_device *dev) > return 0; > } > > +static void i8xx_error_irq_ack(struct drm_i915_private *dev_priv, > + u16 *eir, u16 *eir_stuck) > +{ > + u16 emr; > + > + *eir = I915_READ16(EIR); > + > + if (*eir) > + I915_WRITE16(EIR, *eir); > + > + *eir_stuck = I915_READ16(EIR); Nit: this could store a new error interrupt after the above read to eir_stuck instead of eir, but we won't lose the event in any case, so: Reviewed-by: Imre Deak <imre.deak@intel.com> > + if (*eir_stuck == 0) > + return; > + > + /* > + * Toggle all EMR bits to make sure we get an edge > + * in the ISR master error bit if we don't clear > + * all the EIR bits. Otherwise the edge triggered > + * IIR on i965/g4x wouldn't notice that an interrupt > + * is still pending. Also some EIR bits can't be > + * cleared except by handling the underlying error > + * (or by a GPU reset) so we mask any bit that > + * remains set. > + */ > + emr = I915_READ16(EMR); > + I915_WRITE16(EMR, 0xffff); > + I915_WRITE16(EMR, emr | *eir_stuck); > +} > + > +static void i8xx_error_irq_handler(struct drm_i915_private *dev_priv, > + u16 eir, u16 eir_stuck) > +{ > + DRM_DEBUG("Master Error: EIR 0x%04x\n", eir); > + > + if (eir_stuck) > + DRM_DEBUG_DRIVER("EIR stuck: 0x%04x, masked\n", eir_stuck); > +} > + > +static void i9xx_error_irq_ack(struct drm_i915_private *dev_priv, > + u32 *eir, u32 *eir_stuck) > +{ > + u32 emr; > + > + *eir = I915_READ(EIR); > + > + I915_WRITE(EIR, *eir); > + > + *eir_stuck = I915_READ(EIR); > + if (*eir_stuck == 0) > + return; > + > + /* > + * Toggle all EMR bits to make sure we get an edge > + * in the ISR master error bit if we don't clear > + * all the EIR bits. Otherwise the edge triggered > + * IIR on i965/g4x wouldn't notice that an interrupt > + * is still pending. Also some EIR bits can't be > + * cleared except by handling the underlying error > + * (or by a GPU reset) so we mask any bit that > + * remains set. > + */ > + emr = I915_READ(EMR); > + I915_WRITE(EMR, 0xffffffff); > + I915_WRITE(EMR, emr | *eir_stuck); > +} > + > +static void i9xx_error_irq_handler(struct drm_i915_private *dev_priv, > + u32 eir, u32 eir_stuck) > +{ > + DRM_DEBUG("Master Error, EIR 0x%08x\n", eir); > + > + if (eir_stuck) > + DRM_DEBUG_DRIVER("EIR stuck: 0x%08x, masked\n", eir_stuck); > +} > + > static irqreturn_t i8xx_irq_handler(int irq, void *arg) > { > struct drm_device *dev = arg; > @@ -4121,6 +4196,7 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u16 eir = 0, eir_stuck = 0; > u16 iir; > > iir = I915_READ16(IIR); > @@ -4133,13 +4209,16 @@ static irqreturn_t i8xx_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i8xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE16(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > notify_ring(dev_priv->engine[RCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i8xx_error_irq_handler(dev_priv, eir, eir_stuck); > > i8xx_pipestat_irq_handler(dev_priv, iir, pipe_stats); > } while (0); > @@ -4220,6 +4299,7 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u32 eir = 0, eir_stuck = 0; > u32 hotplug_status = 0; > u32 iir; > > @@ -4237,13 +4317,16 @@ static irqreturn_t i915_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > notify_ring(dev_priv->engine[RCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > > if (hotplug_status) > i9xx_hpd_irq_handler(dev_priv, hotplug_status); > @@ -4297,14 +4380,14 @@ static int i965_irq_postinstall(struct drm_device *dev) > I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT); > + I915_MASTER_ERROR_INTERRUPT); > > enable_mask = > I915_ASLE_INTERRUPT | > I915_DISPLAY_PORT_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > - I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT | > I915_USER_INTERRUPT; > > if (IS_G4X(dev_priv)) > @@ -4364,6 +4447,7 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > > do { > u32 pipe_stats[I915_MAX_PIPES] = {}; > + u32 eir = 0, eir_stuck = 0; > u32 hotplug_status = 0; > u32 iir; > > @@ -4380,6 +4464,9 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > * signalled in iir */ > i9xx_pipestat_irq_ack(dev_priv, iir, pipe_stats); > > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_ack(dev_priv, &eir, &eir_stuck); > + > I915_WRITE(IIR, iir); > > if (iir & I915_USER_INTERRUPT) > @@ -4388,8 +4475,8 @@ static irqreturn_t i965_irq_handler(int irq, void *arg) > if (iir & I915_BSD_USER_INTERRUPT) > notify_ring(dev_priv->engine[VCS]); > > - if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT) > - DRM_DEBUG("Command parser error, iir 0x%08x\n", iir); > + if (iir & I915_MASTER_ERROR_INTERRUPT) > + i9xx_error_irq_handler(dev_priv, eir, eir_stuck); > > if (hotplug_status) > i9xx_hpd_irq_handler(dev_priv, hotplug_status); > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 987def26ce82..50a47753014b 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2805,7 +2805,6 @@ enum i915_power_well_id { > #define I915_DISPLAY_PORT_INTERRUPT (1<<17) > #define I915_DISPLAY_PIPE_C_HBLANK_INTERRUPT (1<<16) > #define I915_MASTER_ERROR_INTERRUPT (1<<15) > -#define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) > #define I915_DISPLAY_PIPE_B_HBLANK_INTERRUPT (1<<14) > #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) /* p-state */ > #define I915_DISPLAY_PIPE_A_HBLANK_INTERRUPT (1<<13) > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala 2018-06-11 20:02 ` [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack Ville Syrjala @ 2018-06-11 20:02 ` Ville Syrjala 2018-07-03 12:00 ` Imre Deak 2018-06-11 20:46 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Patchwork ` (4 subsequent siblings) 7 siblings, 1 reply; 20+ messages in thread From: Ville Syrjala @ 2018-06-11 20:02 UTC (permalink / raw) To: intel-gfx From: Ville Syrjälä <ville.syrjala@linux.intel.com> For whatever reason we only unmask and enable the master error interrut on gen4. With the EIR handling fixed let's do that on gen2/3 as well. Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> --- drivers/gpu/drm/i915/i915_irq.c | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c index 985a137901fb..b4a5582c5042 100644 --- a/drivers/gpu/drm/i915/i915_irq.c +++ b/drivers/gpu/drm/i915/i915_irq.c @@ -4088,11 +4088,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev) /* Unmask the interrupts that we always want on. */ dev_priv->irq_mask = ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT); enable_mask = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT; GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); @@ -4256,12 +4258,14 @@ static int i915_irq_postinstall(struct drm_device *dev) dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT); enable_mask = I915_ASLE_INTERRUPT | I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | + I915_MASTER_ERROR_INTERRUPT | I915_USER_INTERRUPT; if (I915_HAS_HOTPLUG(dev_priv)) { -- 2.16.4 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 20+ messages in thread
* Re: [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 2018-06-11 20:02 ` [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 Ville Syrjala @ 2018-07-03 12:00 ` Imre Deak 0 siblings, 0 replies; 20+ messages in thread From: Imre Deak @ 2018-07-03 12:00 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx On Mon, Jun 11, 2018 at 11:02:58PM +0300, Ville Syrjala wrote: > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > For whatever reason we only unmask and enable the master error > interrut on gen4. With the EIR handling fixed let's do that > on gen2/3 as well. > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Imre Deak <imre.deak@intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 8 ++++++-- > 1 file changed, 6 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 985a137901fb..b4a5582c5042 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -4088,11 +4088,13 @@ static int i8xx_irq_postinstall(struct drm_device *dev) > /* Unmask the interrupts that we always want on. */ > dev_priv->irq_mask = > ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); > + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT); > > enable_mask = > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT | > I915_USER_INTERRUPT; > > GEN2_IRQ_INIT(, dev_priv->irq_mask, enable_mask); > @@ -4256,12 +4258,14 @@ static int i915_irq_postinstall(struct drm_device *dev) > dev_priv->irq_mask = > ~(I915_ASLE_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > - I915_DISPLAY_PIPE_B_EVENT_INTERRUPT); > + I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT); > > enable_mask = > I915_ASLE_INTERRUPT | > I915_DISPLAY_PIPE_A_EVENT_INTERRUPT | > I915_DISPLAY_PIPE_B_EVENT_INTERRUPT | > + I915_MASTER_ERROR_INTERRUPT | > I915_USER_INTERRUPT; > > if (I915_HAS_HOTPLUG(dev_priv)) { > -- > 2.16.4 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala ` (2 preceding siblings ...) 2018-06-11 20:02 ` [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 Ville Syrjala @ 2018-06-11 20:46 ` Patchwork 2018-06-11 20:53 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson ` (3 subsequent siblings) 7 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-11 20:46 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x URL : https://patchwork.freedesktop.org/series/44589/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4304 -> Patchwork_9264 = == Summary - WARNING == Minor unknown changes coming with Patchwork_9264 need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9264, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://patchwork.freedesktop.org/api/1.0/series/44589/revisions/1/mbox/ == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9264: === IGT changes === ==== Warnings ==== igt@gem_exec_gttfill@basic: fi-pnv-d510: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9264 that come from known issues: === IGT changes === ==== Issues hit ==== igt@gem_exec_gttfill@basic: fi-byt-n2820: PASS -> FAIL (fdo#106744) igt@kms_flip@basic-flip-vs-dpms: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000) +1 igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-cnl-psr: PASS -> DMESG-WARN (fdo#104951) ==== Possible fixes ==== igt@kms_flip@basic-plain-flip: fi-glk-j4005: DMESG-WARN (fdo#106097) -> PASS +1 fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713 fdo#104951 https://bugs.freedesktop.org/show_bug.cgi?id=104951 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097 fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744 == Participating hosts (42 -> 37) == Missing (5): fi-ctg-p8600 fi-bsw-cyan fi-ilk-m540 fi-skl-gvtdvm fi-skl-6700hq == Build changes == * Linux: CI_DRM_4304 -> Patchwork_9264 CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9264: 66e1f3ae34d4e6ca72a84d7b1dd9a522aabdbb0f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 66e1f3ae34d4 drm/i915: Unmask and enable master error interrupt on gen2/3 e8c6aae5de28 drm/i915: Fix pre-ILK error interrupt ack cf7a9668c170 drm/i915: Fix hotplug irq ack on i965/g4x 66a139d11c6e drm/i915: Fix PIPESTATE irq ack on i965/g4x == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9264/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala ` (3 preceding siblings ...) 2018-06-11 20:46 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Patchwork @ 2018-06-11 20:53 ` Chris Wilson 2018-06-14 18:16 ` Ville Syrjälä 2018-06-12 2:34 ` ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork ` (2 subsequent siblings) 7 siblings, 1 reply; 20+ messages in thread From: Chris Wilson @ 2018-06-11 20:53 UTC (permalink / raw) To: Ville Syrjala, intel-gfx; +Cc: stable Quoting Ville Syrjala (2018-06-11 21:02:55) > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > On i965/g4x IIR is edge triggered. So in order for IIR to notice that > there is still a pending interrupt we have to force and edge in ISR. > For the ISR/IIR pipe event bits we can do that by temporarily > clearing all the PIPESTAT enable bits when we ack the status bits. > This will force the ISR pipe event bit low, and it can then go back > high when we restore the PIPESTAT enable bits. > > This avoids the following race: > 1. stat = read(PIPESTAT) > 2. an enabled PIPESTAT status bit goes high > 3. write(PIPESTAT, enable|stat); > 4. write(IIR, PIPE_EVENT) > > The end result is IIR==0 and ISR!=0. This can lead to nasty > vblank wait/flip_done timeouts if another interrupt source > doesn't trick us into looking at the PIPESTAT status bits despite > the IIR PIPE_EVENT bit being low. > > Before i965 IIR was level triggered so this problem can't actually > happen there. And curiously VLV/CHV went back to the level triggered > scheme as well. But for simplicity we'll use the same i965/g4x > compatible code for all platforms. > > Cc: stable@vger.kernel.org > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > --- > drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++-- > 1 file changed, 10 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index 2fd92a886789..364e1c85315e 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -1893,9 +1893,17 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, > > /* > * Clear the PIPE*STAT regs before the IIR > + * > + * Toggle the enable bits to make sure we get an > + * edge in the ISR pipe event bit if we don't clear > + * all the enabled status bits. Otherwise the edge > + * triggered IIR on i965/g4x wouldn't notice that > + * an interrupt is still pending. > */ > - if (pipe_stats[pipe]) > - I915_WRITE(reg, enable_mask | pipe_stats[pipe]); > + if (pipe_stats[pipe]) { > + I915_WRITE(reg, pipe_stats[pipe]); Ack status, disable all. > + I915_WRITE(reg, enable_mask); Enable, an asserted bit should trigger a new edge. It certainly does as you explain, now I just hope the hw feels the same! Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> -Chris ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x 2018-06-11 20:53 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson @ 2018-06-14 18:16 ` Ville Syrjälä 0 siblings, 0 replies; 20+ messages in thread From: Ville Syrjälä @ 2018-06-14 18:16 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, stable On Mon, Jun 11, 2018 at 09:53:52PM +0100, Chris Wilson wrote: > Quoting Ville Syrjala (2018-06-11 21:02:55) > > From: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > > > On i965/g4x IIR is edge triggered. So in order for IIR to notice that > > there is still a pending interrupt we have to force and edge in ISR. > > For the ISR/IIR pipe event bits we can do that by temporarily > > clearing all the PIPESTAT enable bits when we ack the status bits. > > This will force the ISR pipe event bit low, and it can then go back > > high when we restore the PIPESTAT enable bits. > > > > This avoids the following race: > > 1. stat = read(PIPESTAT) > > 2. an enabled PIPESTAT status bit goes high > > 3. write(PIPESTAT, enable|stat); > > 4. write(IIR, PIPE_EVENT) > > > > The end result is IIR==0 and ISR!=0. This can lead to nasty > > vblank wait/flip_done timeouts if another interrupt source > > doesn't trick us into looking at the PIPESTAT status bits despite > > the IIR PIPE_EVENT bit being low. > > > > Before i965 IIR was level triggered so this problem can't actually > > happen there. And curiously VLV/CHV went back to the level triggered > > scheme as well. But for simplicity we'll use the same i965/g4x > > compatible code for all platforms. > > > > Cc: stable@vger.kernel.org > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 > > Signed-off-by: Ville Syrj�l� <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 2fd92a886789..364e1c85315e 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1893,9 +1893,17 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, > > > > /* > > * Clear the PIPE*STAT regs before the IIR > > + * > > + * Toggle the enable bits to make sure we get an > > + * edge in the ISR pipe event bit if we don't clear > > + * all the enabled status bits. Otherwise the edge > > + * triggered IIR on i965/g4x wouldn't notice that > > + * an interrupt is still pending. > > */ > > - if (pipe_stats[pipe]) > > - I915_WRITE(reg, enable_mask | pipe_stats[pipe]); > > + if (pipe_stats[pipe]) { > > + I915_WRITE(reg, pipe_stats[pipe]); > > Ack status, disable all. > > > + I915_WRITE(reg, enable_mask); > > Enable, an asserted bit should trigger a new edge. > > It certainly does as you explain, now I just hope the hw feels the same! > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> s/PIPESTATE/PIPESTAT/ (can't count how many times I've done that one wrong) and pushed to dinq. Thanks for the review. -- Ville Syrj�l� Intel ^ permalink raw reply [flat|nested] 20+ messages in thread
* Re: [Intel-gfx] [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x @ 2018-06-14 18:16 ` Ville Syrjälä 0 siblings, 0 replies; 20+ messages in thread From: Ville Syrjälä @ 2018-06-14 18:16 UTC (permalink / raw) To: Chris Wilson; +Cc: intel-gfx, stable On Mon, Jun 11, 2018 at 09:53:52PM +0100, Chris Wilson wrote: > Quoting Ville Syrjala (2018-06-11 21:02:55) > > From: Ville Syrjälä <ville.syrjala@linux.intel.com> > > > > On i965/g4x IIR is edge triggered. So in order for IIR to notice that > > there is still a pending interrupt we have to force and edge in ISR. > > For the ISR/IIR pipe event bits we can do that by temporarily > > clearing all the PIPESTAT enable bits when we ack the status bits. > > This will force the ISR pipe event bit low, and it can then go back > > high when we restore the PIPESTAT enable bits. > > > > This avoids the following race: > > 1. stat = read(PIPESTAT) > > 2. an enabled PIPESTAT status bit goes high > > 3. write(PIPESTAT, enable|stat); > > 4. write(IIR, PIPE_EVENT) > > > > The end result is IIR==0 and ISR!=0. This can lead to nasty > > vblank wait/flip_done timeouts if another interrupt source > > doesn't trick us into looking at the PIPESTAT status bits despite > > the IIR PIPE_EVENT bit being low. > > > > Before i965 IIR was level triggered so this problem can't actually > > happen there. And curiously VLV/CHV went back to the level triggered > > scheme as well. But for simplicity we'll use the same i965/g4x > > compatible code for all platforms. > > > > Cc: stable@vger.kernel.org > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106033 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105225 > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106030 > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> > > --- > > drivers/gpu/drm/i915/i915_irq.c | 12 ++++++++++-- > > 1 file changed, 10 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > > index 2fd92a886789..364e1c85315e 100644 > > --- a/drivers/gpu/drm/i915/i915_irq.c > > +++ b/drivers/gpu/drm/i915/i915_irq.c > > @@ -1893,9 +1893,17 @@ static void i9xx_pipestat_irq_ack(struct drm_i915_private *dev_priv, > > > > /* > > * Clear the PIPE*STAT regs before the IIR > > + * > > + * Toggle the enable bits to make sure we get an > > + * edge in the ISR pipe event bit if we don't clear > > + * all the enabled status bits. Otherwise the edge > > + * triggered IIR on i965/g4x wouldn't notice that > > + * an interrupt is still pending. > > */ > > - if (pipe_stats[pipe]) > > - I915_WRITE(reg, enable_mask | pipe_stats[pipe]); > > + if (pipe_stats[pipe]) { > > + I915_WRITE(reg, pipe_stats[pipe]); > > Ack status, disable all. > > > + I915_WRITE(reg, enable_mask); > > Enable, an asserted bit should trigger a new edge. > > It certainly does as you explain, now I just hope the hw feels the same! > > Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk> s/PIPESTATE/PIPESTAT/ (can't count how many times I've done that one wrong) and pushed to dinq. Thanks for the review. -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala ` (4 preceding siblings ...) 2018-06-11 20:53 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson @ 2018-06-12 2:34 ` Patchwork 2018-06-14 18:20 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) Patchwork 2018-06-15 2:11 ` ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-12 2:34 UTC (permalink / raw) To: Ville Syrjala; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x URL : https://patchwork.freedesktop.org/series/44589/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4304_full -> Patchwork_9264_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9264_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9264_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9264_full: === IGT changes === ==== Warnings ==== igt@gem_exec_schedule@deep-bsd1: shard-kbl: SKIP -> PASS +1 igt@gem_tiled_blits@normal: shard-glk: SKIP -> PASS == Known issues == Here are the changes found in Patchwork_9264_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_atomic_transition@1x-modeset-transitions-nonblocking: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@2x-modeset-vs-vblank-race: shard-hsw: PASS -> FAIL (fdo#103060) igt@kms_flip@modeset-vs-vblank-race: shard-glk: PASS -> FAIL (fdo#103060) igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_flip_tiling@flip-x-tiled: shard-glk: PASS -> FAIL (fdo#104724, fdo#103822) igt@kms_flip_tiling@flip-y-tiled: shard-glk: PASS -> FAIL (fdo#104724) igt@kms_setmode@basic: shard-kbl: PASS -> FAIL (fdo#99912) ==== Possible fixes ==== igt@drv_selftest@live_gtt: shard-kbl: FAIL (fdo#105347) -> PASS igt@drv_suspend@shrink: shard-hsw: INCOMPLETE (fdo#103540) -> PASS shard-glk: INCOMPLETE (fdo#103359, k.org#198133) -> PASS igt@kms_cursor_legacy@2x-nonblocking-modeset-vs-cursor-atomic: shard-glk: FAIL (fdo#106509, fdo#105454) -> PASS igt@kms_flip@plain-flip-fb-recreate: shard-glk: FAIL (fdo#100368) -> PASS igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: FAIL (fdo#103925, fdo#104724) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359 fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540 fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105454 https://bugs.freedesktop.org/show_bug.cgi?id=105454 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106509 https://bugs.freedesktop.org/show_bug.cgi?id=106509 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4304 -> Patchwork_9264 CI_DRM_4304: 2313a1dc588ef63d9650ccbaaf576bc4b47dc255 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4515: a0f2d23b7d3d4226a0a7637a9240bfa86f08c1d3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9264: 66e1f3ae34d4e6ca72a84d7b1dd9a522aabdbb0f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9264/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala ` (5 preceding siblings ...) 2018-06-12 2:34 ` ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork @ 2018-06-14 18:20 ` Patchwork 2018-06-15 2:11 ` ✓ Fi.CI.IGT: " Patchwork 7 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-14 18:20 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) URL : https://patchwork.freedesktop.org/series/44589/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4318 -> Patchwork_9305 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/44589/revisions/2/mbox/ == Known issues == Here are the changes found in Patchwork_9305 that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_module_reload@basic-reload-inject: fi-glk-j4005: PASS -> DMESG-WARN (fdo#106725, fdo#106248) igt@kms_flip@basic-flip-vs-wf_vblank: fi-glk-j4005: PASS -> FAIL (fdo#100368) igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c: fi-skl-6260u: PASS -> INCOMPLETE (fdo#104108) ==== Possible fixes ==== igt@kms_flip@basic-flip-vs-modeset: fi-glk-j4005: DMESG-WARN (fdo#106000) -> PASS +1 igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence: fi-glk-j4005: DMESG-WARN (fdo#106238) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108 fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000 fdo#106238 https://bugs.freedesktop.org/show_bug.cgi?id=106238 fdo#106248 https://bugs.freedesktop.org/show_bug.cgi?id=106248 fdo#106725 https://bugs.freedesktop.org/show_bug.cgi?id=106725 == Participating hosts (43 -> 38) == Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u == Build changes == * Linux: CI_DRM_4318 -> Patchwork_9305 CI_DRM_4318: 51c35728be7da2a316981544aa370e9ff56f3b27 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9305: a829c81624f1419ed1bf9742076838aafee17f47 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == a829c81624f1 drm/i915: Unmask and enable master error interrupt on gen2/3 687db66f4574 drm/i915: Fix pre-ILK error interrupt ack 18505f21b0fe drm/i915: Fix hotplug irq ack on i965/g4x 5ea72593b0ed drm/i915: Fix PIPESTATE irq ack on i965/g4x == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9305/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala ` (6 preceding siblings ...) 2018-06-14 18:20 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) Patchwork @ 2018-06-15 2:11 ` Patchwork 7 siblings, 0 replies; 20+ messages in thread From: Patchwork @ 2018-06-15 2:11 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx == Series Details == Series: series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) URL : https://patchwork.freedesktop.org/series/44589/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4318_full -> Patchwork_9305_full = == Summary - WARNING == Minor unknown changes coming with Patchwork_9305_full need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_9305_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. == Possible new issues == Here are the unknown changes that may have been introduced in Patchwork_9305_full: === IGT changes === ==== Warnings ==== igt@gem_exec_schedule@deep-bsd2: shard-kbl: PASS -> SKIP +2 == Known issues == Here are the changes found in Patchwork_9305_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@drv_selftest@live_gtt: shard-glk: PASS -> FAIL (fdo#105347) igt@drv_selftest@live_hangcheck: shard-glk: PASS -> DMESG-FAIL (fdo#106560) igt@gem_ppgtt@blt-vs-render-ctx0: shard-kbl: PASS -> INCOMPLETE (fdo#106023, fdo#103665) igt@kms_atomic_transition@1x-modeset-transitions-nonblocking-fencing: shard-glk: PASS -> FAIL (fdo#105703) igt@kms_flip@flip-vs-expired-vblank-interruptible: shard-glk: PASS -> FAIL (fdo#102887, fdo#105363) igt@kms_flip@plain-flip-fb-recreate: shard-glk: PASS -> FAIL (fdo#100368) igt@perf_pmu@other-init-2: shard-snb: PASS -> INCOMPLETE (fdo#105411) ==== Possible fixes ==== igt@drv_selftest@live_gtt: shard-apl: FAIL (fdo#105347) -> PASS igt@gem_exec_suspend@basic-s3: shard-kbl: INCOMPLETE (fdo#103665) -> PASS igt@kms_cursor_legacy@cursor-vs-flip-toggle: shard-kbl: FAIL (fdo#103355) -> PASS igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-glk: FAIL (fdo#105363) -> PASS igt@kms_frontbuffer_tracking@fbc-2p-primscrn-shrfb-plflip-blt: shard-glk: FAIL (fdo#104724, fdo#103167) -> PASS igt@prime_vgem@basic-fence-flip: shard-snb: FAIL (fdo#104008) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167 fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355 fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665 fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008 fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724 fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347 fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363 fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411 fdo#105703 https://bugs.freedesktop.org/show_bug.cgi?id=105703 fdo#106023 https://bugs.freedesktop.org/show_bug.cgi?id=106023 fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4318 -> Patchwork_9305 CI_DRM_4318: 51c35728be7da2a316981544aa370e9ff56f3b27 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4519: 3381a56be31defb3b5c23a4fbc19ac26a000c35b @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9305: a829c81624f1419ed1bf9742076838aafee17f47 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9305/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 20+ messages in thread
end of thread, other threads:[~2018-07-03 12:01 UTC | newest] Thread overview: 20+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-06-11 20:02 [PATCH 1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Ville Syrjala 2018-06-11 20:02 ` [PATCH 2/4] drm/i915: Fix hotplug " Ville Syrjala 2018-06-11 20:58 ` [Intel-gfx] " Chris Wilson 2018-06-14 16:27 ` Ville Syrjälä 2018-06-14 16:27 ` Ville Syrjälä 2018-06-14 17:56 ` [PATCH v2 " Ville Syrjala 2018-07-03 9:56 ` [Intel-gfx] " Imre Deak 2018-07-03 9:56 ` Imre Deak 2018-06-11 20:02 ` [PATCH 3/4] drm/i915: Fix pre-ILK error interrupt ack Ville Syrjala 2018-07-03 11:58 ` [Intel-gfx] " Imre Deak 2018-07-03 11:58 ` Imre Deak 2018-06-11 20:02 ` [PATCH 4/4] drm/i915: Unmask and enable master error interrupt on gen2/3 Ville Syrjala 2018-07-03 12:00 ` Imre Deak 2018-06-11 20:46 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x Patchwork 2018-06-11 20:53 ` [Intel-gfx] [PATCH 1/4] " Chris Wilson 2018-06-14 18:16 ` Ville Syrjälä 2018-06-14 18:16 ` Ville Syrjälä 2018-06-12 2:34 ` ✓ Fi.CI.IGT: success for series starting with [1/4] " Patchwork 2018-06-14 18:20 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915: Fix PIPESTATE irq ack on i965/g4x (rev2) Patchwork 2018-06-15 2:11 ` ✓ Fi.CI.IGT: " Patchwork
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