[Qemu-devel] [PATCH 0/3] i386: improve output from "-cpu help" argument

[Qemu-devel] [PATCH 0/3] i386: improve output from "-cpu help" argument

[Daniel P. Berrangé]

This short series is a set of improvements to the "-cpu help" output for
the x86 emulator. The patches describe what's change in each step, but
it is best visualized by looking at before/after state.

Before:

   Available CPUs:
   x86              486
   x86   Broadwell-IBRS  Intel Core Processor (Broadwell, IBRS)
   x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS)
   x86  Broadwell-noTSX  Intel Core Processor (Broadwell, no TSX)
   x86        Broadwell  Intel Core Processor (Broadwell)
   x86           Conroe  Intel Celeron_4x0 (Conroe/Merom Class Core 2)
   x86        EPYC-IBPB  AMD EPYC Processor (with IBPB)
   x86             EPYC  AMD EPYC Processor
   x86     Haswell-IBRS  Intel Core Processor (Haswell, IBRS)
   x86 Haswell-noTSX-IBRS  Intel Core Processor (Haswell, no TSX, IBRS)
   x86    Haswell-noTSX  Intel Core Processor (Haswell, no TSX)
   x86          Haswell  Intel Core Processor (Haswell)
   x86   IvyBridge-IBRS  Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)
   x86        IvyBridge  Intel Xeon E3-12xx v2 (Ivy Bridge)
   x86     Nehalem-IBRS  Intel Core i7 9xx (Nehalem Core i7, IBRS update)
   x86          Nehalem  Intel Core i7 9xx (Nehalem Class Core i7)
   x86       Opteron_G1  AMD Opteron 240 (Gen 1 Class Opteron)
   x86       Opteron_G2  AMD Opteron 22xx (Gen 2 Class Opteron)
   x86       Opteron_G3  AMD Opteron 23xx (Gen 3 Class Opteron)
   x86       Opteron_G4  AMD Opteron 62xx class CPU
   x86       Opteron_G5  AMD Opteron 63xx class CPU
   x86           Penryn  Intel Core 2 Duo P9xxx (Penryn Class Core 2)
   x86 SandyBridge-IBRS  Intel Xeon E312xx (Sandy Bridge, IBRS update)
   x86      SandyBridge  Intel Xeon E312xx (Sandy Bridge)
   x86 Skylake-Client-IBRS  Intel Core Processor (Skylake, IBRS)
   x86   Skylake-Client  Intel Core Processor (Skylake)
   x86 Skylake-Server-IBRS  Intel Xeon Processor (Skylake, IBRS)
   x86   Skylake-Server  Intel Xeon Processor (Skylake)
   x86    Westmere-IBRS  Westmere E56xx/L56xx/X56xx (IBRS update)
   x86         Westmere  Westmere E56xx/L56xx/X56xx (Nehalem-C)
   x86           athlon  QEMU Virtual CPU version 2.5+
   x86         core2duo  Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz
   x86          coreduo  Genuine Intel(R) CPU           T2600  @ 2.16GHz
   x86            kvm32  Common 32-bit KVM processor
   x86            kvm64  Common KVM processor
   x86             n270  Intel(R) Atom(TM) CPU N270   @ 1.60GHz
   x86          pentium
   x86         pentium2
   x86         pentium3
   x86           phenom  AMD Phenom(tm) 9550 Quad-Core Processor
   x86           qemu32  QEMU Virtual CPU version 2.5+
   x86           qemu64  QEMU Virtual CPU version 2.5+
   x86             base  base CPU model type with no features enabled
   x86             host  KVM processor with all supported host features (only available in KVM mode)
   x86              max  Enables all features supported by the accelerator in the current host

   Recognized CPUID flags:
     fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 pn clflush ds acpi mmx fxsr sse sse2 ss ht tm ia64 pbe
     pni pclmulqdq dtes64 monitor ds-cpl vmx smx est tm2 ssse3 cid fma cx16 xtpr pdcm pcid dca sse4.1 sse4.2 x2apic movbe popcnt tsc-deadline aes xsave osxsave avx f16c rdrand hypervisor
     fsgsbase tsc-adjust bmi1 hle avx2 smep bmi2 erms invpcid rtm mpx avx512f avx512dq rdseed adx smap avx512ifma pcommit clflushopt clwb avx512pf avx512er avx512cd sha-ni avx512bw avx512vl
     avx512vbmi umip pku ospke avx512-vpopcntdq la57 rdpid
     avx512-4vnniw avx512-4fmaps spec-ctrl
     syscall nx mmxext fxsr-opt pdpe1gb rdtscp lm 3dnowext 3dnow
     lahf-lm cmp-legacy svm extapic cr8legacy abm sse4a misalignsse 3dnowprefetch osvw ibs xop skinit wdt lwp fma4 tce nodeid-msr tbm topoext perfctr-core perfctr-nb
     invtsc
     ibpb
     xstore xstore-en xcrypt xcrypt-en ace2 ace2-en phe phe-en pmm pmm-en
     kvmclock kvm-nopiodelay kvm-mmu kvmclock kvm-asyncpf kvm-steal-time kvm-pv-eoi kvm-pv-unhalt kvm-pv-tlb-flush kvmclock-stable-bit

     npt lbrv svm-lock nrip-save tsc-scale vmcb-clean flushbyasid decodeassists pause-filter pfthreshold
     xsaveopt xsavec xgetbv1 xsaves
     arat

After:

   Available CPUs:
   x86 486
   x86 Broadwell             Intel Core Processor (Broadwell)
   x86 Broadwell-IBRS        Intel Core Processor (Broadwell, IBRS)
   x86 Broadwell-noTSX       Intel Core Processor (Broadwell, no TSX)
   x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS)
   x86 Conroe                Intel Celeron_4x0 (Conroe/Merom Class Core 2)
   x86 EPYC                  AMD EPYC Processor
   x86 EPYC-IBPB             AMD EPYC Processor (with IBPB)
   x86 Haswell               Intel Core Processor (Haswell)
   x86 Haswell-IBRS          Intel Core Processor (Haswell, IBRS)
   x86 Haswell-noTSX         Intel Core Processor (Haswell, no TSX)
   x86 Haswell-noTSX-IBRS    Intel Core Processor (Haswell, no TSX, IBRS)
   x86 IvyBridge             Intel Xeon E3-12xx v2 (Ivy Bridge)
   x86 IvyBridge-IBRS        Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)
   x86 Nehalem               Intel Core i7 9xx (Nehalem Class Core i7)
   x86 Nehalem-IBRS          Intel Core i7 9xx (Nehalem Core i7, IBRS update)
   x86 Opteron_G1            AMD Opteron 240 (Gen 1 Class Opteron)
   x86 Opteron_G2            AMD Opteron 22xx (Gen 2 Class Opteron)
   x86 Opteron_G3            AMD Opteron 23xx (Gen 3 Class Opteron)
   x86 Opteron_G4            AMD Opteron 62xx class CPU
   x86 Opteron_G5            AMD Opteron 63xx class CPU
   x86 Penryn                Intel Core 2 Duo P9xxx (Penryn Class Core 2)
   x86 SandyBridge           Intel Xeon E312xx (Sandy Bridge)
   x86 SandyBridge-IBRS      Intel Xeon E312xx (Sandy Bridge, IBRS update)
   x86 Skylake-Client        Intel Core Processor (Skylake)
   x86 Skylake-Client-IBRS   Intel Core Processor (Skylake, IBRS)
   x86 Skylake-Server        Intel Xeon Processor (Skylake)
   x86 Skylake-Server-IBRS   Intel Xeon Processor (Skylake, IBRS)
   x86 Westmere              Westmere E56xx/L56xx/X56xx (Nehalem-C)
   x86 Westmere-IBRS         Westmere E56xx/L56xx/X56xx (IBRS update)
   x86 athlon                QEMU Virtual CPU version 2.5+
   x86 core2duo              Intel(R) Core(TM)2 Duo CPU     T7700  @ 2.40GHz
   x86 coreduo               Genuine Intel(R) CPU           T2600  @ 2.16GHz
   x86 kvm32                 Common 32-bit KVM processor
   x86 kvm64                 Common KVM processor
   x86 n270                  Intel(R) Atom(TM) CPU N270   @ 1.60GHz
   x86 pentium
   x86 pentium2
   x86 pentium3
   x86 phenom                AMD Phenom(tm) 9550 Quad-Core Processor
   x86 qemu32                QEMU Virtual CPU version 2.5+
   x86 qemu64                QEMU Virtual CPU version 2.5+
   x86 base                  base CPU model type with no features enabled
   x86 host                  Enables all features supported by the accelerator in the current host
   x86 max                   Enables all features supported by the accelerator in the current host

   Recognized CPUID flags:
     3dnow 3dnowext 3dnowprefetch abm ace2 ace2-en acpi adx aes apic arat avx
     avx2 avx512-4fmaps avx512-4vnniw avx512-vpopcntdq avx512bitalg avx512bw
     avx512cd avx512dq avx512er avx512f avx512ifma avx512pf avx512vbmi
     avx512vbmi2 avx512vl avx512vnni bmi1 bmi2 cid clflush clflushopt clwb
     cmov cmp-legacy cr8legacy cx16 cx8 dca de decodeassists ds ds-cpl dtes64
     erms est extapic f16c flushbyasid fma fma4 fpu fsgsbase fxsr fxsr-opt
     gfni hle ht hypervisor ia64 ibpb ibs intel-pt invpcid invtsc kvm-asyncpf
     kvm-hint-dedicated kvm-mmu kvm-nopiodelay kvm-pv-eoi kvm-pv-tlb-flush
     kvm-pv-unhalt kvm-steal-time kvmclock kvmclock kvmclock-stable-bit la57
     lahf-lm lbrv lm lwp mca mce misalignsse mmx mmxext monitor movbe mpx msr
     mtrr nodeid-msr npt nrip-save nx ospke osvw osxsave pae pat pause-filter
     pbe pcid pclmulqdq pcommit pdcm pdpe1gb perfctr-core perfctr-nb
     pfthreshold pge phe phe-en pku pmm pmm-en pn pni popcnt pse pse36 rdpid
     rdrand rdseed rdtscp rtm sep sha-ni skinit smap smep smx spec-ctrl ss sse
     sse2 sse4.1 sse4.2 sse4a ssse3 svm svm-lock syscall tbm tce tm tm2
     topoext tsc tsc-adjust tsc-deadline tsc-scale umip vaes vmcb-clean vme
     vmx vpclmulqdq wdt x2apic xcrypt xcrypt-en xgetbv1 xop xsave xsavec
     xsaveopt xsaves xstore xstore-en xtpr

One possible change, that I didn't include in patch 2, is to sort the
CPU model names case insensitively. That would be a more natural way of
doing alphabetical sorting for human output. The flip side is that it is
quite nice that the "modern" CPU models are all upper case and so appear
"first" in the listing. Except "486" is first no matter what. Ho, Hum.

Daniel P. Berrangé (3):
  i386: improve alignment of CPU model listing
  i386: improve sorting of CPU model names
  i386: display known CPUID features linewrapped, in alphabetical order

 target/i386/cpu.c | 57 ++++++++++++++++++++++++++++++-----------------
 1 file changed, 37 insertions(+), 20 deletions(-)

-- 
2.17.0

[Qemu-devel] [PATCH 1/3] i386: improve alignment of CPU model listing

[Daniel P. Berrangé]

Since the addition of the -IBRS CPU model variants, the descriptions
shown by '-cpu help' are not well aligned, as several model names
overflow the space allowed. Right aligning the CPU model names is also
not attractive, because it obscures the common name prefixes of many
models. The CPU model name field needs to be 4 characters larger, and
be left aligned instead.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
 target/i386/cpu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 94260412e2..aa4d9949b4 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3206,7 +3206,7 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
         desc = cc->cpu_def->model_id;
     }
 
-    (*s->cpu_fprintf)(s->file, "x86 %16s  %-48s\n",
+    (*s->cpu_fprintf)(s->file, "x86 %-20s  %-48s\n",
                       name, desc);
     g_free(name);
 }
-- 
2.17.0

[Qemu-devel] [PATCH 2/3] i386: improve sorting of CPU model names

[Daniel P. Berrangé]

The current list of CPU model names output by "-cpu help" is sorted
alphabetically based on the internal QOM class name. The text that is
displayed, however, uses the CPU model name, which is equivalent to the
QOM class name, minus a suffix. Unfortunately that suffix has an effect
on the sort ordering, for example, causing the various Broadwell
variants to appear reversed:

  x86 486
  x86 Broadwell-IBRS        Intel Core Processor (Broadwell, IBRS)
  x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS
  x86 Broadwell-noTSX       Intel Core Processor (Broadwell, no TSX)
  x86 Broadwell             Intel Core Processor (Broadwell)
  x86 Conroe                Intel Celeron_4x0 (Conroe/Merom Class Core 2)

By sorting on the actual CPU model name text that is displayed, the
result is

  x86 486
  x86 Broadwell             Intel Core Processor (Broadwell)
  x86 Broadwell-IBRS        Intel Core Processor (Broadwell, IBRS)
  x86 Broadwell-noTSX       Intel Core Processor (Broadwell, no TSX)
  x86 Broadwell-noTSX-IBRS  Intel Core Processor (Broadwell, no TSX, IBRS)
  x86 Conroe                Intel Celeron_4x0 (Conroe/Merom Class Core 2)

This requires extra string allocations during sorting, but this is not a
concern given the usage scenario and the number of CPU models that exist.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
 target/i386/cpu.c | 14 +++++++++-----
 1 file changed, 9 insertions(+), 5 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index aa4d9949b4..cb074082b3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3177,15 +3177,19 @@ static gint x86_cpu_list_compare(gconstpointer a, gconstpointer b)
     ObjectClass *class_b = (ObjectClass *)b;
     X86CPUClass *cc_a = X86_CPU_CLASS(class_a);
     X86CPUClass *cc_b = X86_CPU_CLASS(class_b);
-    const char *name_a, *name_b;
+    char *name_a, *name_b;
+    int ret;
 
     if (cc_a->ordering != cc_b->ordering) {
-        return cc_a->ordering - cc_b->ordering;
+        ret = cc_a->ordering - cc_b->ordering;
     } else {
-        name_a = object_class_get_name(class_a);
-        name_b = object_class_get_name(class_b);
-        return strcmp(name_a, name_b);
+        name_a = x86_cpu_class_get_model_name(cc_a);
+        name_b = x86_cpu_class_get_model_name(cc_b);
+        ret = strcmp(name_a, name_b);
+        g_free(name_a);
+        g_free(name_b);
     }
+    return ret;
 }
 
 static GSList *get_sorted_cpu_model_list(void)
-- 
2.17.0

[Qemu-devel] [PATCH 3/3] i386: display known CPUID features linewrapped, in alphabetical order

[Daniel P. Berrangé]

When using '-cpu help' the list of CPUID features is grouped according
to the internal low level CPUID grouping. The data printed results in
very long lines too.

This combines to make it hard for users to read the output and identify
if QEMU knows about the feature they wish to use.

This change gets rid of the grouping of features and treats all flags as
single list. The list is sorted into alphabetical order and the printing
with line wrapping at the 77th column.

Signed-off-by: Daniel P. Berrangé <berrange@redhat.com>
---
 target/i386/cpu.c | 41 +++++++++++++++++++++++++++--------------
 1 file changed, 27 insertions(+), 14 deletions(-)

diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index cb074082b3..8043e41be8 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -3157,17 +3157,21 @@ static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
 
 /* Print all cpuid feature names in featureset
  */
-static void listflags(FILE *f, fprintf_function print, const char **featureset)
+static void listflags(FILE *f, fprintf_function print, GList *features)
 {
-    int bit;
-    bool first = true;
-
-    for (bit = 0; bit < 32; bit++) {
-        if (featureset[bit]) {
-            print(f, "%s%s", first ? "" : " ", featureset[bit]);
-            first = false;
+    size_t len = 0;
+    GList *tmp;
+
+    for (tmp = features; tmp; tmp = tmp->next) {
+        const char *name = tmp->data;
+        if ((len + strlen(name) + 1) >= 75) {
+            print(f, "\n");
+            len = 0;
         }
+        print(f, "%s%s", len == 0 ? "  " : " ", name);
+        len += strlen(name) + 1;
     }
+    print(f, "\n");
 }
 
 /* Sort alphabetically by type name, respecting X86CPUClass::ordering. */
@@ -3218,26 +3222,35 @@ static void x86_cpu_list_entry(gpointer data, gpointer user_data)
 /* list available CPU models and flags */
 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
 {
-    int i;
+    int i, j;
     CPUListState s = {
         .file = f,
         .cpu_fprintf = cpu_fprintf,
     };
     GSList *list;
+    GList *names = NULL;
 
     (*cpu_fprintf)(f, "Available CPUs:\n");
     list = get_sorted_cpu_model_list();
     g_slist_foreach(list, x86_cpu_list_entry, &s);
     g_slist_free(list);
 
-    (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
+    names = NULL;
     for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
         FeatureWordInfo *fw = &feature_word_info[i];
-
-        (*cpu_fprintf)(f, "  ");
-        listflags(f, cpu_fprintf, fw->feat_names);
-        (*cpu_fprintf)(f, "\n");
+        for (j = 0; j < 32; j++) {
+            if (fw->feat_names[j]) {
+                names = g_list_append(names, (gpointer)fw->feat_names[j]);
+            }
+        }
     }
+
+    names = g_list_sort(names, (GCompareFunc)strcmp);
+
+    (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
+    listflags(f, cpu_fprintf, names);
+    (*cpu_fprintf)(f, "\n");
+    g_list_free(names);
 }
 
 static void x86_cpu_definition_entry(gpointer data, gpointer user_data)
-- 
2.17.0

Re: [Qemu-devel] [PATCH 3/3] i386: display known CPUID features linewrapped, in alphabetical order

[Eduardo Habkost]

On Wed, Jun 06, 2018 at 05:55:27PM +0100, Daniel P. Berrangé wrote:
[...]
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index cb074082b3..8043e41be8 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -3157,17 +3157,21 @@ static void x86_cpu_class_check_missing_features(X86CPUClass *xcc,
>  
>  /* Print all cpuid feature names in featureset
>   */
> -static void listflags(FILE *f, fprintf_function print, const char **featureset)
> +static void listflags(FILE *f, fprintf_function print, GList *features)
>  {
> -    int bit;
> -    bool first = true;
> -
> -    for (bit = 0; bit < 32; bit++) {
> -        if (featureset[bit]) {
> -            print(f, "%s%s", first ? "" : " ", featureset[bit]);
> -            first = false;
> +    size_t len = 0;
> +    GList *tmp;
> +
> +    for (tmp = features; tmp; tmp = tmp->next) {
> +        const char *name = tmp->data;
> +        if ((len + strlen(name) + 1) >= 75) {
> +            print(f, "\n");
> +            len = 0;
>          }
> +        print(f, "%s%s", len == 0 ? "  " : " ", name);
> +        len += strlen(name) + 1;
>      }
> +    print(f, "\n");

I'd love to have generic helper functions to format text like
this, but that's not a reason to block this patch from being
included.  I will queue the series on x86-next.  Thanks!

-- 
Eduardo

Re: [Qemu-devel] [PATCH 0/3] i386: improve output from "-cpu help" argument

[Eduardo Habkost]

On Wed, Jun 06, 2018 at 05:55:24PM +0100, Daniel P. Berrangé wrote:
> This short series is a set of improvements to the "-cpu help" output for
> the x86 emulator. The patches describe what's change in each step, but
> it is best visualized by looking at before/after state.
[...]

Queue on x86-next, thanks!

-- 
Eduardo