* [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy
@ 2018-06-20 11:54 Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/rendercopy: Use gen4 definitions if applicable Lukasz Kalamarz
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Lukasz Kalamarz @ 2018-06-20 11:54 UTC (permalink / raw)
To: igt-dev
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Add rendercopy implementation for gen4/5. Basic structure
copied from the gen6 implementation, and the gen4/5 specific
bits were mostly lifted from sna.
v2: Renamed registers definitions, which are GEN4 specific
to include that prefix (Lukasz)
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
---
lib/Makefile.sources | 2 +
lib/gen4_render.h | 628 ++++++++++++++++++++++++++++++++++++++++++
lib/intel_batchbuffer.c | 2 +
lib/meson.build | 1 +
lib/rendercopy.h | 5 +
lib/rendercopy_gen4.c | 704 ++++++++++++++++++++++++++++++++++++++++++++++++
6 files changed, 1342 insertions(+)
create mode 100644 lib/gen4_render.h
create mode 100644 lib/rendercopy_gen4.c
diff --git a/lib/Makefile.sources b/lib/Makefile.sources
index 042c1d3b..e0ebd02c 100644
--- a/lib/Makefile.sources
+++ b/lib/Makefile.sources
@@ -71,10 +71,12 @@ lib_source_list = \
gen8_media.h \
rendercopy_i915.c \
rendercopy_i830.c \
+ gen4_render.h \
gen6_render.h \
gen7_render.h \
gen8_render.h \
gen9_render.h \
+ rendercopy_gen4.c \
rendercopy_gen6.c \
rendercopy_gen7.c \
rendercopy_gen8.c \
diff --git a/lib/gen4_render.h b/lib/gen4_render.h
new file mode 100644
index 00000000..866ab39c
--- /dev/null
+++ b/lib/gen4_render.h
@@ -0,0 +1,628 @@
+#ifndef GEN4_RENDER_H
+#define GEN4_RENDER_H
+
+#include <stdint.h>
+
+#define GEN4_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
+ ((Pipeline) << 27) | \
+ ((Opcode) << 24) | \
+ ((Subopcode) << 16))
+
+#define GEN4_URB_FENCE GEN4_3D(0, 0, 0)
+# define UF0_CS_REALLOC (1 << 13)
+# define UF0_VFE_REALLOC (1 << 12)
+# define UF0_SF_REALLOC (1 << 11)
+# define UF0_CLIP_REALLOC (1 << 10)
+# define UF0_GS_REALLOC (1 << 9)
+# define UF0_VS_REALLOC (1 << 8)
+# define UF1_CLIP_FENCE_SHIFT 20
+# define UF1_GS_FENCE_SHIFT 10
+# define UF1_VS_FENCE_SHIFT 0
+# define UF2_CS_FENCE_SHIFT 20
+# define UF2_VFE_FENCE_SHIFT 10
+# define UF2_SF_FENCE_SHIFT 0
+
+#define GEN4_CS_URB_STATE GEN4_3D(0, 0, 1)
+
+#define GEN4_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1)
+# define BASE_ADDRESS_MODIFY (1 << 0)
+
+#define GEN4_STATE_SIP GEN4_3D(0, 1, 2)
+
+#define GEN4_PIPELINE_SELECT GEN4_3D(0, 1, 4)
+#define G4X_PIPELINE_SELECT GEN4_3D(1, 1, 4)
+# define PIPELINE_SELECT_3D 0
+# define PIPELINE_SELECT_MEDIA 1
+
+#define GEN4_3DSTATE_PIPELINED_POINTERS GEN4_3D(3, 0, 0)
+# define GEN4_GS_DISABLE 0
+# define GEN4_GS_ENABLE 1
+# define GEN4_CLIP_DISABLE 0
+# define GEN4_CLIP_ENABLE 1
+
+#define GEN4_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 1)
+
+#define GEN4_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 8)
+# define GEN4_VB0_BUFFER_INDEX_SHIFT 27
+# define GEN4_VB0_VERTEXDATA (0 << 26)
+# define GEN4_VB0_INSTANCEDATA (1 << 26)
+# define VB0_BUFFER_PITCH_SHIFT 0
+
+#define GEN4_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 9)
+# define GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT 27
+# define GEN4_VE0_VALID (1 << 26)
+# define VE0_FORMAT_SHIFT 16
+# define VE0_OFFSET_SHIFT 0
+# define VE1_VFCOMPONENT_0_SHIFT 28
+# define VE1_VFCOMPONENT_1_SHIFT 24
+# define VE1_VFCOMPONENT_2_SHIFT 20
+# define VE1_VFCOMPONENT_3_SHIFT 16
+# define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0
+
+#define GEN4_VFCOMPONENT_NOSTORE 0
+#define GEN4_VFCOMPONENT_STORE_SRC 1
+#define GEN4_VFCOMPONENT_STORE_0 2
+#define GEN4_VFCOMPONENT_STORE_1_FLT 3
+#define GEN4_VFCOMPONENT_STORE_1_INT 4
+#define GEN4_VFCOMPONENT_STORE_VID 5
+#define GEN4_VFCOMPONENT_STORE_IID 6
+#define GEN4_VFCOMPONENT_STORE_PID 7
+
+#define GEN4_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0)
+
+#define GEN4_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 5)
+# define GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29
+# define GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18
+
+#define GEN4_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
+#define GEN4_DEPTHFORMAT_D32_FLOAT 1
+#define GEN4_DEPTHFORMAT_D24_UNORM_S8_UINT 2
+#define GEN4_DEPTHFORMAT_D24_UNORM_X8_UINT 3
+#define GEN4_DEPTHFORMAT_D16_UNORM 5
+
+#define GEN4_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10)
+# define GEN4_3DSTATE_DEPTH_CLEAR_VALID (1 << 15)
+
+#define GEN4_3DPRIMITIVE GEN4_3D(3, 3, 0)
+# define GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
+# define GEN4_3DPRIMITIVE_VERTEX_RANDOM (1 << 15)
+# define GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT 10
+
+#define _3DPRIM_POINTLIST 0x01
+#define _3DPRIM_LINELIST 0x02
+#define _3DPRIM_LINESTRIP 0x03
+#define _3DPRIM_TRILIST 0x04
+#define _3DPRIM_TRISTRIP 0x05
+#define _3DPRIM_TRIFAN 0x06
+#define _3DPRIM_QUADLIST 0x07
+#define _3DPRIM_QUADSTRIP 0x08
+#define _3DPRIM_LINELIST_ADJ 0x09
+#define _3DPRIM_LINESTRIP_ADJ 0x0A
+#define _3DPRIM_TRILIST_ADJ 0x0B
+#define _3DPRIM_TRISTRIP_ADJ 0x0C
+#define _3DPRIM_TRISTRIP_REVERSE 0x0D
+#define _3DPRIM_POLYGON 0x0E
+#define _3DPRIM_RECTLIST 0x0F
+#define _3DPRIM_LINELOOP 0x10
+#define _3DPRIM_POINTLIST_BF 0x11
+#define _3DPRIM_LINESTRIP_CONT 0x12
+#define _3DPRIM_LINESTRIP_BF 0x13
+#define _3DPRIM_LINESTRIP_CONT_BF 0x14
+#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
+
+#define GEN4_CULLMODE_BOTH 0
+#define GEN4_CULLMODE_NONE 1
+#define GEN4_CULLMODE_FRONT 2
+#define GEN4_CULLMODE_BACK 3
+
+#define GEN4_BORDER_COLOR_MODE_DEFAULT 0
+#define GEN4_BORDER_COLOR_MODE_LEGACY 1
+
+#define GEN4_MAPFILTER_NEAREST 0
+#define GEN4_MAPFILTER_LINEAR 1
+#define GEN4_MAPFILTER_ANISOTROPIC 2
+#define GEN4_MAPFILTER_MONO 6
+
+#define GEN4_MIPFILTER_NONE 0
+#define GEN4_MIPFILTER_NEAREST 1
+#define GEN4_MIPFILTER_LINEAR 3
+
+#define GEN4_PREFILTER_ALWAYS 0
+#define GEN4_PREFILTER_NEVER 1
+#define GEN4_PREFILTER_LESS 2
+#define GEN4_PREFILTER_EQUAL 3
+#define GEN4_PREFILTER_LEQUAL 4
+#define GEN4_PREFILTER_GREATER 5
+#define GEN4_PREFILTER_NOTEQUAL 6
+#define GEN4_PREFILTER_GEQUAL 7
+
+#define GEN4_TEXCOORDMODE_WRAP 0
+#define GEN4_TEXCOORDMODE_MIRROR 1
+#define GEN4_TEXCOORDMODE_CLAMP 2
+#define GEN4_TEXCOORDMODE_CUBE 3
+#define GEN4_TEXCOORDMODE_CLAMP_BORDER 4
+#define GEN4_TEXCOORDMODE_MIRROR_ONCE 5
+
+#define GEN4_LOD_PRECLAMP_D3D 0
+#define GEN4_LOD_PRECLAMP_OGL 1
+
+/* The hardware supports two different modes for border color. The
+ * default (OpenGL) mode uses floating-point color channels, while the
+ * legacy mode uses 4 bytes.
+ *
+ * More significantly, the legacy mode respects the components of the
+ * border color for channels not present in the source, (whereas the
+ * default mode will ignore the border color's alpha channel and use
+ * alpha==1 for an RGB source, for example).
+ *
+ * The legacy mode matches the semantics specified by the Render
+ * extension.
+ */
+struct gen4_sampler_default_border_color {
+ float color[4];
+};
+
+struct gen4_sampler_legacy_border_color {
+ uint8_t color[4];
+};
+
+struct gen4_sampler_state {
+ struct {
+ uint32_t shadow_function:3;
+ uint32_t lod_bias:11;
+ uint32_t min_filter:3;
+ uint32_t mag_filter:3;
+ uint32_t mip_filter:2;
+ uint32_t base_level:5;
+ uint32_t pad0:1;
+ uint32_t lod_preclamp:1;
+ uint32_t border_color_mode:1;
+ uint32_t pad1:1;
+ uint32_t disable:1;
+ } ss0;
+
+ struct {
+ uint32_t r_wrap_mode:3;
+ uint32_t t_wrap_mode:3;
+ uint32_t s_wrap_mode:3;
+ uint32_t cube_ctlr_mode:1;
+ uint32_t pad:2;
+ uint32_t max_lod:10;
+ uint32_t min_lod:10;
+ } ss1;
+
+ struct {
+ uint32_t pad:5;
+ uint32_t border_color_pointer:27;
+ } ss2;
+
+ struct {
+ uint32_t pad:13;
+ uint32_t address_rounding_enable:6;
+ uint32_t max_aniso:3;
+ uint32_t chroma_key_mode:1;
+ uint32_t chroma_key_index:2;
+ uint32_t chroma_key_enable:1;
+ uint32_t monochrome_filter_width:3;
+ uint32_t monochrome_filter_height:3;
+ } ss3;
+};
+
+typedef enum {
+ SAMPLER_FILTER_NEAREST = 0,
+ SAMPLER_FILTER_BILINEAR,
+ FILTER_COUNT
+} sampler_filter_t;
+
+typedef enum {
+ SAMPLER_EXTEND_NONE = 0,
+ SAMPLER_EXTEND_REPEAT,
+ SAMPLER_EXTEND_PAD,
+ SAMPLER_EXTEND_REFLECT,
+ EXTEND_COUNT
+} sampler_extend_t;
+
+struct gen4_surface_state {
+ struct {
+ unsigned int cube_pos_z:1;
+ unsigned int cube_neg_z:1;
+ unsigned int cube_pos_y:1;
+ unsigned int cube_neg_y:1;
+ unsigned int cube_pos_x:1;
+ unsigned int cube_neg_x:1;
+ unsigned int media_boundary_pixel_mode:2;
+ unsigned int render_cache_read_mode:1;
+ unsigned int cube_corner_mode:1;
+ unsigned int mipmap_layout_mode:1;
+ unsigned int vert_line_stride_ofs:1;
+ unsigned int vert_line_stride:1;
+ unsigned int color_blend:1;
+ unsigned int writedisable_blue:1;
+ unsigned int writedisable_green:1;
+ unsigned int writedisable_red:1;
+ unsigned int writedisable_alpha:1;
+ unsigned int surface_format:9;
+ unsigned int data_return_format:1;
+ unsigned int pad0:1;
+ unsigned int surface_type:3;
+ } ss0;
+
+ struct {
+ unsigned int base_addr;
+ } ss1;
+
+ struct {
+ unsigned int render_target_rotation:2;
+ unsigned int mip_count:4;
+ unsigned int width:13;
+ unsigned int height:13;
+ } ss2;
+
+ struct {
+ unsigned int tile_walk:1;
+ unsigned int tiled_surface:1;
+ unsigned int pad0:1;
+ unsigned int pitch:17;
+ unsigned int pad1:1;
+ unsigned int depth:11;
+ } ss3;
+
+ struct {
+ unsigned int pad:8;
+ unsigned int render_target_view_extent:9;
+ unsigned int min_array_elt:11;
+ unsigned int min_lod:4;
+ } ss4;
+
+ struct {
+ unsigned int pad:20;
+ unsigned int y_offset:4;
+ unsigned int pad1:1;
+ unsigned int x_offset:7;
+ } ss5;
+};
+
+struct gen4_cc_viewport {
+ float min_depth;
+ float max_depth;
+};
+
+struct gen4_vs_state {
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer:26;
+ } vs0;
+
+ struct {
+ unsigned int pad0:7;
+ unsigned int sw_exception_enable:1;
+ unsigned int pad1:3;
+ unsigned int mask_stack_exception_enable:1;
+ unsigned int pad2:1;
+ unsigned int illegal_op_exception_enable:1;
+ unsigned int pad3:2;
+ unsigned int floating_point_mode:1;
+ unsigned int thread_priority:1;
+ unsigned int binding_table_entry_count:8;
+ unsigned int pad4:5;
+ unsigned int single_program_flow:1;
+ } vs1;
+
+ struct {
+ unsigned int per_thread_scratch_space:4;
+ unsigned int pad0:6;
+ unsigned int scratch_space_pointer:22;
+ } vs2;
+
+ struct {
+ unsigned int dispatch_grf_start_reg:4;
+ unsigned int urb_entry_read_offset:6;
+ unsigned int pad0:1;
+ unsigned int urb_entry_read_length:6;
+ unsigned int pad1:1;
+ unsigned int const_urb_entry_read_offset:6;
+ unsigned int pad2:1;
+ unsigned int const_urb_entry_read_length:6;
+ unsigned int pad3:1;
+ } vs3;
+
+ struct {
+ unsigned int pad0:10;
+ unsigned int stats_enable:1;
+ unsigned int nr_urb_entries:7;
+ unsigned int pad1:1;
+ unsigned int urb_entry_allocation_size:5;
+ unsigned int pad2:1;
+ unsigned int max_threads:6;
+ unsigned int pad3:1;
+ } vs4;
+
+ struct {
+ unsigned int sampler_count:3;
+ unsigned int pad:2;
+ unsigned int sampler_state_pointer:27;
+ } vs5;
+
+ struct {
+ unsigned int vs_enable:1;
+ unsigned int vert_cache_disable:1;
+ unsigned int pad:30;
+ } vs6;
+};
+
+struct gen4_sf_state {
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer:26;
+ } sf0;
+
+ struct {
+ unsigned int barycentric_interp:1; /* ilk */
+ unsigned int pad0:6;
+ unsigned int sw_exception_enable:1;
+ unsigned int pad1:3;
+ unsigned int mask_stack_exception_enable:1;
+ unsigned int pad2:1;
+ unsigned int illegal_op_exception_enable:1;
+ unsigned int pad3:2;
+ unsigned int floating_point_mode:1;
+ unsigned int thread_priority:1;
+ unsigned int binding_table_entry_count:8;
+ unsigned int pad4:6;
+ } sf1;
+
+ struct {
+ unsigned int per_thread_scratch_space:4;
+ unsigned int pad0:6;
+ unsigned int scratch_space_pointer:22;
+ } sf2;
+
+ struct {
+ unsigned int dispatch_grf_start_reg:4;
+ unsigned int urb_entry_read_offset:6;
+ unsigned int pad0:1;
+ unsigned int urb_entry_read_length:7;
+ unsigned int const_urb_entry_read_offset:6;
+ unsigned int pad1:1;
+ unsigned int const_urb_entry_read_length:6;
+ unsigned int pad2:1;
+ } sf3;
+
+ struct {
+ unsigned int pad0:10;
+ unsigned int stats_enable:1;
+ unsigned int nr_urb_entries:8;
+ unsigned int urb_entry_allocation_size:6;
+ unsigned int max_threads:6;
+ unsigned int pad2:1;
+ } sf4;
+
+ struct {
+ unsigned int front_winding:1;
+ unsigned int viewport_transform:1;
+ unsigned int pad:3;
+ unsigned int sf_viewport_state_offset:27;
+ } sf5;
+
+ struct {
+ unsigned int pad:9;
+ unsigned int dest_org_vbias:4;
+ unsigned int dest_org_hbias:4;
+ unsigned int scissor:1;
+ unsigned int disable_2x2_trifilter:1;
+ unsigned int disable_zero_trifilter:1;
+ unsigned int point_rast_rule:2;
+ unsigned int line_endcap_aa_region_width:2;
+ unsigned int line_width:4;
+ unsigned int fast_scissor_disable:1;
+ unsigned int cull_mode:2;
+ unsigned int aa_enable:1;
+ } sf6;
+
+ struct {
+ unsigned int point_size:11;
+ unsigned int use_point_size_state:1;
+ unsigned int subpixel_precision:1;
+ unsigned int sprite_point:1;
+ unsigned int aa_line_dist_mode:1;
+ unsigned int pad:10;
+ unsigned int trifan_pv:2;
+ unsigned int linestrip_pv:2;
+ unsigned int tristrip_pv:2;
+ unsigned int line_last_pixel_enable:1;
+ } sf7;
+};
+
+struct gen4_wm_state {
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer:26;
+ } wm0;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int sw_exception_enable:1;
+ unsigned int mask_stack_exception_enable:1;
+ unsigned int pad2:1;
+ unsigned int illegal_op_exception_enable:1;
+ unsigned int pad3:3;
+ unsigned int depth_coeff_urb_read_offset:6;
+ unsigned int pad4:2;
+ unsigned int floating_point_mode:1;
+ unsigned int thread_priority:1;
+ unsigned int binding_table_entry_count:8;
+ unsigned int pad5:5;
+ unsigned int single_program_flow:1;
+ } wm1;
+
+ struct {
+ unsigned int per_thread_scratch_space:4;
+ unsigned int pad0:6;
+ unsigned int scratch_space_pointer:22;
+ } wm2;
+
+ struct {
+ unsigned int dispatch_grf_start_reg:4;
+ unsigned int urb_entry_read_offset:6;
+ unsigned int pad0:1;
+ unsigned int urb_entry_read_length:7;
+ unsigned int const_urb_entry_read_offset:6;
+ unsigned int pad1:1;
+ unsigned int const_urb_entry_read_length:6;
+ unsigned int pad2:1;
+ } wm3;
+
+ struct {
+ unsigned int stats_enable:1;
+ unsigned int pad0:1;
+ unsigned int sampler_count:3;
+ unsigned int sampler_state_pointer:27;
+ } wm4;
+
+ struct {
+ unsigned int enable_8_pix:1;
+ unsigned int enable_16_pix:1;
+ unsigned int enable_32_pix:1;
+ unsigned int enable_cont_32_pix:1; /* ctg+ */
+ unsigned int enable_cont_64_pix:1; /* ctg+ */
+ unsigned int pad0:1;
+ unsigned int fast_span_coverage:1; /* ilk */
+ unsigned int depth_clear:1; /* ilk */
+ unsigned int depth_resolve:1; /* ilk */
+ unsigned int hier_depth_resolve:1; /* ilk */
+ unsigned int legacy_global_depth_bias:1;
+ unsigned int line_stipple:1;
+ unsigned int depth_offset:1;
+ unsigned int polygon_stipple:1;
+ unsigned int line_aa_region_width:2;
+ unsigned int line_endcap_aa_region_width:2;
+ unsigned int early_depth_test:1;
+ unsigned int thread_dispatch_enable:1;
+ unsigned int program_uses_depth:1;
+ unsigned int program_computes_dpeth:1;
+ unsigned int program_uses_killpixel:1;
+ unsigned int legacy_line_rast:1;
+ unsigned int transposed_urb_read:1;
+ unsigned int max_threads:7;
+ } wm5;
+
+ struct {
+ float global_depth_offset_constant;
+ } wm6;
+
+ struct {
+ float global_depth_offset_scale;
+ } wm7;
+
+ /* ilk only from now on */
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_1:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_1:26;
+ } wm8;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_2:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_2:26;
+ } wm9;
+
+ struct {
+ unsigned int pad0:1;
+ unsigned int grf_reg_count_3:3;
+ unsigned int pad1:2;
+ unsigned int kernel_start_pointer_3:26;
+ } wm10;
+};
+
+struct gen4_color_calc_state {
+ struct {
+ unsigned int pad0:3;
+ unsigned int bf_stencil_pass_depth_pass_op:3;
+ unsigned int bf_stencil_pass_depth_fail_op:3;
+ unsigned int bf_stencil_fail_op:3;
+ unsigned int bf_stencil_func:3;
+ unsigned int bf_stencil_enable:1;
+ unsigned int pad1:2;
+ unsigned int stencil_write_enable:1;
+ unsigned int stencil_pass_depth_pass_op:3;
+ unsigned int stencil_pass_depth_fail_op:3;
+ unsigned int stencil_fail_op:3;
+ unsigned int stencil_func:3;
+ unsigned int stencil_enable:1;
+ } cc0;
+
+ struct {
+ unsigned int bf_stencil_ref:8;
+ unsigned int stencil_write_mask:8;
+ unsigned int stencil_test_mask:8;
+ unsigned int stencil_ref:8;
+ } cc1;
+
+ struct {
+ unsigned int logicop_enable:1;
+ unsigned int pad0:10;
+ unsigned int depth_write_enable:1;
+ unsigned int depth_test_function:3;
+ unsigned int depth_test:1;
+ unsigned int bf_stencil_write_mask:8;
+ unsigned int bf_stencil_test_mask:8;
+ } cc2;
+
+ struct {
+ unsigned int pad0:8;
+ unsigned int alpha_test_func:3;
+ unsigned int alpha_test:1;
+ unsigned int blend_enable:1;
+ unsigned int ia_blend_enable:1;
+ unsigned int pad1:1;
+ unsigned int alpha_test_format:1;
+ unsigned int pad2:16;
+ } cc3;
+
+ struct {
+ unsigned int pad0:5;
+ unsigned int cc_viewport_state_offset:27;
+ } cc4;
+
+ struct {
+ unsigned int pad0:2;
+ unsigned int ia_dest_blend_factor:5;
+ unsigned int ia_src_blend_factor:5;
+ unsigned int ia_blend_function:3;
+ unsigned int stats_enable:1;
+ unsigned int logicop_func:4;
+ unsigned int pad1:10;
+ unsigned int round_disable:1;
+ unsigned int dither_enable:1;
+ } cc5;
+
+ struct {
+ unsigned int clamp_post_alpha_blend:1;
+ unsigned int clamp_pre_alpha_blend:1;
+ unsigned int clamp_range:2;
+ unsigned int pad0:11;
+ unsigned int y_dither_offset:2;
+ unsigned int x_dither_offset:2;
+ unsigned int dest_blend_factor:5;
+ unsigned int src_blend_factor:5;
+ unsigned int blend_function:3;
+ } cc6;
+
+ struct {
+ union {
+ float f;
+ unsigned char ub[4];
+ } alpha_ref;
+ } cc7;
+};
+
+#endif
diff --git a/lib/intel_batchbuffer.c b/lib/intel_batchbuffer.c
index a85c760c..8eb101cd 100644
--- a/lib/intel_batchbuffer.c
+++ b/lib/intel_batchbuffer.c
@@ -833,6 +833,8 @@ igt_render_copyfunc_t igt_get_render_copyfunc(int devid)
copy = gen2_render_copyfunc;
else if (IS_GEN3(devid))
copy = gen3_render_copyfunc;
+ else if (IS_GEN4(devid) || IS_GEN5(devid))
+ copy = gen4_render_copyfunc;
else if (IS_GEN6(devid))
copy = gen6_render_copyfunc;
else if (IS_GEN7(devid))
diff --git a/lib/meson.build b/lib/meson.build
index 1a355414..78590c0b 100644
--- a/lib/meson.build
+++ b/lib/meson.build
@@ -32,6 +32,7 @@ lib_sources = [
'gpu_cmds.c',
'rendercopy_i915.c',
'rendercopy_i830.c',
+ 'rendercopy_gen4.c',
'rendercopy_gen6.c',
'rendercopy_gen7.c',
'rendercopy_gen8.c',
diff --git a/lib/rendercopy.h b/lib/rendercopy.h
index fdc3cabb..19b29dbb 100644
--- a/lib/rendercopy.h
+++ b/lib/rendercopy.h
@@ -43,6 +43,11 @@ void gen6_render_copyfunc(struct intel_batchbuffer *batch,
struct igt_buf *src, unsigned src_x, unsigned src_y,
unsigned width, unsigned height,
struct igt_buf *dst, unsigned dst_x, unsigned dst_y);
+void gen4_render_copyfunc(struct intel_batchbuffer *batch,
+ drm_intel_context *context,
+ struct igt_buf *src, unsigned src_x, unsigned src_y,
+ unsigned width, unsigned height,
+ struct igt_buf *dst, unsigned dst_x, unsigned dst_y);
void gen3_render_copyfunc(struct intel_batchbuffer *batch,
drm_intel_context *context,
struct igt_buf *src, unsigned src_x, unsigned src_y,
diff --git a/lib/rendercopy_gen4.c b/lib/rendercopy_gen4.c
new file mode 100644
index 00000000..97994ff5
--- /dev/null
+++ b/lib/rendercopy_gen4.c
@@ -0,0 +1,704 @@
+#include "rendercopy.h"
+#include "intel_chipset.h"
+#include "gen4_render.h"
+#include "surfaceformat.h"
+
+#include <assert.h>
+
+#define VERTEX_SIZE (3*4)
+
+#define URB_VS_ENTRY_SIZE 1
+#define URB_GS_ENTRY_SIZE 0
+#define URB_CL_ENTRY_SIZE 0
+#define URB_SF_ENTRY_SIZE 2
+#define URB_CS_ENTRY_SIZE 1
+
+#define GEN4_GRF_BLOCKS(nreg) (((nreg) + 15) / 16 - 1)
+#define SF_KERNEL_NUM_GRF 16
+#define PS_KERNEL_NUM_GRF 32
+
+static const uint32_t gen4_sf_kernel_nomask[][4] = {
+ { 0x00400031, 0x20c01fbd, 0x0069002c, 0x01110001 },
+ { 0x00600001, 0x206003be, 0x00690060, 0x00000000 },
+ { 0x00600040, 0x20e077bd, 0x00690080, 0x006940a0 },
+ { 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 },
+ { 0x00600040, 0x20e077bd, 0x006900a0, 0x00694060 },
+ { 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x008d0000, 0x8640c800 },
+};
+
+static const uint32_t gen5_sf_kernel_nomask[][4] = {
+ { 0x00400031, 0x20c01fbd, 0x1069002c, 0x02100001 },
+ { 0x00600001, 0x206003be, 0x00690060, 0x00000000 },
+ { 0x00600040, 0x20e077bd, 0x00690080, 0x006940a0 },
+ { 0x00600041, 0x202077be, 0x008d00e0, 0x000000c0 },
+ { 0x00600040, 0x20e077bd, 0x006900a0, 0x00694060 },
+ { 0x00600041, 0x204077be, 0x008d00e0, 0x000000c8 },
+ { 0x00600031, 0x20001fbc, 0x648d0000, 0x8808c800 },
+};
+
+static const uint32_t gen4_ps_kernel_nomask_affine[][4] = {
+ { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
+ { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
+ { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
+ { 0x00802059, 0x200077bc, 0x00000060, 0x008d0100 },
+ { 0x00802048, 0x204077be, 0x00000064, 0x008d0140 },
+ { 0x00802059, 0x200077bc, 0x00000070, 0x008d0100 },
+ { 0x00802048, 0x208077be, 0x00000074, 0x008d0140 },
+ { 0x00600201, 0x20200022, 0x008d0000, 0x00000000 },
+ { 0x00000201, 0x20280062, 0x00000000, 0x00000000 },
+ { 0x01800031, 0x21801d09, 0x008d0000, 0x02580001 },
+ { 0x00600001, 0x204003be, 0x008d0180, 0x00000000 },
+ { 0x00601001, 0x20c003be, 0x008d01a0, 0x00000000 },
+ { 0x00600001, 0x206003be, 0x008d01c0, 0x00000000 },
+ { 0x00601001, 0x20e003be, 0x008d01e0, 0x00000000 },
+ { 0x00600001, 0x208003be, 0x008d0200, 0x00000000 },
+ { 0x00601001, 0x210003be, 0x008d0220, 0x00000000 },
+ { 0x00600001, 0x20a003be, 0x008d0240, 0x00000000 },
+ { 0x00601001, 0x212003be, 0x008d0260, 0x00000000 },
+ { 0x00600201, 0x202003be, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x20001d28, 0x008d0000, 0x85a04800 },
+};
+
+static const uint32_t gen5_ps_kernel_nomask_affine[][4] = {
+ { 0x00800040, 0x23c06d29, 0x00480028, 0x10101010 },
+ { 0x00800040, 0x23806d29, 0x0048002a, 0x11001100 },
+ { 0x00802040, 0x2100753d, 0x008d03c0, 0x00004020 },
+ { 0x00802040, 0x2140753d, 0x008d0380, 0x00004024 },
+ { 0x00802059, 0x200077bc, 0x00000060, 0x008d0100 },
+ { 0x00802048, 0x204077be, 0x00000064, 0x008d0140 },
+ { 0x00802059, 0x200077bc, 0x00000070, 0x008d0100 },
+ { 0x00802048, 0x208077be, 0x00000074, 0x008d0140 },
+ { 0x01800031, 0x21801fa9, 0x208d0000, 0x0a8a0001 },
+ { 0x00802001, 0x304003be, 0x008d0180, 0x00000000 },
+ { 0x00802001, 0x306003be, 0x008d01c0, 0x00000000 },
+ { 0x00802001, 0x308003be, 0x008d0200, 0x00000000 },
+ { 0x00802001, 0x30a003be, 0x008d0240, 0x00000000 },
+ { 0x00600201, 0x202003be, 0x008d0020, 0x00000000 },
+ { 0x00800031, 0x20001d28, 0x548d0000, 0x94084800 },
+};
+
+static uint32_t
+batch_used(struct intel_batchbuffer *batch)
+{
+ return batch->ptr - batch->buffer;
+}
+
+static uint32_t
+batch_round_upto(struct intel_batchbuffer *batch, uint32_t divisor)
+{
+ uint32_t offset = batch_used(batch);
+ offset = (offset + divisor - 1) / divisor * divisor;
+ batch->ptr = batch->buffer + offset;
+ return offset;
+}
+
+static int gen4_max_vs_nr_urb_entries(uint32_t devid)
+{
+ return IS_GEN5(devid) ? 256 : 32;
+}
+
+static int gen4_max_sf_nr_urb_entries(uint32_t devid)
+{
+ return IS_GEN5(devid) ? 128 : 64;
+}
+
+static int gen4_urb_size(uint32_t devid)
+{
+ return IS_GEN5(devid) ? 1024 : IS_G4X(devid) ? 384 : 256;
+}
+
+static int gen4_max_sf_threads(uint32_t devid)
+{
+ return IS_GEN5(devid) ? 48 : 24;
+}
+
+static int gen4_max_wm_threads(uint32_t devid)
+{
+ return IS_GEN5(devid) ? 72 : IS_G4X(devid) ? 50 : 32;
+}
+
+static void
+gen4_render_flush(struct intel_batchbuffer *batch,
+ drm_intel_context *context, uint32_t batch_end)
+{
+ int ret;
+
+ ret = drm_intel_bo_subdata(batch->bo, 0, 4096, batch->buffer);
+ if (ret == 0)
+ ret = drm_intel_gem_bo_context_exec(batch->bo, context,
+ batch_end, 0);
+ assert(ret == 0);
+}
+
+static uint32_t
+gen4_bind_buf(struct intel_batchbuffer *batch,
+ struct igt_buf *buf,
+ uint32_t format, int is_dst)
+{
+ struct gen4_surface_state *ss;
+ uint32_t write_domain, read_domain;
+ int ret;
+
+ if (is_dst) {
+ write_domain = read_domain = I915_GEM_DOMAIN_RENDER;
+ } else {
+ write_domain = 0;
+ read_domain = I915_GEM_DOMAIN_SAMPLER;
+ }
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32);
+
+ ss->ss0.surface_type = SURFACE_2D;
+ ss->ss0.surface_format = format;
+
+ ss->ss0.data_return_format = SURFACERETURNFORMAT_FLOAT32;
+ ss->ss0.color_blend = 1;
+ ss->ss1.base_addr = buf->bo->offset;
+
+ ret = drm_intel_bo_emit_reloc(batch->bo,
+ intel_batchbuffer_subdata_offset(batch, ss) + 4,
+ buf->bo, 0,
+ read_domain, write_domain);
+ assert(ret == 0);
+
+ ss->ss2.height = igt_buf_height(buf) - 1;
+ ss->ss2.width = igt_buf_width(buf) - 1;
+ ss->ss3.pitch = buf->stride - 1;
+ ss->ss3.tiled_surface = buf->tiling != I915_TILING_NONE;
+ ss->ss3.tile_walk = buf->tiling == I915_TILING_Y;
+
+ return intel_batchbuffer_subdata_offset(batch, ss);
+}
+
+static uint32_t
+gen4_bind_surfaces(struct intel_batchbuffer *batch,
+ struct igt_buf *src,
+ struct igt_buf *dst)
+{
+ uint32_t *binding_table;
+
+ binding_table = intel_batchbuffer_subdata_alloc(batch, 32, 32);
+
+ binding_table[0] =
+ gen4_bind_buf(batch, dst, SURFACEFORMAT_B8G8R8A8_UNORM, 1);
+ binding_table[1] =
+ gen4_bind_buf(batch, src, SURFACEFORMAT_B8G8R8A8_UNORM, 0);
+
+ return intel_batchbuffer_subdata_offset(batch, binding_table);
+}
+
+static void
+gen4_emit_sip(struct intel_batchbuffer *batch)
+{
+ OUT_BATCH(GEN4_STATE_SIP | (2 - 2));
+ OUT_BATCH(0);
+}
+
+static void
+gen4_emit_state_base_address(struct intel_batchbuffer *batch)
+{
+ if (IS_GEN5(batch->devid)) {
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (8 - 2));
+ OUT_RELOC(batch->bo, /* general */
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BASE_ADDRESS_MODIFY);
+ OUT_RELOC(batch->bo, /* surface */
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0); /* media */
+ OUT_RELOC(batch->bo, /* instruction */
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BASE_ADDRESS_MODIFY);
+
+ /* upper bounds, disable */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* general */
+ OUT_BATCH(0); /* media */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* instruction */
+ } else {
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (6 - 2));
+ OUT_RELOC(batch->bo, /* general */
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BASE_ADDRESS_MODIFY);
+ OUT_RELOC(batch->bo, /* surface */
+ I915_GEM_DOMAIN_INSTRUCTION, 0,
+ BASE_ADDRESS_MODIFY);
+ OUT_BATCH(0); /* media */
+
+ /* upper bounds, disable */
+ OUT_BATCH(BASE_ADDRESS_MODIFY); /* general */
+ OUT_BATCH(0); /* media */
+ }
+}
+
+static void
+gen4_emit_pipelined_pointers(struct intel_batchbuffer *batch,
+ uint32_t vs, uint32_t sf,
+ uint32_t wm, uint32_t cc)
+{
+ OUT_BATCH(GEN4_3DSTATE_PIPELINED_POINTERS | (7 - 2));
+ OUT_BATCH(vs);
+ OUT_BATCH(GEN4_GS_DISABLE);
+ OUT_BATCH(GEN4_CLIP_DISABLE);
+ OUT_BATCH(sf);
+ OUT_BATCH(wm);
+ OUT_BATCH(cc);
+}
+
+static void
+gen4_emit_urb(struct intel_batchbuffer *batch)
+{
+ int vs_entries = gen4_max_vs_nr_urb_entries(batch->devid);
+ int gs_entries = 0;
+ int cl_entries = 0;
+ int sf_entries = gen4_max_sf_nr_urb_entries(batch->devid);
+ int cs_entries = 0;
+
+ int urb_vs_end = vs_entries * URB_VS_ENTRY_SIZE;
+ int urb_gs_end = urb_vs_end + gs_entries * URB_GS_ENTRY_SIZE;
+ int urb_cl_end = urb_gs_end + cl_entries * URB_CL_ENTRY_SIZE;
+ int urb_sf_end = urb_cl_end + sf_entries * URB_SF_ENTRY_SIZE;
+ int urb_cs_end = urb_sf_end + cs_entries * URB_CS_ENTRY_SIZE;
+
+ assert(urb_cs_end <= gen4_urb_size(batch->devid));
+
+ intel_batchbuffer_align(batch, 16);
+
+ OUT_BATCH(GEN4_URB_FENCE |
+ UF0_CS_REALLOC |
+ UF0_SF_REALLOC |
+ UF0_CLIP_REALLOC |
+ UF0_GS_REALLOC |
+ UF0_VS_REALLOC |
+ (3 - 2));
+ OUT_BATCH(urb_cl_end << UF1_CLIP_FENCE_SHIFT |
+ urb_gs_end << UF1_GS_FENCE_SHIFT |
+ urb_vs_end << UF1_VS_FENCE_SHIFT);
+ OUT_BATCH(urb_cs_end << UF2_CS_FENCE_SHIFT |
+ urb_sf_end << UF2_SF_FENCE_SHIFT);
+
+ OUT_BATCH(GEN4_CS_URB_STATE | (2 - 2));
+ OUT_BATCH((URB_CS_ENTRY_SIZE - 1) << 4 | cs_entries << 0);
+}
+
+static void
+gen4_emit_null_depth_buffer(struct intel_batchbuffer *batch)
+{
+ if (IS_G4X(batch->devid) || IS_GEN5(batch->devid)) {
+ OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (6 - 2));
+ OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ } else {
+ OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (5 - 2));
+ OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ OUT_BATCH(0);
+ }
+
+ if (IS_GEN5(batch->devid)) {
+ OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2));
+ OUT_BATCH(0);
+ }
+}
+
+static void
+gen4_emit_invariant(struct intel_batchbuffer *batch)
+{
+ OUT_BATCH(MI_FLUSH | MI_INHIBIT_RENDER_CACHE_FLUSH);
+
+ if (IS_GEN5(batch->devid) || IS_G4X(batch->devid))
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ else
+ OUT_BATCH(GEN4_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+}
+
+static uint32_t
+gen4_create_vs_state(struct intel_batchbuffer *batch)
+{
+ struct gen4_vs_state *vs;
+ int nr_urb_entries;
+
+ vs = intel_batchbuffer_subdata_alloc(batch, sizeof(*vs), 32);
+
+ /* Set up the vertex shader to be disabled (passthrough) */
+ nr_urb_entries = gen4_max_vs_nr_urb_entries(batch->devid);
+ if (IS_GEN5(batch->devid))
+ nr_urb_entries >>= 2;
+ vs->vs4.nr_urb_entries = nr_urb_entries;
+ vs->vs4.urb_entry_allocation_size = URB_VS_ENTRY_SIZE - 1;
+ vs->vs6.vs_enable = 0;
+ vs->vs6.vert_cache_disable = 1;
+
+ return intel_batchbuffer_subdata_offset(batch, vs);
+}
+
+static uint32_t
+gen4_create_sf_state(struct intel_batchbuffer *batch,
+ uint32_t kernel)
+{
+ struct gen4_sf_state *sf;
+
+ sf = intel_batchbuffer_subdata_alloc(batch, sizeof(*sf), 32);
+
+ sf->sf0.grf_reg_count = GEN4_GRF_BLOCKS(SF_KERNEL_NUM_GRF);
+ sf->sf0.kernel_start_pointer = kernel >> 6;
+
+ sf->sf3.urb_entry_read_length = 1; /* 1 URB per vertex */
+ /* don't smash vertex header, read start from dw8 */
+ sf->sf3.urb_entry_read_offset = 1;
+ sf->sf3.dispatch_grf_start_reg = 3;
+
+ sf->sf4.max_threads = gen4_max_sf_threads(batch->devid) - 1;;
+ sf->sf4.urb_entry_allocation_size = URB_SF_ENTRY_SIZE - 1;
+ sf->sf4.nr_urb_entries = gen4_max_sf_nr_urb_entries(batch->devid);
+
+ sf->sf6.cull_mode = GEN4_CULLMODE_NONE;
+ sf->sf6.dest_org_vbias = 0x8;
+ sf->sf6.dest_org_hbias = 0x8;
+
+ return intel_batchbuffer_subdata_offset(batch, sf);
+}
+
+static uint32_t
+gen4_create_wm_state(struct intel_batchbuffer *batch,
+ uint32_t kernel,
+ uint32_t sampler)
+{
+ struct gen4_wm_state *wm;
+
+ wm = intel_batchbuffer_subdata_alloc(batch, sizeof(*wm), 32);
+
+ assert((kernel & 63) == 0);
+ wm->wm0.kernel_start_pointer = kernel >> 6;
+ wm->wm0.grf_reg_count = GEN4_GRF_BLOCKS(PS_KERNEL_NUM_GRF);
+
+ wm->wm3.urb_entry_read_offset = 0;
+ wm->wm3.dispatch_grf_start_reg = 3;
+
+ assert((sampler & 31) == 0);
+ wm->wm4.sampler_state_pointer = sampler >> 5;
+ wm->wm4.sampler_count = 1;
+
+ wm->wm5.max_threads = gen4_max_wm_threads(batch->devid);
+ wm->wm5.thread_dispatch_enable = 1;
+ wm->wm5.enable_16_pix = 1;
+ wm->wm5.early_depth_test = 1;
+
+ if (IS_GEN5(batch->devid))
+ wm->wm1.binding_table_entry_count = 0;
+ else
+ wm->wm1.binding_table_entry_count = 2;
+ wm->wm3.urb_entry_read_length = 2;
+
+ return intel_batchbuffer_subdata_offset(batch, wm);
+}
+
+static void
+gen4_emit_binding_table(struct intel_batchbuffer *batch,
+ uint32_t wm_table)
+{
+ OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS | (6 - 2));
+ OUT_BATCH(0); /* vs */
+ OUT_BATCH(0); /* gs */
+ OUT_BATCH(0); /* clip */
+ OUT_BATCH(0); /* sf */
+ OUT_BATCH(wm_table); /* ps */
+}
+
+static void
+gen4_emit_drawing_rectangle(struct intel_batchbuffer *batch,
+ struct igt_buf *dst)
+{
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(0);
+ OUT_BATCH((igt_buf_height(dst) - 1) << 16 |
+ (igt_buf_width(dst) - 1));
+ OUT_BATCH(0);
+}
+
+static void
+gen4_emit_vertex_elements(struct intel_batchbuffer *batch)
+{
+
+ if (IS_GEN5(batch->devid)) {
+ /* The VUE layout
+ * dword 0-3: pad (0.0, 0.0, 0.0, 0.0),
+ * dword 4-7: position (x, y, 1.0, 1.0),
+ * dword 8-11: texture coordinate 0 (u0, v0, 0, 0)
+ *
+ * dword 4-11 are fetched from vertex buffer
+ */
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
+
+ /* pad */
+ OUT_BATCH(0 << GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN4_VE0_VALID |
+ SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+
+ /* x,y */
+ OUT_BATCH(0 << GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN4_VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+
+ /* u0, v0 */
+ OUT_BATCH(0 << GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN4_VE0_VALID |
+ SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
+ 4 << VE0_OFFSET_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ } else {
+ /* The VUE layout
+ * dword 0-3: position (x, y, 1.0, 1.0),
+ * dword 4-7: texture coordinate 0 (u0, v0, 0, 0)
+ *
+ * dword 0-7 are fetched from vertex buffer
+ */
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 2 + 1 - 2));
+
+ /* x,y */
+ OUT_BATCH(0 << GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN4_VE0_VALID |
+ SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
+ 0 << VE0_OFFSET_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT |
+ 4 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
+
+ /* u0, v0 */
+ OUT_BATCH(0 << GEN4_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN4_VE0_VALID |
+ SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
+ 4 << VE0_OFFSET_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT |
+ 8 << VE1_DESTINATION_ELEMENT_OFFSET_SHIFT);
+ }
+}
+
+static uint32_t
+gen4_create_cc_viewport(struct intel_batchbuffer *batch)
+{
+ struct gen4_cc_viewport *vp;
+
+ vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
+
+ vp->min_depth = -1.e35;
+ vp->max_depth = 1.e35;
+
+ return intel_batchbuffer_subdata_offset(batch, vp);
+}
+
+static uint32_t
+gen4_create_cc_state(struct intel_batchbuffer *batch,
+ uint32_t cc_vp)
+{
+ struct gen4_color_calc_state *cc;
+
+ cc = intel_batchbuffer_subdata_alloc(batch, sizeof(*cc), 64);
+
+ cc->cc4.cc_viewport_state_offset = cc_vp;
+
+ return intel_batchbuffer_subdata_offset(batch, cc);
+}
+
+static uint32_t
+gen4_create_sf_kernel(struct intel_batchbuffer *batch)
+{
+ if (IS_GEN5(batch->devid))
+ return intel_batchbuffer_copy_data(batch, gen5_sf_kernel_nomask,
+ sizeof(gen5_sf_kernel_nomask),
+ 64);
+ else
+ return intel_batchbuffer_copy_data(batch, gen4_sf_kernel_nomask,
+ sizeof(gen4_sf_kernel_nomask),
+ 64);
+}
+
+static uint32_t
+gen4_create_ps_kernel(struct intel_batchbuffer *batch)
+{
+ if (IS_GEN5(batch->devid))
+ return intel_batchbuffer_copy_data(batch, gen5_ps_kernel_nomask_affine,
+ sizeof(gen5_ps_kernel_nomask_affine),
+ 64);
+ else
+ return intel_batchbuffer_copy_data(batch, gen4_ps_kernel_nomask_affine,
+ sizeof(gen4_ps_kernel_nomask_affine),
+ 64);
+}
+
+static uint32_t
+gen4_create_sampler(struct intel_batchbuffer *batch,
+ sampler_filter_t filter,
+ sampler_extend_t extend)
+{
+ struct gen4_sampler_state *ss;
+
+ ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32);
+
+ ss->ss0.lod_preclamp = GEN4_LOD_PRECLAMP_OGL;
+
+ /* We use the legacy mode to get the semantics specified by
+ * the Render extension. */
+ ss->ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY;
+
+ switch (filter) {
+ default:
+ case SAMPLER_FILTER_NEAREST:
+ ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
+ break;
+ case SAMPLER_FILTER_BILINEAR:
+ ss->ss0.min_filter = GEN4_MAPFILTER_LINEAR;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_LINEAR;
+ break;
+ }
+
+ switch (extend) {
+ default:
+ case SAMPLER_EXTEND_NONE:
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ break;
+ case SAMPLER_EXTEND_REPEAT:
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ break;
+ case SAMPLER_EXTEND_PAD:
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ break;
+ case SAMPLER_EXTEND_REFLECT:
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ break;
+ }
+
+ return intel_batchbuffer_subdata_offset(batch, ss);
+}
+
+static void gen4_emit_vertex_buffer(struct intel_batchbuffer *batch)
+{
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(GEN4_VB0_VERTEXDATA |
+ 0 << GEN4_VB0_BUFFER_INDEX_SHIFT |
+ VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
+ OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
+ if (IS_GEN5(batch->devid))
+ OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, batch->bo->size - 1);
+ else
+ OUT_BATCH(batch->bo->size / VERTEX_SIZE - 1);
+ OUT_BATCH(0);
+}
+
+static uint32_t gen4_emit_primitive(struct intel_batchbuffer *batch)
+{
+ uint32_t offset;
+
+ OUT_BATCH(GEN4_3DPRIMITIVE |
+ GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
+ _3DPRIM_RECTLIST << GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT |
+ 0 << 9 |
+ (6 - 2));
+ OUT_BATCH(3); /* vertex count */
+ offset = batch_used(batch);
+ OUT_BATCH(0); /* vertex_index */
+ OUT_BATCH(1); /* single instance */
+ OUT_BATCH(0); /* start instance location */
+ OUT_BATCH(0); /* index buffer offset, ignored */
+
+ return offset;
+}
+
+void gen4_render_copyfunc(struct intel_batchbuffer *batch,
+ drm_intel_context *context,
+ struct igt_buf *src, unsigned src_x, unsigned src_y,
+ unsigned width, unsigned height,
+ struct igt_buf *dst, unsigned dst_x, unsigned dst_y)
+{
+ uint32_t cc, cc_vp;
+ uint32_t wm, wm_sampler, wm_kernel, wm_table;
+ uint32_t sf, sf_kernel;
+ uint32_t vs;
+ uint32_t offset, batch_end;
+
+ intel_batchbuffer_flush_with_context(batch, context);
+
+ batch->ptr = batch->buffer + 1024;
+ intel_batchbuffer_subdata_alloc(batch, 64, 64);
+
+ vs = gen4_create_vs_state(batch);
+
+ sf_kernel = gen4_create_sf_kernel(batch);
+ sf = gen4_create_sf_state(batch, sf_kernel);
+
+ wm_table = gen4_bind_surfaces(batch, src, dst);
+ wm_kernel = gen4_create_ps_kernel(batch);
+ wm_sampler = gen4_create_sampler(batch,
+ SAMPLER_FILTER_NEAREST,
+ SAMPLER_EXTEND_NONE);
+ wm = gen4_create_wm_state(batch, wm_kernel, wm_sampler);
+
+ cc_vp = gen4_create_cc_viewport(batch);
+ cc = gen4_create_cc_state(batch, cc_vp);
+
+ batch->ptr = batch->buffer;
+
+ gen4_emit_invariant(batch);
+ gen4_emit_state_base_address(batch);
+ gen4_emit_sip(batch);
+ gen4_emit_null_depth_buffer(batch);
+
+ gen4_emit_drawing_rectangle(batch, dst);
+ gen4_emit_binding_table(batch, wm_table);
+ gen4_emit_vertex_elements(batch);
+ gen4_emit_pipelined_pointers(batch, vs, sf, wm, cc);
+ gen4_emit_urb(batch);
+
+ gen4_emit_vertex_buffer(batch);
+ offset = gen4_emit_primitive(batch);
+
+ OUT_BATCH(MI_BATCH_BUFFER_END);
+ batch_end = intel_batchbuffer_align(batch, 8);
+
+ *(uint32_t*)(batch->buffer + offset) =
+ batch_round_upto(batch, VERTEX_SIZE)/VERTEX_SIZE;
+
+ emit_vertex_2s(batch, dst_x + width, dst_y + height);
+ emit_vertex_normalized(batch, src_x + width, igt_buf_width(src));
+ emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
+
+ emit_vertex_2s(batch, dst_x, dst_y + height);
+ emit_vertex_normalized(batch, src_x, igt_buf_width(src));
+ emit_vertex_normalized(batch, src_y + height, igt_buf_height(src));
+
+ emit_vertex_2s(batch, dst_x, dst_y);
+ emit_vertex_normalized(batch, src_x, igt_buf_width(src));
+ emit_vertex_normalized(batch, src_y, igt_buf_height(src));
+
+ gen4_render_flush(batch, context, batch_end);
+ intel_batchbuffer_reset(batch);
+}
--
2.14.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t v2 2/3] lib/rendercopy: Use gen4 definitions if applicable
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
@ 2018-06-20 11:54 ` Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 3/3] lib/gen6_render: Drop duplicated definitions Lukasz Kalamarz
` (3 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Lukasz Kalamarz @ 2018-06-20 11:54 UTC (permalink / raw)
To: igt-dev
Instead of using definitions duplicated in gen7_render header,
we should use the oldest definition that is working with chosen
gen. This patch reuse gen6 definitons if registers/fields/shifts
that were introduced in other genX_render headers.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
lib/gen6_render.h | 103 +++++++++++---------------
lib/gen7_render.h | 56 +++++++-------
lib/gen8_render.h | 56 +++++++-------
lib/gen9_render.h | 4 +-
lib/rendercopy_gen6.c | 98 ++++++++++++------------
lib/rendercopy_gen7.c | 64 ++++++++--------
lib/rendercopy_gen8.c | 58 +++++++--------
lib/rendercopy_gen9.c | 58 +++++++--------
tools/null_state_gen/intel_renderstate_gen6.c | 92 +++++++++++------------
tools/null_state_gen/intel_renderstate_gen7.c | 62 ++++++++--------
tools/null_state_gen/intel_renderstate_gen8.c | 26 +++----
tools/null_state_gen/intel_renderstate_gen9.c | 24 +++---
12 files changed, 344 insertions(+), 357 deletions(-)
diff --git a/lib/gen6_render.h b/lib/gen6_render.h
index 8f0beda2..6bf468df 100644
--- a/lib/gen6_render.h
+++ b/lib/gen6_render.h
@@ -3,37 +3,38 @@
#include <stdint.h>
#include "surfaceformat.h"
+#include "gen4_render.h"
#define GEN6_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
((Pipeline) << 27) | \
((Opcode) << 24) | \
((Subopcode) << 16))
-#define GEN6_STATE_BASE_ADDRESS GEN6_3D(0, 1, 1)
+#define GEN6_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1)
# define BASE_ADDRESS_MODIFY (1 << 0)
# define BUFFER_SIZE_MODIFY (1 << 0)
-#define GEN6_STATE_SIP GEN6_3D(0, 1, 2)
+#define GEN6_STATE_SIP GEN4_3D(0, 1, 2)
-#define GEN6_3DSTATE_VF_STATISTICS GEN6_3D(1, 0, 0xB)
-#define GEN6_PIPELINE_SELECT GEN6_3D(1, 1, 4)
+#define GEN6_3DSTATE_VF_STATISTICS GEN4_3D(1, 0, 0xB)
+#define GEN6_PIPELINE_SELECT GEN4_3D(1, 1, 4)
# define PIPELINE_SELECT_3D 0
# define PIPELINE_SELECT_MEDIA 1
-#define GEN6_MEDIA_STATE_POINTERS GEN6_3D(2, 0, 0)
-#define GEN6_MEDIA_OBJECT GEN6_3D(2, 1, 0)
+#define GEN6_MEDIA_STATE_POINTERS GEN4_3D(2, 0, 0)
+#define GEN6_MEDIA_OBJECT GEN4_3D(2, 1, 0)
-#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN6_3D(3, 0, 0x01)
+#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 0x01)
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */
-#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN6_3D(3, 0, 0x02)
+#define GEN6_3DSTATE_SAMPLER_STATE_POINTERS GEN4_3D(3, 0, 0x02)
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_PS (1 << 12)
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_GS (1 << 9)
# define GEN6_3DSTATE_SAMPLER_STATE_MODIFY_VS (1 << 8)
-#define GEN6_3DSTATE_URB GEN6_3D(3, 0, 0x05)
+#define GEN6_3DSTATE_URB GEN4_3D(3, 0, 0x05)
/* DW1 */
# define GEN6_3DSTATE_URB_VS_SIZE_SHIFT 16
# define GEN6_3DSTATE_URB_VS_ENTRIES_SHIFT 0
@@ -41,25 +42,25 @@
# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8
# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0
-#define GEN6_3DSTATE_VERTEX_BUFFERS GEN6_3D(3, 0, 0x08)
-#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN6_3D(3, 0, 0x09)
-#define GEN6_3DSTATE_INDEX_BUFFER GEN6_3D(3, 0, 0x0A)
-#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN6_3D(3, 0, 0x0D)
+#define GEN6_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 0x08)
+#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 0x09)
+#define GEN6_3DSTATE_INDEX_BUFFER GEN4_3D(3, 0, 0x0A)
+#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN4_3D(3, 0, 0x0D)
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CC (1 << 12)
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_SF (1 << 11)
# define GEN6_3DSTATE_VIEWPORT_STATE_MODIFY_CLIP (1 << 10)
-#define GEN6_3DSTATE_CC_STATE_POINTERS GEN6_3D(3, 0, 0x0E)
+#define GEN6_3DSTATE_CC_STATE_POINTERS GEN4_3D(3, 0, 0x0E)
-#define GEN6_3DSTATE_VS GEN6_3D(3, 0, 0x10)
+#define GEN6_3DSTATE_VS GEN4_3D(3, 0, 0x10)
-#define GEN6_3DSTATE_GS GEN6_3D(3, 0, 0x11)
+#define GEN6_3DSTATE_GS GEN4_3D(3, 0, 0x11)
/* DW4 */
# define GEN6_3DSTATE_GS_DISPATCH_START_GRF_SHIFT 0
-#define GEN6_3DSTATE_CLIP GEN6_3D(3, 0, 0x12)
+#define GEN6_3DSTATE_CLIP GEN4_3D(3, 0, 0x12)
-#define GEN6_3DSTATE_SF GEN6_3D(3, 0, 0x13)
+#define GEN6_3DSTATE_SF GEN4_3D(3, 0, 0x13)
/* DW1 */
# define GEN6_3DSTATE_SF_NUM_OUTPUTS_SHIFT 22
# define GEN6_3DSTATE_SF_URB_ENTRY_READ_LENGTH_SHIFT 11
@@ -76,7 +77,7 @@
# define GEN6_3DSTATE_SF_TRIFAN_PROVOKE_SHIFT 25
# define GEN6_3DSTATE_SF_VERTEX_SUB_PIXEL_PRECISION_SHIFT 12
-#define GEN6_3DSTATE_WM GEN6_3D(3, 0, 0x14)
+#define GEN6_3DSTATE_WM GEN4_3D(3, 0, 0x14)
/* DW2 */
# define GEN6_3DSTATE_WM_SAMPLER_COUNT_SHIFT 27
# define GEN6_3DSTATE_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT 18
@@ -96,28 +97,28 @@
# define GEN6_3DSTATE_WM_PERSPECTIVE_CENTROID_BARYCENTRIC (1 << 11)
# define GEN6_3DSTATE_WM_PERSPECTIVE_PIXEL_BARYCENTRIC (1 << 10)
-#define GEN6_3DSTATE_CONSTANT_VS GEN6_3D(3, 0, 0x15)
-#define GEN6_3DSTATE_CONSTANT_GS GEN6_3D(3, 0, 0x16)
-#define GEN6_3DSTATE_CONSTANT_PS GEN6_3D(3, 0, 0x17)
+#define GEN6_3DSTATE_CONSTANT_VS GEN4_3D(3, 0, 0x15)
+#define GEN6_3DSTATE_CONSTANT_GS GEN4_3D(3, 0, 0x16)
+#define GEN6_3DSTATE_CONSTANT_PS GEN4_3D(3, 0, 0x17)
-#define GEN6_3DSTATE_SAMPLE_MASK GEN6_3D(3, 0, 0x18)
+#define GEN6_3DSTATE_SAMPLE_MASK GEN4_3D(3, 0, 0x18)
-#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN6_3D(3, 1, 0x00)
-#define GEN6_3DSTATE_CONSTANT_COLOR GEN6_3D(3, 1, 0x01)
-#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN6_3D(3, 1, 0x02)
-#define GEN6_3DSTATE_CHROMA_KEY GEN6_3D(3, 1, 0x04)
-#define GEN6_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 1, 0x05)
+#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0x00)
+#define GEN6_3DSTATE_CONSTANT_COLOR GEN4_3D(3, 1, 0x01)
+#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN4_3D(3, 1, 0x02)
+#define GEN6_3DSTATE_CHROMA_KEY GEN4_3D(3, 1, 0x04)
+#define GEN6_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 0x05)
# define GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29
# define GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18
-#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN6_3D(3, 1, 0x06)
-#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN6_3D(3, 1, 0x07)
-#define GEN6_3DSTATE_LINE_STIPPLE GEN6_3D(3, 1, 0x08)
-#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN6_3D(3, 1, 0x09)
+#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN4_3D(3, 1, 0x06)
+#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN4_3D(3, 1, 0x07)
+#define GEN6_3DSTATE_LINE_STIPPLE GEN4_3D(3, 1, 0x08)
+#define GEN6_3DSTATE_GLOBAL_DEPTH_OFFSET_CLAMP GEN4_3D(3, 1, 0x09)
/* These two are BLC and CTG only, not BW or CL */
-#define GEN6_3DSTATE_AA_LINE_PARAMS GEN6_3D(3, 1, 0x0A)
-#define GEN6_3DSTATE_GS_SVB_INDEX GEN6_3D(3, 1, 0x0B)
-#define GEN6_3DSTATE_MULTISAMPLE GEN6_3D(3, 1, 0x0D)
+#define GEN6_3DSTATE_AA_LINE_PARAMS GEN4_3D(3, 1, 0x0A)
+#define GEN6_3DSTATE_GS_SVB_INDEX GEN4_3D(3, 1, 0x0B)
+#define GEN6_3DSTATE_MULTISAMPLE GEN4_3D(3, 1, 0x0D)
/* DW1 */
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER (0 << 4)
# define GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_UPPER_LEFT (1 << 4)
@@ -125,7 +126,7 @@
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1)
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1)
-#define GEN6_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 1, 0x10)
+#define GEN6_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10)
/* DW1 */
# define GEN6_3DSTATE_DEPTH_CLEAR_VALID (1 << 15)
# define GEN6_PIPE_CONTROL_NOWRITE (0 << 14)
@@ -141,25 +142,25 @@
# define GEN6_PIPE_CONTROL_LOCAL_PGTT (0 << 2)
# define GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH (1 << 0)
-#define GEN6_3DSTATE_MONOFILTER_SIZE GEN6_3D(3, 1, 0x11)
-#define GEN6_PIPE_CONTROL GEN6_3D(3, 2, 0)
+#define GEN6_3DSTATE_MONOFILTER_SIZE GEN4_3D(3, 1, 0x11)
+#define GEN6_PIPE_CONTROL GEN4_3D(3, 2, 0)
-#define GEN6_3DPRIMITIVE GEN6_3D(3, 3, 0)
+#define GEN6_3DPRIMITIVE GEN4_3D(3, 3, 0)
# define GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
# define GEN6_3DPRIMITIVE_VERTEX_RANDOM (1 << 15)
/* Primitive types are in gen6_defines.h */
# define GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT 10
/* VERTEX_BUFFER_STATE Structure */
-#define VB0_BUFFER_INDEX_SHIFT 26
-#define VB0_VERTEXDATA (0 << 20)
-#define VB0_INSTANCEDATA (1 << 20)
+#define GEN6_VB0_BUFFER_INDEX_SHIFT 26
+#define GEN6_VB0_VERTEXDATA (0 << 20)
+#define GEN6_VB0_INSTANCEDATA (1 << 20)
#define VB0_BUFFER_PITCH_SHIFT 0
#define VB0_NULL_VERTEX_BUFFER (1 << 13)
/* VERTEX_ELEMENT_STATE Structure */
-#define VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */
-#define VE0_VALID (1 << 25) /* for GEN6 */
+#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */
+#define GEN6_VE0_VALID (1 << 25) /* for GEN6 */
#define VE0_FORMAT_SHIFT 16
#define VE0_OFFSET_SHIFT 0
#define VE1_VFCOMPONENT_0_SHIFT 28
@@ -1072,18 +1073,4 @@ struct gen6_cc_viewport {
float max_depth;
};
-typedef enum {
- SAMPLER_FILTER_NEAREST = 0,
- SAMPLER_FILTER_BILINEAR,
- FILTER_COUNT
-} sampler_filter_t;
-
-typedef enum {
- SAMPLER_EXTEND_NONE = 0,
- SAMPLER_EXTEND_REPEAT,
- SAMPLER_EXTEND_PAD,
- SAMPLER_EXTEND_REFLECT,
- EXTEND_COUNT
-} sampler_extend_t;
-
#endif
diff --git a/lib/gen7_render.h b/lib/gen7_render.h
index 60e9aad4..4bde0d5f 100644
--- a/lib/gen7_render.h
+++ b/lib/gen7_render.h
@@ -85,21 +85,21 @@
# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL (0 << 8)
# define GEN7_3DPRIM_VERTEXBUFFER_ACCESS_RANDOM (1 << 8)
-#define GEN7_3DSTATE_CLEAR_PARAMS GEN6_3D(3, 0, 0x04)
-#define GEN7_3DSTATE_DEPTH_BUFFER GEN6_3D(3, 0, 0x05)
+#define GEN7_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 0, 0x04)
+#define GEN7_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 0, 0x05)
# define GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29
# define GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18
/* DW1 */
# define GEN7_3DSTATE_DEPTH_CLEAR_VALID (1 << 15)
-#define GEN7_3DSTATE_CONSTANT_HS GEN6_3D(3, 0, 0x19)
-#define GEN7_3DSTATE_CONSTANT_DS GEN6_3D(3, 0, 0x1a)
+#define GEN7_3DSTATE_CONSTANT_HS GEN4_3D(3, 0, 0x19)
+#define GEN7_3DSTATE_CONSTANT_DS GEN4_3D(3, 0, 0x1a)
-#define GEN7_3DSTATE_HS GEN6_3D(3, 0, 0x1b)
-#define GEN7_3DSTATE_TE GEN6_3D(3, 0, 0x1c)
-#define GEN7_3DSTATE_DS GEN6_3D(3, 0, 0x1d)
-#define GEN7_3DSTATE_STREAMOUT GEN6_3D(3, 0, 0x1e)
-#define GEN7_3DSTATE_SBE GEN6_3D(3, 0, 0x1f)
+#define GEN7_3DSTATE_HS GEN4_3D(3, 0, 0x1b)
+#define GEN7_3DSTATE_TE GEN4_3D(3, 0, 0x1c)
+#define GEN7_3DSTATE_DS GEN4_3D(3, 0, 0x1d)
+#define GEN7_3DSTATE_STREAMOUT GEN4_3D(3, 0, 0x1e)
+#define GEN7_3DSTATE_SBE GEN4_3D(3, 0, 0x1f)
/* DW1 */
# define GEN7_SBE_SWIZZLE_CONTROL_MODE (1 << 28)
@@ -109,7 +109,7 @@
# define GEN7_SBE_URB_ENTRY_READ_LENGTH_SHIFT 11
# define GEN7_SBE_URB_ENTRY_READ_OFFSET_SHIFT 4
-#define GEN7_3DSTATE_PS GEN6_3D(3, 0, 0x20)
+#define GEN7_3DSTATE_PS GEN4_3D(3, 0, 0x20)
/* DW1: kernel pointer */
/* DW2 */
# define GEN7_PS_SPF_MODE (1 << 31)
@@ -140,33 +140,33 @@
/* DW6: kernel 1 pointer */
/* DW7: kernel 2 pointer */
-#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL GEN6_3D(3, 0, 0x21)
-#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN6_3D(3, 0, 0x23)
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CL GEN4_3D(3, 0, 0x21)
+#define GEN7_3DSTATE_VIEWPORT_STATE_POINTERS_CC GEN4_3D(3, 0, 0x23)
-#define GEN7_3DSTATE_BLEND_STATE_POINTERS GEN6_3D(3, 0, 0x24)
-#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS GEN6_3D(3, 0, 0x25)
+#define GEN7_3DSTATE_BLEND_STATE_POINTERS GEN4_3D(3, 0, 0x24)
+#define GEN7_3DSTATE_DEPTH_STENCIL_STATE_POINTERS GEN4_3D(3, 0, 0x25)
-#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS GEN6_3D(3, 0, 0x26)
-#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS GEN6_3D(3, 0, 0x27)
-#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS GEN6_3D(3, 0, 0x28)
-#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS GEN6_3D(3, 0, 0x29)
-#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS GEN6_3D(3, 0, 0x2a)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_VS GEN4_3D(3, 0, 0x26)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_HS GEN4_3D(3, 0, 0x27)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_DS GEN4_3D(3, 0, 0x28)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_GS GEN4_3D(3, 0, 0x29)
+#define GEN7_3DSTATE_BINDING_TABLE_POINTERS_PS GEN4_3D(3, 0, 0x2a)
-#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS GEN6_3D(3, 0, 0x2b)
-#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN6_3D(3, 0, 0x2e)
-#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN6_3D(3, 0, 0x2f)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_VS GEN4_3D(3, 0, 0x2b)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_GS GEN4_3D(3, 0, 0x2e)
+#define GEN7_3DSTATE_SAMPLER_STATE_POINTERS_PS GEN4_3D(3, 0, 0x2f)
-#define GEN7_3DSTATE_URB_VS GEN6_3D(3, 0, 0x30)
-#define GEN7_3DSTATE_URB_HS GEN6_3D(3, 0, 0x31)
-#define GEN7_3DSTATE_URB_DS GEN6_3D(3, 0, 0x32)
-#define GEN7_3DSTATE_URB_GS GEN6_3D(3, 0, 0x33)
+#define GEN7_3DSTATE_URB_VS GEN4_3D(3, 0, 0x30)
+#define GEN7_3DSTATE_URB_HS GEN4_3D(3, 0, 0x31)
+#define GEN7_3DSTATE_URB_DS GEN4_3D(3, 0, 0x32)
+#define GEN7_3DSTATE_URB_GS GEN4_3D(3, 0, 0x33)
/* DW1 */
# define GEN7_URB_ENTRY_NUMBER_SHIFT 0
# define GEN7_URB_ENTRY_SIZE_SHIFT 16
# define GEN7_URB_STARTING_ADDRESS_SHIFT 25
-#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN6_3D(3, 1, 0x12)
-#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS GEN6_3D(3, 1, 0x16)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_VS GEN4_3D(3, 1, 0x12)
+#define GEN7_3DSTATE_PUSH_CONSTANT_ALLOC_PS GEN4_3D(3, 1, 0x16)
/* DW1 */
# define GEN7_PUSH_CONSTANT_BUFFER_OFFSET_SHIFT 16
diff --git a/lib/gen8_render.h b/lib/gen8_render.h
index 79f2f388..74f9b99c 100644
--- a/lib/gen8_render.h
+++ b/lib/gen8_render.h
@@ -5,21 +5,21 @@
# define GEN8_WM_LEGACY_DIAMOND_LINE_RASTERIZATION (1 << 26)
-#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS GEN6_3D(3, 0, 0xf)
-#define GEN8_3DSTATE_STENCIL_BUFFER GEN6_3D(3, 0, 0x06)
-#define GEN8_3DSTATE_HIER_DEPTH_BUFFER GEN6_3D(3, 0, 0x07)
-#define GEN8_3DSTATE_MULTISAMPLE GEN6_3D(3, 0, 0x0d)
+#define GEN8_3DSTATE_SCISSOR_STATE_POINTERS GEN4_3D(3, 0, 0xf)
+#define GEN8_3DSTATE_STENCIL_BUFFER GEN4_3D(3, 0, 0x06)
+#define GEN8_3DSTATE_HIER_DEPTH_BUFFER GEN4_3D(3, 0, 0x07)
+#define GEN8_3DSTATE_MULTISAMPLE GEN4_3D(3, 0, 0x0d)
# define GEN8_3DSTATE_MULTISAMPLE_NUMSAMPLES_2 (1 << 1)
# define GEN9_3DSTATE_MULTISAMPLE_NUMSAMPLES_16 (4 << 1)
-#define GEN8_3DSTATE_WM_HZ_OP GEN6_3D(3, 0, 0x52)
+#define GEN8_3DSTATE_WM_HZ_OP GEN4_3D(3, 0, 0x52)
-#define GEN8_3DSTATE_VF_INSTANCING GEN6_3D(3, 0, 0x49)
+#define GEN8_3DSTATE_VF_INSTANCING GEN4_3D(3, 0, 0x49)
# define GEN8_SBE_FORCE_URB_ENTRY_READ_LENGTH (1 << 29)
# define GEN8_SBE_FORCE_URB_ENTRY_READ_OFFSET (1 << 28)
# define GEN8_SBE_URB_ENTRY_READ_OFFSET_SHIFT 5
-#define GEN8_3DSTATE_SBE_SWIZ GEN6_3D(3, 0, 0x51)
-#define GEN8_3DSTATE_RASTER GEN6_3D(3, 0, 0x50)
+#define GEN8_3DSTATE_SBE_SWIZ GEN4_3D(3, 0, 0x51)
+#define GEN8_3DSTATE_RASTER GEN4_3D(3, 0, 0x50)
# define GEN8_RASTER_FRONT_WINDING_CCW (1 << 21)
# define GEN8_RASTER_CULL_NONE (1 << 16)
@@ -28,34 +28,34 @@
# define GEN8_VS_FLOATING_POINT_MODE_ALTERNATE (1 << 16)
#define GEN8_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP \
- GEN6_3D(3, 0, 0x21)
-#define GEN8_3DSTATE_PS_BLEND GEN6_3D(3, 0, 0x4d)
+ GEN4_3D(3, 0, 0x21)
+#define GEN8_3DSTATE_PS_BLEND GEN4_3D(3, 0, 0x4d)
# define GEN8_PS_BLEND_HAS_WRITEABLE_RT (1 << 30)
-#define GEN8_3DSTATE_WM_DEPTH_STENCIL GEN6_3D(3, 0, 0x4e)
-#define GEN8_3DSTATE_PS_EXTRA GEN6_3D(3,0, 0x4f)
+#define GEN8_3DSTATE_WM_DEPTH_STENCIL GEN4_3D(3, 0, 0x4e)
+#define GEN8_3DSTATE_PS_EXTRA GEN4_3D(3,0, 0x4f)
# define GEN8_PSX_PIXEL_SHADER_VALID (1 << 31)
# define GEN8_PSX_ATTRIBUTE_ENABLE (1 << 8)
-#define GEN8_3DSTATE_DS_STATE_POINTERS GEN6_3D(3, 0, 0x25)
+#define GEN8_3DSTATE_DS_STATE_POINTERS GEN4_3D(3, 0, 0x25)
-#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS GEN6_3D(3, 0, 0x2c)
-#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS GEN6_3D(3, 0, 0x2d)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_HS GEN4_3D(3, 0, 0x2c)
+#define GEN8_3DSTATE_SAMPLER_STATE_POINTERS_DS GEN4_3D(3, 0, 0x2d)
-#define GEN8_3DSTATE_VF GEN6_3D(3, 0, 0x0c)
-#define GEN8_3DSTATE_VF_TOPOLOGY GEN6_3D(3, 0, 0x4b)
+#define GEN8_3DSTATE_VF GEN4_3D(3, 0, 0x0c)
+#define GEN8_3DSTATE_VF_TOPOLOGY GEN4_3D(3, 0, 0x4b)
-#define GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC GEN6_3D(3, 1, 0x19)
-#define GEN8_3DSTATE_GATHER_POOL_ALLOC GEN6_3D(3, 1, 0x1a)
-#define GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC GEN6_3D(3, 1, 0x1b)
-#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN6_3D(3, 1, 0x13)
-#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN6_3D(3, 1, 0x14)
-#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS GEN6_3D(3, 1, 0x15)
+#define GEN8_3DSTATE_BIND_TABLE_POOL_ALLOC GEN4_3D(3, 1, 0x19)
+#define GEN8_3DSTATE_GATHER_POOL_ALLOC GEN4_3D(3, 1, 0x1a)
+#define GEN8_3DSTATE_DX9_CONSTANT_BUFFER_POOL_ALLOC GEN4_3D(3, 1, 0x1b)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_HS GEN4_3D(3, 1, 0x13)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_DS GEN4_3D(3, 1, 0x14)
+#define GEN8_3DSTATE_PUSH_CONSTANT_ALLOC_GS GEN4_3D(3, 1, 0x15)
-#define GEN8_3DSTATE_VF_SGVS GEN6_3D(3, 0, 0x4a)
-#define GEN8_3DSTATE_SO_DECL_LIST GEN6_3D(3, 1, 0x17)
-#define GEN8_3DSTATE_SO_BUFFER GEN6_3D(3, 1, 0x18)
-#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0 GEN6_3D(3, 1, 0x02)
-#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1 GEN6_3D(3, 1, 0x0c)
+#define GEN8_3DSTATE_VF_SGVS GEN4_3D(3, 0, 0x4a)
+#define GEN8_3DSTATE_SO_DECL_LIST GEN4_3D(3, 1, 0x17)
+#define GEN8_3DSTATE_SO_BUFFER GEN4_3D(3, 1, 0x18)
+#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD0 GEN4_3D(3, 1, 0x02)
+#define GEN8_3DSTATE_SAMPLER_PALETTE_LOAD1 GEN4_3D(3, 1, 0x0c)
/* Some random bits that we care about */
#define GEN8_VB0_BUFFER_ADDR_MOD_EN (1 << 14)
diff --git a/lib/gen9_render.h b/lib/gen9_render.h
index 90f56053..77f4966c 100644
--- a/lib/gen9_render.h
+++ b/lib/gen9_render.h
@@ -3,7 +3,7 @@
#include "gen8_render.h"
-#define GEN9_3DSTATE_COMPONENT_PACKING GEN6_3D(3, 0, 0x55)
+#define GEN9_3DSTATE_COMPONENT_PACKING GEN4_3D(3, 0, 0x55)
#define GEN9_SBE_ACTIVE_COMPONENT_NONE 0
#define GEN9_SBE_ACTIVE_COMPONENT_XY 1
@@ -11,6 +11,6 @@
#define GEN9_SBE_ACTIVE_COMPONENT_XYZW 3
#define GEN9_PIPELINE_SELECTION_MASK (3 << 8)
-#define GEN9_PIPELINE_SELECT (GEN6_3D(1, 1, 4) | (3 << 8))
+#define GEN9_PIPELINE_SELECT (GEN4_3D(1, 1, 4) | (3 << 8))
#endif
diff --git a/lib/rendercopy_gen6.c b/lib/rendercopy_gen6.c
index 031d864b..713aadee 100644
--- a/lib/rendercopy_gen6.c
+++ b/lib/rendercopy_gen6.c
@@ -129,7 +129,7 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch,
static void
gen6_emit_sip(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_SIP | 0);
+ OUT_BATCH(GEN4_STATE_SIP | 0);
OUT_BATCH(0);
}
@@ -146,7 +146,7 @@ gen6_emit_urb(struct intel_batchbuffer *batch)
static void
gen6_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0); /* general */
OUT_RELOC(batch->bo, /* surface */
I915_GEM_DOMAIN_INSTRUCTION, 0,
@@ -237,23 +237,23 @@ gen6_emit_wm_constants(struct intel_batchbuffer *batch)
static void
gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2));
+ OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2));
OUT_BATCH(0);
}
static void
gen6_emit_invariant(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
@@ -332,7 +332,7 @@ gen6_emit_wm(struct intel_batchbuffer *batch, int kernel)
static void
gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
{
- OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS |
+ OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS |
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
(4 - 2));
OUT_BATCH(0); /* vs */
@@ -343,7 +343,7 @@ gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
static void
gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0);
OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
OUT_BATCH(0);
@@ -359,39 +359,39 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
*
* dword 4-11 are fetched from vertex buffer
*/
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* u0, v0 */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
gen6_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen6_cc_viewport *vp;
+ struct gen4_cc_viewport *vp;
vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
@@ -439,41 +439,41 @@ gen6_create_sampler(struct intel_batchbuffer *batch,
/* We use the legacy mode to get the semantics specified by
* the Render extension. */
- ss->ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
+ ss->ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY;
switch (filter) {
default:
case SAMPLER_FILTER_NEAREST:
- ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+ ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
break;
case SAMPLER_FILTER_BILINEAR:
- ss->ss0.min_filter = GEN6_MAPFILTER_LINEAR;
- ss->ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
+ ss->ss0.min_filter = GEN4_MAPFILTER_LINEAR;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_LINEAR;
break;
}
switch (extend) {
default:
case SAMPLER_EXTEND_NONE:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
break;
case SAMPLER_EXTEND_REPEAT:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
break;
case SAMPLER_EXTEND_PAD:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
break;
case SAMPLER_EXTEND_REFLECT:
- ss->ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss->ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss->ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
+ ss->ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss->ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss->ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
break;
}
@@ -482,9 +482,9 @@ gen6_create_sampler(struct intel_batchbuffer *batch,
static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3);
- OUT_BATCH(VB0_VERTEXDATA |
- 0 << VB0_BUFFER_INDEX_SHIFT |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3);
+ OUT_BATCH(GEN6_VB0_VERTEXDATA |
+ 0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, 0);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, batch->bo->size-1);
@@ -495,9 +495,9 @@ static uint32_t gen6_emit_primitive(struct intel_batchbuffer *batch)
{
uint32_t offset;
- OUT_BATCH(GEN6_3DPRIMITIVE |
- GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL |
- _3DPRIM_RECTLIST << GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT |
+ OUT_BATCH(GEN4_3DPRIMITIVE |
+ GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL |
+ _3DPRIM_RECTLIST << GEN4_3DPRIMITIVE_TOPOLOGY_SHIFT |
0 << 9 |
4);
OUT_BATCH(3); /* vertex count */
diff --git a/lib/rendercopy_gen7.c b/lib/rendercopy_gen7.c
index bdcf3c7b..29f3ec6c 100644
--- a/lib/rendercopy_gen7.c
+++ b/lib/rendercopy_gen7.c
@@ -101,35 +101,35 @@ gen7_bind_buf(struct intel_batchbuffer *batch,
static void
gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
((2 * (1 + 2)) + 1 - 2));
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* s,t */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
@@ -166,9 +166,9 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
int width, int height,
uint32_t offset)
{
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2));
- OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT |
- VB0_VERTEXDATA |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
+ GEN6_VB0_VERTEXDATA |
GEN7_VB0_ADDRESS_MODIFY_ENABLE |
4 * 2 << VB0_BUFFER_PITCH_SHIFT);
@@ -207,7 +207,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch,
static void
gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0);
OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
OUT_BATCH(0);
@@ -232,7 +232,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch)
static void
gen7_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
@@ -248,7 +248,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
static uint32_t
gen7_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen6_cc_viewport *vp;
+ struct gen4_cc_viewport *vp;
vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
vp->min_depth = -1.e35;
@@ -275,12 +275,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch)
ss = intel_batchbuffer_subdata_alloc(batch, sizeof(*ss), 32);
- ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+ ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
- ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
ss->ss3.non_normalized_coord = 1;
@@ -476,8 +476,8 @@ static void
gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0); /* disable depth, stencil and hiz */
OUT_BATCH(0);
OUT_BATCH(0);
@@ -520,7 +520,7 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch,
igt_assert(batch->ptr < &batch->buffer[4095]);
batch->ptr = batch->buffer;
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen7_emit_state_base_address(batch);
gen7_emit_multisample(batch);
@@ -546,8 +546,8 @@ void gen7_render_copyfunc(struct intel_batchbuffer *batch,
gen7_emit_binding_table(batch, src, dst, ps_binding_table);
gen7_emit_drawing_rectangle(batch, dst);
- OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2));
- OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
OUT_BATCH(3);
OUT_BATCH(0);
OUT_BATCH(1); /* single instance */
diff --git a/lib/rendercopy_gen8.c b/lib/rendercopy_gen8.c
index 2b5d9b52..12ea55bf 100644
--- a/lib/rendercopy_gen8.c
+++ b/lib/rendercopy_gen8.c
@@ -229,11 +229,11 @@ gen8_create_sampler(struct intel_batchbuffer *batch,
annotation_add_state(aub, AUB_TRACE_SAMPLER_STATE,
offset, sizeof(*ss));
- ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
/* I've experimented with non-normalized coordinates and using the LD
* sampler fetch, but couldn't make it work. */
@@ -315,18 +315,18 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
* dword 4-7: position (x, y, 0, 1.0),
* dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0)
*/
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
/* Element state 0. These are 4 dwords of 0 required for the VUE format.
* We don't really know or care what they do.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* Element state 1 - Our "destination" vertices. These are passed down
* through the pipeline, and eventually make it to the pixel shader as
@@ -334,25 +334,25 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
* signed/scaled because of gen6 rendercopy. I see no particular reason
* for doing this though.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* Element state 2. Last but not least we store the U,V components as
* normalized floats. These will be used in the pixel shader to sample
* from the source buffer.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
/*
@@ -363,8 +363,8 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
*/
static void gen8_emit_vertex_buffer(struct intel_batchbuffer *batch,
uint32_t offset) {
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
- OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
+ OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
@@ -415,7 +415,7 @@ static uint32_t
gen6_create_cc_viewport(struct intel_batchbuffer *batch,
struct annotations_context *aub)
{
- struct gen6_cc_viewport *vp;
+ struct gen4_cc_viewport *vp;
uint32_t offset;
vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
@@ -469,7 +469,7 @@ gen6_create_scissor_rect(struct intel_batchbuffer *batch,
static void
gen8_emit_sip(struct intel_batchbuffer *batch) {
- OUT_BATCH(GEN6_STATE_SIP | (3 - 2));
+ OUT_BATCH(GEN4_STATE_SIP | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
}
@@ -490,7 +490,7 @@ gen7_emit_push_constants(struct intel_batchbuffer *batch) {
static void
gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2));
/* general */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
@@ -827,7 +827,7 @@ gen7_emit_clear(struct intel_batchbuffer *batch) {
static void
gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0);
OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
OUT_BATCH(0);
@@ -846,7 +846,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7-2));
OUT_BATCH(0); /* gen8+ ignore the topology type field */
OUT_BATCH(3); /* vertex count */
OUT_BATCH(0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
@@ -930,7 +930,7 @@ void gen8_render_copyfunc(struct intel_batchbuffer *batch,
/* Start emitting the commands. The order roughly follows the mesa blorp
* order */
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen8_emit_sip(batch);
diff --git a/lib/rendercopy_gen9.c b/lib/rendercopy_gen9.c
index 0157ced9..75d0f7f4 100644
--- a/lib/rendercopy_gen9.c
+++ b/lib/rendercopy_gen9.c
@@ -224,11 +224,11 @@ gen8_create_sampler(struct intel_batchbuffer *batch) {
annotation_add_state(&aub_annotations, AUB_TRACE_SAMPLER_STATE,
offset, sizeof(*ss));
- ss->ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
- ss->ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss->ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss->ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
+ ss->ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss->ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
/* I've experimented with non-normalized coordinates and using the LD
* sampler fetch, but couldn't make it work. */
@@ -309,18 +309,18 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
* dword 4-7: position (x, y, 0, 1.0),
* dword 8-11: texture coordinate 0 (u0, v0, 0, 1.0)
*/
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (3 * 2 + 1 - 2));
/* Element state 0. These are 4 dwords of 0 required for the VUE format.
* We don't really know or care what they do.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* we specify 0, but it's really does not exist */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* Element state 1 - Our "destination" vertices. These are passed down
* through the pipeline, and eventually make it to the pixel shader as
@@ -328,25 +328,25 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
* signed/scaled because of gen6 rendercopy. I see no particular reason
* for doing this though.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* Element state 2. Last but not least we store the U,V components as
* normalized floats. These will be used in the pixel shader to sample
* from the source buffer.
*/
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
/*
@@ -357,8 +357,8 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch) {
*/
static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch,
uint32_t offset) {
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
- OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (1 + (4 * 1) - 2));
+ OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT | /* VB 0th index */
GEN8_VB0_BUFFER_ADDR_MOD_EN | /* Address Modify Enable */
VERTEX_SIZE << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC(batch->bo, I915_GEM_DOMAIN_VERTEX, 0, offset);
@@ -406,7 +406,7 @@ gen8_create_blend_state(struct intel_batchbuffer *batch)
static uint32_t
gen6_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen6_cc_viewport *vp;
+ struct gen4_cc_viewport *vp;
uint32_t offset;
vp = intel_batchbuffer_subdata_alloc(batch, sizeof(*vp), 32);
@@ -457,7 +457,7 @@ gen6_create_scissor_rect(struct intel_batchbuffer *batch)
static void
gen8_emit_sip(struct intel_batchbuffer *batch) {
- OUT_BATCH(GEN6_STATE_SIP | (3 - 2));
+ OUT_BATCH(GEN4_STATE_SIP | (3 - 2));
OUT_BATCH(0);
OUT_BATCH(0);
}
@@ -482,7 +482,7 @@ gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
/* WaBindlessSurfaceStateModifyEnable:skl,bxt */
/* The length has to be one less if we dont modify
bindless state */
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (19 - 1 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (19 - 1 - 2));
/* general */
OUT_BATCH(0 | BASE_ADDRESS_MODIFY);
@@ -831,7 +831,7 @@ gen7_emit_clear(struct intel_batchbuffer *batch) {
static void
gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch, struct igt_buf *dst)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0);
OUT_BATCH((igt_buf_height(dst) - 1) << 16 | (igt_buf_width(dst) - 1));
OUT_BATCH(0);
@@ -853,7 +853,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch, uint32_t offset
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7-2));
OUT_BATCH(0); /* gen8+ ignore the topology type field */
OUT_BATCH(3); /* vertex count */
OUT_BATCH(0); /* We're specifying this instead with offset in GEN6_3DSTATE_VERTEX_BUFFERS */
@@ -933,7 +933,7 @@ void gen9_render_copyfunc(struct intel_batchbuffer *batch,
/* Start emitting the commands. The order roughly follows the mesa blorp
* order */
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D |
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D |
GEN9_PIPELINE_SELECTION_MASK);
gen8_emit_sip(batch);
diff --git a/tools/null_state_gen/intel_renderstate_gen6.c b/tools/null_state_gen/intel_renderstate_gen6.c
index 13b1e92e..c779ea42 100644
--- a/tools/null_state_gen/intel_renderstate_gen6.c
+++ b/tools/null_state_gen/intel_renderstate_gen6.c
@@ -81,7 +81,7 @@ gen6_bind_surfaces(struct intel_batchbuffer *batch)
static void
gen6_emit_sip(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_SIP | 0);
+ OUT_BATCH(GEN4_STATE_SIP | 0);
OUT_BATCH(0);
}
@@ -98,7 +98,7 @@ gen6_emit_urb(struct intel_batchbuffer *batch)
static void
gen6_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0); /* general */
OUT_RELOC(batch,
I915_GEM_DOMAIN_INSTRUCTION, 0,
@@ -189,23 +189,23 @@ gen6_emit_wm_constants(struct intel_batchbuffer *batch)
static void
gen6_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_DEPTH_BUFFER | (7 - 2));
- OUT_BATCH(SURFACE_NULL << GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN6_DEPTHFORMAT_D32_FLOAT << GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
+ OUT_BATCH(GEN4_3DSTATE_DEPTH_BUFFER | (7 - 2));
+ OUT_BATCH(SURFACE_NULL << GEN4_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
+ GEN4_DEPTHFORMAT_D32_FLOAT << GEN4_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN6_3DSTATE_CLEAR_PARAMS | (2 - 2));
+ OUT_BATCH(GEN4_3DSTATE_CLEAR_PARAMS | (2 - 2));
OUT_BATCH(0);
}
static void
gen6_emit_invariant(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE | (3 - 2));
OUT_BATCH(GEN6_3DSTATE_MULTISAMPLE_PIXEL_LOCATION_CENTER |
@@ -284,7 +284,7 @@ gen6_emit_wm(struct intel_batchbuffer *batch, int kernel)
static void
gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
{
- OUT_BATCH(GEN6_3DSTATE_BINDING_TABLE_POINTERS |
+ OUT_BATCH(GEN4_3DSTATE_BINDING_TABLE_POINTERS |
GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS |
(4 - 2));
OUT_BATCH(0); /* vs */
@@ -295,7 +295,7 @@ gen6_emit_binding_table(struct intel_batchbuffer *batch, uint32_t wm_table)
static void
gen6_emit_drawing_rectangle(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
OUT_BATCH(0xffffffff);
OUT_BATCH(0 | 0);
OUT_BATCH(0);
@@ -311,39 +311,39 @@ gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
*
* dword 4-11 are fetched from vertex buffer
*/
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | (2 * 3 + 1 - 2));
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* u0, v0 */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32_FLOAT << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
gen6_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen6_cc_viewport vp;
+ struct gen4_cc_viewport vp;
memset(&vp, 0, sizeof(vp));
@@ -392,41 +392,41 @@ gen6_create_sampler(struct intel_batchbuffer *batch,
/* We use the legacy mode to get the semantics specified by
* the Render extension. */
- ss.ss0.border_color_mode = GEN6_BORDER_COLOR_MODE_LEGACY;
+ ss.ss0.border_color_mode = GEN4_BORDER_COLOR_MODE_LEGACY;
switch (filter) {
default:
case SAMPLER_FILTER_NEAREST:
- ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+ ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
break;
case SAMPLER_FILTER_BILINEAR:
- ss.ss0.min_filter = GEN6_MAPFILTER_LINEAR;
- ss.ss0.mag_filter = GEN6_MAPFILTER_LINEAR;
+ ss.ss0.min_filter = GEN4_MAPFILTER_LINEAR;
+ ss.ss0.mag_filter = GEN4_MAPFILTER_LINEAR;
break;
}
switch (extend) {
default:
case SAMPLER_EXTEND_NONE:
- ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
- ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP_BORDER;
+ ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
+ ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP_BORDER;
break;
case SAMPLER_EXTEND_REPEAT:
- ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
- ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_WRAP;
+ ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
+ ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_WRAP;
break;
case SAMPLER_EXTEND_PAD:
- ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
break;
case SAMPLER_EXTEND_REFLECT:
- ss.ss1.r_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss.ss1.s_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
- ss.ss1.t_wrap_mode = GEN6_TEXCOORDMODE_MIRROR;
+ ss.ss1.r_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss.ss1.s_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
+ ss.ss1.t_wrap_mode = GEN4_TEXCOORDMODE_MIRROR;
break;
}
@@ -450,9 +450,9 @@ static void gen6_emit_vertex_buffer(struct intel_batchbuffer *batch)
offset = gen6_create_vertex_buffer(batch);
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | 3);
- OUT_BATCH(VB0_VERTEXDATA |
- 0 << VB0_BUFFER_INDEX_SHIFT |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | 3);
+ OUT_BATCH(GEN6_VB0_VERTEXDATA |
+ 0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
VB0_NULL_VERTEX_BUFFER |
0 << VB0_BUFFER_PITCH_SHIFT);
OUT_RELOC_STATE(batch, I915_GEM_DOMAIN_VERTEX, 0, offset);
diff --git a/tools/null_state_gen/intel_renderstate_gen7.c b/tools/null_state_gen/intel_renderstate_gen7.c
index 75ee9d6d..519ad30a 100644
--- a/tools/null_state_gen/intel_renderstate_gen7.c
+++ b/tools/null_state_gen/intel_renderstate_gen7.c
@@ -49,36 +49,36 @@ gen7_bind_buf_null(struct intel_batchbuffer *batch)
static void
gen7_emit_vertex_elements(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
((2 * (1 + 2)) + 1 - 2));
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R32G32B32A32_FLOAT <<
VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT);
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* x,y */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
0 << VE0_OFFSET_SHIFT); /* offsets vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
/* s,t */
- OUT_BATCH(0 << VE0_VERTEX_BUFFER_INDEX_SHIFT | VE0_VALID |
+ OUT_BATCH(0 << GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT | GEN6_VE0_VALID |
SURFACEFORMAT_R16G16_SSCALED << VE0_FORMAT_SHIFT |
4 << VE0_OFFSET_SHIFT); /* offset vb in bytes */
- OUT_BATCH(GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
+ OUT_BATCH(GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_SRC << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_1_FLT << VE1_VFCOMPONENT_3_SHIFT);
}
static uint32_t
@@ -95,9 +95,9 @@ static void gen7_emit_vertex_buffer(struct intel_batchbuffer *batch)
offset = gen7_create_vertex_buffer(batch);
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | (5 - 2));
- OUT_BATCH(0 << VB0_BUFFER_INDEX_SHIFT |
- VB0_VERTEXDATA |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | (5 - 2));
+ OUT_BATCH(0 << GEN6_VB0_BUFFER_INDEX_SHIFT |
+ GEN6_VB0_VERTEXDATA |
GEN7_VB0_ADDRESS_MODIFY_ENABLE |
VB0_NULL_VERTEX_BUFFER |
4*2 << VB0_BUFFER_PITCH_SHIFT);
@@ -130,7 +130,7 @@ gen7_emit_binding_table(struct intel_batchbuffer *batch)
static void
gen7_emit_drawing_rectangle(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
+ OUT_BATCH(GEN4_3DSTATE_DRAWING_RECTANGLE | (4 - 2));
/* Purposedly set min > max for null rectangle */
OUT_BATCH(0xffffffff);
OUT_BATCH(0 | 0);
@@ -155,7 +155,7 @@ gen7_create_blend_state(struct intel_batchbuffer *batch)
static void
gen7_emit_state_base_address(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (10 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (10 - 2));
OUT_BATCH(0);
OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
OUT_RELOC(batch, I915_GEM_DOMAIN_INSTRUCTION, 0, BASE_ADDRESS_MODIFY);
@@ -171,7 +171,7 @@ gen7_emit_state_base_address(struct intel_batchbuffer *batch)
static uint32_t
gen7_create_cc_viewport(struct intel_batchbuffer *batch)
{
- struct gen6_cc_viewport vp;
+ struct gen4_cc_viewport vp;
memset(&vp, 0, sizeof(vp));
vp.min_depth = -1.e35;
@@ -196,12 +196,12 @@ gen7_create_sampler(struct intel_batchbuffer *batch)
struct gen7_sampler_state ss;
memset(&ss, 0, sizeof(ss));
- ss.ss0.min_filter = GEN6_MAPFILTER_NEAREST;
- ss.ss0.mag_filter = GEN6_MAPFILTER_NEAREST;
+ ss.ss0.min_filter = GEN4_MAPFILTER_NEAREST;
+ ss.ss0.mag_filter = GEN4_MAPFILTER_NEAREST;
- ss.ss3.r_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss.ss3.s_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
- ss.ss3.t_wrap_mode = GEN6_TEXCOORDMODE_CLAMP;
+ ss.ss3.r_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss.ss3.s_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
+ ss.ss3.t_wrap_mode = GEN4_TEXCOORDMODE_CLAMP;
ss.ss3.non_normalized_coord = 1;
@@ -402,7 +402,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
{
OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER | (7 - 2));
OUT_BATCH(SURFACE_NULL << GEN7_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT |
- GEN6_DEPTHFORMAT_D32_FLOAT <<
+ GEN4_DEPTHFORMAT_D32_FLOAT <<
GEN7_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT);
OUT_BATCH(0); /* disable depth, stencil and hiz */
OUT_BATCH(0);
@@ -417,7 +417,7 @@ gen7_emit_null_depth_buffer(struct intel_batchbuffer *batch)
void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen7_emit_state_base_address(batch);
gen7_emit_multisample(batch);
@@ -442,8 +442,8 @@ void gen7_setup_null_render_state(struct intel_batchbuffer *batch)
gen7_emit_binding_table(batch);
gen7_emit_drawing_rectangle(batch);
- OUT_BATCH(GEN6_3DPRIMITIVE | (7 - 2));
- OUT_BATCH(GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7 - 2));
+ OUT_BATCH(GEN4_3DPRIMITIVE_VERTEX_SEQUENTIAL | _3DPRIM_RECTLIST);
OUT_BATCH(3);
OUT_BATCH(0);
OUT_BATCH(1); /* single instance */
diff --git a/tools/null_state_gen/intel_renderstate_gen8.c b/tools/null_state_gen/intel_renderstate_gen8.c
index c6973e0e..0e99b71d 100644
--- a/tools/null_state_gen/intel_renderstate_gen8.c
+++ b/tools/null_state_gen/intel_renderstate_gen8.c
@@ -152,7 +152,7 @@ static void gen8_emit_so_buffer(struct intel_batchbuffer *batch, const int index
static void gen8_emit_state_base_address(struct intel_batchbuffer *batch) {
const unsigned offset = 0;
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS | (16 - 2));
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS | (16 - 2));
/* general */
OUT_RELOC(batch, 0, 0, offset | BASE_ADDRESS_MODIFY);
@@ -200,10 +200,10 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
const int buffers = 33;
int i;
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS | ((4 * buffers) - 1));
for (i = 0; i < buffers; i++) {
- OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT |
+ OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
GEN8_VB0_BUFFER_ADDR_MOD_EN);
OUT_BATCH(0); /* Addr */
OUT_BATCH(0);
@@ -216,16 +216,16 @@ static void gen6_emit_vertex_elements(struct intel_batchbuffer *batch)
const int elements = 34;
int i;
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1)));
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS | ((2 * elements - 1)));
for (i = 0; i < elements; i++) {
if (i == 0) {
- OUT_BATCH(VE0_VALID | i);
+ OUT_BATCH(GEN6_VE0_VALID | i);
OUT_BATCH(
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT
);
} else {
OUT_BATCH(0);
@@ -314,7 +314,7 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *
static void gen8_emit_primitive(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7-2));
OUT_BATCH(4); /* gen8+ ignore the topology type field */
OUT_BATCH(1); /* vertex count */
OUT_BATCH(0);
@@ -334,7 +334,7 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
OUT_BATCH(0);
OUT_BATCH(0);
- OUT_BATCH(GEN6_PIPELINE_SELECT | PIPELINE_SELECT_3D);
+ OUT_BATCH(G4X_PIPELINE_SELECT | PIPELINE_SELECT_3D);
gen8_emit_wm(batch);
gen8_emit_ps(batch);
@@ -383,8 +383,8 @@ void gen8_setup_null_render_state(struct intel_batchbuffer *batch)
gen8_emit_state_base_address(batch);
- OUT_CMD(GEN6_STATE_SIP, 3);
- OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4);
+ OUT_CMD(GEN4_STATE_SIP, 3);
+ OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
gen8_emit_chroma_key(batch, 0);
diff --git a/tools/null_state_gen/intel_renderstate_gen9.c b/tools/null_state_gen/intel_renderstate_gen9.c
index 9f338bbf..dc5c831a 100644
--- a/tools/null_state_gen/intel_renderstate_gen9.c
+++ b/tools/null_state_gen/intel_renderstate_gen9.c
@@ -163,11 +163,11 @@ static void gen8_emit_vertex_buffers(struct intel_batchbuffer *batch)
const int buffers = 33;
int i;
- OUT_BATCH(GEN6_3DSTATE_VERTEX_BUFFERS |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_BUFFERS |
(((4 * buffers) + 1)- 2) /* DWORD count - 2 */);
for (i = 0; i < buffers; i++) {
- OUT_BATCH(i << VB0_BUFFER_INDEX_SHIFT |
+ OUT_BATCH(i << GEN6_VB0_BUFFER_INDEX_SHIFT |
GEN8_VB0_BUFFER_ADDR_MOD_EN);
OUT_BATCH(0); /* Address */
OUT_BATCH(0);
@@ -180,16 +180,16 @@ static void gen8_emit_vertex_elements(struct intel_batchbuffer *batch)
const int elements = 34;
int i;
- OUT_BATCH(GEN6_3DSTATE_VERTEX_ELEMENTS |
+ OUT_BATCH(GEN4_3DSTATE_VERTEX_ELEMENTS |
(((2 * elements) + 1) - 2) /* DWORD count - 2 */);
/* Element 0 */
- OUT_BATCH(VE0_VALID);
+ OUT_BATCH(GEN6_VE0_VALID);
OUT_BATCH(
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
- GEN6_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_0_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_1_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_2_SHIFT |
+ GEN4_VFCOMPONENT_STORE_0 << VE1_VFCOMPONENT_3_SHIFT);
/* Elements 1 -> 33 */
for (i = 1; i < elements; i++) {
OUT_BATCH(0);
@@ -277,7 +277,7 @@ static void gen8_emit_viewport_state_pointers_sf_clip(struct intel_batchbuffer *
static void gen8_emit_primitive(struct intel_batchbuffer *batch)
{
- OUT_BATCH(GEN6_3DPRIMITIVE | (7-2));
+ OUT_BATCH(GEN4_3DPRIMITIVE | (7-2));
OUT_BATCH(4); /* gen8+ ignore the topology type field */
OUT_BATCH(1); /* vertex count */
OUT_BATCH(0);
@@ -288,7 +288,7 @@ static void gen8_emit_primitive(struct intel_batchbuffer *batch)
static void gen9_emit_state_base_address(struct intel_batchbuffer *batch) {
const unsigned offset = 0;
- OUT_BATCH(GEN6_STATE_BASE_ADDRESS |
+ OUT_BATCH(GEN4_STATE_BASE_ADDRESS |
(19 - 2) /* DWORD count - 2 */);
/* general state base address - requires BB address
@@ -414,8 +414,8 @@ void gen9_setup_null_render_state(struct intel_batchbuffer *batch)
/* State base addresses */
gen9_emit_state_base_address(batch);
- OUT_CMD(GEN6_STATE_SIP, 3);
- OUT_CMD(GEN6_3DSTATE_DRAWING_RECTANGLE, 4);
+ OUT_CMD(GEN4_STATE_SIP, 3);
+ OUT_CMD(GEN4_3DSTATE_DRAWING_RECTANGLE, 4);
OUT_CMD(GEN7_3DSTATE_DEPTH_BUFFER, 8);
/* Chroma key */
--
2.14.3
_______________________________________________
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igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] [PATCH i-g-t v2 3/3] lib/gen6_render: Drop duplicated definitions
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/rendercopy: Use gen4 definitions if applicable Lukasz Kalamarz
@ 2018-06-20 11:54 ` Lukasz Kalamarz
2018-06-20 12:34 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy Patchwork
` (2 subsequent siblings)
4 siblings, 0 replies; 6+ messages in thread
From: Lukasz Kalamarz @ 2018-06-20 11:54 UTC (permalink / raw)
To: igt-dev
Dropping duplicated definitions of registers,fields
and shiftsm, which were implemented in gen4 and
does not changed in gen6.
Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
Cc: Katarzyna Dec <katarzyna.dec@intel.com>
Cc: Antonio Argenziano <antonio.argenziano@intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
lib/gen6_render.h | 137 +-----------------------------------------------------
1 file changed, 2 insertions(+), 135 deletions(-)
diff --git a/lib/gen6_render.h b/lib/gen6_render.h
index 6bf468df..f45c8ae7 100644
--- a/lib/gen6_render.h
+++ b/lib/gen6_render.h
@@ -5,26 +5,15 @@
#include "surfaceformat.h"
#include "gen4_render.h"
-#define GEN6_3D(Pipeline,Opcode,Subopcode) ((3 << 29) | \
- ((Pipeline) << 27) | \
- ((Opcode) << 24) | \
- ((Subopcode) << 16))
-
-#define GEN6_STATE_BASE_ADDRESS GEN4_3D(0, 1, 1)
-# define BASE_ADDRESS_MODIFY (1 << 0)
+/* GEN6_STATE_BASE_ADDRESS */
# define BUFFER_SIZE_MODIFY (1 << 0)
-#define GEN6_STATE_SIP GEN4_3D(0, 1, 2)
-
#define GEN6_3DSTATE_VF_STATISTICS GEN4_3D(1, 0, 0xB)
-#define GEN6_PIPELINE_SELECT GEN4_3D(1, 1, 4)
-# define PIPELINE_SELECT_3D 0
-# define PIPELINE_SELECT_MEDIA 1
#define GEN6_MEDIA_STATE_POINTERS GEN4_3D(2, 0, 0)
#define GEN6_MEDIA_OBJECT GEN4_3D(2, 1, 0)
-#define GEN6_3DSTATE_BINDING_TABLE_POINTERS GEN4_3D(3, 0, 0x01)
+/* GEN6_3DSTATE_BINDING_TABLE_POINTERS */
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_PS (1 << 12)/* for GEN6 */
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_GS (1 << 9) /* for GEN6 */
# define GEN6_3DSTATE_BINDING_TABLE_MODIFY_VS (1 << 8) /* for GEN6 */
@@ -42,7 +31,6 @@
# define GEN6_3DSTATE_URB_GS_ENTRIES_SHIFT 8
# define GEN6_3DSTATE_URB_GS_SIZE_SHIFT 0
-#define GEN6_3DSTATE_VERTEX_BUFFERS GEN4_3D(3, 0, 0x08)
#define GEN6_3DSTATE_VERTEX_ELEMENTS GEN4_3D(3, 0, 0x09)
#define GEN6_3DSTATE_INDEX_BUFFER GEN4_3D(3, 0, 0x0A)
#define GEN6_3DSTATE_VIEWPORT_STATE_POINTERS GEN4_3D(3, 0, 0x0D)
@@ -103,13 +91,9 @@
#define GEN6_3DSTATE_SAMPLE_MASK GEN4_3D(3, 0, 0x18)
-#define GEN6_3DSTATE_DRAWING_RECTANGLE GEN4_3D(3, 1, 0x00)
#define GEN6_3DSTATE_CONSTANT_COLOR GEN4_3D(3, 1, 0x01)
#define GEN6_3DSTATE_SAMPLER_PALETTE_LOAD GEN4_3D(3, 1, 0x02)
#define GEN6_3DSTATE_CHROMA_KEY GEN4_3D(3, 1, 0x04)
-#define GEN6_3DSTATE_DEPTH_BUFFER GEN4_3D(3, 1, 0x05)
-# define GEN6_3DSTATE_DEPTH_BUFFER_TYPE_SHIFT 29
-# define GEN6_3DSTATE_DEPTH_BUFFER_FORMAT_SHIFT 18
#define GEN6_3DSTATE_POLY_STIPPLE_OFFSET GEN4_3D(3, 1, 0x06)
#define GEN6_3DSTATE_POLY_STIPPLE_PATTERN GEN4_3D(3, 1, 0x07)
@@ -126,9 +110,7 @@
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_4 (2 << 1)
# define GEN6_3DSTATE_MULTISAMPLE_NUMSAMPLES_8 (3 << 1)
-#define GEN6_3DSTATE_CLEAR_PARAMS GEN4_3D(3, 1, 0x10)
/* DW1 */
-# define GEN6_3DSTATE_DEPTH_CLEAR_VALID (1 << 15)
# define GEN6_PIPE_CONTROL_NOWRITE (0 << 14)
# define GEN6_PIPE_CONTROL_WRITE_QWORD (1 << 14)
# define GEN6_PIPE_CONTROL_WRITE_DEPTH (2 << 14)
@@ -145,29 +127,15 @@
#define GEN6_3DSTATE_MONOFILTER_SIZE GEN4_3D(3, 1, 0x11)
#define GEN6_PIPE_CONTROL GEN4_3D(3, 2, 0)
-#define GEN6_3DPRIMITIVE GEN4_3D(3, 3, 0)
-# define GEN6_3DPRIMITIVE_VERTEX_SEQUENTIAL (0 << 15)
-# define GEN6_3DPRIMITIVE_VERTEX_RANDOM (1 << 15)
-/* Primitive types are in gen6_defines.h */
-# define GEN6_3DPRIMITIVE_TOPOLOGY_SHIFT 10
-
/* VERTEX_BUFFER_STATE Structure */
#define GEN6_VB0_BUFFER_INDEX_SHIFT 26
#define GEN6_VB0_VERTEXDATA (0 << 20)
#define GEN6_VB0_INSTANCEDATA (1 << 20)
-#define VB0_BUFFER_PITCH_SHIFT 0
#define VB0_NULL_VERTEX_BUFFER (1 << 13)
/* VERTEX_ELEMENT_STATE Structure */
#define GEN6_VE0_VERTEX_BUFFER_INDEX_SHIFT 26 /* for GEN6 */
#define GEN6_VE0_VALID (1 << 25) /* for GEN6 */
-#define VE0_FORMAT_SHIFT 16
-#define VE0_OFFSET_SHIFT 0
-#define VE1_VFCOMPONENT_0_SHIFT 28
-#define VE1_VFCOMPONENT_1_SHIFT 24
-#define VE1_VFCOMPONENT_2_SHIFT 20
-#define VE1_VFCOMPONENT_3_SHIFT 16
-#define VE1_DESTINATION_ELEMENT_OFFSET_SHIFT 0
#define GEN6_SVG_CTL 0x7400
# define GEN6_SVG_CTL_GS_BA (0 << 8)
@@ -302,26 +270,6 @@
#define GEN6_EU_ATT_CLR_1 0x8834
#define GEN6_EU_RDATA 0x8840
-/* for GEN6+ */
-#define UF0_CS_REALLOC (1 << 13)
-#define UF0_VFE_REALLOC (1 << 12)
-#define UF0_SF_REALLOC (1 << 11)
-#define UF0_CLIP_REALLOC (1 << 10)
-#define UF0_GS_REALLOC (1 << 9)
-#define UF0_VS_REALLOC (1 << 8)
-#define UF1_CLIP_FENCE_SHIFT 20
-#define UF1_GS_FENCE_SHIFT 10
-#define UF1_VS_FENCE_SHIFT 0
-#define UF2_CS_FENCE_SHIFT 20
-#define UF2_VFE_FENCE_SHIFT 10
-#define UF2_SF_FENCE_SHIFT 0
-
-/* for GEN6_3DSTATE_PIPELINED_POINTERS */
-#define GEN6_GS_DISABLE 0
-#define GEN6_GS_ENABLE 1
-#define GEN6_CLIP_DISABLE 0
-#define GEN6_CLIP_ENABLE 1
-
/* 3D state */
#define _3DOP_3DSTATE_PIPELINED 0x0
#define _3DOP_3DSTATE_NONPIPELINED 0x1
@@ -346,28 +294,6 @@
#define _3DCONTROL 0x00
#define _3DPRIMITIVE 0x00
-#define _3DPRIM_POINTLIST 0x01
-#define _3DPRIM_LINELIST 0x02
-#define _3DPRIM_LINESTRIP 0x03
-#define _3DPRIM_TRILIST 0x04
-#define _3DPRIM_TRISTRIP 0x05
-#define _3DPRIM_TRIFAN 0x06
-#define _3DPRIM_QUADLIST 0x07
-#define _3DPRIM_QUADSTRIP 0x08
-#define _3DPRIM_LINELIST_ADJ 0x09
-#define _3DPRIM_LINESTRIP_ADJ 0x0A
-#define _3DPRIM_TRILIST_ADJ 0x0B
-#define _3DPRIM_TRISTRIP_ADJ 0x0C
-#define _3DPRIM_TRISTRIP_REVERSE 0x0D
-#define _3DPRIM_POLYGON 0x0E
-#define _3DPRIM_RECTLIST 0x0F
-#define _3DPRIM_LINELOOP 0x10
-#define _3DPRIM_POINTLIST_BF 0x11
-#define _3DPRIM_LINESTRIP_CONT 0x12
-#define _3DPRIM_LINESTRIP_BF 0x13
-#define _3DPRIM_LINESTRIP_CONT_BF 0x14
-#define _3DPRIM_TRIFAN_NOSTIPPLE 0x15
-
#define _3DPRIM_VERTEXBUFFER_ACCESS_SEQUENTIAL 0
#define _3DPRIM_VERTEXBUFFER_ACCESS_RANDOM 1
@@ -438,19 +364,9 @@
#define GEN6_COVERAGE_PIXELS_2 2
#define GEN6_COVERAGE_PIXELS_4 3
-#define GEN6_CULLMODE_BOTH 0
-#define GEN6_CULLMODE_NONE 1
-#define GEN6_CULLMODE_FRONT 2
-#define GEN6_CULLMODE_BACK 3
-
#define GEN6_DEFAULTCOLOR_R8G8B8A8_UNORM 0
#define GEN6_DEFAULTCOLOR_R32G32B32A32_FLOAT 1
-#define GEN6_DEPTHFORMAT_D32_FLOAT_S8X24_UINT 0
-#define GEN6_DEPTHFORMAT_D32_FLOAT 1
-#define GEN6_DEPTHFORMAT_D24_UNORM_S8_UINT 2
-#define GEN6_DEPTHFORMAT_D16_UNORM 5
-
#define GEN6_FLOATING_POINT_IEEE_754 0
#define GEN6_FLOATING_POINT_NON_IEEE_754 1
@@ -478,26 +394,9 @@
#define GEN6_LOGICOPFUNCTION_OR 14
#define GEN6_LOGICOPFUNCTION_SET 15
-#define GEN6_MAPFILTER_NEAREST 0x0
-#define GEN6_MAPFILTER_LINEAR 0x1
-#define GEN6_MAPFILTER_ANISOTROPIC 0x2
-
-#define GEN6_MIPFILTER_NONE 0
-#define GEN6_MIPFILTER_NEAREST 1
-#define GEN6_MIPFILTER_LINEAR 3
-
#define GEN6_POLYGON_FRONT_FACING 0
#define GEN6_POLYGON_BACK_FACING 1
-#define GEN6_PREFILTER_ALWAYS 0x0
-#define GEN6_PREFILTER_NEVER 0x1
-#define GEN6_PREFILTER_LESS 0x2
-#define GEN6_PREFILTER_EQUAL 0x3
-#define GEN6_PREFILTER_LEQUAL 0x4
-#define GEN6_PREFILTER_GREATER 0x5
-#define GEN6_PREFILTER_NOTEQUAL 0x6
-#define GEN6_PREFILTER_GEQUAL 0x7
-
#define GEN6_PROVOKING_VERTEX_0 0
#define GEN6_PROVOKING_VERTEX_1 1
#define GEN6_PROVOKING_VERTEX_2 2
@@ -518,16 +417,6 @@
#define GEN6_STENCILOP_DECR 6
#define GEN6_STENCILOP_INVERT 7
-#define GEN6_BORDER_COLOR_MODE_DEFAULT 0
-#define GEN6_BORDER_COLOR_MODE_LEGACY 1
-
-#define GEN6_TEXCOORDMODE_WRAP 0
-#define GEN6_TEXCOORDMODE_MIRROR 1
-#define GEN6_TEXCOORDMODE_CLAMP 2
-#define GEN6_TEXCOORDMODE_CUBE 3
-#define GEN6_TEXCOORDMODE_CLAMP_BORDER 4
-#define GEN6_TEXCOORDMODE_MIRROR_ONCE 5
-
#define GEN6_THREAD_PRIORITY_NORMAL 0
#define GEN6_THREAD_PRIORITY_HIGH 1
@@ -540,15 +429,6 @@
#define GEN6_VERTEXBUFFER_ACCESS_VERTEXDATA 0
#define GEN6_VERTEXBUFFER_ACCESS_INSTANCEDATA 1
-#define GEN6_VFCOMPONENT_NOSTORE 0
-#define GEN6_VFCOMPONENT_STORE_SRC 1
-#define GEN6_VFCOMPONENT_STORE_0 2
-#define GEN6_VFCOMPONENT_STORE_1_FLT 3
-#define GEN6_VFCOMPONENT_STORE_1_INT 4
-#define GEN6_VFCOMPONENT_STORE_VID 5
-#define GEN6_VFCOMPONENT_STORE_IID 6
-#define GEN6_VFCOMPONENT_STORE_PID 7
-
/* Execution Unit (EU) defines */
#define GEN6_ALIGN_1 0
@@ -867,14 +747,6 @@
* The legacy mode matches the semantics specified by the Render
* extension.
*/
-struct gen6_sampler_default_border_color {
- float color[4];
-};
-
-struct gen6_sampler_legacy_border_color {
- uint8_t color[4];
-};
-
struct gen6_sampler_state {
struct {
uint32_t shadow_function:3;
@@ -1068,9 +940,4 @@ struct gen6_surface_state {
} ss5;
};
-struct gen6_cc_viewport {
- float min_depth;
- float max_depth;
-};
-
#endif
--
2.14.3
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/rendercopy: Use gen4 definitions if applicable Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 3/3] lib/gen6_render: Drop duplicated definitions Lukasz Kalamarz
@ 2018-06-20 12:34 ` Patchwork
2018-06-20 14:15 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2018-06-21 10:46 ` [igt-dev] [PATCH i-g-t v2 1/3] " Katarzyna Dec
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-06-20 12:34 UTC (permalink / raw)
To: Lukasz Kalamarz; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy
URL : https://patchwork.freedesktop.org/series/45071/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4344 -> IGTPW_1488 =
== Summary - WARNING ==
Minor unknown changes coming with IGTPW_1488 need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in IGTPW_1488, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://patchwork.freedesktop.org/api/1.0/series/45071/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in IGTPW_1488:
=== IGT changes ===
==== Warnings ====
igt@gem_render_linear_blits@basic:
fi-bwr-2160: SKIP -> PASS +1
igt@gem_render_tiled_blits@basic:
fi-elk-e7500: SKIP -> PASS +1
fi-ilk-650: SKIP -> PASS +2
== Known issues ==
Here are the changes found in IGTPW_1488 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_ctx_create@basic-files:
fi-skl-guc: PASS -> DMESG-WARN (fdo#106954)
igt@gem_exec_gttfill@basic:
fi-byt-n2820: PASS -> FAIL (fdo#106744)
igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#105719)
igt@kms_flip@basic-flip-vs-dpms:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106000)
igt@kms_pipe_crc_basic@read-crc-pipe-c-frame-sequence:
fi-glk-j4005: PASS -> DMESG-WARN (fdo#106097) +2
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#105719 https://bugs.freedesktop.org/show_bug.cgi?id=105719
fdo#106000 https://bugs.freedesktop.org/show_bug.cgi?id=106000
fdo#106097 https://bugs.freedesktop.org/show_bug.cgi?id=106097
fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744
fdo#106954 https://bugs.freedesktop.org/show_bug.cgi?id=106954
== Participating hosts (43 -> 36) ==
Missing (7): fi-ilk-m540 fi-bxt-dsi fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-cnl-psr
== Build changes ==
* IGT: IGT_4524 -> IGTPW_1488
CI_DRM_4344: 922a029a1d0ecf5c7e5c86a372a5d3df3fd35483 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1488: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1488/
IGT_4524: 9ab9268fa7eeda0a7ea6eb2ab02bb6c5b9c91ba0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1488/issues.html
_______________________________________________
igt-dev mailing list
igt-dev@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/igt-dev
^ permalink raw reply [flat|nested] 6+ messages in thread
* [igt-dev] ✓ Fi.CI.IGT: success for series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
` (2 preceding siblings ...)
2018-06-20 12:34 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy Patchwork
@ 2018-06-20 14:15 ` Patchwork
2018-06-21 10:46 ` [igt-dev] [PATCH i-g-t v2 1/3] " Katarzyna Dec
4 siblings, 0 replies; 6+ messages in thread
From: Patchwork @ 2018-06-20 14:15 UTC (permalink / raw)
To: Lukasz Kalamarz; +Cc: igt-dev
== Series Details ==
Series: series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy
URL : https://patchwork.freedesktop.org/series/45071/
State : success
== Summary ==
= CI Bug Log - changes from IGT_4524_full -> IGTPW_1488_full =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/45071/revisions/1/mbox/
== Known issues ==
Here are the changes found in IGTPW_1488_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
shard-kbl: NOTRUN -> DMESG-FAIL (fdo#106947)
igt@gem_exec_nop@signal-all:
shard-glk: PASS -> DMESG-WARN (fdo#105763)
igt@gem_mocs_settings@mocs-rc6-ctx-render:
shard-snb: SKIP -> INCOMPLETE (fdo#105411)
igt@kms_cursor_legacy@cursorb-vs-flipb-toggle:
shard-glk: PASS -> DMESG-WARN (fdo#106538, fdo#105763)
igt@kms_flip@2x-flip-vs-expired-vblank:
shard-hsw: PASS -> FAIL (fdo#102887)
igt@kms_flip@2x-plain-flip-fb-recreate-interruptible:
shard-glk: PASS -> FAIL (fdo#103928)
igt@kms_rotation_crc@sprite-rotation-180:
shard-snb: PASS -> FAIL (fdo#104724, fdo#103925)
igt@testdisplay:
shard-glk: PASS -> INCOMPLETE (k.org#198133, fdo#103359)
==== Possible fixes ====
igt@drv_selftest@live_evict:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@drv_selftest@live_gtt:
shard-kbl: FAIL (fdo#105347) -> PASS
igt@drv_selftest@live_hangcheck:
shard-apl: DMESG-FAIL (fdo#106560, fdo#106947) -> PASS
igt@gem_busy@extended-bsd1:
shard-snb: INCOMPLETE (fdo#105411) -> SKIP
igt@kms_available_modes_crc@available_mode_test_crc:
shard-snb: FAIL (fdo#106641) -> PASS
igt@kms_flip@2x-plain-flip-ts-check:
shard-glk: FAIL (fdo#100368) -> PASS
igt@kms_flip_tiling@flip-y-tiled:
shard-glk: FAIL (fdo#104724, fdo#103822) -> PASS
igt@kms_rotation_crc@sprite-rotation-270:
shard-kbl: FAIL (fdo#104724, fdo#103925) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106641 https://bugs.freedesktop.org/show_bug.cgi?id=106641
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* IGT: IGT_4524 -> IGTPW_1488
* Linux: CI_DRM_4342 -> CI_DRM_4344
CI_DRM_4342: dd55db88fc3f54a96c15467ce534e83a8788ab73 @ git://anongit.freedesktop.org/gfx-ci/linux
CI_DRM_4344: 922a029a1d0ecf5c7e5c86a372a5d3df3fd35483 @ git://anongit.freedesktop.org/gfx-ci/linux
IGTPW_1488: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1488/
IGT_4524: 9ab9268fa7eeda0a7ea6eb2ab02bb6c5b9c91ba0 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1488/shards.html
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^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
` (3 preceding siblings ...)
2018-06-20 14:15 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
@ 2018-06-21 10:46 ` Katarzyna Dec
4 siblings, 0 replies; 6+ messages in thread
From: Katarzyna Dec @ 2018-06-21 10:46 UTC (permalink / raw)
To: Lukasz Kalamarz; +Cc: igt-dev
On Wed, Jun 20, 2018 at 01:54:34PM +0200, Lukasz Kalamarz wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Add rendercopy implementation for gen4/5. Basic structure
> copied from the gen6 implementation, and the gen4/5 specific
> bits were mostly lifted from sna.
>
> v2: Renamed registers definitions, which are GEN4 specific
> to include that prefix (Lukasz)
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Signed-off-by: Lukasz Kalamarz <lukasz.kalamarz@intel.com>
> Cc: Katarzyna Dec <katarzyna.dec@intel.com>
> Cc: Antonio Argenziano <antonio.argenziano@intel.com>
> Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Generally whole series looks ok. The only note to all 3 patches is
to use checkpatch to check style errors (check it on files, e.g.
checkpatch.pl -f gen4_render.h).
Not all comments from checkpatch should be applied, because not all
make sense in this case.
Some defines are not algined. I have applied all 3 patches and
checked, because looking into *.patch seemed like there is a lot
of them.
Kasia :)
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^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-06-21 10:46 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-06-20 11:54 [igt-dev] [PATCH i-g-t v2 1/3] lib/rendercopy: Add gen4/5 rendercopy Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 2/3] lib/rendercopy: Use gen4 definitions if applicable Lukasz Kalamarz
2018-06-20 11:54 ` [igt-dev] [PATCH i-g-t v2 3/3] lib/gen6_render: Drop duplicated definitions Lukasz Kalamarz
2018-06-20 12:34 ` [igt-dev] ✓ Fi.CI.BAT: success for series starting with [i-g-t,v2,1/3] lib/rendercopy: Add gen4/5 rendercopy Patchwork
2018-06-20 14:15 ` [igt-dev] ✓ Fi.CI.IGT: " Patchwork
2018-06-21 10:46 ` [igt-dev] [PATCH i-g-t v2 1/3] " Katarzyna Dec
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