[PATCH] drm/i915: Enable hw workaround to bypass alpha

[PATCH] drm/i915: Enable hw workaround to bypass alpha

[Vandita Kulkarni]

Alpha blending with alpha 0 and 0xff passes through
alpha math and rounding logic causing differences
compared to fully transparent or opaque plane,resulting
in CRC mismatch.
This WA on icl and above enables hardware to bypass alpha
math and rounding for per pixel alpha values of 00 and 0xff

Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
---
 drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
 drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
 2 files changed, 20 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 4bfd7a9..6e59bfe 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7366,6 +7366,14 @@ enum {
 #define BDW_SCRATCH1					_MMIO(0xb11c)
 #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
 
+/*GEN11 chicken */
+#define _PIPEA_CHICKEN			0x70038
+#define _PIPEB_CHICKEN			0x71038
+#define _PIPEC_CHICKEN			0x72038
+#define  PER_PIXEL_ALPHA_BYPASS_EN	(1<<7)
+#define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
+						   _PIPEB_CHICKEN)
+
 /* PCH */
 
 /* south display engine interrupt: IBX */
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2c8fef3..ca5882c 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	struct intel_atomic_state *old_intel_state =
 		to_intel_atomic_state(old_state);
 	bool psl_clkgate_wa;
+	u32 pipe_chicken;
 
 	if (WARN_ON(intel_crtc->active))
 		return;
@@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
 	 */
 	intel_color_load_luts(&pipe_config->base);
 
+	/*
+	 * Display WA #1153: enable hardware to bypass the alpha math
+	 * and rounding for per-pixel values 00 and 0xff
+	 */
+	if (INTEL_GEN(dev_priv) >= 11) {
+		pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
+		if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
+			I915_WRITE_FW(PIPE_CHICKEN(pipe),
+				  pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);
+	}
+
 	intel_ddi_set_pipe_settings(pipe_config);
 	if (!transcoder_is_dsi(cpu_transcoder))
 		intel_ddi_enable_transcoder_func(pipe_config);
-- 
1.9.1

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✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable hw workaround to bypass alpha

[Patchwork]

== Series Details ==

Series: drm/i915: Enable hw workaround to bypass alpha
URL   : https://patchwork.freedesktop.org/series/45173/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
1c10ad664cb9 drm/i915: Enable hw workaround to bypass alpha
-:27: CHECK:SPACING: spaces preferred around that '<<' (ctx:VxV)
#27: FILE: drivers/gpu/drm/i915/i915_reg.h:7373:
+#define  PER_PIXEL_ALPHA_BYPASS_EN	(1<<7)
                                   	  ^

-:58: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#58: FILE: drivers/gpu/drm/i915/intel_display.c:5703:
+			I915_WRITE_FW(PIPE_CHICKEN(pipe),
+				  pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);

total: 0 errors, 0 warnings, 2 checks, 38 lines checked

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✓ Fi.CI.BAT: success for drm/i915: Enable hw workaround to bypass alpha

[Patchwork]

== Series Details ==

Series: drm/i915: Enable hw workaround to bypass alpha
URL   : https://patchwork.freedesktop.org/series/45173/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4359 -> Patchwork_9383 =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9383 need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9383, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/45173/revisions/1/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9383:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_gttfill@basic:
      fi-pnv-d510:        PASS -> SKIP

    
== Known issues ==

  Here are the changes found in Patchwork_9383 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@debugfs_test@read_all_entries:
      fi-snb-2520m:       PASS -> INCOMPLETE (fdo#103713)

    igt@gem_exec_gttfill@basic:
      fi-byt-n2820:       PASS -> FAIL (fdo#106744)

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         PASS -> INCOMPLETE (fdo#103927)

    
    ==== Possible fixes ====

    igt@gem_ctx_create@basic-files:
      fi-skl-gvtdvm:      INCOMPLETE (fdo#106988, fdo#105600) -> PASS

    
  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105600 https://bugs.freedesktop.org/show_bug.cgi?id=105600
  fdo#106744 https://bugs.freedesktop.org/show_bug.cgi?id=106744
  fdo#106988 https://bugs.freedesktop.org/show_bug.cgi?id=106988


== Participating hosts (42 -> 37) ==

  Missing    (5): fi-byt-squawks fi-kbl-x1275 fi-ilk-m540 fi-glk-dsi fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4359 -> Patchwork_9383

  CI_DRM_4359: fe0300c16bff0f9c82050e56cdbc3880f87e39bd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4527: 04afec3ccfcb35e994f2e78254ff499f6b94f097 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9383: 1c10ad664cb90e427538aa0b5c248ff1e28626c5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

1c10ad664cb9 drm/i915: Enable hw workaround to bypass alpha

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9383/issues.html
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Re: [PATCH] drm/i915: Enable hw workaround to bypass alpha

[Lankhorst, Maarten]

[-- Attachment #1.1: Type: text/plain, Size: 2544 bytes --]

tor 2018-06-21 klockan 19:00 +0530 skrev Vandita Kulkarni:
> Alpha blending with alpha 0 and 0xff passes through
> alpha math and rounding logic causing differences
> compared to fully transparent or opaque plane,resulting
> in CRC mismatch.
> This WA on icl and above enables hardware to bypass alpha
> math and rounding for per pixel alpha values of 00 and 0xff
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
Thanks, pushed with my r-b. :)
>  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 4bfd7a9..6e59bfe 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7366,6 +7366,14 @@ enum {
>  #define BDW_SCRATCH1					_MMIO(0x
> b11c)
>  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
>  
> +/*GEN11 chicken */
> +#define _PIPEA_CHICKEN			0x70038
> +#define _PIPEB_CHICKEN			0x71038
> +#define _PIPEC_CHICKEN			0x72038
> +#define  PER_PIXEL_ALPHA_BYPASS_EN	(1<<7)
> +#define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe,
> _PIPEA_CHICKEN,\
> +						   _PIPEB_CHICKEN)
> +
>  /* PCH */
>  
>  /* south display engine interrupt: IBX */
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 2c8fef3..ca5882c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>  	struct intel_atomic_state *old_intel_state =
>  		to_intel_atomic_state(old_state);
>  	bool psl_clkgate_wa;
> +	u32 pipe_chicken;
>  
>  	if (WARN_ON(intel_crtc->active))
>  		return;
> @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
>  	 */
>  	intel_color_load_luts(&pipe_config->base);
>  
> +	/*
> +	 * Display WA #1153: enable hardware to bypass the alpha
> math
> +	 * and rounding for per-pixel values 00 and 0xff
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
> +		if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
> +			I915_WRITE_FW(PIPE_CHICKEN(pipe),
> +				  pipe_chicken |
> PER_PIXEL_ALPHA_BYPASS_EN);
> +	}
> +
>  	intel_ddi_set_pipe_settings(pipe_config);
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_ddi_enable_transcoder_func(pipe_config);

[-- Attachment #1.2: smime.p7s --]
[-- Type: application/x-pkcs7-signature, Size: 3282 bytes --]

[-- Attachment #2: Type: text/plain, Size: 160 bytes --]

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✓ Fi.CI.IGT: success for drm/i915: Enable hw workaround to bypass alpha

[Patchwork]

== Series Details ==

Series: drm/i915: Enable hw workaround to bypass alpha
URL   : https://patchwork.freedesktop.org/series/45173/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4359_full -> Patchwork_9383_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_9383_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      shard-apl:          PASS -> DMESG-FAIL (fdo#106560, fdo#106947)
      shard-glk:          PASS -> DMESG-FAIL (fdo#106560, fdo#106947)

    igt@gem_ctx_switch@basic-all-light:
      shard-hsw:          PASS -> INCOMPLETE (fdo#103540)

    igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
      shard-hsw:          PASS -> FAIL (fdo#103060)

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          PASS -> FAIL (fdo#104724)

    igt@kms_flip_tiling@flip-to-y-tiled:
      shard-glk:          PASS -> FAIL (fdo#103822, fdo#104724) +1

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_gtt:
      shard-kbl:          FAIL (fdo#105347) -> PASS

    igt@drv_selftest@live_hugepages:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    
  fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#104724 https://bugs.freedesktop.org/show_bug.cgi?id=104724
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4359 -> Patchwork_9383

  CI_DRM_4359: fe0300c16bff0f9c82050e56cdbc3880f87e39bd @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4527: 04afec3ccfcb35e994f2e78254ff499f6b94f097 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9383: 1c10ad664cb90e427538aa0b5c248ff1e28626c5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9383/shards.html
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Re: [PATCH] drm/i915: Enable hw workaround to bypass alpha

[Ville Syrjälä]

On Thu, Jun 21, 2018 at 07:00:15PM +0530, Vandita Kulkarni wrote:
> Alpha blending with alpha 0 and 0xff passes through
> alpha math and rounding logic causing differences
> compared to fully transparent or opaque plane,resulting
> in CRC mismatch.
> This WA on icl and above enables hardware to bypass alpha
> math and rounding for per pixel alpha values of 00 and 0xff
> 
> Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
>  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
>  2 files changed, 20 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4bfd7a9..6e59bfe 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -7366,6 +7366,14 @@ enum {
>  #define BDW_SCRATCH1					_MMIO(0xb11c)
>  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 << 2)
>  
> +/*GEN11 chicken */
> +#define _PIPEA_CHICKEN			0x70038
> +#define _PIPEB_CHICKEN			0x71038
> +#define _PIPEC_CHICKEN			0x72038
> +#define  PER_PIXEL_ALPHA_BYPASS_EN	(1<<7)
> +#define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe, _PIPEA_CHICKEN,\
> +						   _PIPEB_CHICKEN)
> +
>  /* PCH */
>  
>  /* south display engine interrupt: IBX */
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2c8fef3..ca5882c 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	struct intel_atomic_state *old_intel_state =
>  		to_intel_atomic_state(old_state);
>  	bool psl_clkgate_wa;
> +	u32 pipe_chicken;
>  
>  	if (WARN_ON(intel_crtc->active))
>  		return;
> @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct intel_crtc_state *pipe_config,
>  	 */
>  	intel_color_load_luts(&pipe_config->base);
>  
> +	/*
> +	 * Display WA #1153: enable hardware to bypass the alpha math
> +	 * and rounding for per-pixel values 00 and 0xff
> +	 */

This is an odd place for a register write. Why here instead of
init_clock_gating()?

> +	if (INTEL_GEN(dev_priv) >= 11) {
> +		pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
> +		if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
> +			I915_WRITE_FW(PIPE_CHICKEN(pipe),
> +				  pipe_chicken | PER_PIXEL_ALPHA_BYPASS_EN);

That check for the bit already being set is quite pointless.

> +	}
> +
>  	intel_ddi_set_pipe_settings(pipe_config);
>  	if (!transcoder_is_dsi(cpu_transcoder))
>  		intel_ddi_enable_transcoder_func(pipe_config);
> -- 
> 1.9.1
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/i915: Enable hw workaround to bypass alpha

[Kulkarni, Vandita]

> -----Original Message-----
> From: Ville Syrjälä [mailto:ville.syrjala@linux.intel.com]
> Sent: Friday, June 22, 2018 12:42 AM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Lankhorst, Maarten
> <maarten.lankhorst@intel.com>
> Subject: Re: [Intel-gfx] [PATCH] drm/i915: Enable hw workaround to bypass
> alpha
> 
> On Thu, Jun 21, 2018 at 07:00:15PM +0530, Vandita Kulkarni wrote:
> > Alpha blending with alpha 0 and 0xff passes through alpha math and
> > rounding logic causing differences compared to fully transparent or
> > opaque plane,resulting in CRC mismatch.
> > This WA on icl and above enables hardware to bypass alpha math and
> > rounding for per pixel alpha values of 00 and 0xff
> >
> > Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_reg.h      |  8 ++++++++
> >  drivers/gpu/drm/i915/intel_display.c | 12 ++++++++++++
> >  2 files changed, 20 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > b/drivers/gpu/drm/i915/i915_reg.h index 4bfd7a9..6e59bfe 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -7366,6 +7366,14 @@ enum {
> >  #define BDW_SCRATCH1
> 	_MMIO(0xb11c)
> >  #define  GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE	(1 <<
> 2)
> >
> > +/*GEN11 chicken */
> > +#define _PIPEA_CHICKEN			0x70038
> > +#define _PIPEB_CHICKEN			0x71038
> > +#define _PIPEC_CHICKEN			0x72038
> > +#define  PER_PIXEL_ALPHA_BYPASS_EN	(1<<7)
> > +#define PIPE_CHICKEN(pipe)		_MMIO_PIPE(pipe,
> _PIPEA_CHICKEN,\
> > +						   _PIPEB_CHICKEN)
> > +
> >  /* PCH */
> >
> >  /* south display engine interrupt: IBX */ diff --git
> > a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 2c8fef3..ca5882c 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -5632,6 +5632,7 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
> >  	struct intel_atomic_state *old_intel_state =
> >  		to_intel_atomic_state(old_state);
> >  	bool psl_clkgate_wa;
> > +	u32 pipe_chicken;
> >
> >  	if (WARN_ON(intel_crtc->active))
> >  		return;
> > @@ -5691,6 +5692,17 @@ static void haswell_crtc_enable(struct
> intel_crtc_state *pipe_config,
> >  	 */
> >  	intel_color_load_luts(&pipe_config->base);
> >
> > +	/*
> > +	 * Display WA #1153: enable hardware to bypass the alpha math
> > +	 * and rounding for per-pixel values 00 and 0xff
> > +	 */
> 
> This is an odd place for a register write. Why here instead of
> init_clock_gating()?

This reg is per pipe. The macro takes pipe num.
Also I am not sure if it is ok to write alpha related WA in init_clock_gating.
I couldn't find more appropriate place to add this. Hence I added it here.

> 
> > +	if (INTEL_GEN(dev_priv) >= 11) {
> > +		pipe_chicken = I915_READ(PIPE_CHICKEN(pipe));
> > +		if (!(pipe_chicken & PER_PIXEL_ALPHA_BYPASS_EN))
> > +			I915_WRITE_FW(PIPE_CHICKEN(pipe),
> > +				  pipe_chicken |
> PER_PIXEL_ALPHA_BYPASS_EN);
> 
> That check for the bit already being set is quite pointless.

Since we are not disabling it, not to write it again if enabled, this check is added.
> 
> > +	}
> > +
> >  	intel_ddi_set_pipe_settings(pipe_config);
> >  	if (!transcoder_is_dsi(cpu_transcoder))
> >  		intel_ddi_enable_transcoder_func(pipe_config);
> > --
> > 1.9.1
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> --
> Ville Syrjälä
> Intel
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