From: Miquel Raynal <miquel.raynal@bootlin.com> To: Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Marc Zyngier <marc.zyngier@arm.com>, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Andrew Lunn <andrew@lunn.ch>, Gregory Clement <gregory.clement@bootlin.com>, Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Mark Rutland <mark.rutland@arm.com>, devicetree@vger.kernel.org, Haim Boot <hayim@marvell.com>, Antoine Tenart <antoine.tenart@bootlin.com>, Hanna Hawa <hannah@marvell.com>, Maxime Chevallier <maxime.chevallier@bootlin.com>, Nadav Haklai <nadavh@marvell.com>, Rob Herring <robh+dt@kernel.org>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Miquel Raynal <miquel.raynal@bootlin.com>, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 00/17] Add System Error Interrupt support to Armada SoCs Date: Fri, 22 Jun 2018 17:14:15 +0200 [thread overview] Message-ID: <20180622151432.1566-1-miquel.raynal@bootlin.com> (raw) The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired inputs. Its purpose is to aggregate all CP interrupts and report them to the AP through MSIs. The ICU writes into GIC registers (AP side) by way of the interconnect. These interrupts can be of several groups: - SecuRe (SR); - Non-SecuRe (NSR); - System Error Interrupts (SEI); - RAM Error Interrupts (REI); - ... Each ICU wired interrupt can be of any of these groups. The group is encoded in the MSI payload. Until now, only the non-secure interrupts (NSR) were handled by the ICU driver. Interrupts of another group could work by chance because the ICU driver does not erase all ATF configuration; it only erases the configuration for NSR interrupts. This series aims at adding support for the System Error Interrupts (SEI). For this purpose, the ICU driver is a bit reworked to separate the ICU 'generic' configuration from the NSR-related handling. Then, the SEI driver (part of the GIC) is introduced and finally, support for SEI interrupts are also added to the ICU driver. The SEI driver is a bit different than its cousin the GICP because it must handle MSIs from the CPs, as well as wired interrupts from the AP itself. MSIs and wired interrupts will automatically update two registers (GICP_SECR0/GICP_SECR1) that will trigger a single top-level interrupt (SPI #32). As this is my first contribution in the IRQ subsystem I might have missed some specificities or misunderstood the API, please do not hesitate to correct me if I'm wrong. Also, for the sake of understandability (and because I love ASCII art), this is a try to explain the ICU/SEI architecture: +----------------------------------------------------------------------+ | | | | | SPIa SPIb SPIz SPI 32 | | ^ ^ ^ ^ | | | | . . . | | | | | | | | | | | | . . . | | | | +------------------------+ +---------------------------------+ | | | | | | | | | | | | | | | | | | SEI | | | | | | | . . . | | | ________|_______ | | | | | | | | | /___SEI_SECR_____\ | | | | |____|___________| | | / | \\ | | | | \_GICP_SETSPI _/ | | / | \\ | | | | || | | / ... | \\ | | | | GICP || | | | | \\ | | | +----------------||------+ +--|----------|------------||-----+ | | || | | || | | || | ... | || | | || | | || | | || | | || | | \\_______ int 0 ... int 20 // | | \_NSR__ \ // | | \\ ____________________// | | \\ /________SEI_________/ | | AP 806 \\// | | || | +---------------------------------||-----------------------------------+ || || Interconnect ||\ ||\\______ || \______ <---> Others CP 110 || +---------------------------------||-----------------------------------+ | || | | CP 110 || | | || | | +-------------------------||------------------------+ | | | || MSI | | | | ICU || | | | | /--------------/ \------\ | | | | / /-------/ \ | | | | / / / \ | | | | / / / . . . \ | | | | / / / \ | | | | NSR NSR SEI NSR | | | | | | | | | | | +----^-------^-------^-----------------^------------+ | | | | | | | | | | | . . . | | | | | | | | | int 0 int 1 int 2 int 206 | | | | | +----------------------------------------------------------------------+ Thank you, Miquèl Changes since v2: ================= * Rebased on top of v4.18-rc1 platform-msi: ------------- * New patch to allow using MSI tree domains. irqchip/irq-mvebu-sei: add new driver for Marvell SEI ------------------------------------------------------ * Updated commit message with Marc comments * Wrote two functions to fill ->irq_set_type() in the irq_chip structures, one accepting only rising edge interrupts (for MSI), another one accepting only high level interrupts (for wired IRQ). * Changed the spin lock protecting the allocated SEIs bitmap into a mutex. * Changed the bitmap allocation line to respect the actual number of MSIs instead of pretending having SEI_IRQ_COUNT (64) MSI available. * I did not split the code to have one function per domain because it would duplicate a _lot_ of code. Requested some advices instead. * Stopped using the fwnode when creating the AP (wired) IRQ domain. * Implemented the AP IRQ domain ->match() hook. * Used marvell,sei-xx-ranges properties to get the relevant IRQ numbers from DT. 'xx' is either 'ap' or 'cp'. irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) --------------------------------------------------------------------- * Added a patch to ease the creation of tree domains (changes in the core). * Changed the code accordingly to use tree domains. * Created a couple of helpers to do the bitmap allocation/release. * Removed the .offset_clr_a[hl] entries of the sei_subset_data structure to avoid confusion. These registers actually exist, but are not used here because the upper block (SEI) only supports edge-MSI and not level-MSI like the NSR one. dt-bindings/interrupt-controller: update Marvell ICU bindings -------------------------------------------------------------- * Explained better in the commit message that backward compatibility is not broken. * Changed subnodes names to be 'interrupt-controller' as requested. * Added a range associated to each sub-node (as well as in the DT). * Replaced spaces by tabs. * Merged the SEI's subnodes so that there is only one SEI node and no subnodes anymore. Changes since v1: ================= General ------- * Spelling/function names/comments. * Added Reviewed-by tags. * Rebased on top of Marc Zyngier level-MSI series (tip:irq/core). SEI --- * Change the license for GPL-2.0 only in irq-mvebu-sei.c C file. * Used alphabetic ordering when adding SEI driver in Makefile. * Re-ordered register definitions by increasing offset. * s/NB/COUNT/ in register definitions. * avoid enabling all interrupt by default. * fixed mask/unmask functions using the wrong hwirq number. * removed hackish doorbell mechanism. * Removed the ->xlate hook assigned for CP MSIs. * Used devm_*() helpers. * s/top_level_spi/parent_irq/ in probe. * Added forgotten of_node_put(child). * Reset the SEI registers before registering the IRQ domains. * Introduced new DT property "marvell,sei-ranges" instead of using "reg" to declare the range of MSI interrupts vs. wired interrupts in the SEI subnodes. * Finally did not change the ->alloc() about the fwspec->param[1] line (to be checked by Marc). ICU --- * Updated the ICU documentation so the legacy bindings are still documented somewhere. * Added stable tags on the commit fixing the CP110 ICU node size. * Removed the "syscon" compatible from the ICU node, instead the syscon is created at probe time. * s/user data/private data/ in the title of commit "irqchip/irq-mvebu-icu: fix wrong user data retrieval" Miquel Raynal (17): platform-msi: allow creation of MSI domain without interrupt number dt-bindings/interrupt-controller: fix Marvell ICU length in the example arm64: dts: marvell: fix CP110 ICU node size irqchip/irq-mvebu-icu: fix wrong private data retrieval irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts irqchip/irq-mvebu-icu: switch to regmap irqchip/irq-mvebu-icu: make irq_domain local irqchip/irq-mvebu-icu: disociate ICU and NSR irqchip/irq-mvebu-icu: support ICU subnodes irqchip/irq-mvebu-sei: add new driver for Marvell SEI arm64: marvell: enable SEI driver irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) dt-bindings/interrupt-controller: update Marvell ICU bindings dt-bindings/interrupt-controller: add documentation for Marvell SEI controller arm64: dts: marvell: add AP806 SEI subnode arm64: dts: marvell: use new bindings for CP110 interrupts arm64: dts: marvell: add CP110 ICU SEI subnode .../bindings/interrupt-controller/marvell,icu.txt | 85 +++- .../bindings/interrupt-controller/marvell,sei.txt | 39 ++ arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 11 + arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 127 +++--- drivers/base/platform-msi.c | 2 +- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mvebu-icu.c | 319 ++++++++++++--- drivers/irqchip/irq-mvebu-sei.c | 444 +++++++++++++++++++++ 10 files changed, 899 insertions(+), 133 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt create mode 100644 drivers/irqchip/irq-mvebu-sei.c -- 2.14.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
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From: miquel.raynal@bootlin.com (Miquel Raynal) To: linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 00/17] Add System Error Interrupt support to Armada SoCs Date: Fri, 22 Jun 2018 17:14:15 +0200 [thread overview] Message-ID: <20180622151432.1566-1-miquel.raynal@bootlin.com> (raw) The ICU is an IRQ chip found in Armada CP110. It currently has 207 wired inputs. Its purpose is to aggregate all CP interrupts and report them to the AP through MSIs. The ICU writes into GIC registers (AP side) by way of the interconnect. These interrupts can be of several groups: - SecuRe (SR); - Non-SecuRe (NSR); - System Error Interrupts (SEI); - RAM Error Interrupts (REI); - ... Each ICU wired interrupt can be of any of these groups. The group is encoded in the MSI payload. Until now, only the non-secure interrupts (NSR) were handled by the ICU driver. Interrupts of another group could work by chance because the ICU driver does not erase all ATF configuration; it only erases the configuration for NSR interrupts. This series aims at adding support for the System Error Interrupts (SEI). For this purpose, the ICU driver is a bit reworked to separate the ICU 'generic' configuration from the NSR-related handling. Then, the SEI driver (part of the GIC) is introduced and finally, support for SEI interrupts are also added to the ICU driver. The SEI driver is a bit different than its cousin the GICP because it must handle MSIs from the CPs, as well as wired interrupts from the AP itself. MSIs and wired interrupts will automatically update two registers (GICP_SECR0/GICP_SECR1) that will trigger a single top-level interrupt (SPI #32). As this is my first contribution in the IRQ subsystem I might have missed some specificities or misunderstood the API, please do not hesitate to correct me if I'm wrong. Also, for the sake of understandability (and because I love ASCII art), this is a try to explain the ICU/SEI architecture: +----------------------------------------------------------------------+ | | | | | SPIa SPIb SPIz SPI 32 | | ^ ^ ^ ^ | | | | . . . | | | | | | | | | | | | . . . | | | | +------------------------+ +---------------------------------+ | | | | | | | | | | | | | | | | | | SEI | | | | | | | . . . | | | ________|_______ | | | | | | | | | /___SEI_SECR_____\ | | | | |____|___________| | | / | \\ | | | | \_GICP_SETSPI _/ | | / | \\ | | | | || | | / ... | \\ | | | | GICP || | | | | \\ | | | +----------------||------+ +--|----------|------------||-----+ | | || | | || | | || | ... | || | | || | | || | | || | | || | | \\_______ int 0 ... int 20 // | | \_NSR__ \ // | | \\ ____________________// | | \\ /________SEI_________/ | | AP 806 \\// | | || | +---------------------------------||-----------------------------------+ || || Interconnect ||\ ||\\______ || \______ <---> Others CP 110 || +---------------------------------||-----------------------------------+ | || | | CP 110 || | | || | | +-------------------------||------------------------+ | | | || MSI | | | | ICU || | | | | /--------------/ \------\ | | | | / /-------/ \ | | | | / / / \ | | | | / / / . . . \ | | | | / / / \ | | | | NSR NSR SEI NSR | | | | | | | | | | | +----^-------^-------^-----------------^------------+ | | | | | | | | | | | . . . | | | | | | | | | int 0 int 1 int 2 int 206 | | | | | +----------------------------------------------------------------------+ Thank you, Miqu?l Changes since v2: ================= * Rebased on top of v4.18-rc1 platform-msi: ------------- * New patch to allow using MSI tree domains. irqchip/irq-mvebu-sei: add new driver for Marvell SEI ------------------------------------------------------ * Updated commit message with Marc comments * Wrote two functions to fill ->irq_set_type() in the irq_chip structures, one accepting only rising edge interrupts (for MSI), another one accepting only high level interrupts (for wired IRQ). * Changed the spin lock protecting the allocated SEIs bitmap into a mutex. * Changed the bitmap allocation line to respect the actual number of MSIs instead of pretending having SEI_IRQ_COUNT (64) MSI available. * I did not split the code to have one function per domain because it would duplicate a _lot_ of code. Requested some advices instead. * Stopped using the fwnode when creating the AP (wired) IRQ domain. * Implemented the AP IRQ domain ->match() hook. * Used marvell,sei-xx-ranges properties to get the relevant IRQ numbers from DT. 'xx' is either 'ap' or 'cp'. irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) --------------------------------------------------------------------- * Added a patch to ease the creation of tree domains (changes in the core). * Changed the code accordingly to use tree domains. * Created a couple of helpers to do the bitmap allocation/release. * Removed the .offset_clr_a[hl] entries of the sei_subset_data structure to avoid confusion. These registers actually exist, but are not used here because the upper block (SEI) only supports edge-MSI and not level-MSI like the NSR one. dt-bindings/interrupt-controller: update Marvell ICU bindings -------------------------------------------------------------- * Explained better in the commit message that backward compatibility is not broken. * Changed subnodes names to be 'interrupt-controller' as requested. * Added a range associated to each sub-node (as well as in the DT). * Replaced spaces by tabs. * Merged the SEI's subnodes so that there is only one SEI node and no subnodes anymore. Changes since v1: ================= General ------- * Spelling/function names/comments. * Added Reviewed-by tags. * Rebased on top of Marc Zyngier level-MSI series (tip:irq/core). SEI --- * Change the license for GPL-2.0 only in irq-mvebu-sei.c C file. * Used alphabetic ordering when adding SEI driver in Makefile. * Re-ordered register definitions by increasing offset. * s/NB/COUNT/ in register definitions. * avoid enabling all interrupt by default. * fixed mask/unmask functions using the wrong hwirq number. * removed hackish doorbell mechanism. * Removed the ->xlate hook assigned for CP MSIs. * Used devm_*() helpers. * s/top_level_spi/parent_irq/ in probe. * Added forgotten of_node_put(child). * Reset the SEI registers before registering the IRQ domains. * Introduced new DT property "marvell,sei-ranges" instead of using "reg" to declare the range of MSI interrupts vs. wired interrupts in the SEI subnodes. * Finally did not change the ->alloc() about the fwspec->param[1] line (to be checked by Marc). ICU --- * Updated the ICU documentation so the legacy bindings are still documented somewhere. * Added stable tags on the commit fixing the CP110 ICU node size. * Removed the "syscon" compatible from the ICU node, instead the syscon is created at probe time. * s/user data/private data/ in the title of commit "irqchip/irq-mvebu-icu: fix wrong user data retrieval" Miquel Raynal (17): platform-msi: allow creation of MSI domain without interrupt number dt-bindings/interrupt-controller: fix Marvell ICU length in the example arm64: dts: marvell: fix CP110 ICU node size irqchip/irq-mvebu-icu: fix wrong private data retrieval irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts irqchip/irq-mvebu-icu: switch to regmap irqchip/irq-mvebu-icu: make irq_domain local irqchip/irq-mvebu-icu: disociate ICU and NSR irqchip/irq-mvebu-icu: support ICU subnodes irqchip/irq-mvebu-sei: add new driver for Marvell SEI arm64: marvell: enable SEI driver irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) dt-bindings/interrupt-controller: update Marvell ICU bindings dt-bindings/interrupt-controller: add documentation for Marvell SEI controller arm64: dts: marvell: add AP806 SEI subnode arm64: dts: marvell: use new bindings for CP110 interrupts arm64: dts: marvell: add CP110 ICU SEI subnode .../bindings/interrupt-controller/marvell,icu.txt | 85 +++- .../bindings/interrupt-controller/marvell,sei.txt | 39 ++ arch/arm64/Kconfig.platforms | 1 + arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 11 + arch/arm64/boot/dts/marvell/armada-cp110.dtsi | 127 +++--- drivers/base/platform-msi.c | 2 +- drivers/irqchip/Kconfig | 3 + drivers/irqchip/Makefile | 1 + drivers/irqchip/irq-mvebu-icu.c | 319 ++++++++++++--- drivers/irqchip/irq-mvebu-sei.c | 444 +++++++++++++++++++++ 10 files changed, 899 insertions(+), 133 deletions(-) create mode 100644 Documentation/devicetree/bindings/interrupt-controller/marvell,sei.txt create mode 100644 drivers/irqchip/irq-mvebu-sei.c -- 2.14.1
next reply other threads:[~2018-06-22 15:14 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-06-22 15:14 Miquel Raynal [this message] 2018-06-22 15:14 ` [PATCH v3 00/17] Add System Error Interrupt support to Armada SoCs Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 01/17] platform-msi: allow creation of MSI domain without interrupt number Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 11:12 ` Marc Zyngier 2018-06-28 11:12 ` Marc Zyngier 2018-06-29 7:40 ` Miquel Raynal 2018-06-29 7:40 ` Miquel Raynal 2018-06-29 14:38 ` Marc Zyngier 2018-06-29 14:38 ` Marc Zyngier 2018-06-29 14:43 ` Miquel Raynal 2018-06-29 14:43 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 02/17] dt-bindings/interrupt-controller: fix Marvell ICU length in the example Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 03/17] arm64: dts: marvell: fix CP110 ICU node size Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-25 15:05 ` Gregory CLEMENT 2018-06-25 15:05 ` Gregory CLEMENT 2018-06-25 15:09 ` Miquel Raynal 2018-06-25 15:09 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 04/17] irqchip/irq-mvebu-icu: fix wrong private data retrieval Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 05/17] irqchip/irq-mvebu-icu: clarify the reset operation of configured interrupts Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 06/17] irqchip/irq-mvebu-icu: switch to regmap Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 12:05 ` Marc Zyngier 2018-06-28 12:05 ` Marc Zyngier 2018-06-29 15:27 ` Miquel Raynal 2018-06-29 15:27 ` Miquel Raynal 2018-06-29 17:17 ` Marc Zyngier 2018-06-29 17:17 ` Marc Zyngier 2018-06-29 18:20 ` Miquel Raynal 2018-06-29 18:20 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 07/17] irqchip/irq-mvebu-icu: make irq_domain local Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 12:10 ` Marc Zyngier 2018-06-28 12:10 ` Marc Zyngier 2018-06-29 12:32 ` Miquel Raynal 2018-06-29 12:32 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 08/17] irqchip/irq-mvebu-icu: disociate ICU and NSR Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 12:24 ` Marc Zyngier 2018-06-28 12:24 ` Marc Zyngier 2018-06-29 12:30 ` Miquel Raynal 2018-06-29 12:30 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 09/17] irqchip/irq-mvebu-icu: support ICU subnodes Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 12:45 ` Marc Zyngier 2018-06-28 12:45 ` Marc Zyngier 2018-06-29 12:34 ` Miquel Raynal 2018-06-29 12:34 ` Miquel Raynal 2018-07-04 9:09 ` Miquel Raynal 2018-07-04 9:09 ` Miquel Raynal 2018-07-04 12:43 ` Marc Zyngier 2018-07-04 12:43 ` Marc Zyngier 2018-07-04 15:16 ` Miquel Raynal 2018-07-04 15:16 ` Miquel Raynal 2018-07-05 8:19 ` Marc Zyngier 2018-07-05 8:19 ` Marc Zyngier 2018-06-22 15:14 ` [PATCH v3 10/17] irqchip/irq-mvebu-sei: add new driver for Marvell SEI Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 14:54 ` Marc Zyngier 2018-06-28 14:54 ` Marc Zyngier 2018-06-29 12:41 ` Miquel Raynal 2018-06-29 12:41 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 11/17] arm64: marvell: enable SEI driver Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 12/17] irqchip/irq-mvebu-icu: add support for System Error Interrupts (SEI) Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-28 16:49 ` Marc Zyngier 2018-06-28 16:49 ` Marc Zyngier 2018-06-28 17:12 ` Miquel Raynal 2018-06-28 17:12 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 13/17] dt-bindings/interrupt-controller: update Marvell ICU bindings Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 14/17] dt-bindings/interrupt-controller: add documentation for Marvell SEI controller Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 15/17] arm64: dts: marvell: add AP806 SEI subnode Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 16/17] arm64: dts: marvell: use new bindings for CP110 interrupts Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal 2018-06-22 15:14 ` [PATCH v3 17/17] arm64: dts: marvell: add CP110 ICU SEI subnode Miquel Raynal 2018-06-22 15:14 ` Miquel Raynal
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