* [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0
@ 2018-07-02 15:09 Stafford Horne
2018-07-02 15:09 ` [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
` (25 more replies)
0 siblings, 26 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:09 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Stafford Horne
Hi Peter,
Changes since v1:
- Un"fixed" an incorrect checkpatch warning pointed out by Richard.
Please consider for pull.
The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
are available in the Git repository at:
git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702
for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:
target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)
----------------------------------------------------------------
OpenRISC cleanups and Fixes for QEMU 3.0
Mostly patches from Richard Henderson fixing multiple things:
* Fix singlestepping in GDB.
* Use more TB linking.
* Fixes to exit TB after updating SPRs to enable registering of state
changes.
* Significant optimizations and refactors to the TLB
* Split out disassembly from translation.
* Add qemu-or1k to qemu-binfmt-conf.sh.
* Implement signal handling for linux-user.
Then there are a few fixups from me:
* Fix delay slot detections to match hardware, this was masking a bug
in the linus kernel.
* Fix stores to the PIC mask register
----------------------------------------------------------------
Richard Henderson (23):
target/openrisc: Fix mtspr shadow gprs
target/openrisc: Add print_insn_or1k
target/openrisc: Log interrupts
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
target/openrisc: Fix singlestep_enabled
target/openrisc: Link more translation blocks
target/openrisc: Split out is_user
target/openrisc: Exit the TB after l.mtspr
target/openrisc: Form the spr index from tcg
target/openrisc: Merge tlb allocation into CPUOpenRISCState
target/openrisc: Remove indirect function calls for mmu
target/openrisc: Merge mmu_helper.c into mmu.c
target/openrisc: Reduce tlb to a single dimension
target/openrisc: Fix tlb flushing in mtspr
target/openrisc: Fix cpu_mmu_index
target/openrisc: Use identical sizes for ITLB and DTLB
target/openrisc: Stub out handle_mmu_fault for softmmu
target/openrisc: Increase the TLB size
target/openrisc: Reorg tlb lookup
target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
linux-user: Implement signals for openrisc
linux-user: Fix struct sigaltstack for openrisc
Stafford Horne (2):
target/openrisc: Fix delay slot exception flag to match spec
target/openrisc: Fix writes to interrupt mask register
linux-user/openrisc/signal.c | 217 ++++++++-----------
linux-user/openrisc/target_signal.h | 2 +-
linux-user/openrisc/target_syscall.h | 28 +--
linux-user/signal.c | 2 +-
scripts/qemu-binfmt-conf.sh | 10 +-
target/openrisc/Makefile.objs | 5 +-
target/openrisc/cpu.c | 17 +-
target/openrisc/cpu.h | 61 +++---
target/openrisc/disas.c | 170 +++++++++++++++
target/openrisc/helper.h | 4 +-
target/openrisc/interrupt.c | 55 +++--
target/openrisc/interrupt_helper.c | 35 +---
target/openrisc/machine.c | 44 +---
target/openrisc/mmu.c | 279 +++++++++---------------
target/openrisc/mmu_helper.c | 40 ----
target/openrisc/sys_helper.c | 84 ++++----
target/openrisc/translate.c | 303 ++++++++++-----------------
17 files changed, 603 insertions(+), 753 deletions(-)
create mode 100644 target/openrisc/disas.c
delete mode 100644 target/openrisc/mmu_helper.c
--
2.17.0
^ permalink raw reply [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
@ 2018-07-02 15:09 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 02/25] target/openrisc: Add print_insn_or1k Stafford Horne
` (24 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:09 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
Missing break when this feature was added in 89e71e873d
("target/openrisc: implement shadow registers"). This was causing
strange issues as we get writes into the translation block jump cache
and other bits of state.
Fixes: 89e71e873d ("target/openrisc: implement shadow registers")
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/sys_helper.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index b284064381..2f337363ec 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -98,6 +98,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
case TO_SPR(0, 1024) ... TO_SPR(0, 1024 + (16 * 32)): /* Shadow GPRs */
idx = (spr - 1024);
env->shadow_gpr[idx / 32][idx % 32] = rb;
+ break;
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 02/25] target/openrisc: Add print_insn_or1k
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 15:09 ` [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 03/25] target/openrisc: Log interrupts Stafford Horne
` (23 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
Rather than emit disassembly while translating, reuse the
generated decoder to build a separate disassembler.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/Makefile.objs | 3 +-
target/openrisc/cpu.c | 6 ++
target/openrisc/cpu.h | 1 +
target/openrisc/disas.c | 170 ++++++++++++++++++++++++++++++++++
target/openrisc/translate.c | 114 -----------------------
5 files changed, 179 insertions(+), 115 deletions(-)
create mode 100644 target/openrisc/disas.c
diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index 1b98a911ea..8b8a890c59 100644
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -1,5 +1,5 @@
obj-$(CONFIG_SOFTMMU) += machine.o
-obj-y += cpu.o exception.o interrupt.o mmu.o translate.o
+obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o
obj-y += exception_helper.o fpu_helper.o \
interrupt_helper.o mmu_helper.o sys_helper.o
obj-y += gdbstub.o
@@ -12,3 +12,4 @@ target/openrisc/decode.inc.c: \
$(PYTHON) $(DECODETREE) -o $@ $<, "GEN", $(TARGET_DIR)$@)
target/openrisc/translate.o: target/openrisc/decode.inc.c
+target/openrisc/disas.o: target/openrisc/decode.inc.c
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index a692a98ec0..fa8e342ff7 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -35,6 +35,11 @@ static bool openrisc_cpu_has_work(CPUState *cs)
CPU_INTERRUPT_TIMER);
}
+static void openrisc_disas_set_info(CPUState *cpu, disassemble_info *info)
+{
+ info->print_insn = print_insn_or1k;
+}
+
/* CPUClass::reset() */
static void openrisc_cpu_reset(CPUState *s)
{
@@ -152,6 +157,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data)
#endif
cc->gdb_num_core_regs = 32 + 3;
cc->tcg_initialize = openrisc_translate_init;
+ cc->disas_set_info = openrisc_disas_set_info;
}
/* Sort alphabetically by type name, except for "any". */
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 35cab65f11..c871d6bfe1 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -358,6 +358,7 @@ void openrisc_translate_init(void);
int openrisc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size,
int rw, int mmu_idx);
int cpu_openrisc_signal_handler(int host_signum, void *pinfo, void *puc);
+int print_insn_or1k(bfd_vma addr, disassemble_info *info);
#define cpu_list cpu_openrisc_list
#define cpu_signal_handler cpu_openrisc_signal_handler
diff --git a/target/openrisc/disas.c b/target/openrisc/disas.c
new file mode 100644
index 0000000000..4bfd2dd8a6
--- /dev/null
+++ b/target/openrisc/disas.c
@@ -0,0 +1,170 @@
+/*
+ * OpenRISC disassembler
+ *
+ * Copyright (c) 2018 Richard Henderson <rth@twiddle.net>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu-common.h"
+#include "disas/bfd.h"
+#include "qemu/bitops.h"
+#include "cpu.h"
+
+typedef disassemble_info DisasContext;
+
+/* Include the auto-generated decoder. */
+#include "decode.inc.c"
+
+#define output(mnemonic, format, ...) \
+ (info->fprintf_func(info->stream, "%-9s " format, \
+ mnemonic, ##__VA_ARGS__))
+
+int print_insn_or1k(bfd_vma addr, disassemble_info *info)
+{
+ bfd_byte buffer[4];
+ uint32_t insn;
+ int status;
+
+ status = info->read_memory_func(addr, buffer, 4, info);
+ if (status != 0) {
+ info->memory_error_func(status, addr, info);
+ return -1;
+ }
+ insn = bfd_getb32(buffer);
+
+ if (!decode(info, insn)) {
+ output(".long", "%#08x", insn);
+ }
+ return 4;
+}
+
+#define INSN(opcode, format, ...) \
+static bool trans_l_##opcode(disassemble_info *info, \
+ arg_l_##opcode *a, uint32_t insn) \
+{ \
+ output("l." #opcode, format, ##__VA_ARGS__); \
+ return true; \
+}
+
+INSN(add, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(addc, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(sub, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(and, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(or, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(xor, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(sll, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(srl, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(sra, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(ror, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(exths, "r%d, r%d", a->d, a->a)
+INSN(extbs, "r%d, r%d", a->d, a->a)
+INSN(exthz, "r%d, r%d", a->d, a->a)
+INSN(extbz, "r%d, r%d", a->d, a->a)
+INSN(cmov, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(ff1, "r%d, r%d", a->d, a->a)
+INSN(fl1, "r%d, r%d", a->d, a->a)
+INSN(mul, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(mulu, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(div, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(divu, "r%d, r%d, r%d", a->d, a->a, a->b)
+INSN(muld, "r%d, r%d", a->a, a->b)
+INSN(muldu, "r%d, r%d", a->a, a->b)
+INSN(j, "%d", a->n)
+INSN(jal, "%d", a->n)
+INSN(bf, "%d", a->n)
+INSN(bnf, "%d", a->n)
+INSN(jr, "r%d", a->b)
+INSN(jalr, "r%d", a->b)
+INSN(lwa, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lwz, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lws, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lbz, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lbs, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lhz, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(lhs, "r%d, %d(r%d)", a->d, a->i, a->a)
+INSN(swa, "%d(r%d), r%d", a->i, a->a, a->b)
+INSN(sw, "%d(r%d), r%d", a->i, a->a, a->b)
+INSN(sb, "%d(r%d), r%d", a->i, a->a, a->b)
+INSN(sh, "%d(r%d), r%d", a->i, a->a, a->b)
+INSN(nop, "")
+INSN(addi, "r%d, r%d, %d", a->d, a->a, a->i)
+INSN(addic, "r%d, r%d, %d", a->d, a->a, a->i)
+INSN(muli, "r%d, r%d, %d", a->d, a->a, a->i)
+INSN(maci, "r%d, %d", a->a, a->i)
+INSN(andi, "r%d, r%d, %d", a->d, a->a, a->k)
+INSN(ori, "r%d, r%d, %d", a->d, a->a, a->k)
+INSN(xori, "r%d, r%d, %d", a->d, a->a, a->i)
+INSN(mfspr, "r%d, r%d, %d", a->d, a->a, a->k)
+INSN(mtspr, "r%d, r%d, %d", a->a, a->b, a->k)
+INSN(mac, "r%d, r%d", a->a, a->b)
+INSN(msb, "r%d, r%d", a->a, a->b)
+INSN(macu, "r%d, r%d", a->a, a->b)
+INSN(msbu, "r%d, r%d", a->a, a->b)
+INSN(slli, "r%d, r%d, %d", a->d, a->a, a->l)
+INSN(srli, "r%d, r%d, %d", a->d, a->a, a->l)
+INSN(srai, "r%d, r%d, %d", a->d, a->a, a->l)
+INSN(rori, "r%d, r%d, %d", a->d, a->a, a->l)
+INSN(movhi, "r%d, %d", a->d, a->k)
+INSN(macrc, "r%d", a->d)
+INSN(sfeq, "r%d, r%d", a->a, a->b)
+INSN(sfne, "r%d, r%d", a->a, a->b)
+INSN(sfgtu, "r%d, r%d", a->a, a->b)
+INSN(sfgeu, "r%d, r%d", a->a, a->b)
+INSN(sfltu, "r%d, r%d", a->a, a->b)
+INSN(sfleu, "r%d, r%d", a->a, a->b)
+INSN(sfgts, "r%d, r%d", a->a, a->b)
+INSN(sfges, "r%d, r%d", a->a, a->b)
+INSN(sflts, "r%d, r%d", a->a, a->b)
+INSN(sfles, "r%d, r%d", a->a, a->b)
+INSN(sfeqi, "r%d, %d", a->a, a->i)
+INSN(sfnei, "r%d, %d", a->a, a->i)
+INSN(sfgtui, "r%d, %d", a->a, a->i)
+INSN(sfgeui, "r%d, %d", a->a, a->i)
+INSN(sfltui, "r%d, %d", a->a, a->i)
+INSN(sfleui, "r%d, %d", a->a, a->i)
+INSN(sfgtsi, "r%d, %d", a->a, a->i)
+INSN(sfgesi, "r%d, %d", a->a, a->i)
+INSN(sfltsi, "r%d, %d", a->a, a->i)
+INSN(sflesi, "r%d, %d", a->a, a->i)
+INSN(sys, "%d", a->k)
+INSN(trap, "%d", a->k)
+INSN(msync, "")
+INSN(psync, "")
+INSN(csync, "")
+INSN(rfe, "")
+
+#define FP_INSN(opcode, suffix, format, ...) \
+static bool trans_lf_##opcode##_##suffix(disassemble_info *info, \
+ arg_lf_##opcode##_##suffix *a, uint32_t insn) \
+{ \
+ output("lf." #opcode "." #suffix, format, ##__VA_ARGS__); \
+ return true; \
+}
+
+FP_INSN(add, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(sub, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(mul, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(div, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(rem, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(itof, s, "r%d, r%d", a->d, a->a)
+FP_INSN(ftoi, s, "r%d, r%d", a->d, a->a)
+FP_INSN(madd, s, "r%d, r%d, r%d", a->d, a->a, a->b)
+FP_INSN(sfeq, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfne, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfgt, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfge, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sflt, s, "r%d, r%d", a->a, a->b)
+FP_INSN(sfle, s, "r%d, r%d", a->a, a->b)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index d69f8d0422..fbdc2058dc 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -36,10 +36,6 @@
#include "trace-tcg.h"
#include "exec/log.h"
-#define LOG_DIS(str, ...) \
- qemu_log_mask(CPU_LOG_TB_IN_ASM, "%08x: " str, dc->base.pc_next, \
- ## __VA_ARGS__)
-
/* is_jmp field values */
#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
@@ -457,7 +453,6 @@ static void gen_msbu(DisasContext *dc, TCGv srca, TCGv srcb)
static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.add r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
gen_add(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -465,7 +460,6 @@ static bool trans_l_add(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.addc r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
gen_addc(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -473,7 +467,6 @@ static bool trans_l_addc(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.sub r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
gen_sub(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -481,7 +474,6 @@ static bool trans_l_sub(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.and r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_and_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -489,7 +481,6 @@ static bool trans_l_and(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.or r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_or_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -497,7 +488,6 @@ static bool trans_l_or(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.xor r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_xor_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -505,7 +495,6 @@ static bool trans_l_xor(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.sll r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_shl_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -513,7 +502,6 @@ static bool trans_l_sll(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.srl r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_shr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -521,7 +509,6 @@ static bool trans_l_srl(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.sra r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_sar_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -529,7 +516,6 @@ static bool trans_l_sra(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.ror r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
tcg_gen_rotr_tl(cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -537,7 +523,6 @@ static bool trans_l_ror(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.exths r%d, r%d\n", a->d, a->a);
check_r0_write(a->d);
tcg_gen_ext16s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
@@ -545,7 +530,6 @@ static bool trans_l_exths(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.extbs r%d, r%d\n", a->d, a->a);
check_r0_write(a->d);
tcg_gen_ext8s_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
@@ -553,7 +537,6 @@ static bool trans_l_extbs(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.exthz r%d, r%d\n", a->d, a->a);
check_r0_write(a->d);
tcg_gen_ext16u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
@@ -561,7 +544,6 @@ static bool trans_l_exthz(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.extbz r%d, r%d\n", a->d, a->a);
check_r0_write(a->d);
tcg_gen_ext8u_tl(cpu_R[a->d], cpu_R[a->a]);
return true;
@@ -570,7 +552,6 @@ static bool trans_l_extbz(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn)
{
TCGv zero;
- LOG_DIS("l.cmov r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
zero = tcg_const_tl(0);
@@ -582,8 +563,6 @@ static bool trans_l_cmov(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.ff1 r%d, r%d\n", a->d, a->a);
-
check_r0_write(a->d);
tcg_gen_ctzi_tl(cpu_R[a->d], cpu_R[a->a], -1);
tcg_gen_addi_tl(cpu_R[a->d], cpu_R[a->d], 1);
@@ -592,8 +571,6 @@ static bool trans_l_ff1(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("l.fl1 r%d, r%d\n", a->d, a->a);
-
check_r0_write(a->d);
tcg_gen_clzi_tl(cpu_R[a->d], cpu_R[a->a], TARGET_LONG_BITS);
tcg_gen_subfi_tl(cpu_R[a->d], TARGET_LONG_BITS, cpu_R[a->d]);
@@ -602,8 +579,6 @@ static bool trans_l_fl1(DisasContext *dc, arg_da *a, uint32_t insn)
static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.mul r%d, r%d, r%d\n", a->d, a->a, a->b);
-
check_r0_write(a->d);
gen_mul(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -611,8 +586,6 @@ static bool trans_l_mul(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.mulu r%d, r%d, r%d\n", a->d, a->a, a->b);
-
check_r0_write(a->d);
gen_mulu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -620,8 +593,6 @@ static bool trans_l_mulu(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.div r%d, r%d, r%d\n", a->d, a->a, a->b);
-
check_r0_write(a->d);
gen_div(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -629,8 +600,6 @@ static bool trans_l_div(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("l.divu r%d, r%d, r%d\n", a->d, a->a, a->b);
-
check_r0_write(a->d);
gen_divu(dc, cpu_R[a->d], cpu_R[a->a], cpu_R[a->b]);
return true;
@@ -638,14 +607,12 @@ static bool trans_l_divu(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_l_muld(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.muld r%d, r%d\n", a->a, a->b);
gen_muld(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_muldu(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.muldu r%d, r%d\n", a->a, a->b);
gen_muldu(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
@@ -654,7 +621,6 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn)
{
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
- LOG_DIS("l.j %d\n", a->n);
tcg_gen_movi_tl(jmp_pc, tmp_pc);
dc->delayed_branch = 2;
return true;
@@ -665,7 +631,6 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn)
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
target_ulong ret_pc = dc->base.pc_next + 8;
- LOG_DIS("l.jal %d\n", a->n);
tcg_gen_movi_tl(cpu_R[9], ret_pc);
/* Optimize jal being used to load the PC for PIC. */
if (tmp_pc != ret_pc) {
@@ -692,21 +657,18 @@ static void do_bf(DisasContext *dc, arg_l_bf *a, TCGCond cond)
static bool trans_l_bf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
{
- LOG_DIS("l.bf %d\n", a->n);
do_bf(dc, a, TCG_COND_NE);
return true;
}
static bool trans_l_bnf(DisasContext *dc, arg_l_bf *a, uint32_t insn)
{
- LOG_DIS("l.bnf %d\n", a->n);
do_bf(dc, a, TCG_COND_EQ);
return true;
}
static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn)
{
- LOG_DIS("l.jr r%d\n", a->b);
tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
dc->delayed_branch = 2;
return true;
@@ -714,7 +676,6 @@ static bool trans_l_jr(DisasContext *dc, arg_l_jr *a, uint32_t insn)
static bool trans_l_jalr(DisasContext *dc, arg_l_jalr *a, uint32_t insn)
{
- LOG_DIS("l.jalr r%d\n", a->b);
tcg_gen_mov_tl(jmp_pc, cpu_R[a->b]);
tcg_gen_movi_tl(cpu_R[9], dc->base.pc_next + 8);
dc->delayed_branch = 2;
@@ -725,8 +686,6 @@ static bool trans_l_lwa(DisasContext *dc, arg_load *a, uint32_t insn)
{
TCGv ea;
- LOG_DIS("l.lwa r%d, r%d, %d\n", a->d, a->a, a->i);
-
check_r0_write(a->d);
ea = tcg_temp_new();
tcg_gen_addi_tl(ea, cpu_R[a->a], a->i);
@@ -750,42 +709,36 @@ static void do_load(DisasContext *dc, arg_load *a, TCGMemOp mop)
static bool trans_l_lwz(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lwz r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_TEUL);
return true;
}
static bool trans_l_lws(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lws r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_TESL);
return true;
}
static bool trans_l_lbz(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lbz r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_UB);
return true;
}
static bool trans_l_lbs(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lbs r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_SB);
return true;
}
static bool trans_l_lhz(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lhz r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_TEUW);
return true;
}
static bool trans_l_lhs(DisasContext *dc, arg_load *a, uint32_t insn)
{
- LOG_DIS("l.lhs r%d, r%d, %d\n", a->d, a->a, a->i);
do_load(dc, a, MO_TESW);
return true;
}
@@ -795,8 +748,6 @@ static bool trans_l_swa(DisasContext *dc, arg_store *a, uint32_t insn)
TCGv ea, val;
TCGLabel *lab_fail, *lab_done;
- LOG_DIS("l.swa r%d, r%d, %d\n", a->a, a->b, a->i);
-
ea = tcg_temp_new();
tcg_gen_addi_tl(ea, cpu_R[a->a], a->i);
@@ -837,28 +788,24 @@ static void do_store(DisasContext *dc, arg_store *a, TCGMemOp mop)
static bool trans_l_sw(DisasContext *dc, arg_store *a, uint32_t insn)
{
- LOG_DIS("l.sw r%d, r%d, %d\n", a->a, a->b, a->i);
do_store(dc, a, MO_TEUL);
return true;
}
static bool trans_l_sb(DisasContext *dc, arg_store *a, uint32_t insn)
{
- LOG_DIS("l.sb r%d, r%d, %d\n", a->a, a->b, a->i);
do_store(dc, a, MO_UB);
return true;
}
static bool trans_l_sh(DisasContext *dc, arg_store *a, uint32_t insn)
{
- LOG_DIS("l.sh r%d, r%d, %d\n", a->a, a->b, a->i);
do_store(dc, a, MO_TEUW);
return true;
}
static bool trans_l_nop(DisasContext *dc, arg_l_nop *a, uint32_t insn)
{
- LOG_DIS("l.nop %d\n", a->k);
return true;
}
@@ -866,7 +813,6 @@ static bool trans_l_addi(DisasContext *dc, arg_rri *a, uint32_t insn)
{
TCGv t0;
- LOG_DIS("l.addi r%d, r%d, %d\n", a->d, a->a, a->i);
check_r0_write(a->d);
t0 = tcg_const_tl(a->i);
gen_add(dc, cpu_R[a->d], cpu_R[a->a], t0);
@@ -878,7 +824,6 @@ static bool trans_l_addic(DisasContext *dc, arg_rri *a, uint32_t insn)
{
TCGv t0;
- LOG_DIS("l.addic r%d, r%d, %d\n", a->d, a->a, a->i);
check_r0_write(a->d);
t0 = tcg_const_tl(a->i);
gen_addc(dc, cpu_R[a->d], cpu_R[a->a], t0);
@@ -890,7 +835,6 @@ static bool trans_l_muli(DisasContext *dc, arg_rri *a, uint32_t insn)
{
TCGv t0;
- LOG_DIS("l.muli r%d, r%d, %d\n", a->d, a->a, a->i);
check_r0_write(a->d);
t0 = tcg_const_tl(a->i);
gen_mul(dc, cpu_R[a->d], cpu_R[a->a], t0);
@@ -902,7 +846,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn)
{
TCGv t0;
- LOG_DIS("l.maci r%d, %d\n", a->a, a->i);
t0 = tcg_const_tl(a->i);
gen_mac(dc, cpu_R[a->a], t0);
tcg_temp_free(t0);
@@ -911,7 +854,6 @@ static bool trans_l_maci(DisasContext *dc, arg_l_maci *a, uint32_t insn)
static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn)
{
- LOG_DIS("l.andi r%d, r%d, %d\n", a->d, a->a, a->k);
check_r0_write(a->d);
tcg_gen_andi_tl(cpu_R[a->d], cpu_R[a->a], a->k);
return true;
@@ -919,7 +861,6 @@ static bool trans_l_andi(DisasContext *dc, arg_rrk *a, uint32_t insn)
static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn)
{
- LOG_DIS("l.ori r%d, r%d, %d\n", a->d, a->a, a->k);
check_r0_write(a->d);
tcg_gen_ori_tl(cpu_R[a->d], cpu_R[a->a], a->k);
return true;
@@ -927,7 +868,6 @@ static bool trans_l_ori(DisasContext *dc, arg_rrk *a, uint32_t insn)
static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn)
{
- LOG_DIS("l.xori r%d, r%d, %d\n", a->d, a->a, a->i);
check_r0_write(a->d);
tcg_gen_xori_tl(cpu_R[a->d], cpu_R[a->a], a->i);
return true;
@@ -935,7 +875,6 @@ static bool trans_l_xori(DisasContext *dc, arg_rri *a, uint32_t insn)
static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
{
- LOG_DIS("l.mfspr r%d, r%d, %d\n", a->d, a->a, a->k);
check_r0_write(a->d);
#ifdef CONFIG_USER_ONLY
@@ -954,8 +893,6 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
{
- LOG_DIS("l.mtspr r%d, r%d, %d\n", a->a, a->b, a->k);
-
#ifdef CONFIG_USER_ONLY
gen_illegal_exception(dc);
#else
@@ -972,35 +909,30 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
static bool trans_l_mac(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
gen_mac(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_msb(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
gen_msb(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_macu(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.mac r%d, r%d\n", a->a, a->b);
gen_macu(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_msbu(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("l.msb r%d, r%d\n", a->a, a->b);
gen_msbu(dc, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
{
- LOG_DIS("l.slli r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_shli_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
@@ -1008,7 +940,6 @@ static bool trans_l_slli(DisasContext *dc, arg_dal *a, uint32_t insn)
static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
{
- LOG_DIS("l.srli r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_shri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
@@ -1016,7 +947,6 @@ static bool trans_l_srli(DisasContext *dc, arg_dal *a, uint32_t insn)
static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
{
- LOG_DIS("l.srai r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_sari_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
@@ -1024,7 +954,6 @@ static bool trans_l_srai(DisasContext *dc, arg_dal *a, uint32_t insn)
static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
{
- LOG_DIS("l.rori r%d, r%d, %d\n", a->d, a->a, a->l);
check_r0_write(a->d);
tcg_gen_rotri_tl(cpu_R[a->d], cpu_R[a->a], a->l & (TARGET_LONG_BITS - 1));
return true;
@@ -1032,7 +961,6 @@ static bool trans_l_rori(DisasContext *dc, arg_dal *a, uint32_t insn)
static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
{
- LOG_DIS("l.movhi r%d, %d\n", a->d, a->k);
check_r0_write(a->d);
tcg_gen_movi_tl(cpu_R[a->d], a->k << 16);
return true;
@@ -1040,7 +968,6 @@ static bool trans_l_movhi(DisasContext *dc, arg_l_movhi *a, uint32_t insn)
static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
{
- LOG_DIS("l.macrc r%d\n", a->d);
check_r0_write(a->d);
tcg_gen_trunc_i64_tl(cpu_R[a->d], cpu_mac);
tcg_gen_movi_i64(cpu_mac, 0);
@@ -1049,147 +976,126 @@ static bool trans_l_macrc(DisasContext *dc, arg_l_macrc *a, uint32_t insn)
static bool trans_l_sfeq(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfeq r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfne(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfne r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfgtu(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfgtu r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfgeu(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfgeu r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfltu(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfltu r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfleu(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfleu r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfgts(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfgts r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfges(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfges r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sflts(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sflts r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfles(DisasContext *dc, arg_ab *a, TCGCond cond)
{
- LOG_DIS("l.sfles r%d, r%d\n", a->a, a->b);
tcg_gen_setcond_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], cpu_R[a->b]);
return true;
}
static bool trans_l_sfeqi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfeqi r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_EQ, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfnei(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfnei r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_NE, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfgtui(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfgtui r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_GTU, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfgeui(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfgeui r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_GEU, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfltui(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfltui r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfleui(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfleui r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_LEU, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfgtsi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfgtsi r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_GT, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfgesi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfgesi r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_GE, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sfltsi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sfltsi r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_LT, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sflesi(DisasContext *dc, arg_ai *a, TCGCond cond)
{
- LOG_DIS("l.sflesi r%d, %d\n", a->a, a->i);
tcg_gen_setcondi_tl(TCG_COND_LE, cpu_sr_f, cpu_R[a->a], a->i);
return true;
}
static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
{
- LOG_DIS("l.sys %d\n", a->k);
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_SYSCALL);
dc->base.is_jmp = DISAS_NORETURN;
@@ -1198,7 +1104,6 @@ static bool trans_l_sys(DisasContext *dc, arg_l_sys *a, uint32_t insn)
static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)
{
- LOG_DIS("l.trap %d\n", a->k);
tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
gen_exception(dc, EXCP_TRAP);
dc->base.is_jmp = DISAS_NORETURN;
@@ -1207,27 +1112,22 @@ static bool trans_l_trap(DisasContext *dc, arg_l_trap *a, uint32_t insn)
static bool trans_l_msync(DisasContext *dc, arg_l_msync *a, uint32_t insn)
{
- LOG_DIS("l.msync\n");
tcg_gen_mb(TCG_MO_ALL);
return true;
}
static bool trans_l_psync(DisasContext *dc, arg_l_psync *a, uint32_t insn)
{
- LOG_DIS("l.psync\n");
return true;
}
static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)
{
- LOG_DIS("l.csync\n");
return true;
}
static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
{
- LOG_DIS("l.rfe\n");
-
#ifdef CONFIG_USER_ONLY
gen_illegal_exception(dc);
#else
@@ -1274,56 +1174,48 @@ static void do_fpcmp(DisasContext *dc, arg_ab *a,
static bool trans_lf_add_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.add.s r%d, r%d, r%d\n", a->d, a->a, a->b);
do_fp3(dc, a, gen_helper_float_add_s);
return true;
}
static bool trans_lf_sub_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.sub.s r%d, r%d, r%d\n", a->d, a->a, a->b);
do_fp3(dc, a, gen_helper_float_sub_s);
return true;
}
static bool trans_lf_mul_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.mul.s r%d, r%d, r%d\n", a->d, a->a, a->b);
do_fp3(dc, a, gen_helper_float_mul_s);
return true;
}
static bool trans_lf_div_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.div.s r%d, r%d, r%d\n", a->d, a->a, a->b);
do_fp3(dc, a, gen_helper_float_div_s);
return true;
}
static bool trans_lf_rem_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.rem.s r%d, r%d, r%d\n", a->d, a->a, a->b);
do_fp3(dc, a, gen_helper_float_rem_s);
return true;
}
static bool trans_lf_itof_s(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("lf.itof.s r%d, r%d\n", a->d, a->a);
do_fp2(dc, a, gen_helper_itofs);
return true;
}
static bool trans_lf_ftoi_s(DisasContext *dc, arg_da *a, uint32_t insn)
{
- LOG_DIS("lf.ftoi.s r%d, r%d\n", a->d, a->a);
do_fp2(dc, a, gen_helper_ftois);
return true;
}
static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn)
{
- LOG_DIS("lf.madd.s r%d, r%d, r%d\n", a->d, a->a, a->b);
check_r0_write(a->d);
gen_helper_float_madd_s(cpu_R[a->d], cpu_env, cpu_R[a->d],
cpu_R[a->a], cpu_R[a->b]);
@@ -1333,42 +1225,36 @@ static bool trans_lf_madd_s(DisasContext *dc, arg_dab *a, uint32_t insn)
static bool trans_lf_sfeq_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sfeq.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_eq_s, false, false);
return true;
}
static bool trans_lf_sfne_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sfne.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_eq_s, true, false);
return true;
}
static bool trans_lf_sfgt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sfgt.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_lt_s, false, true);
return true;
}
static bool trans_lf_sfge_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sfge.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_le_s, false, true);
return true;
}
static bool trans_lf_sflt_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sflt.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_lt_s, false, false);
return true;
}
static bool trans_lf_sfle_s(DisasContext *dc, arg_ab *a, uint32_t insn)
{
- LOG_DIS("lf.sfle.s r%d, r%d\n", a->a, a->b);
do_fpcmp(dc, a, gen_helper_float_le_s, false, false);
return true;
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 03/25] target/openrisc: Log interrupts
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 15:09 ` [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 02/25] target/openrisc: Add print_insn_or1k Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Stafford Horne
` (22 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 30 +++++++++++++++++++++++++-----
1 file changed, 25 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 3959671c59..25351d5de3 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -32,6 +32,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
CPUOpenRISCState *env = &cpu->env;
+ int exception = cs->exception_index;
env->epcr = env->pc;
if (env->dflag) {
@@ -41,12 +42,12 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
} else {
env->sr &= ~SR_DSX;
}
- if (cs->exception_index == EXCP_SYSCALL) {
+ if (exception == EXCP_SYSCALL) {
env->epcr += 4;
}
/* When we have an illegal instruction the error effective address
shall be set to the illegal instruction address. */
- if (cs->exception_index == EXCP_ILLEGAL) {
+ if (exception == EXCP_ILLEGAL) {
env->eear = env->pc;
}
@@ -66,8 +67,27 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
- if (cs->exception_index > 0 && cs->exception_index < EXCP_NR) {
- hwaddr vect_pc = cs->exception_index << 8;
+ if (exception > 0 && exception < EXCP_NR) {
+ static const char * const int_name[EXCP_NR] = {
+ [EXCP_RESET] = "RESET",
+ [EXCP_BUSERR] = "BUSERR (bus error)",
+ [EXCP_DPF] = "DFP (data protection fault)",
+ [EXCP_IPF] = "IPF (code protection fault)",
+ [EXCP_TICK] = "TICK (timer interrupt)",
+ [EXCP_ALIGN] = "ALIGN",
+ [EXCP_ILLEGAL] = "ILLEGAL",
+ [EXCP_INT] = "INT (device interrupt)",
+ [EXCP_DTLBMISS] = "DTLBMISS (data tlb miss)",
+ [EXCP_ITLBMISS] = "ITLBMISS (code tlb miss)",
+ [EXCP_RANGE] = "RANGE",
+ [EXCP_SYSCALL] = "SYSCALL",
+ [EXCP_FPE] = "FPE",
+ [EXCP_TRAP] = "TRAP",
+ };
+
+ qemu_log_mask(CPU_LOG_INT, "INT: %s\n", int_name[exception]);
+
+ hwaddr vect_pc = exception << 8;
if (env->cpucfgr & CPUCFGR_EVBARP) {
vect_pc |= env->evbar;
}
@@ -76,7 +96,7 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
}
env->pc = vect_pc;
} else {
- cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
+ cpu_abort(cs, "Unhandled exception 0x%x\n", exception);
}
#endif
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (2 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 03/25] target/openrisc: Log interrupts Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Stafford Horne
` (21 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
These values are unused.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/translate.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index fbdc2058dc..f5af515979 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -37,9 +37,7 @@
#include "exec/log.h"
/* is_jmp field values */
-#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
-#define DISAS_TB_JUMP DISAS_TARGET_2 /* only pc was modified statically */
typedef struct DisasContext {
DisasContextBase base;
@@ -1353,8 +1351,6 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
gen_goto_tb(dc, 0, dc->base.pc_next);
break;
case DISAS_NORETURN:
- case DISAS_JUMP:
- case DISAS_TB_JUMP:
break;
case DISAS_UPDATE:
/* indicate that the hash table must be used
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (3 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled Stafford Horne
` (20 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
No need to use the interrupt mechanisms when we can
simply exit the tb directly.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt_helper.c | 3 +--
target/openrisc/translate.c | 6 +++---
2 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index 56620e0571..b865738f8b 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -26,7 +26,6 @@
void HELPER(rfe)(CPUOpenRISCState *env)
{
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
- CPUState *cs = CPU(cpu);
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
@@ -53,8 +52,8 @@ void HELPER(rfe)(CPUOpenRISCState *env)
}
if (need_flush_tlb) {
+ CPUState *cs = CPU(cpu);
tlb_flush(cs);
}
#endif
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
}
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index f5af515979..43bdf378eb 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -37,6 +37,7 @@
#include "exec/log.h"
/* is_jmp field values */
+#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
typedef struct DisasContext {
@@ -1133,7 +1134,7 @@ static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
gen_illegal_exception(dc);
} else {
gen_helper_rfe(cpu_env);
- dc->base.is_jmp = DISAS_UPDATE;
+ dc->base.is_jmp = DISAS_EXIT;
}
#endif
return true;
@@ -1353,8 +1354,7 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
case DISAS_NORETURN:
break;
case DISAS_UPDATE:
- /* indicate that the hash table must be used
- to find the next TB */
+ case DISAS_EXIT:
tcg_gen_exit_tb(NULL, 0);
break;
default:
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (4 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks Stafford Horne
` (19 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
We failed to store to cpu_pc before raising the exception,
which caused us to re-execute the same insn that we stepped.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/translate.c | 35 +++++++++++++++++------------------
1 file changed, 17 insertions(+), 18 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 43bdf378eb..22848b17ad 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -1335,31 +1335,30 @@ static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ /* If we have already exited the TB, nothing following has effect. */
+ if (dc->base.is_jmp == DISAS_NORETURN) {
+ return;
+ }
+
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
- if (dc->base.is_jmp == DISAS_NEXT) {
- dc->base.is_jmp = DISAS_UPDATE;
- tcg_gen_movi_tl(cpu_pc, dc->base.pc_next);
- }
- if (unlikely(dc->base.singlestep_enabled)) {
- gen_exception(dc, EXCP_DEBUG);
- } else {
- switch (dc->base.is_jmp) {
- case DISAS_TOO_MANY:
- gen_goto_tb(dc, 0, dc->base.pc_next);
- break;
- case DISAS_NORETURN:
- break;
- case DISAS_UPDATE:
- case DISAS_EXIT:
+ switch (dc->base.is_jmp) {
+ case DISAS_TOO_MANY:
+ gen_goto_tb(dc, 0, dc->base.pc_next);
+ break;
+ case DISAS_UPDATE:
+ case DISAS_EXIT:
+ if (unlikely(dc->base.singlestep_enabled)) {
+ gen_exception(dc, EXCP_DEBUG);
+ } else {
tcg_gen_exit_tb(NULL, 0);
- break;
- default:
- g_assert_not_reached();
}
+ break;
+ default:
+ g_assert_not_reached();
}
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (5 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user Stafford Horne
` (18 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
Track direct jumps via dc->jmp_pc_imm. Use that in
preference to jmp_pc when possible. Emit goto_tb in
that case, and lookup_and_goto_tb otherwise.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/translate.c | 96 +++++++++++++++++++++----------------
1 file changed, 55 insertions(+), 41 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 22848b17ad..a618d39242 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -38,13 +38,16 @@
/* is_jmp field values */
#define DISAS_EXIT DISAS_TARGET_0 /* force exit to main loop */
-#define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically */
+#define DISAS_JUMP DISAS_TARGET_1 /* exit via jmp_pc/jmp_pc_imm */
typedef struct DisasContext {
DisasContextBase base;
uint32_t mem_idx;
uint32_t tb_flags;
uint32_t delayed_branch;
+
+ /* If not -1, jmp_pc contains this value and so is a direct jump. */
+ target_ulong jmp_pc_imm;
} DisasContext;
/* Include the auto-generated decoder. */
@@ -160,34 +163,6 @@ static void check_ov64s(DisasContext *dc)
} \
} while (0)
-static inline bool use_goto_tb(DisasContext *dc, target_ulong dest)
-{
- if (unlikely(dc->base.singlestep_enabled)) {
- return false;
- }
-
-#ifndef CONFIG_USER_ONLY
- return (dc->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK);
-#else
- return true;
-#endif
-}
-
-static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
-{
- if (use_goto_tb(dc, dest)) {
- tcg_gen_movi_tl(cpu_pc, dest);
- tcg_gen_goto_tb(n);
- tcg_gen_exit_tb(dc->base.tb, n);
- } else {
- tcg_gen_movi_tl(cpu_pc, dest);
- if (dc->base.singlestep_enabled) {
- gen_exception(dc, EXCP_DEBUG);
- }
- tcg_gen_exit_tb(NULL, 0);
- }
-}
-
static void gen_ove_cy(DisasContext *dc)
{
if (dc->tb_flags & SR_OVE) {
@@ -621,6 +596,7 @@ static bool trans_l_j(DisasContext *dc, arg_l_j *a, uint32_t insn)
target_ulong tmp_pc = dc->base.pc_next + a->n * 4;
tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ dc->jmp_pc_imm = tmp_pc;
dc->delayed_branch = 2;
return true;
}
@@ -634,6 +610,7 @@ static bool trans_l_jal(DisasContext *dc, arg_l_jal *a, uint32_t insn)
/* Optimize jal being used to load the PC for PIC. */
if (tmp_pc != ret_pc) {
tcg_gen_movi_tl(jmp_pc, tmp_pc);
+ dc->jmp_pc_imm = tmp_pc;
dc->delayed_branch = 2;
}
return true;
@@ -1267,6 +1244,8 @@ static void openrisc_tr_init_disas_context(DisasContextBase *dcb, CPUState *cs)
dc->mem_idx = cpu_mmu_index(env, false);
dc->tb_flags = dc->base.tb->flags;
dc->delayed_branch = (dc->tb_flags & TB_FLAGS_DFLAG) != 0;
+ dc->jmp_pc_imm = -1;
+
bound = -(dc->base.pc_first | TARGET_PAGE_MASK) / 4;
dc->base.max_insns = MIN(dc->base.max_insns, bound);
}
@@ -1319,37 +1298,72 @@ static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
}
dc->base.pc_next += 4;
- /* delay slot */
- if (dc->delayed_branch) {
- dc->delayed_branch--;
- if (!dc->delayed_branch) {
- tcg_gen_mov_tl(cpu_pc, jmp_pc);
- tcg_gen_discard_tl(jmp_pc);
- dc->base.is_jmp = DISAS_UPDATE;
- return;
- }
+ /* When exiting the delay slot normally, exit via jmp_pc.
+ * For DISAS_NORETURN, we have raised an exception and already exited.
+ * For DISAS_EXIT, we found l.rfe in a delay slot. There's nothing
+ * in the manual saying this is illegal, but it surely it should.
+ * At least or1ksim overrides pcnext and ignores the branch.
+ */
+ if (dc->delayed_branch
+ && --dc->delayed_branch == 0
+ && dc->base.is_jmp == DISAS_NEXT) {
+ dc->base.is_jmp = DISAS_JUMP;
}
}
static void openrisc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
+ target_ulong jmp_dest;
/* If we have already exited the TB, nothing following has effect. */
if (dc->base.is_jmp == DISAS_NORETURN) {
return;
}
+ /* Adjust the delayed branch state for the next TB. */
if ((dc->tb_flags & TB_FLAGS_DFLAG ? 1 : 0) != (dc->delayed_branch != 0)) {
tcg_gen_movi_i32(cpu_dflag, dc->delayed_branch != 0);
}
- tcg_gen_movi_tl(cpu_ppc, dc->base.pc_next - 4);
+ /* For DISAS_TOO_MANY, jump to the next insn. */
+ jmp_dest = dc->base.pc_next;
+ tcg_gen_movi_tl(cpu_ppc, jmp_dest - 4);
+
switch (dc->base.is_jmp) {
+ case DISAS_JUMP:
+ jmp_dest = dc->jmp_pc_imm;
+ if (jmp_dest == -1) {
+ /* The jump destination is indirect/computed; use jmp_pc. */
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ if (unlikely(dc->base.singlestep_enabled)) {
+ gen_exception(dc, EXCP_DEBUG);
+ } else {
+ tcg_gen_lookup_and_goto_ptr();
+ }
+ break;
+ }
+ /* The jump destination is direct; use jmp_pc_imm.
+ However, we will have stored into jmp_pc as well;
+ we know now that it wasn't needed. */
+ tcg_gen_discard_tl(jmp_pc);
+ /* fallthru */
+
case DISAS_TOO_MANY:
- gen_goto_tb(dc, 0, dc->base.pc_next);
+ if (unlikely(dc->base.singlestep_enabled)) {
+ tcg_gen_movi_tl(cpu_pc, jmp_dest);
+ gen_exception(dc, EXCP_DEBUG);
+ } else if ((dc->base.pc_first ^ jmp_dest) & TARGET_PAGE_MASK) {
+ tcg_gen_movi_tl(cpu_pc, jmp_dest);
+ tcg_gen_lookup_and_goto_ptr();
+ } else {
+ tcg_gen_goto_tb(0);
+ tcg_gen_movi_tl(cpu_pc, jmp_dest);
+ tcg_gen_exit_tb(dc->base.tb, 0);
+ }
break;
- case DISAS_UPDATE:
+
case DISAS_EXIT:
if (unlikely(dc->base.singlestep_enabled)) {
gen_exception(dc, EXCP_DEBUG);
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (6 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr Stafford Horne
` (17 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
This allows us to limit the amount of ifdefs and isolate
the test for usermode.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/translate.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index a618d39242..db149986af 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -50,6 +50,15 @@ typedef struct DisasContext {
target_ulong jmp_pc_imm;
} DisasContext;
+static inline bool is_user(DisasContext *dc)
+{
+#ifdef CONFIG_USER_ONLY
+ return true;
+#else
+ return dc->mem_idx == MMU_USER_IDX;
+#endif
+}
+
/* Include the auto-generated decoder. */
#include "decode.inc.c"
@@ -853,33 +862,25 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
{
check_r0_write(a->d);
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
TCGv_i32 ti = tcg_const_i32(a->k);
gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
tcg_temp_free_i32(ti);
}
-#endif
return true;
}
static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
{
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
TCGv_i32 ti = tcg_const_i32(a->k);
gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
tcg_temp_free_i32(ti);
}
-#endif
return true;
}
@@ -1104,16 +1105,12 @@ static bool trans_l_csync(DisasContext *dc, arg_l_csync *a, uint32_t insn)
static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
{
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
gen_helper_rfe(cpu_env);
dc->base.is_jmp = DISAS_EXIT;
}
-#endif
return true;
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (7 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg Stafford Horne
` (16 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
A store to SR changes interrupt state, which should return
to the main loop to recognize that state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/translate.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index db149986af..59605aacca 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -877,7 +877,22 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti = tcg_const_i32(a->k);
+ TCGv_i32 ti;
+
+ /* For SR, we will need to exit the TB to recognize the new
+ * exception state. For NPC, in theory this counts as a branch
+ * (although the SPR only exists for use by an ICE). Save all
+ * of the cpu state first, allowing it to be overwritten.
+ */
+ if (dc->delayed_branch) {
+ tcg_gen_mov_tl(cpu_pc, jmp_pc);
+ tcg_gen_discard_tl(jmp_pc);
+ } else {
+ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next + 4);
+ }
+ dc->base.is_jmp = DISAS_EXIT;
+
+ ti = tcg_const_i32(a->k);
gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
tcg_temp_free_i32(ti);
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (8 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState Stafford Horne
` (15 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
Rather than pass base+offset to the helper, pass the full index.
In most cases the base is r0 and optimization yields a constant.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/helper.h | 4 ++--
target/openrisc/sys_helper.c | 9 +++------
target/openrisc/translate.c | 16 +++++++++-------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/target/openrisc/helper.h b/target/openrisc/helper.h
index e37dabc77a..9db9bf3963 100644
--- a/target/openrisc/helper.h
+++ b/target/openrisc/helper.h
@@ -56,5 +56,5 @@ FOP_CMP(le)
DEF_HELPER_FLAGS_1(rfe, 0, void, env)
/* sys */
-DEF_HELPER_FLAGS_4(mtspr, 0, void, env, tl, tl, tl)
-DEF_HELPER_FLAGS_4(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl, tl)
+DEF_HELPER_FLAGS_3(mtspr, 0, void, env, tl, tl)
+DEF_HELPER_FLAGS_3(mfspr, TCG_CALL_NO_WG, tl, env, tl, tl)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 2f337363ec..2c959f63f4 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -27,13 +27,11 @@
#define TO_SPR(group, number) (((group) << 11) + (number))
-void HELPER(mtspr)(CPUOpenRISCState *env,
- target_ulong ra, target_ulong rb, target_ulong offset)
+void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
{
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- int spr = (ra | offset);
int idx;
switch (spr) {
@@ -202,13 +200,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
#endif
}
-target_ulong HELPER(mfspr)(CPUOpenRISCState *env,
- target_ulong rd, target_ulong ra, uint32_t offset)
+target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
+ target_ulong spr)
{
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
- int spr = (ra | offset);
int idx;
switch (spr) {
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 59605aacca..64b5e84630 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -865,9 +865,10 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr *a, uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti = tcg_const_i32(a->k);
- gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
- tcg_temp_free_i32(ti);
+ TCGv spr = tcg_temp_new();
+ tcg_gen_ori_tl(spr, cpu_R[a->a], a->k);
+ gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], spr);
+ tcg_temp_free(spr);
}
return true;
}
@@ -877,7 +878,7 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
- TCGv_i32 ti;
+ TCGv spr;
/* For SR, we will need to exit the TB to recognize the new
* exception state. For NPC, in theory this counts as a branch
@@ -892,9 +893,10 @@ static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
}
dc->base.is_jmp = DISAS_EXIT;
- ti = tcg_const_i32(a->k);
- gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
- tcg_temp_free_i32(ti);
+ spr = tcg_temp_new();
+ tcg_gen_ori_tl(spr, cpu_R[a->a], a->k);
+ gen_helper_mtspr(cpu_env, spr, cpu_R[a->b]);
+ tcg_temp_free(spr);
}
return true;
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (9 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu Stafford Horne
` (14 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
There is no reason to allocate this separately. This was probably
copied from target/mips which makes the same mistake.
While doing so, move tlb into the clear-on-reset range. While not
all of the TLB bits are guaranteed zero on reset, all of the valid
bits are cleared, and the rest of the bits are unspecified.
Therefore clearing the whole of the TLB is correct.
Reviewed-by: Stafford Horne <shorne@gmail.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.h | 6 ++++--
target/openrisc/interrupt.c | 4 ++--
target/openrisc/interrupt_helper.c | 8 +++----
target/openrisc/machine.c | 15 ++++++-------
target/openrisc/mmu.c | 34 ++++++++++++++----------------
target/openrisc/sys_helper.c | 28 ++++++++++++------------
6 files changed, 46 insertions(+), 49 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index c871d6bfe1..96b7f58659 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -301,6 +301,10 @@ typedef struct CPUOpenRISCState {
uint32_t dflag; /* In delay slot (boolean) */
+#ifndef CONFIG_USER_ONLY
+ CPUOpenRISCTLBContext tlb;
+#endif
+
/* Fields up to this point are cleared by a CPU reset */
struct {} end_reset_fields;
@@ -310,8 +314,6 @@ typedef struct CPUOpenRISCState {
uint32_t cpucfgr; /* CPU configure register */
#ifndef CONFIG_USER_ONLY
- CPUOpenRISCTLBContext * tlb;
-
QEMUTimer *timer;
uint32_t ttmr; /* Timer tick mode register */
int is_counting;
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 25351d5de3..2d0b55afa9 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -63,8 +63,8 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr &= ~SR_TEE;
env->pmr &= ~PMR_DME;
env->pmr &= ~PMR_SME;
- env->tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
- env->tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
+ env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
+ env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
if (exception > 0 && exception < EXCP_NR) {
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index b865738f8b..dc97b38704 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -36,18 +36,18 @@ void HELPER(rfe)(CPUOpenRISCState *env)
#ifndef CONFIG_USER_ONLY
if (cpu->env.sr & SR_DME) {
- cpu->env.tlb->cpu_openrisc_map_address_data =
+ cpu->env.tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- cpu->env.tlb->cpu_openrisc_map_address_data =
+ cpu->env.tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (cpu->env.sr & SR_IME) {
- cpu->env.tlb->cpu_openrisc_map_address_code =
+ cpu->env.tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- cpu->env.tlb->cpu_openrisc_map_address_code =
+ cpu->env.tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 0a793eb14d..c10d28b055 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -30,18 +30,18 @@ static int env_post_load(void *opaque, int version_id)
/* Restore MMU handlers */
if (env->sr & SR_DME) {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (env->sr & SR_IME) {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
@@ -77,10 +77,6 @@ static const VMStateDescription vmstate_cpu_tlb = {
}
};
-#define VMSTATE_CPU_TLB(_f, _s) \
- VMSTATE_STRUCT_POINTER(_f, _s, vmstate_cpu_tlb, CPUOpenRISCTLBContext)
-
-
static int get_sr(QEMUFile *f, void *opaque, size_t size, VMStateField *field)
{
CPUOpenRISCState *env = opaque;
@@ -143,7 +139,8 @@ static const VMStateDescription vmstate_env = {
VMSTATE_UINT32(fpcsr, CPUOpenRISCState),
VMSTATE_UINT64(mac, CPUOpenRISCState),
- VMSTATE_CPU_TLB(tlb, CPUOpenRISCState),
+ VMSTATE_STRUCT(tlb, CPUOpenRISCState, 1,
+ vmstate_cpu_tlb, CPUOpenRISCTLBContext),
VMSTATE_TIMER_PTR(timer, CPUOpenRISCState),
VMSTATE_UINT32(ttmr, CPUOpenRISCState),
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 2bd782f89b..5665bb7cc9 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -46,19 +46,19 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
int idx = vpn & ITLB_MASK;
int right = 0;
- if ((cpu->env.tlb->itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb->itlb[0][idx].mr & 1)) {
+ if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
- if (cpu->env.tlb->itlb[0][idx].tr & SXE) {
+ if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
right |= PAGE_EXEC;
}
} else {
- if (cpu->env.tlb->itlb[0][idx].tr & UXE) {
+ if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
right |= PAGE_EXEC;
}
}
@@ -67,7 +67,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb->itlb[0][idx].tr & TARGET_PAGE_MASK) |
+ *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@@ -81,25 +81,25 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
int idx = vpn & DTLB_MASK;
int right = 0;
- if ((cpu->env.tlb->dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb->dtlb[0][idx].mr & 1)) {
+ if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
if (cpu->env.sr & SR_SM) { /* supervisor mode */
- if (cpu->env.tlb->dtlb[0][idx].tr & SRE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb->dtlb[0][idx].tr & SWE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
right |= PAGE_WRITE;
}
} else {
- if (cpu->env.tlb->dtlb[0][idx].tr & URE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb->dtlb[0][idx].tr & UWE) {
+ if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
right |= PAGE_WRITE;
}
}
@@ -111,7 +111,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb->dtlb[0][idx].tr & TARGET_PAGE_MASK) |
+ *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
(address & (TARGET_PAGE_SIZE-1));
*prot = right;
return TLBRET_MATCH;
@@ -126,10 +126,10 @@ static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
if (rw == MMU_INST_FETCH) { /* ITLB */
*physical = 0;
- ret = cpu->env.tlb->cpu_openrisc_map_address_code(cpu, physical,
+ ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical,
prot, address, rw);
} else { /* DTLB */
- ret = cpu->env.tlb->cpu_openrisc_map_address_data(cpu, physical,
+ ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical,
prot, address, rw);
}
@@ -247,9 +247,7 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
{
- cpu->env.tlb = g_malloc0(sizeof(CPUOpenRISCTLBContext));
-
- cpu->env.tlb->cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
- cpu->env.tlb->cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
+ cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
+ cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
}
#endif
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 2c959f63f4..ff315f6f1a 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -61,18 +61,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
cpu_set_sr(env, rb);
if (env->sr & SR_DME) {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_data;
} else {
- env->tlb->cpu_openrisc_map_address_data =
+ env->tlb.cpu_openrisc_map_address_data =
&cpu_openrisc_get_phys_nommu;
}
if (env->sr & SR_IME) {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_code;
} else {
- env->tlb->cpu_openrisc_map_address_code =
+ env->tlb.cpu_openrisc_map_address_code =
&cpu_openrisc_get_phys_nommu;
}
break;
@@ -101,14 +101,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb->dtlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK);
}
- env->tlb->dtlb[0][idx].mr = rb;
+ env->tlb.dtlb[0][idx].mr = rb;
break;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- env->tlb->dtlb[0][idx].tr = rb;
+ env->tlb.dtlb[0][idx].tr = rb;
break;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -120,14 +120,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb->itlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK);
}
- env->tlb->itlb[0][idx].mr = rb;
+ env->tlb.itlb[0][idx].mr = rb;
break;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- env->tlb->itlb[0][idx].tr = rb;
+ env->tlb.itlb[0][idx].tr = rb;
break;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
@@ -259,11 +259,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
- return env->tlb->dtlb[0][idx].mr;
+ return env->tlb.dtlb[0][idx].mr;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- return env->tlb->dtlb[0][idx].tr;
+ return env->tlb.dtlb[0][idx].tr;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -275,11 +275,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
- return env->tlb->itlb[0][idx].mr;
+ return env->tlb.itlb[0][idx].mr;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- return env->tlb->itlb[0][idx].tr;
+ return env->tlb.itlb[0][idx].tr;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (10 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c Stafford Horne
` (13 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
There is no reason to use an indirect branch instead
of simply testing the SR bits that control mmu state.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 4 --
target/openrisc/cpu.h | 11 -----
target/openrisc/interrupt.c | 2 -
target/openrisc/interrupt_helper.c | 25 ++---------
target/openrisc/machine.c | 26 ------------
target/openrisc/mmu.c | 68 +++++++++++++-----------------
target/openrisc/sys_helper.c | 15 -------
7 files changed, 32 insertions(+), 119 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index fa8e342ff7..b92de51ecf 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -92,10 +92,6 @@ static void openrisc_cpu_initfn(Object *obj)
OpenRISCCPU *cpu = OPENRISC_CPU(obj);
cs->env_ptr = &cpu->env;
-
-#ifndef CONFIG_USER_ONLY
- cpu_openrisc_mmu_init(cpu);
-#endif
}
/* CPU models */
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 96b7f58659..a27adad085 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -379,17 +379,6 @@ void cpu_openrisc_count_update(OpenRISCCPU *cpu);
void cpu_openrisc_timer_update(OpenRISCCPU *cpu);
void cpu_openrisc_count_start(OpenRISCCPU *cpu);
void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
-
-void cpu_openrisc_mmu_init(OpenRISCCPU *cpu);
-int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw);
-int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw);
-int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw);
#endif
#define OPENRISC_CPU_TYPE_SUFFIX "-" TYPE_OPENRISC_CPU
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 2d0b55afa9..23abcf29ed 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -63,8 +63,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->sr &= ~SR_TEE;
env->pmr &= ~PMR_DME;
env->pmr &= ~PMR_SME;
- env->tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
- env->tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
env->lock_addr = -1;
if (exception > 0 && exception < EXCP_NR) {
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index dc97b38704..a2e9003969 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -29,31 +29,12 @@ void HELPER(rfe)(CPUOpenRISCState *env)
#ifndef CONFIG_USER_ONLY
int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
(cpu->env.esr & (SR_SM | SR_IME | SR_DME));
-#endif
- cpu->env.pc = cpu->env.epcr;
- cpu_set_sr(&cpu->env, cpu->env.esr);
- cpu->env.lock_addr = -1;
-
-#ifndef CONFIG_USER_ONLY
- if (cpu->env.sr & SR_DME) {
- cpu->env.tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_data;
- } else {
- cpu->env.tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_nommu;
- }
-
- if (cpu->env.sr & SR_IME) {
- cpu->env.tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_code;
- } else {
- cpu->env.tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_nommu;
- }
-
if (need_flush_tlb) {
CPUState *cs = CPU(cpu);
tlb_flush(cs);
}
#endif
+ cpu->env.pc = cpu->env.epcr;
+ cpu->env.lock_addr = -1;
+ cpu_set_sr(&cpu->env, cpu->env.esr);
}
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index c10d28b055..73e0abcfd7 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -24,31 +24,6 @@
#include "hw/boards.h"
#include "migration/cpu.h"
-static int env_post_load(void *opaque, int version_id)
-{
- CPUOpenRISCState *env = opaque;
-
- /* Restore MMU handlers */
- if (env->sr & SR_DME) {
- env->tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_data;
- } else {
- env->tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_nommu;
- }
-
- if (env->sr & SR_IME) {
- env->tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_code;
- } else {
- env->tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_nommu;
- }
-
-
- return 0;
-}
-
static const VMStateDescription vmstate_tlb_entry = {
.name = "tlb_entry",
.version_id = 1,
@@ -102,7 +77,6 @@ static const VMStateDescription vmstate_env = {
.name = "env",
.version_id = 6,
.minimum_version_id = 6,
- .post_load = env_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINTTL_2DARRAY(shadow_gpr, CPUOpenRISCState, 16, 32),
VMSTATE_UINTTL(pc, CPUOpenRISCState),
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 5665bb7cc9..b2effaa6d7 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -29,18 +29,16 @@
#endif
#ifndef CONFIG_USER_ONLY
-int cpu_openrisc_get_phys_nommu(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw)
+static inline int get_phys_nommu(hwaddr *physical, int *prot,
+ target_ulong address)
{
*physical = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
-int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw)
+static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
+ target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & ITLB_MASK;
@@ -52,8 +50,7 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
-
- if (cpu->env.sr & SR_SM) { /* supervisor mode */
+ if (supervisor) {
if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
right |= PAGE_EXEC;
}
@@ -62,7 +59,6 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
right |= PAGE_EXEC;
}
}
-
if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
return TLBRET_BADADDR;
}
@@ -73,9 +69,8 @@ int cpu_openrisc_get_phys_code(OpenRISCCPU *cpu,
return TLBRET_MATCH;
}
-int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address, int rw)
+static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
+ target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & DTLB_MASK;
@@ -87,8 +82,7 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
return TLBRET_INVALID;
}
-
- if (cpu->env.sr & SR_SM) { /* supervisor mode */
+ if (supervisor) {
if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
right |= PAGE_READ;
}
@@ -117,20 +111,24 @@ int cpu_openrisc_get_phys_data(OpenRISCCPU *cpu,
return TLBRET_MATCH;
}
-static int cpu_openrisc_get_phys_addr(OpenRISCCPU *cpu,
- hwaddr *physical,
- int *prot, target_ulong address,
- int rw)
+static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical,
+ int *prot, target_ulong address, int rw)
{
- int ret = TLBRET_MATCH;
-
- if (rw == MMU_INST_FETCH) { /* ITLB */
- *physical = 0;
- ret = cpu->env.tlb.cpu_openrisc_map_address_code(cpu, physical,
- prot, address, rw);
- } else { /* DTLB */
- ret = cpu->env.tlb.cpu_openrisc_map_address_data(cpu, physical,
- prot, address, rw);
+ bool supervisor = (cpu->env.sr & SR_SM) != 0;
+ int ret;
+
+ /* Assume nommu results for a moment. */
+ ret = get_phys_nommu(physical, prot, address);
+
+ /* Overwrite with TLB lookup if enabled. */
+ if (rw == MMU_INST_FETCH) {
+ if (cpu->env.sr & SR_IME) {
+ ret = get_phys_code(cpu, physical, prot, address, rw, supervisor);
+ }
+ } else {
+ if (cpu->env.sr & SR_DME) {
+ ret = get_phys_data(cpu, physical, prot, address, rw, supervisor);
+ }
}
return ret;
@@ -186,8 +184,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
hwaddr physical = 0;
int prot = 0;
- ret = cpu_openrisc_get_phys_addr(cpu, &physical, &prot,
- address, rw);
+ ret = get_phys_addr(cpu, &physical, &prot, address, rw);
if (ret == TLBRET_MATCH) {
tlb_set_page(cs, address & TARGET_PAGE_MASK,
@@ -225,17 +222,16 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
/* Check memory for any kind of address, since during debug the
gdb can ask for anything, check data tlb for address */
- miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
+ miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
/* Check instruction tlb */
if (miss) {
- miss = cpu_openrisc_get_phys_addr(cpu, &phys_addr, &prot, addr,
- MMU_INST_FETCH);
+ miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
}
/* Last, fall back to a plain address */
if (miss) {
- miss = cpu_openrisc_get_phys_nommu(cpu, &phys_addr, &prot, addr, 0);
+ miss = get_phys_nommu(&phys_addr, &prot, addr);
}
if (miss) {
@@ -244,10 +240,4 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return phys_addr;
}
}
-
-void cpu_openrisc_mmu_init(OpenRISCCPU *cpu)
-{
- cpu->env.tlb.cpu_openrisc_map_address_code = &cpu_openrisc_get_phys_nommu;
- cpu->env.tlb.cpu_openrisc_map_address_data = &cpu_openrisc_get_phys_nommu;
-}
#endif
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index ff315f6f1a..9b4339b34e 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -60,21 +60,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
tlb_flush(cs);
}
cpu_set_sr(env, rb);
- if (env->sr & SR_DME) {
- env->tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_data;
- } else {
- env->tlb.cpu_openrisc_map_address_data =
- &cpu_openrisc_get_phys_nommu;
- }
-
- if (env->sr & SR_IME) {
- env->tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_code;
- } else {
- env->tlb.cpu_openrisc_map_address_code =
- &cpu_openrisc_get_phys_nommu;
- }
break;
case TO_SPR(0, 18): /* PPC */
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (11 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension Stafford Horne
` (12 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
With tlb_fill in mmu.c, we can simplify things further.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/Makefile.objs | 2 +-
target/openrisc/mmu.c | 11 ++++++++++
target/openrisc/mmu_helper.c | 40 -----------------------------------
3 files changed, 12 insertions(+), 41 deletions(-)
delete mode 100644 target/openrisc/mmu_helper.c
diff --git a/target/openrisc/Makefile.objs b/target/openrisc/Makefile.objs
index 8b8a890c59..b5432f4684 100644
--- a/target/openrisc/Makefile.objs
+++ b/target/openrisc/Makefile.objs
@@ -1,7 +1,7 @@
obj-$(CONFIG_SOFTMMU) += machine.o
obj-y += cpu.o exception.o interrupt.o mmu.o translate.o disas.o
obj-y += exception_helper.o fpu_helper.o \
- interrupt_helper.o mmu_helper.o sys_helper.o
+ interrupt_helper.o sys_helper.o
obj-y += gdbstub.o
DECODETREE = $(SRC_PATH)/scripts/decodetree.py
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index b2effaa6d7..9b4b5cf04f 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -240,4 +240,15 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
return phys_addr;
}
}
+
+void tlb_fill(CPUState *cs, target_ulong addr, int size,
+ MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
+{
+ int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size,
+ access_type, mmu_idx);
+ if (ret) {
+ /* Raise Exception. */
+ cpu_loop_exit_restore(cs, retaddr);
+ }
+}
#endif
diff --git a/target/openrisc/mmu_helper.c b/target/openrisc/mmu_helper.c
deleted file mode 100644
index 97e1d17b5a..0000000000
--- a/target/openrisc/mmu_helper.c
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * OpenRISC MMU helper routines
- *
- * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com>
- * Zhizhou Zhang <etouzh@gmail.com>
- *
- * This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU Lesser General Public
- * License as published by the Free Software Foundation; either
- * version 2 of the License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
- * Lesser General Public License for more details.
- *
- * You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, see <http://www.gnu.org/licenses/>.
- */
-
-#include "qemu/osdep.h"
-#include "cpu.h"
-#include "exec/exec-all.h"
-#include "exec/cpu_ldst.h"
-
-#ifndef CONFIG_USER_ONLY
-
-void tlb_fill(CPUState *cs, target_ulong addr, int size,
- MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
-{
- int ret;
-
- ret = openrisc_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx);
-
- if (ret) {
- /* Raise Exception. */
- cpu_loop_exit_restore(cs, retaddr);
- }
-}
-#endif
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (12 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr Stafford Horne
` (11 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
While we had defines for *_WAYS, we didn't define more than 1.
Reduce the complexity by eliminating this unused dimension.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.h | 6 ++----
target/openrisc/machine.c | 6 ++----
target/openrisc/mmu.c | 30 ++++++++++++++++--------------
target/openrisc/sys_helper.c | 20 ++++++++++----------
4 files changed, 30 insertions(+), 32 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index a27adad085..eaf6cdd40e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -222,10 +222,8 @@ enum {
/* TLB size */
enum {
- DTLB_WAYS = 1,
DTLB_SIZE = 64,
DTLB_MASK = (DTLB_SIZE-1),
- ITLB_WAYS = 1,
ITLB_SIZE = 64,
ITLB_MASK = (ITLB_SIZE-1),
};
@@ -256,8 +254,8 @@ typedef struct OpenRISCTLBEntry {
#ifndef CONFIG_USER_ONLY
typedef struct CPUOpenRISCTLBContext {
- OpenRISCTLBEntry itlb[ITLB_WAYS][ITLB_SIZE];
- OpenRISCTLBEntry dtlb[DTLB_WAYS][DTLB_SIZE];
+ OpenRISCTLBEntry itlb[ITLB_SIZE];
+ OpenRISCTLBEntry dtlb[DTLB_SIZE];
int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
hwaddr *physical,
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 73e0abcfd7..b795b56dc6 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -42,11 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
- VMSTATE_STRUCT_2DARRAY(itlb, CPUOpenRISCTLBContext,
- ITLB_WAYS, ITLB_SIZE, 0,
+ VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
- VMSTATE_STRUCT_2DARRAY(dtlb, CPUOpenRISCTLBContext,
- DTLB_WAYS, DTLB_SIZE, 0,
+ VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
VMSTATE_END_OF_LIST()
}
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 9b4b5cf04f..856969a7f2 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -43,19 +43,21 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & ITLB_MASK;
int right = 0;
+ uint32_t mr = cpu->env.tlb.itlb[idx].mr;
+ uint32_t tr = cpu->env.tlb.itlb[idx].tr;
- if ((cpu->env.tlb.itlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb.itlb[0][idx].mr & 1)) {
+ if (!(mr & 1)) {
return TLBRET_INVALID;
}
if (supervisor) {
- if (cpu->env.tlb.itlb[0][idx].tr & SXE) {
+ if (tr & SXE) {
right |= PAGE_EXEC;
}
} else {
- if (cpu->env.tlb.itlb[0][idx].tr & UXE) {
+ if (tr & UXE) {
right |= PAGE_EXEC;
}
}
@@ -63,8 +65,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb.itlb[0][idx].tr & TARGET_PAGE_MASK) |
- (address & (TARGET_PAGE_SIZE-1));
+ *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
*prot = right;
return TLBRET_MATCH;
}
@@ -75,25 +76,27 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
int vpn = address >> TARGET_PAGE_BITS;
int idx = vpn & DTLB_MASK;
int right = 0;
+ uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
+ uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
- if ((cpu->env.tlb.dtlb[0][idx].mr >> TARGET_PAGE_BITS) != vpn) {
+ if ((mr >> TARGET_PAGE_BITS) != vpn) {
return TLBRET_NOMATCH;
}
- if (!(cpu->env.tlb.dtlb[0][idx].mr & 1)) {
+ if (!(mr & 1)) {
return TLBRET_INVALID;
}
if (supervisor) {
- if (cpu->env.tlb.dtlb[0][idx].tr & SRE) {
+ if (tr & SRE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb.dtlb[0][idx].tr & SWE) {
+ if (tr & SWE) {
right |= PAGE_WRITE;
}
} else {
- if (cpu->env.tlb.dtlb[0][idx].tr & URE) {
+ if (tr & URE) {
right |= PAGE_READ;
}
- if (cpu->env.tlb.dtlb[0][idx].tr & UWE) {
+ if (tr & UWE) {
right |= PAGE_WRITE;
}
}
@@ -105,8 +108,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
return TLBRET_BADADDR;
}
- *physical = (cpu->env.tlb.dtlb[0][idx].tr & TARGET_PAGE_MASK) |
- (address & (TARGET_PAGE_SIZE-1));
+ *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
*prot = right;
return TLBRET_MATCH;
}
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 9b4339b34e..7f458b0d17 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -86,14 +86,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.dtlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK);
}
- env->tlb.dtlb[0][idx].mr = rb;
+ env->tlb.dtlb[idx].mr = rb;
break;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- env->tlb.dtlb[0][idx].tr = rb;
+ env->tlb.dtlb[idx].tr = rb;
break;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -105,14 +105,14 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.itlb[0][idx].mr & TARGET_PAGE_MASK);
+ tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK);
}
- env->tlb.itlb[0][idx].mr = rb;
+ env->tlb.itlb[idx].mr = rb;
break;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- env->tlb.itlb[0][idx].tr = rb;
+ env->tlb.itlb[idx].tr = rb;
break;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
@@ -244,11 +244,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
- return env->tlb.dtlb[0][idx].mr;
+ return env->tlb.dtlb[idx].mr;
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
- return env->tlb.dtlb[0][idx].tr;
+ return env->tlb.dtlb[idx].tr;
case TO_SPR(1, 768) ... TO_SPR(1, 895): /* DTLBW1MR 0-127 */
case TO_SPR(1, 896) ... TO_SPR(1, 1023): /* DTLBW1TR 0-127 */
@@ -260,11 +260,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
- return env->tlb.itlb[0][idx].mr;
+ return env->tlb.itlb[idx].mr;
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
- return env->tlb.itlb[0][idx].tr;
+ return env->tlb.itlb[idx].tr;
case TO_SPR(2, 768) ... TO_SPR(2, 895): /* ITLBW1MR 0-127 */
case TO_SPR(2, 896) ... TO_SPR(2, 1023): /* ITLBW1TR 0-127 */
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (13 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index Stafford Horne
` (10 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
The previous code was confused, avoiding the flush of the old entry
if the new entry is invalid. We need to flush the old page if the
old entry is valid and the new page if the new entry is valid.
This bug was masked by over-flushing elsewhere.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/sys_helper.c | 21 +++++++++++++++------
1 file changed, 15 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 7f458b0d17..c9702cd26c 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -32,6 +32,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
#ifndef CONFIG_USER_ONLY
OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
CPUState *cs = CPU(cpu);
+ target_ulong mr;
int idx;
switch (spr) {
@@ -85,12 +86,15 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
- if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.dtlb[idx].mr & TARGET_PAGE_MASK);
+ mr = env->tlb.dtlb[idx].mr;
+ if (mr & 1) {
+ tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
+ }
+ if (rb & 1) {
+ tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
}
env->tlb.dtlb[idx].mr = rb;
break;
-
case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env->tlb.dtlb[idx].tr = rb;
@@ -102,14 +106,18 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 1280) ... TO_SPR(1, 1407): /* DTLBW3MR 0-127 */
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
+
case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
- if (!(rb & 1)) {
- tlb_flush_page(cs, env->tlb.itlb[idx].mr & TARGET_PAGE_MASK);
+ mr = env->tlb.itlb[idx].mr;
+ if (mr & 1) {
+ tlb_flush_page(cs, mr & TARGET_PAGE_MASK);
+ }
+ if (rb & 1) {
+ tlb_flush_page(cs, rb & TARGET_PAGE_MASK);
}
env->tlb.itlb[idx].mr = rb;
break;
-
case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env->tlb.itlb[idx].tr = rb;
@@ -121,6 +129,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(2, 1280) ... TO_SPR(2, 1407): /* ITLBW3MR 0-127 */
case TO_SPR(2, 1408) ... TO_SPR(2, 1535): /* ITLBW3TR 0-127 */
break;
+
case TO_SPR(5, 1): /* MACLO */
env->mac = deposit64(env->mac, 0, 32, rb);
break;
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (14 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB Stafford Horne
` (9 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
The code in cpu_mmu_index does not properly honor SR_DME.
This bug has workarounds elsewhere in that we flush the
tlb more often than necessary, on the state changes that
should be reflected in a change of mmu_index.
Fixing this means that we can respect the mmu_index that
is given to tlb_flush.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.h | 23 +++++++++++++--------
target/openrisc/interrupt.c | 4 ----
target/openrisc/interrupt_helper.c | 15 +++-----------
target/openrisc/mmu.c | 33 +++++++++++++++++++++++++++---
target/openrisc/sys_helper.c | 4 ----
target/openrisc/translate.c | 2 +-
6 files changed, 49 insertions(+), 32 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index eaf6cdd40e..c3a968ec4d 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -385,9 +385,12 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu);
#include "exec/cpu-all.h"
-#define TB_FLAGS_DFLAG 1
-#define TB_FLAGS_R0_0 2
+#define TB_FLAGS_SM SR_SM
+#define TB_FLAGS_DME SR_DME
+#define TB_FLAGS_IME SR_IME
#define TB_FLAGS_OVE SR_OVE
+#define TB_FLAGS_DFLAG 2 /* reuse SR_TEE */
+#define TB_FLAGS_R0_0 4 /* reuse SR_IEE */
static inline uint32_t cpu_get_gpr(const CPUOpenRISCState *env, int i)
{
@@ -405,17 +408,21 @@ static inline void cpu_get_tb_cpu_state(CPUOpenRISCState *env,
{
*pc = env->pc;
*cs_base = 0;
- *flags = (env->dflag
- | (cpu_get_gpr(env, 0) == 0 ? TB_FLAGS_R0_0 : 0)
- | (env->sr & SR_OVE));
+ *flags = (env->dflag ? TB_FLAGS_DFLAG : 0)
+ | (cpu_get_gpr(env, 0) ? 0 : TB_FLAGS_R0_0)
+ | (env->sr & (SR_SM | SR_DME | SR_IME | SR_OVE));
}
static inline int cpu_mmu_index(CPUOpenRISCState *env, bool ifetch)
{
- if (!(env->sr & SR_IME)) {
- return MMU_NOMMU_IDX;
+ int ret = MMU_NOMMU_IDX; /* mmu is disabled */
+
+ if (env->sr & (ifetch ? SR_IME : SR_DME)) {
+ /* The mmu is enabled; test supervisor state. */
+ ret = env->sr & SR_SM ? MMU_SUPERVISOR_IDX : MMU_USER_IDX;
}
- return (env->sr & SR_SM) == 0 ? MMU_USER_IDX : MMU_SUPERVISOR_IDX;
+
+ return ret;
}
static inline uint32_t cpu_get_sr(const CPUOpenRISCState *env)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 23abcf29ed..138ad17f00 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -51,10 +51,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->eear = env->pc;
}
- /* For machine-state changed between user-mode and supervisor mode,
- we need flush TLB when we enter&exit EXCP. */
- tlb_flush(cs);
-
env->esr = cpu_get_sr(env);
env->sr &= ~SR_DME;
env->sr &= ~SR_IME;
diff --git a/target/openrisc/interrupt_helper.c b/target/openrisc/interrupt_helper.c
index a2e9003969..9c5489f5f7 100644
--- a/target/openrisc/interrupt_helper.c
+++ b/target/openrisc/interrupt_helper.c
@@ -25,16 +25,7 @@
void HELPER(rfe)(CPUOpenRISCState *env)
{
- OpenRISCCPU *cpu = openrisc_env_get_cpu(env);
-#ifndef CONFIG_USER_ONLY
- int need_flush_tlb = (cpu->env.sr & (SR_SM | SR_IME | SR_DME)) ^
- (cpu->env.esr & (SR_SM | SR_IME | SR_DME));
- if (need_flush_tlb) {
- CPUState *cs = CPU(cpu);
- tlb_flush(cs);
- }
-#endif
- cpu->env.pc = cpu->env.epcr;
- cpu->env.lock_addr = -1;
- cpu_set_sr(&cpu->env, cpu->env.esr);
+ env->pc = env->epcr;
+ env->lock_addr = -1;
+ cpu_set_sr(env, env->esr);
}
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index 856969a7f2..b293b64e98 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -246,9 +246,36 @@ hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
- int ret = openrisc_cpu_handle_mmu_fault(cs, addr, size,
- access_type, mmu_idx);
- if (ret) {
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ int ret, prot = 0;
+ hwaddr physical = 0;
+
+ if (mmu_idx == MMU_NOMMU_IDX) {
+ ret = get_phys_nommu(&physical, &prot, addr);
+ } else {
+ bool super = mmu_idx == MMU_SUPERVISOR_IDX;
+ if (access_type == MMU_INST_FETCH) {
+ ret = get_phys_code(cpu, &physical, &prot, addr, 2, super);
+ } else {
+ ret = get_phys_data(cpu, &physical, &prot, addr,
+ access_type == MMU_DATA_STORE, super);
+ }
+ }
+
+ if (ret == TLBRET_MATCH) {
+ tlb_set_page(cs, addr & TARGET_PAGE_MASK,
+ physical & TARGET_PAGE_MASK, prot,
+ mmu_idx, TARGET_PAGE_SIZE);
+ } else if (ret < 0) {
+ int rw;
+ if (access_type == MMU_INST_FETCH) {
+ rw = 2;
+ } else if (access_type == MMU_DATA_STORE) {
+ rw = 1;
+ } else {
+ rw = 0;
+ }
+ cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret);
/* Raise Exception. */
cpu_loop_exit_restore(cs, retaddr);
}
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index c9702cd26c..852b219f9b 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -56,10 +56,6 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
break;
case TO_SPR(0, 17): /* SR */
- if ((env->sr & (SR_IME | SR_DME | SR_SM)) ^
- (rb & (SR_IME | SR_DME | SR_SM))) {
- tlb_flush(cs);
- }
cpu_set_sr(env, rb);
break;
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index 64b5e84630..a271cd3903 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -55,7 +55,7 @@ static inline bool is_user(DisasContext *dc)
#ifdef CONFIG_USER_ONLY
return true;
#else
- return dc->mem_idx == MMU_USER_IDX;
+ return !(dc->tb_flags & TB_FLAGS_SM);
#endif
}
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (15 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu Stafford Horne
` (8 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
The sizes are already the same, however, we can improve things
if they are identical by design.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.h | 10 ++++------
target/openrisc/machine.c | 4 ++--
target/openrisc/mmu.c | 4 ++--
target/openrisc/sys_helper.c | 16 ++++++++--------
4 files changed, 16 insertions(+), 18 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index c3a968ec4d..47e94659e1 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -222,10 +222,8 @@ enum {
/* TLB size */
enum {
- DTLB_SIZE = 64,
- DTLB_MASK = (DTLB_SIZE-1),
- ITLB_SIZE = 64,
- ITLB_MASK = (ITLB_SIZE-1),
+ TLB_SIZE = 64,
+ TLB_MASK = TLB_SIZE - 1,
};
/* TLB prot */
@@ -254,8 +252,8 @@ typedef struct OpenRISCTLBEntry {
#ifndef CONFIG_USER_ONLY
typedef struct CPUOpenRISCTLBContext {
- OpenRISCTLBEntry itlb[ITLB_SIZE];
- OpenRISCTLBEntry dtlb[DTLB_SIZE];
+ OpenRISCTLBEntry itlb[TLB_SIZE];
+ OpenRISCTLBEntry dtlb[TLB_SIZE];
int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu,
hwaddr *physical,
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index b795b56dc6..3fc837b925 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -42,9 +42,9 @@ static const VMStateDescription vmstate_cpu_tlb = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
- VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, ITLB_SIZE, 0,
+ VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
- VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, DTLB_SIZE, 0,
+ VMSTATE_STRUCT_ARRAY(dtlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
VMSTATE_END_OF_LIST()
}
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index b293b64e98..a4613e9ae4 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -41,7 +41,7 @@ static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
- int idx = vpn & ITLB_MASK;
+ int idx = vpn & TLB_MASK;
int right = 0;
uint32_t mr = cpu->env.tlb.itlb[idx].mr;
uint32_t tr = cpu->env.tlb.itlb[idx].tr;
@@ -74,7 +74,7 @@ static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
target_ulong address, int rw, bool supervisor)
{
int vpn = address >> TARGET_PAGE_BITS;
- int idx = vpn & DTLB_MASK;
+ int idx = vpn & TLB_MASK;
int right = 0;
uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 852b219f9b..541615bfb3 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -80,7 +80,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
env->shadow_gpr[idx / 32][idx % 32] = rb;
break;
- case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
+ case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
mr = env->tlb.dtlb[idx].mr;
if (mr & 1) {
@@ -91,7 +91,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
env->tlb.dtlb[idx].mr = rb;
break;
- case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
+ case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
env->tlb.dtlb[idx].tr = rb;
break;
@@ -103,7 +103,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
- case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
+ case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
mr = env->tlb.itlb[idx].mr;
if (mr & 1) {
@@ -114,7 +114,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
env->tlb.itlb[idx].mr = rb;
break;
- case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
+ case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
env->tlb.itlb[idx].tr = rb;
break;
@@ -247,11 +247,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
idx = (spr - 1024);
return env->shadow_gpr[idx / 32][idx % 32];
- case TO_SPR(1, 512) ... TO_SPR(1, 512+DTLB_SIZE-1): /* DTLBW0MR 0-127 */
+ case TO_SPR(1, 512) ... TO_SPR(1, 512 + TLB_SIZE - 1): /* DTLBW0MR 0-127 */
idx = spr - TO_SPR(1, 512);
return env->tlb.dtlb[idx].mr;
- case TO_SPR(1, 640) ... TO_SPR(1, 640+DTLB_SIZE-1): /* DTLBW0TR 0-127 */
+ case TO_SPR(1, 640) ... TO_SPR(1, 640 + TLB_SIZE - 1): /* DTLBW0TR 0-127 */
idx = spr - TO_SPR(1, 640);
return env->tlb.dtlb[idx].tr;
@@ -263,11 +263,11 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
case TO_SPR(1, 1408) ... TO_SPR(1, 1535): /* DTLBW3TR 0-127 */
break;
- case TO_SPR(2, 512) ... TO_SPR(2, 512+ITLB_SIZE-1): /* ITLBW0MR 0-127 */
+ case TO_SPR(2, 512) ... TO_SPR(2, 512 + TLB_SIZE - 1): /* ITLBW0MR 0-127 */
idx = spr - TO_SPR(2, 512);
return env->tlb.itlb[idx].mr;
- case TO_SPR(2, 640) ... TO_SPR(2, 640+ITLB_SIZE-1): /* ITLBW0TR 0-127 */
+ case TO_SPR(2, 640) ... TO_SPR(2, 640 + TLB_SIZE - 1): /* ITLBW0TR 0-127 */
idx = spr - TO_SPR(2, 640);
return env->tlb.itlb[idx].tr;
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (16 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size Stafford Horne
` (7 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
This hook is only used by CONFIG_USER_ONLY.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/mmu.c | 35 +++++------------------------------
1 file changed, 5 insertions(+), 30 deletions(-)
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index a4613e9ae4..f4c0a3e217 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -177,42 +177,17 @@ static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
cpu->env.lock_addr = -1;
}
-#ifndef CONFIG_USER_ONLY
int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
int rw, int mmu_idx)
{
+#ifdef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- int ret = 0;
- hwaddr physical = 0;
- int prot = 0;
-
- ret = get_phys_addr(cpu, &physical, &prot, address, rw);
-
- if (ret == TLBRET_MATCH) {
- tlb_set_page(cs, address & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot,
- mmu_idx, TARGET_PAGE_SIZE);
- ret = 0;
- } else if (ret < 0) {
- cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
- ret = 1;
- }
-
- return ret;
-}
+ cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0);
+ return 1;
#else
-int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
- int rw, int mmu_idx)
-{
- OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- int ret = 0;
-
- cpu_openrisc_raise_mmu_exception(cpu, address, rw, ret);
- ret = 1;
-
- return ret;
-}
+ g_assert_not_reached();
#endif
+}
#ifndef CONFIG_USER_ONLY
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (17 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup Stafford Horne
` (6 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
The architecture supports 128 TLB entries. There is no reason
not to provide all of them. In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
- Change VMState version.
---
target/openrisc/cpu.c | 6 ++++--
target/openrisc/cpu.h | 2 +-
target/openrisc/machine.c | 5 ++---
3 files changed, 7 insertions(+), 6 deletions(-)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index b92de51ecf..e01ce9ed1c 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
UPR_PMP;
- cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
- cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
+ cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
+ | (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
+ cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
+ | (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x00000000;
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index 47e94659e1..b180e30e9e 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -222,7 +222,7 @@ enum {
/* TLB size */
enum {
- TLB_SIZE = 64,
+ TLB_SIZE = 128,
TLB_MASK = TLB_SIZE - 1,
};
diff --git a/target/openrisc/machine.c b/target/openrisc/machine.c
index 3fc837b925..1eedbf3dbe 100644
--- a/target/openrisc/machine.c
+++ b/target/openrisc/machine.c
@@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = {
static const VMStateDescription vmstate_cpu_tlb = {
.name = "cpu_tlb",
- .version_id = 1,
- .minimum_version_id = 1,
- .minimum_version_id_old = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (18 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Stafford Horne
` (5 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Richard Henderson, Stafford Horne
From: Richard Henderson <richard.henderson@linaro.org>
While openrisc has a split i/d tlb, qemu does not. Perform a
lookup on both i & d tlbs in parallel and put the composite
rights into qemu's tlb. This avoids ping-ponging the qemu tlb
between EXEC and READ.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.h | 8 --
target/openrisc/mmu.c | 250 +++++++++++++++---------------------------
2 files changed, 88 insertions(+), 170 deletions(-)
diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h
index b180e30e9e..f1b31bc24a 100644
--- a/target/openrisc/cpu.h
+++ b/target/openrisc/cpu.h
@@ -237,14 +237,6 @@ enum {
UXE = (1 << 7),
};
-/* check if tlb available */
-enum {
- TLBRET_INVALID = -3,
- TLBRET_NOMATCH = -2,
- TLBRET_BADADDR = -1,
- TLBRET_MATCH = 0
-};
-
typedef struct OpenRISCTLBEntry {
uint32_t mr;
uint32_t tr;
diff --git a/target/openrisc/mmu.c b/target/openrisc/mmu.c
index f4c0a3e217..d3796ae41e 100644
--- a/target/openrisc/mmu.c
+++ b/target/openrisc/mmu.c
@@ -29,148 +29,78 @@
#endif
#ifndef CONFIG_USER_ONLY
-static inline int get_phys_nommu(hwaddr *physical, int *prot,
- target_ulong address)
+static inline void get_phys_nommu(hwaddr *phys_addr, int *prot,
+ target_ulong address)
{
- *physical = address;
+ *phys_addr = address;
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
- return TLBRET_MATCH;
}
-static int get_phys_code(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
- target_ulong address, int rw, bool supervisor)
+static int get_phys_mmu(OpenRISCCPU *cpu, hwaddr *phys_addr, int *prot,
+ target_ulong addr, int need, bool super)
{
- int vpn = address >> TARGET_PAGE_BITS;
- int idx = vpn & TLB_MASK;
- int right = 0;
- uint32_t mr = cpu->env.tlb.itlb[idx].mr;
- uint32_t tr = cpu->env.tlb.itlb[idx].tr;
-
- if ((mr >> TARGET_PAGE_BITS) != vpn) {
- return TLBRET_NOMATCH;
- }
- if (!(mr & 1)) {
- return TLBRET_INVALID;
- }
- if (supervisor) {
- if (tr & SXE) {
- right |= PAGE_EXEC;
- }
- } else {
- if (tr & UXE) {
- right |= PAGE_EXEC;
+ int idx = (addr >> TARGET_PAGE_BITS) & TLB_MASK;
+ uint32_t imr = cpu->env.tlb.itlb[idx].mr;
+ uint32_t itr = cpu->env.tlb.itlb[idx].tr;
+ uint32_t dmr = cpu->env.tlb.dtlb[idx].mr;
+ uint32_t dtr = cpu->env.tlb.dtlb[idx].tr;
+ int right, match, valid;
+
+ /* If the ITLB and DTLB indexes map to the same page, we want to
+ load all permissions all at once. If the destination pages do
+ not match, zap the one we don't need. */
+ if (unlikely((itr ^ dtr) & TARGET_PAGE_MASK)) {
+ if (need & PAGE_EXEC) {
+ dmr = dtr = 0;
+ } else {
+ imr = itr = 0;
}
}
- if ((rw & 2) && ((right & PAGE_EXEC) == 0)) {
- return TLBRET_BADADDR;
- }
- *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
- *prot = right;
- return TLBRET_MATCH;
-}
+ /* Check if either of the entries matches the source address. */
+ match = (imr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_EXEC;
+ match |= (dmr ^ addr) & TARGET_PAGE_MASK ? 0 : PAGE_READ | PAGE_WRITE;
-static int get_phys_data(OpenRISCCPU *cpu, hwaddr *physical, int *prot,
- target_ulong address, int rw, bool supervisor)
-{
- int vpn = address >> TARGET_PAGE_BITS;
- int idx = vpn & TLB_MASK;
- int right = 0;
- uint32_t mr = cpu->env.tlb.dtlb[idx].mr;
- uint32_t tr = cpu->env.tlb.dtlb[idx].tr;
+ /* Check if either of the entries is valid. */
+ valid = imr & 1 ? PAGE_EXEC : 0;
+ valid |= dmr & 1 ? PAGE_READ | PAGE_WRITE : 0;
+ valid &= match;
- if ((mr >> TARGET_PAGE_BITS) != vpn) {
- return TLBRET_NOMATCH;
- }
- if (!(mr & 1)) {
- return TLBRET_INVALID;
- }
- if (supervisor) {
- if (tr & SRE) {
- right |= PAGE_READ;
- }
- if (tr & SWE) {
- right |= PAGE_WRITE;
- }
- } else {
- if (tr & URE) {
- right |= PAGE_READ;
- }
- if (tr & UWE) {
- right |= PAGE_WRITE;
- }
- }
-
- if (!(rw & 1) && ((right & PAGE_READ) == 0)) {
- return TLBRET_BADADDR;
- }
- if ((rw & 1) && ((right & PAGE_WRITE) == 0)) {
- return TLBRET_BADADDR;
- }
+ /* Collect the permissions from the entries. */
+ right = itr & (super ? SXE : UXE) ? PAGE_EXEC : 0;
+ right |= dtr & (super ? SRE : URE) ? PAGE_READ : 0;
+ right |= dtr & (super ? SWE : UWE) ? PAGE_WRITE : 0;
+ right &= valid;
- *physical = (tr & TARGET_PAGE_MASK) | (address & ~TARGET_PAGE_MASK);
+ /* Note that above we validated that itr and dtr match on page.
+ So oring them together changes nothing without having to
+ check which one we needed. We also want to store to these
+ variables even on failure, as it avoids compiler warnings. */
+ *phys_addr = ((itr | dtr) & TARGET_PAGE_MASK) | (addr & ~TARGET_PAGE_MASK);
*prot = right;
- return TLBRET_MATCH;
-}
-static int get_phys_addr(OpenRISCCPU *cpu, hwaddr *physical,
- int *prot, target_ulong address, int rw)
-{
- bool supervisor = (cpu->env.sr & SR_SM) != 0;
- int ret;
+ qemu_log_mask(CPU_LOG_MMU,
+ "MMU lookup: need %d match %d valid %d right %d -> %s\n",
+ need, match, valid, right, (need & right) ? "OK" : "FAIL");
- /* Assume nommu results for a moment. */
- ret = get_phys_nommu(physical, prot, address);
+ /* Check the collective permissions are present. */
+ if (likely(need & right)) {
+ return 0; /* success! */
+ }
- /* Overwrite with TLB lookup if enabled. */
- if (rw == MMU_INST_FETCH) {
- if (cpu->env.sr & SR_IME) {
- ret = get_phys_code(cpu, physical, prot, address, rw, supervisor);
- }
+ /* Determine what kind of failure we have. */
+ if (need & valid) {
+ return need & PAGE_EXEC ? EXCP_IPF : EXCP_DPF;
} else {
- if (cpu->env.sr & SR_DME) {
- ret = get_phys_data(cpu, physical, prot, address, rw, supervisor);
- }
+ return need & PAGE_EXEC ? EXCP_ITLBMISS : EXCP_DTLBMISS;
}
-
- return ret;
}
#endif
-static void cpu_openrisc_raise_mmu_exception(OpenRISCCPU *cpu,
- target_ulong address,
- int rw, int tlb_error)
+static void raise_mmu_exception(OpenRISCCPU *cpu, target_ulong address,
+ int exception)
{
CPUState *cs = CPU(cpu);
- int exception = 0;
-
- switch (tlb_error) {
- default:
- if (rw == 2) {
- exception = EXCP_IPF;
- } else {
- exception = EXCP_DPF;
- }
- break;
-#ifndef CONFIG_USER_ONLY
- case TLBRET_BADADDR:
- if (rw == 2) {
- exception = EXCP_IPF;
- } else {
- exception = EXCP_DPF;
- }
- break;
- case TLBRET_INVALID:
- case TLBRET_NOMATCH:
- /* No TLB match for a mapped address */
- if (rw == 2) {
- exception = EXCP_ITLBMISS;
- } else {
- exception = EXCP_DTLBMISS;
- }
- break;
-#endif
- }
cs->exception_index = exception;
cpu->env.eear = address;
@@ -182,7 +112,7 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
{
#ifdef CONFIG_USER_ONLY
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- cpu_openrisc_raise_mmu_exception(cpu, address, rw, 0);
+ raise_mmu_exception(cpu, address, EXCP_DPF);
return 1;
#else
g_assert_not_reached();
@@ -193,27 +123,32 @@ int openrisc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size,
hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+ int prot, excp, sr = cpu->env.sr;
hwaddr phys_addr;
- int prot;
- int miss;
- /* Check memory for any kind of address, since during debug the
- gdb can ask for anything, check data tlb for address */
- miss = get_phys_addr(cpu, &phys_addr, &prot, addr, 0);
+ switch (sr & (SR_DME | SR_IME)) {
+ case SR_DME | SR_IME:
+ /* The mmu is definitely enabled. */
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+ PROT_EXEC | PROT_READ | PROT_WRITE,
+ (sr & SR_SM) != 0);
+ return excp ? -1 : phys_addr;
- /* Check instruction tlb */
- if (miss) {
- miss = get_phys_addr(cpu, &phys_addr, &prot, addr, MMU_INST_FETCH);
- }
-
- /* Last, fall back to a plain address */
- if (miss) {
- miss = get_phys_nommu(&phys_addr, &prot, addr);
- }
+ default:
+ /* The mmu is partially enabled, and we don't really have
+ a "real" access type. Begin by trying the mmu, but if
+ that fails try again without. */
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr,
+ PROT_EXEC | PROT_READ | PROT_WRITE,
+ (sr & SR_SM) != 0);
+ if (!excp) {
+ return phys_addr;
+ }
+ /* fallthru */
- if (miss) {
- return -1;
- } else {
+ case 0:
+ /* The mmu is definitely disabled; lookups never fail. */
+ get_phys_nommu(&phys_addr, &prot, addr);
return phys_addr;
}
}
@@ -222,37 +157,28 @@ void tlb_fill(CPUState *cs, target_ulong addr, int size,
MMUAccessType access_type, int mmu_idx, uintptr_t retaddr)
{
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
- int ret, prot = 0;
- hwaddr physical = 0;
+ int prot, excp;
+ hwaddr phys_addr;
if (mmu_idx == MMU_NOMMU_IDX) {
- ret = get_phys_nommu(&physical, &prot, addr);
+ /* The mmu is disabled; lookups never fail. */
+ get_phys_nommu(&phys_addr, &prot, addr);
+ excp = 0;
} else {
bool super = mmu_idx == MMU_SUPERVISOR_IDX;
- if (access_type == MMU_INST_FETCH) {
- ret = get_phys_code(cpu, &physical, &prot, addr, 2, super);
- } else {
- ret = get_phys_data(cpu, &physical, &prot, addr,
- access_type == MMU_DATA_STORE, super);
- }
+ int need = (access_type == MMU_INST_FETCH ? PROT_EXEC
+ : access_type == MMU_DATA_STORE ? PROT_WRITE
+ : PROT_READ);
+ excp = get_phys_mmu(cpu, &phys_addr, &prot, addr, need, super);
}
- if (ret == TLBRET_MATCH) {
- tlb_set_page(cs, addr & TARGET_PAGE_MASK,
- physical & TARGET_PAGE_MASK, prot,
- mmu_idx, TARGET_PAGE_SIZE);
- } else if (ret < 0) {
- int rw;
- if (access_type == MMU_INST_FETCH) {
- rw = 2;
- } else if (access_type == MMU_DATA_STORE) {
- rw = 1;
- } else {
- rw = 0;
- }
- cpu_openrisc_raise_mmu_exception(cpu, addr, rw, ret);
- /* Raise Exception. */
+ if (unlikely(excp)) {
+ raise_mmu_exception(cpu, addr, excp);
cpu_loop_exit_restore(cs, retaddr);
}
+
+ tlb_set_page(cs, addr & TARGET_PAGE_MASK,
+ phys_addr & TARGET_PAGE_MASK, prot,
+ mmu_idx, TARGET_PAGE_SIZE);
}
#endif
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (19 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc Stafford Horne
` (4 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Development, Richard Henderson, Stafford Horne, Riku Voipio,
Laurent Vivier
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
scripts/qemu-binfmt-conf.sh | 10 +++++++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh
index d7eefda0b8..a5cb96d79a 100755
--- a/scripts/qemu-binfmt-conf.sh
+++ b/scripts/qemu-binfmt-conf.sh
@@ -1,10 +1,10 @@
#!/bin/sh
-# enable automatic i386/ARM/M68K/MIPS/SPARC/PPC/s390/HPPA/Xtensa/microblaze
-# program execution by the kernel
+# Enable automatic program execution by the kernel.
qemu_target_list="i386 i486 alpha arm armeb sparc32plus ppc ppc64 ppc64le m68k \
mips mipsel mipsn32 mipsn32el mips64 mips64el \
-sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb microblaze microblazeel"
+sh4 sh4eb s390x aarch64 aarch64_be hppa riscv32 riscv64 xtensa xtensaeb \
+microblaze microblazeel or1k"
i386_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x03\x00'
i386_mask='\xff\xff\xff\xff\xff\xfe\xfe\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
@@ -124,6 +124,10 @@ microblazeel_magic='\x7fELF\x01\x01\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\
microblazeel_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff\xff'
microblazeel_family=microblazeel
+or1k_magic='\x7fELF\x01\x02\x01\x00\x00\x00\x00\x00\x00\x00\x00\x00\x00\x02\x00\x5c'
+or1k_mask='\xff\xff\xff\xff\xff\xff\xff\x00\xff\xff\xff\xff\xff\xff\xff\xff\xff\xfe\xff\xff'
+or1k_family=or1k
+
qemu_get_family() {
cpu=${HOST_ARCH:-$(uname -m)}
case "$cpu" in
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (20 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-03 22:34 ` Philippe Mathieu-Daudé
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 23/25] linux-user: Fix struct sigaltstack " Stafford Horne
` (3 subsequent siblings)
25 siblings, 1 reply; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Development, Richard Henderson, Stafford Horne, Riku Voipio,
Laurent Vivier
From: Richard Henderson <richard.henderson@linaro.org>
All of the existing code was boilerplate from elsewhere,
and would crash the guest upon the first signal.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
v2:
Add a comment to the new definition of target_pt_regs.
Install the signal mask into the ucontext.
v3:
Incorporate feedback from Laurent.
---
linux-user/openrisc/signal.c | 217 +++++++++++----------------
linux-user/openrisc/target_syscall.h | 28 +---
linux-user/signal.c | 2 +-
target/openrisc/cpu.c | 1 +
4 files changed, 94 insertions(+), 154 deletions(-)
diff --git a/linux-user/openrisc/signal.c b/linux-user/openrisc/signal.c
index 8be0b74001..232ad82b98 100644
--- a/linux-user/openrisc/signal.c
+++ b/linux-user/openrisc/signal.c
@@ -21,124 +21,69 @@
#include "signal-common.h"
#include "linux-user/trace.h"
-struct target_sigcontext {
+typedef struct target_sigcontext {
struct target_pt_regs regs;
abi_ulong oldmask;
- abi_ulong usp;
-};
+} target_sigcontext;
-struct target_ucontext {
+typedef struct target_ucontext {
abi_ulong tuc_flags;
abi_ulong tuc_link;
target_stack_t tuc_stack;
- struct target_sigcontext tuc_mcontext;
+ target_sigcontext tuc_mcontext;
target_sigset_t tuc_sigmask; /* mask last for extensibility */
-};
+} target_ucontext;
-struct target_rt_sigframe {
- abi_ulong pinfo;
- uint64_t puc;
+typedef struct target_rt_sigframe {
struct target_siginfo info;
- struct target_sigcontext sc;
- struct target_ucontext uc;
- unsigned char retcode[16]; /* trampoline code */
-};
-
-/* This is the asm-generic/ucontext.h version */
-#if 0
-static int restore_sigcontext(CPUOpenRISCState *regs,
- struct target_sigcontext *sc)
-{
- unsigned int err = 0;
- unsigned long old_usp;
-
- /* Alwys make any pending restarted system call return -EINTR */
- current_thread_info()->restart_block.fn = do_no_restart_syscall;
+ target_ucontext uc;
+ uint32_t retcode[4]; /* trampoline code */
+} target_rt_sigframe;
- /* restore the regs from &sc->regs (same as sc, since regs is first)
- * (sc is already checked for VERIFY_READ since the sigframe was
- * checked in sys_sigreturn previously)
- */
+static void restore_sigcontext(CPUOpenRISCState *env, target_sigcontext *sc)
+{
+ int i;
+ abi_ulong v;
- if (copy_from_user(regs, &sc, sizeof(struct target_pt_regs))) {
- goto badframe;
+ for (i = 0; i < 32; ++i) {
+ __get_user(v, &sc->regs.gpr[i]);
+ cpu_set_gpr(env, i, v);
}
+ __get_user(env->pc, &sc->regs.pc);
- /* make sure the U-flag is set so user-mode cannot fool us */
-
- regs->sr &= ~SR_SM;
-
- /* restore the old USP as it was before we stacked the sc etc.
- * (we cannot just pop the sigcontext since we aligned the sp and
- * stuff after pushing it)
- */
-
- __get_user(old_usp, &sc->usp);
- phx_signal("old_usp 0x%lx", old_usp);
-
- __PHX__ REALLY /* ??? */
- wrusp(old_usp);
- regs->gpr[1] = old_usp;
-
- /* TODO: the other ports use regs->orig_XX to disable syscall checks
- * after this completes, but we don't use that mechanism. maybe we can
- * use it now ?
- */
-
- return err;
-
-badframe:
- return 1;
+ /* Make sure the supervisor flag is clear. */
+ __get_user(v, &sc->regs.sr);
+ cpu_set_sr(env, v & ~SR_SM);
}
-#endif
/* Set up a signal frame. */
-static void setup_sigcontext(struct target_sigcontext *sc,
- CPUOpenRISCState *regs,
- unsigned long mask)
+static void setup_sigcontext(target_sigcontext *sc, CPUOpenRISCState *env)
{
- unsigned long usp = cpu_get_gpr(regs, 1);
-
- /* copy the regs. they are first in sc so we can use sc directly */
+ int i;
- /*copy_to_user(&sc, regs, sizeof(struct target_pt_regs));*/
-
- /* Set the frametype to CRIS_FRAME_NORMAL for the execution of
- the signal handler. The frametype will be restored to its previous
- value in restore_sigcontext. */
- /*regs->frametype = CRIS_FRAME_NORMAL;*/
-
- /* then some other stuff */
- __put_user(mask, &sc->oldmask);
- __put_user(usp, &sc->usp);
-}
+ for (i = 0; i < 32; ++i) {
+ __put_user(cpu_get_gpr(env, i), &sc->regs.gpr[i]);
+ }
-static inline unsigned long align_sigframe(unsigned long sp)
-{
- return sp & ~3UL;
+ __put_user(env->pc, &sc->regs.pc);
+ __put_user(cpu_get_sr(env), &sc->regs.sr);
}
static inline abi_ulong get_sigframe(struct target_sigaction *ka,
- CPUOpenRISCState *regs,
+ CPUOpenRISCState *env,
size_t frame_size)
{
- unsigned long sp = get_sp_from_cpustate(regs);
- int onsigstack = on_sig_stack(sp);
-
- /* redzone */
- sp = target_sigsp(sp, ka);
-
- sp = align_sigframe(sp - frame_size);
+ target_ulong sp = get_sp_from_cpustate(env);
- /*
- * If we are on the alternate signal stack and would overflow it, don't.
- * Return an always-bogus address instead so we will die with SIGSEGV.
+ /* Honor redzone now. If we swap to signal stack, no need to waste
+ * the 128 bytes by subtracting afterward.
*/
+ sp -= 128;
- if (onsigstack && !likely(on_sig_stack(sp))) {
- return -1L;
- }
+ sp = target_sigsp(sp, ka);
+ sp -= frame_size;
+ sp = QEMU_ALIGN_DOWN(sp, 4);
return sp;
}
@@ -147,11 +92,9 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
target_siginfo_t *info,
target_sigset_t *set, CPUOpenRISCState *env)
{
- int err = 0;
abi_ulong frame_addr;
- unsigned long return_ip;
- struct target_rt_sigframe *frame;
- abi_ulong info_addr, uc_addr;
+ target_rt_sigframe *frame;
+ int i;
frame_addr = get_sigframe(ka, env, sizeof(*frame));
trace_user_setup_rt_frame(env, frame_addr);
@@ -159,47 +102,37 @@ void setup_rt_frame(int sig, struct target_sigaction *ka,
goto give_sigsegv;
}
- info_addr = frame_addr + offsetof(struct target_rt_sigframe, info);
- __put_user(info_addr, &frame->pinfo);
- uc_addr = frame_addr + offsetof(struct target_rt_sigframe, uc);
- __put_user(uc_addr, &frame->puc);
-
if (ka->sa_flags & SA_SIGINFO) {
tswap_siginfo(&frame->info, info);
}
- /*err |= __clear_user(&frame->uc, offsetof(ucontext_t, uc_mcontext));*/
__put_user(0, &frame->uc.tuc_flags);
__put_user(0, &frame->uc.tuc_link);
- target_save_altstack(&frame->uc.tuc_stack, env);
- setup_sigcontext(&frame->sc, env, set->sig[0]);
- /*err |= copy_to_user(frame->uc.tuc_sigmask, set, sizeof(*set));*/
-
- /* trampoline - the desired return ip is the retcode itself */
- return_ip = (unsigned long)&frame->retcode;
- /* This is l.ori r11,r0,__NR_sigreturn, l.sys 1 */
- __put_user(0xa960, (short *)(frame->retcode + 0));
- __put_user(TARGET_NR_rt_sigreturn, (short *)(frame->retcode + 2));
- __put_user(0x20000001, (unsigned long *)(frame->retcode + 4));
- __put_user(0x15000000, (unsigned long *)(frame->retcode + 8));
-
- if (err) {
- goto give_sigsegv;
+ target_save_altstack(&frame->uc.tuc_stack, env);
+ setup_sigcontext(&frame->uc.tuc_mcontext, env);
+ for (i = 0; i < TARGET_NSIG_WORDS; ++i) {
+ __put_user(set->sig[i], &frame->uc.tuc_sigmask.sig[i]);
}
- /* TODO what is the current->exec_domain stuff and invmap ? */
+ /* This is l.ori r11,r0,__NR_sigreturn; l.sys 1; l.nop; l.nop */
+ __put_user(0xa9600000 | TARGET_NR_rt_sigreturn, frame->retcode + 0);
+ __put_user(0x20000001, frame->retcode + 1);
+ __put_user(0x15000000, frame->retcode + 2);
+ __put_user(0x15000000, frame->retcode + 3);
/* Set up registers for signal handler */
- env->pc = (unsigned long)ka->_sa_handler; /* what we enter NOW */
- cpu_set_gpr(env, 9, (unsigned long)return_ip); /* what we enter LATER */
- cpu_set_gpr(env, 3, (unsigned long)sig); /* arg 1: signo */
- cpu_set_gpr(env, 4, (unsigned long)&frame->info); /* arg 2: (siginfo_t*) */
- cpu_set_gpr(env, 5, (unsigned long)&frame->uc); /* arg 3: ucontext */
-
- /* actually move the usp to reflect the stacked frame */
- cpu_set_gpr(env, 1, (unsigned long)frame);
-
+ cpu_set_gpr(env, 9, frame_addr + offsetof(target_rt_sigframe, retcode));
+ cpu_set_gpr(env, 3, sig);
+ cpu_set_gpr(env, 4, frame_addr + offsetof(target_rt_sigframe, info));
+ cpu_set_gpr(env, 5, frame_addr + offsetof(target_rt_sigframe, uc));
+ cpu_set_gpr(env, 1, frame_addr);
+
+ /* For debugging convenience, set ppc to the insn that faulted. */
+ env->ppc = env->pc;
+ /* When setting the PC for the signal handler, exit delay slot. */
+ env->pc = ka->_sa_handler;
+ env->dflag = 0;
return;
give_sigsegv:
@@ -207,16 +140,34 @@ give_sigsegv:
force_sigsegv(sig);
}
-long do_sigreturn(CPUOpenRISCState *env)
-{
- trace_user_do_sigreturn(env, 0);
- fprintf(stderr, "do_sigreturn: not implemented\n");
- return -TARGET_ENOSYS;
-}
-
long do_rt_sigreturn(CPUOpenRISCState *env)
{
+ abi_ulong frame_addr = get_sp_from_cpustate(env);
+ target_rt_sigframe *frame;
+ sigset_t set;
+
trace_user_do_rt_sigreturn(env, 0);
- fprintf(stderr, "do_rt_sigreturn: not implemented\n");
- return -TARGET_ENOSYS;
+ if (!lock_user_struct(VERIFY_READ, frame, frame_addr, 1)) {
+ goto badframe;
+ }
+ if (frame_addr & 3) {
+ goto badframe;
+ }
+
+ target_to_host_sigset(&set, &frame->uc.tuc_sigmask);
+ set_sigmask(&set);
+
+ restore_sigcontext(env, &frame->uc.tuc_mcontext);
+ if (do_sigaltstack(frame_addr + offsetof(target_rt_sigframe, uc.tuc_stack),
+ 0, frame_addr) == -EFAULT) {
+ goto badframe;
+ }
+
+ unlock_user_struct(frame, frame_addr, 0);
+ return cpu_get_gpr(env, 11);
+
+ badframe:
+ unlock_user_struct(frame, frame_addr, 0);
+ force_sig(TARGET_SIGSEGV);
+ return 0;
}
diff --git a/linux-user/openrisc/target_syscall.h b/linux-user/openrisc/target_syscall.h
index 03104f80af..d586d2a018 100644
--- a/linux-user/openrisc/target_syscall.h
+++ b/linux-user/openrisc/target_syscall.h
@@ -1,27 +1,15 @@
#ifndef OPENRISC_TARGET_SYSCALL_H
#define OPENRISC_TARGET_SYSCALL_H
+/* Note that in linux/arch/openrisc/include/uapi/asm/ptrace.h,
+ * this is called user_regs_struct. Given that this is what
+ * is used within struct sigcontext we need this definition.
+ * However, elfload.c wants this name.
+ */
struct target_pt_regs {
- union {
- struct {
- /* Named registers */
- uint32_t sr; /* Stored in place of r0 */
- target_ulong sp; /* r1 */
- };
- struct {
- /* Old style */
- target_ulong offset[2];
- target_ulong gprs[30];
- };
- struct {
- /* New style */
- target_ulong gpr[32];
- };
- };
- target_ulong pc;
- target_ulong orig_gpr11; /* For restarting system calls */
- uint32_t syscallno; /* Syscall number (used by strace) */
- target_ulong dummy; /* Cheap alignment fix */
+ abi_ulong gpr[32];
+ abi_ulong pc;
+ abi_ulong sr;
};
#define UNAME_MACHINE "openrisc"
diff --git a/linux-user/signal.c b/linux-user/signal.c
index be2815b45d..602b631b92 100644
--- a/linux-user/signal.c
+++ b/linux-user/signal.c
@@ -236,7 +236,7 @@ int do_sigprocmask(int how, const sigset_t *set, sigset_t *oldset)
return 0;
}
-#if !defined(TARGET_OPENRISC) && !defined(TARGET_NIOS2)
+#if !defined(TARGET_NIOS2)
/* Just set the guest's signal mask to the specified value; the
* caller is assumed to have called block_signals() already.
*/
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index e01ce9ed1c..fb7cb5c507 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -27,6 +27,7 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
OpenRISCCPU *cpu = OPENRISC_CPU(cs);
cpu->env.pc = value;
+ cpu->env.dflag = 0;
}
static bool openrisc_cpu_has_work(CPUState *cs)
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 23/25] linux-user: Fix struct sigaltstack for openrisc
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (21 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 24/25] target/openrisc: Fix delay slot exception flag to match spec Stafford Horne
` (2 subsequent siblings)
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Development, Richard Henderson, Stafford Horne, Riku Voipio,
Laurent Vivier
From: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Laurent Vivier <laurent@vivier.eu>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
linux-user/openrisc/target_signal.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/linux-user/openrisc/target_signal.h b/linux-user/openrisc/target_signal.h
index c352a8b333..8283eaf544 100644
--- a/linux-user/openrisc/target_signal.h
+++ b/linux-user/openrisc/target_signal.h
@@ -5,8 +5,8 @@
typedef struct target_sigaltstack {
abi_long ss_sp;
+ abi_int ss_flags;
abi_ulong ss_size;
- abi_long ss_flags;
} target_stack_t;
/* sigaltstack controls */
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 24/25] target/openrisc: Fix delay slot exception flag to match spec
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (22 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 23/25] linux-user: Fix struct sigaltstack " Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 25/25] target/openrisc: Fix writes to interrupt mask register Stafford Horne
2018-07-02 15:36 ` [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Peter Maydell
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Stafford Horne
The delay slot exception flag is only set on the SR register during
exception. Previously it was being set on both the ESR and SR this
caused QEMU to differ from the spec. The was apparent as the linux
kernel had a bug where it could boot on QEMU but not on real hardware.
The fixed logic now matches hardware.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/interrupt.c | 19 ++++++++++++-------
1 file changed, 12 insertions(+), 7 deletions(-)
diff --git a/target/openrisc/interrupt.c b/target/openrisc/interrupt.c
index 138ad17f00..bbae956361 100644
--- a/target/openrisc/interrupt.c
+++ b/target/openrisc/interrupt.c
@@ -35,13 +35,6 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
int exception = cs->exception_index;
env->epcr = env->pc;
- if (env->dflag) {
- env->dflag = 0;
- env->sr |= SR_DSX;
- env->epcr -= 4;
- } else {
- env->sr &= ~SR_DSX;
- }
if (exception == EXCP_SYSCALL) {
env->epcr += 4;
}
@@ -51,7 +44,10 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->eear = env->pc;
}
+ /* During exceptions esr is populared with the pre-exception sr. */
env->esr = cpu_get_sr(env);
+ /* In parallel sr is updated to disable mmu, interrupts, timers and
+ set the delay slot exception flag. */
env->sr &= ~SR_DME;
env->sr &= ~SR_IME;
env->sr |= SR_SM;
@@ -61,6 +57,15 @@ void openrisc_cpu_do_interrupt(CPUState *cs)
env->pmr &= ~PMR_SME;
env->lock_addr = -1;
+ /* Set/clear dsx to indicate if we are in a delay slot exception. */
+ if (env->dflag) {
+ env->dflag = 0;
+ env->sr |= SR_DSX;
+ env->epcr -= 4;
+ } else {
+ env->sr &= ~SR_DSX;
+ }
+
if (exception > 0 && exception < EXCP_NR) {
static const char * const int_name[EXCP_NR] = {
[EXCP_RESET] = "RESET",
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* [Qemu-devel] [PULL v2 25/25] target/openrisc: Fix writes to interrupt mask register
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (23 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 24/25] target/openrisc: Fix delay slot exception flag to match spec Stafford Horne
@ 2018-07-02 15:10 ` Stafford Horne
2018-07-02 15:36 ` [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Peter Maydell
25 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-02 15:10 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development, Stafford Horne
The interrupt controller mask register (PICMR) allows writing any value
to any of the 32 interrupt mask bits. Writing a 0 masks the interrupt
writing a 1 unmasks (enables) the the interrupt.
For some reason the old code was or'ing the write values to the PICMR
meaning it was not possible to ever mask a interrupt once it was
enabled.
I have tested this by running linux 4.18 and my regular checks, I don't
see any issues.
Reported-by: Davidson Francis <davidsondfgl@gmail.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/sys_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c
index 541615bfb3..b66a45c1e0 100644
--- a/target/openrisc/sys_helper.c
+++ b/target/openrisc/sys_helper.c
@@ -142,7 +142,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
}
break;
case TO_SPR(9, 0): /* PICMR */
- env->picmr |= rb;
+ env->picmr = rb;
break;
case TO_SPR(9, 2): /* PICSR */
env->picsr &= ~rb;
--
2.17.0
^ permalink raw reply related [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
` (24 preceding siblings ...)
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 25/25] target/openrisc: Fix writes to interrupt mask register Stafford Horne
@ 2018-07-02 15:36 ` Peter Maydell
2018-07-03 13:53 ` Stafford Horne
25 siblings, 1 reply; 35+ messages in thread
From: Peter Maydell @ 2018-07-02 15:36 UTC (permalink / raw)
To: Stafford Horne; +Cc: QEMU Development
On 2 July 2018 at 16:09, Stafford Horne <shorne@gmail.com> wrote:
> Hi Peter,
>
> Changes since v1:
> - Un"fixed" an incorrect checkpatch warning pointed out by Richard.
>
> Please consider for pull.
>
> The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
>
> tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
>
> are available in the Git repository at:
>
> git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702
>
> for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:
>
> target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)
>
> ----------------------------------------------------------------
> OpenRISC cleanups and Fixes for QEMU 3.0
>
> Mostly patches from Richard Henderson fixing multiple things:
> * Fix singlestepping in GDB.
> * Use more TB linking.
> * Fixes to exit TB after updating SPRs to enable registering of state
> changes.
> * Significant optimizations and refactors to the TLB
> * Split out disassembly from translation.
> * Add qemu-or1k to qemu-binfmt-conf.sh.
> * Implement signal handling for linux-user.
>
> Then there are a few fixups from me:
> * Fix delay slot detections to match hardware, this was masking a bug
> in the linus kernel.
> * Fix stores to the PIC mask register
>
> ----------------------------------------------------------------
Compile failure, for the windows crossbuilds:
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c: In function
'openrisc_cpu_get_phys_page_debug':
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:29: error:
'PROT_EXEC' undeclared (first use in this function)
PROT_EXEC | PROT_READ | PROT_WRITE,
^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:29: note:
each undeclared identifier is reported only once for each function it
appears in
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:41: error:
'PROT_READ' undeclared (first use in this function)
PROT_EXEC | PROT_READ | PROT_WRITE,
^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:133:53: error:
'PROT_WRITE' undeclared (first use in this function)
PROT_EXEC | PROT_READ | PROT_WRITE,
^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c: In function 'tlb_fill':
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:169:53: error:
'PROT_EXEC' undeclared (first use in this function)
int need = (access_type == MMU_INST_FETCH ? PROT_EXEC
^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:170:55: error:
'PROT_WRITE' undeclared (first use in this function)
: access_type == MMU_DATA_STORE ? PROT_WRITE
^
/home/petmay01/qemu-for-merges/target/openrisc/mmu.c:171:23: error:
'PROT_READ' undeclared (first use in this function)
: PROT_READ);
^
/home/petmay01/qemu-for-merges/rules.mak:69: recipe for target
'target/openrisc/mmu.o' failed
PROT_READ/WRITE/EXEC are the Posix flags for mmap().
The flags for the 'prot' argument to tlb_set_page()
and similar places are PAGE_READ/WRITE/EXEC.
PS: for trivial respins of a pullreq you don't need to resend
the whole thing, you can just resend the cover letter (and
any individual patches which got major changes).
thanks
-- PMM
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0
2018-07-02 15:36 ` [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Peter Maydell
@ 2018-07-03 13:53 ` Stafford Horne
0 siblings, 0 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-03 13:53 UTC (permalink / raw)
To: Peter Maydell; +Cc: QEMU Development
On Mon, Jul 02, 2018 at 04:36:10PM +0100, Peter Maydell wrote:
> On 2 July 2018 at 16:09, Stafford Horne <shorne@gmail.com> wrote:
> > Hi Peter,
> >
> > Changes since v1:
> > - Un"fixed" an incorrect checkpatch warning pointed out by Richard.
> >
> > Please consider for pull.
> >
> > The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
> >
> > tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
> >
> > are available in the Git repository at:
> >
> > git@github.com:stffrdhrn/qemu.git tags/pull-or-20180702
> >
> > for you to fetch changes up to 33e1acf437ce4f0b67c262fc93b436e2e306f278:
> >
> > target/openrisc: Fix writes to interrupt mask register (2018-07-03 00:05:28 +0900)
> >
> > ----------------------------------------------------------------
> > OpenRISC cleanups and Fixes for QEMU 3.0
> >
> > Mostly patches from Richard Henderson fixing multiple things:
> > * Fix singlestepping in GDB.
> > * Use more TB linking.
> > * Fixes to exit TB after updating SPRs to enable registering of state
> > changes.
> > * Significant optimizations and refactors to the TLB
> > * Split out disassembly from translation.
> > * Add qemu-or1k to qemu-binfmt-conf.sh.
> > * Implement signal handling for linux-user.
> >
> > Then there are a few fixups from me:
> > * Fix delay slot detections to match hardware, this was masking a bug
> > in the linus kernel.
> > * Fix stores to the PIC mask register
> >
> > ----------------------------------------------------------------
>
> Compile failure, for the windows crossbuilds:
>
[...]
> /home/petmay01/qemu-for-merges/target/openrisc/mmu.c:171:23: error:
> 'PROT_READ' undeclared (first use in this function)
> : PROT_READ);
> ^
> /home/petmay01/qemu-for-merges/rules.mak:69: recipe for target
> 'target/openrisc/mmu.o' failed
>
> PROT_READ/WRITE/EXEC are the Posix flags for mmap().
> The flags for the 'prot' argument to tlb_set_page()
> and similar places are PAGE_READ/WRITE/EXEC.
Understood, this should be fixed now, after changing I see no differences.
> PS: for trivial respins of a pullreq you don't need to resend
> the whole thing, you can just resend the cover letter (and
> any individual patches which got major changes).
Thats good to know, I thought it might be annoying to resend the entire series
when all that is needed is the pr cover letter.
I have resent, I hope all is well.
-Stafford
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc Stafford Horne
@ 2018-07-03 22:34 ` Philippe Mathieu-Daudé
2018-07-03 23:51 ` Stafford Horne
0 siblings, 1 reply; 35+ messages in thread
From: Philippe Mathieu-Daudé @ 2018-07-03 22:34 UTC (permalink / raw)
To: Stafford Horne, Peter Maydell
Cc: Riku Voipio, Richard Henderson, QEMU Development, Laurent Vivier
Hi Stafford,
On 07/02/2018 12:10 PM, Stafford Horne wrote:
> From: Richard Henderson <richard.henderson@linaro.org>
>
> All of the existing code was boilerplate from elsewhere,
> and would crash the guest upon the first signal.
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Stafford Horne <shorne@gmail.com>
>
> ---
> v2:
> Add a comment to the new definition of target_pt_regs.
> Install the signal mask into the ucontext.
> v3:
> Incorporate feedback from Laurent.
Oops this is not supposed to enter git history, something is wrong with
your pull request script.
> ---
> linux-user/openrisc/signal.c | 217 +++++++++++----------------
> linux-user/openrisc/target_syscall.h | 28 +---
> linux-user/signal.c | 2 +-
> target/openrisc/cpu.c | 1 +
> 4 files changed, 94 insertions(+), 154 deletions(-)
<snip>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-03 22:34 ` Philippe Mathieu-Daudé
@ 2018-07-03 23:51 ` Stafford Horne
2018-07-04 20:54 ` Richard Henderson
2018-07-07 7:04 ` Alex Bennée
0 siblings, 2 replies; 35+ messages in thread
From: Stafford Horne @ 2018-07-03 23:51 UTC (permalink / raw)
To: Philippe Mathieu-Daudé
Cc: Peter Maydell, Riku Voipio, Richard Henderson,
qemu-devel qemu-devel, Laurent Vivier
Hello,
On Wed, Jul 4, 2018, 7:34 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
> Hi Stafford,
>
> On 07/02/2018 12:10 PM, Stafford Horne wrote:
> > From: Richard Henderson <richard.henderson@linaro.org>
> >
> > All of the existing code was boilerplate from elsewhere,
> > and would crash the guest upon the first signal.
> >
> > Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> > Signed-off-by: Stafford Horne <shorne@gmail.com>
> >
> > ---
> > v2:
> > Add a comment to the new definition of target_pt_regs.
> > Install the signal mask into the ucontext.
> > v3:
> > Incorporate feedback from Laurent.
>
> Oops this is not supposed to enter git history, something is wrong with
> your pull request script.
>
Sorry, I brought these in from Richards tree and saw them but thought it
was fine to keep the annotations.
I'll remove them from patches in the future.
Richard, how do you usually remove these before your pr? I suppose you
have some kind of script?
-stafford
> > ---
> > linux-user/openrisc/signal.c | 217 +++++++++++----------------
> > linux-user/openrisc/target_syscall.h | 28 +---
> > linux-user/signal.c | 2 +-
> > target/openrisc/cpu.c | 1 +
> > 4 files changed, 94 insertions(+), 154 deletions(-)
>
> <snip>
>
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-03 23:51 ` Stafford Horne
@ 2018-07-04 20:54 ` Richard Henderson
2018-07-06 22:22 ` Eric Blake
2018-07-07 7:04 ` Alex Bennée
1 sibling, 1 reply; 35+ messages in thread
From: Richard Henderson @ 2018-07-04 20:54 UTC (permalink / raw)
To: Stafford Horne, Philippe Mathieu-Daudé
Cc: Peter Maydell, Riku Voipio, qemu-devel qemu-devel, Laurent Vivier
On 07/03/2018 04:51 PM, Stafford Horne wrote:
> Richard, how do you usually remove these before your pr? I suppose you have
> some kind of script?
No, I just edit the things by hand.
r~
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-04 20:54 ` Richard Henderson
@ 2018-07-06 22:22 ` Eric Blake
2018-07-06 23:02 ` Stafford Horne
0 siblings, 1 reply; 35+ messages in thread
From: Eric Blake @ 2018-07-06 22:22 UTC (permalink / raw)
To: Richard Henderson, Stafford Horne, Philippe Mathieu-Daudé
Cc: Peter Maydell, Riku Voipio, qemu-devel qemu-devel, Laurent Vivier
On 07/04/2018 03:54 PM, Richard Henderson wrote:
> On 07/03/2018 04:51 PM, Stafford Horne wrote:
>> Richard, how do you usually remove these before your pr? I suppose you have
>> some kind of script?
>
> No, I just edit the things by hand.
I do it by always using 'git am' to suck in patches from the mailing
list, including my own patches, and even if I already have the patch
locally. That is, my workflow for PR bypasses my local work tree to
ensure I don't leave local artifacts around in the PR.
--
Eric Blake, Principal Software Engineer
Red Hat, Inc. +1-919-301-3266
Virtualization: qemu.org | libvirt.org
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-06 22:22 ` Eric Blake
@ 2018-07-06 23:02 ` Stafford Horne
2018-07-07 8:10 ` Laurent Vivier
0 siblings, 1 reply; 35+ messages in thread
From: Stafford Horne @ 2018-07-06 23:02 UTC (permalink / raw)
To: Eric Blake
Cc: Richard Henderson, Philippe Mathieu-Daudé,
Peter Maydell, Riku Voipio, qemu-devel qemu-devel,
Laurent Vivier
On Fri, Jul 06, 2018 at 05:22:15PM -0500, Eric Blake wrote:
> On 07/04/2018 03:54 PM, Richard Henderson wrote:
> > On 07/03/2018 04:51 PM, Stafford Horne wrote:
> > > Richard, how do you usually remove these before your pr? I suppose you have
> > > some kind of script?
> >
> > No, I just edit the things by hand.
>
> I do it by always using 'git am' to suck in patches from the mailing list,
> including my own patches, and even if I already have the patch locally.
> That is, my workflow for PR bypasses my local work tree to ensure I don't
> leave local artifacts around in the PR.
Hi Eric,
How do you carry the Change list for each patch brought in with 'git am' i.e.
v2,v3 when you have updates that need respin? Do you just update that manually
on the .patch files after 'git format-patch'?
I found and tried `git notes` recently which seems to be meant for this.
>From 'git help notes'
Notes can also be added to patches prepared with git format-patch by
using the --notes option. Such notes are added as a patch commentary
after a three dash separator line.
However, I found the notes get lots pretty easily during rebases and would not
survive a 'git am'.
I am sure many have their own methods that work. So far I have been doing
manually just updating the .patch files after 'format-patch'.
-Stafford
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-03 23:51 ` Stafford Horne
2018-07-04 20:54 ` Richard Henderson
@ 2018-07-07 7:04 ` Alex Bennée
1 sibling, 0 replies; 35+ messages in thread
From: Alex Bennée @ 2018-07-07 7:04 UTC (permalink / raw)
To: Stafford Horne
Cc: Philippe Mathieu-Daudé,
Peter Maydell, Riku Voipio, Richard Henderson,
qemu-devel qemu-devel, Laurent Vivier
Stafford Horne <shorne@gmail.com> writes:
> Hello,
>
> On Wed, Jul 4, 2018, 7:34 AM Philippe Mathieu-Daudé <f4bug@amsat.org> wrote:
>
>> Hi Stafford,
>>
>> On 07/02/2018 12:10 PM, Stafford Horne wrote:
>> > From: Richard Henderson <richard.henderson@linaro.org>
<snip>
>
> Sorry, I brought these in from Richards tree and saw them but thought it
> was fine to keep the annotations.
>
> I'll remove them from patches in the future.
>
> Richard, how do you usually remove these before your pr? I suppose you
> have some kind of script?
>
For reference these are my exact-steps:
We need to ensure we have added our signoff and there is no ---
ephemera left from commit history.
,----
| errors=0
| commits=0
| while read rev; do
| author=$(git show -s --format='%an <%ae>' $rev)
| body=$(git show -s --format='%B' $rev)
|
| # Check for Author signoff
| if ! grep -q "^Signed-off-by: $author" <<< "$body"; then
| errors=$((errors+1))
| echo "$rev missing signoff by $author"
| fi
|
| # Check for my signoff
| if ! grep -q "^Signed-off-by: $signoff" <<< "$body"; then
| errors=$((errors+1))
| echo "$rev missing your signoff ($signoff)"
| fi
|
| # Check for stray history
| if grep -q "^--" <<< "$body"; then
| errors=$((errors+1))
| echo "$rev may have history in it"
| fi
|
| commits=$((commits+1))
| done < <(git rev-list "origin/master..HEAD")
|
| echo "Found $errors errors over $commits commits"
`----
If we want to strip history we can run the following:
,----
| current=$(git rev-parse --abbrev-ref HEAD)
| if [ -d "${series}.pull" ]; then
| rm -rf ${series}.pull
| fi
| git format-patch origin/master..${current} -p -o ${series}.pull
| prb=${current}-pr
| echo ${prb}
| git checkout -b ${prb} origin/master
| git am ${series}.pull/*
| rm -rf ${series}.pull
`----
--
Alex Bennée
^ permalink raw reply [flat|nested] 35+ messages in thread
* Re: [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc
2018-07-06 23:02 ` Stafford Horne
@ 2018-07-07 8:10 ` Laurent Vivier
0 siblings, 0 replies; 35+ messages in thread
From: Laurent Vivier @ 2018-07-07 8:10 UTC (permalink / raw)
To: Stafford Horne, Eric Blake
Cc: Richard Henderson, Philippe Mathieu-Daudé,
Peter Maydell, Riku Voipio, qemu-devel qemu-devel
Le 07/07/2018 à 01:02, Stafford Horne a écrit :
> On Fri, Jul 06, 2018 at 05:22:15PM -0500, Eric Blake wrote:
>> On 07/04/2018 03:54 PM, Richard Henderson wrote:
>>> On 07/03/2018 04:51 PM, Stafford Horne wrote:
>>>> Richard, how do you usually remove these before your pr? I suppose you have
>>>> some kind of script?
>>>
>>> No, I just edit the things by hand.
>>
>> I do it by always using 'git am' to suck in patches from the mailing list,
>> including my own patches, and even if I already have the patch locally.
>> That is, my workflow for PR bypasses my local work tree to ensure I don't
>> leave local artifacts around in the PR.
>
> Hi Eric,
>
> How do you carry the Change list for each patch brought in with 'git am' i.e.
> v2,v3 when you have updates that need respin? Do you just update that manually
> on the .patch files after 'git format-patch'?
>
> I found and tried `git notes` recently which seems to be meant for this.
>
> From 'git help notes'
>
> Notes can also be added to patches prepared with git format-patch by
> using the --notes option. Such notes are added as a patch commentary
> after a three dash separator line.
>
> However, I found the notes get lots pretty easily during rebases and would not
> survive a 'git am'.
You need to set notes.rewriteref=refs/notes/commits
Thanks,
Laurent
^ permalink raw reply [flat|nested] 35+ messages in thread
end of thread, other threads:[~2018-07-07 8:10 UTC | newest]
Thread overview: 35+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-02 15:09 [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Stafford Horne
2018-07-02 15:09 ` [Qemu-devel] [PULL v2 01/25] target/openrisc: Fix mtspr shadow gprs Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 02/25] target/openrisc: Add print_insn_or1k Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 03/25] target/openrisc: Log interrupts Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 04/25] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 05/25] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 06/25] target/openrisc: Fix singlestep_enabled Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 07/25] target/openrisc: Link more translation blocks Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 08/25] target/openrisc: Split out is_user Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 09/25] target/openrisc: Exit the TB after l.mtspr Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 10/25] target/openrisc: Form the spr index from tcg Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 11/25] target/openrisc: Merge tlb allocation into CPUOpenRISCState Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 12/25] target/openrisc: Remove indirect function calls for mmu Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 13/25] target/openrisc: Merge mmu_helper.c into mmu.c Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 14/25] target/openrisc: Reduce tlb to a single dimension Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 15/25] target/openrisc: Fix tlb flushing in mtspr Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 16/25] target/openrisc: Fix cpu_mmu_index Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 17/25] target/openrisc: Use identical sizes for ITLB and DTLB Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 18/25] target/openrisc: Stub out handle_mmu_fault for softmmu Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 19/25] target/openrisc: Increase the TLB size Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 20/25] target/openrisc: Reorg tlb lookup Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 21/25] target/openrisc: Add support in scripts/qemu-binfmt-conf.sh Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 22/25] linux-user: Implement signals for openrisc Stafford Horne
2018-07-03 22:34 ` Philippe Mathieu-Daudé
2018-07-03 23:51 ` Stafford Horne
2018-07-04 20:54 ` Richard Henderson
2018-07-06 22:22 ` Eric Blake
2018-07-06 23:02 ` Stafford Horne
2018-07-07 8:10 ` Laurent Vivier
2018-07-07 7:04 ` Alex Bennée
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 23/25] linux-user: Fix struct sigaltstack " Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 24/25] target/openrisc: Fix delay slot exception flag to match spec Stafford Horne
2018-07-02 15:10 ` [Qemu-devel] [PULL v2 25/25] target/openrisc: Fix writes to interrupt mask register Stafford Horne
2018-07-02 15:36 ` [Qemu-devel] [PULL v2 00/25] OpenRISC updates for 3.0 Peter Maydell
2018-07-03 13:53 ` Stafford Horne
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