From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Yixun Lan <yixun.lan@amlogic.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>,
Neil Armstrong <narmstrong@baylibre.com>,
Kevin Hilman <khilman@baylibre.com>,
Carlo Caione <carlo@caione.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Liang Yang <liang.yang@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Jian Hu <jian.hu@amlogic.com>, <linux-clk@vger.kernel.org>,
<linux-amlogic@lists.infradead.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>
Subject: Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs
Date: Tue, 3 Jul 2018 09:21:07 +0200 [thread overview]
Message-ID: <20180703092107.51497a8f@bbrezillon> (raw)
In-Reply-To: <20180703145716.31860-3-yixun.lan@amlogic.com>
On Tue, 3 Jul 2018 14:57:15 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:
> Add two clock bindings IDs which provided by the EMMC clock controller,
> These two clocks will be used by EMMC or NAND driver.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>
> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> new file mode 100644
> index 000000000000..d9972c400e58
> --- /dev/null
> +++ b/include/dt-bindings/clock/emmc-clkc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Meson EMMC sub clock tree IDs
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __EMMC_CLKC_H
> +#define __EMMC_CLKC_H
> +
> +#define CLKID_EMMC_C_MUX 0
Looks like the MUX clk is the parent of the DIV one, and I guess the clk
driver is able to select the best parent+div pair for a requested rate.
Do you really need to expose the MUX to users?
> +#define CLKID_EMMC_C_DIV 1
> +
> +#endif
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Yixun Lan <yixun.lan@amlogic.com>
Cc: Rob Herring <robh@kernel.org>,
devicetree@vger.kernel.org,
Neil Armstrong <narmstrong@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Kevin Hilman <khilman@baylibre.com>,
Michael Turquette <mturquette@baylibre.com>,
linux-kernel@vger.kernel.org,
Martin Blumenstingl <martin.blumenstingl@googlemail.com>,
Jian Hu <jian.hu@amlogic.com>,
Liang Yang <liang.yang@amlogic.com>,
Qiufang Dai <qiufang.dai@amlogic.com>,
Miquel Raynal <miquel.raynal@bootlin.com>,
Carlo Caione <carlo@caione.org>,
linux-amlogic@lists.infradead.org, linux-clk@vger.kernel.org,
linux-arm-kernel@lists.infradead.org,
Jerome Brunet <jbrunet@baylibre.com>
Subject: Re: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs
Date: Tue, 3 Jul 2018 09:21:07 +0200 [thread overview]
Message-ID: <20180703092107.51497a8f@bbrezillon> (raw)
In-Reply-To: <20180703145716.31860-3-yixun.lan@amlogic.com>
On Tue, 3 Jul 2018 14:57:15 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:
> Add two clock bindings IDs which provided by the EMMC clock controller,
> These two clocks will be used by EMMC or NAND driver.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>
> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> new file mode 100644
> index 000000000000..d9972c400e58
> --- /dev/null
> +++ b/include/dt-bindings/clock/emmc-clkc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Meson EMMC sub clock tree IDs
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __EMMC_CLKC_H
> +#define __EMMC_CLKC_H
> +
> +#define CLKID_EMMC_C_MUX 0
Looks like the MUX clk is the parent of the DIV one, and I guess the clk
driver is able to select the best parent+div pair for a requested rate.
Do you really need to expose the MUX to users?
> +#define CLKID_EMMC_C_DIV 1
> +
> +#endif
WARNING: multiple messages have this Message-ID (diff)
From: boris.brezillon@bootlin.com (Boris Brezillon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs
Date: Tue, 3 Jul 2018 09:21:07 +0200 [thread overview]
Message-ID: <20180703092107.51497a8f@bbrezillon> (raw)
In-Reply-To: <20180703145716.31860-3-yixun.lan@amlogic.com>
On Tue, 3 Jul 2018 14:57:15 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:
> Add two clock bindings IDs which provided by the EMMC clock controller,
> These two clocks will be used by EMMC or NAND driver.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>
> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> new file mode 100644
> index 000000000000..d9972c400e58
> --- /dev/null
> +++ b/include/dt-bindings/clock/emmc-clkc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Meson EMMC sub clock tree IDs
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __EMMC_CLKC_H
> +#define __EMMC_CLKC_H
> +
> +#define CLKID_EMMC_C_MUX 0
Looks like the MUX clk is the parent of the DIV one, and I guess the clk
driver is able to select the best parent+div pair for a requested rate.
Do you really need to expose the MUX to users?
> +#define CLKID_EMMC_C_DIV 1
> +
> +#endif
WARNING: multiple messages have this Message-ID (diff)
From: boris.brezillon@bootlin.com (Boris Brezillon)
To: linus-amlogic@lists.infradead.org
Subject: [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs
Date: Tue, 3 Jul 2018 09:21:07 +0200 [thread overview]
Message-ID: <20180703092107.51497a8f@bbrezillon> (raw)
In-Reply-To: <20180703145716.31860-3-yixun.lan@amlogic.com>
On Tue, 3 Jul 2018 14:57:15 +0000
Yixun Lan <yixun.lan@amlogic.com> wrote:
> Add two clock bindings IDs which provided by the EMMC clock controller,
> These two clocks will be used by EMMC or NAND driver.
>
> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com>
> ---
> include/dt-bindings/clock/emmc-clkc.h | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
> create mode 100644 include/dt-bindings/clock/emmc-clkc.h
>
> diff --git a/include/dt-bindings/clock/emmc-clkc.h b/include/dt-bindings/clock/emmc-clkc.h
> new file mode 100644
> index 000000000000..d9972c400e58
> --- /dev/null
> +++ b/include/dt-bindings/clock/emmc-clkc.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
> +/*
> + * Meson EMMC sub clock tree IDs
> + *
> + * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
> + */
> +
> +#ifndef __EMMC_CLKC_H
> +#define __EMMC_CLKC_H
> +
> +#define CLKID_EMMC_C_MUX 0
Looks like the MUX clk is the parent of the DIV one, and I guess the clk
driver is able to select the best parent+div pair for a requested rate.
Do you really need to expose the MUX to users?
> +#define CLKID_EMMC_C_DIV 1
> +
> +#endif
next prev parent reply other threads:[~2018-07-03 7:22 UTC|newest]
Thread overview: 65+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-03 14:57 [PATCH 0/3] clk: meson: add a sub EMMC clock controller support Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 7:17 ` Boris Brezillon
2018-07-03 7:17 ` Boris Brezillon
2018-07-03 7:17 ` Boris Brezillon
2018-07-03 7:17 ` Boris Brezillon
2018-07-03 14:57 ` [PATCH 1/3] clk: meson: add DT documentation for emmc clock controller Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 8:16 ` Jerome Brunet
2018-07-03 8:16 ` Jerome Brunet
2018-07-03 8:16 ` Jerome Brunet
2018-07-03 8:16 ` Jerome Brunet
2018-07-03 9:59 ` Yixun Lan
2018-07-03 9:59 ` Yixun Lan
2018-07-03 9:59 ` Yixun Lan
2018-07-03 9:59 ` Yixun Lan
2018-07-03 14:57 ` [PATCH 2/3] clk: meson: add sub EMMC clock dt-bindings IDs Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 7:21 ` Boris Brezillon [this message]
2018-07-03 7:21 ` Boris Brezillon
2018-07-03 7:21 ` Boris Brezillon
2018-07-03 7:21 ` Boris Brezillon
2018-07-03 7:36 ` Yixun Lan
2018-07-03 7:36 ` Yixun Lan
2018-07-03 7:36 ` Yixun Lan
2018-07-03 7:36 ` Yixun Lan
2018-07-03 8:09 ` Jerome Brunet
2018-07-03 8:09 ` Jerome Brunet
2018-07-03 8:09 ` Jerome Brunet
2018-07-03 8:09 ` Jerome Brunet
2018-07-03 9:56 ` Yixun Lan
2018-07-03 9:56 ` Yixun Lan
2018-07-03 9:56 ` Yixun Lan
2018-07-03 9:56 ` Yixun Lan
2018-07-03 10:01 ` Jerome Brunet
2018-07-03 10:01 ` Jerome Brunet
2018-07-03 10:01 ` Jerome Brunet
2018-07-03 10:01 ` Jerome Brunet
2018-07-03 14:57 ` [PATCH 3/3] clk: meson: add sub EMMC clock controller driver Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 14:57 ` Yixun Lan
2018-07-03 8:51 ` Jerome Brunet
2018-07-03 8:51 ` Jerome Brunet
2018-07-03 8:51 ` Jerome Brunet
2018-07-03 8:51 ` Jerome Brunet
2018-07-03 9:56 ` Yixun Lan
2018-07-03 9:56 ` Yixun Lan
2018-07-03 9:56 ` Yixun Lan
2018-07-03 18:58 ` Martin Blumenstingl
2018-07-03 18:58 ` Martin Blumenstingl
2018-07-03 18:58 ` Martin Blumenstingl
2018-07-04 7:17 ` Yixun Lan
2018-07-04 7:17 ` Yixun Lan
2018-07-04 7:17 ` Yixun Lan
2018-07-04 7:17 ` Yixun Lan
2018-07-04 8:07 ` Jerome Brunet
2018-07-04 8:07 ` Jerome Brunet
2018-07-04 8:07 ` Jerome Brunet
2018-07-04 8:07 ` Jerome Brunet
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