[U-Boot] [PATCH v3 0/7] LS1046A SMMU enabling patches

[U-Boot] [PATCH v3 0/7] LS1046A SMMU enabling patches

[Laurentiu Tudor]

This patch series adds the required devices setup and device tree
fixups for SMMU enablement on LS1046A chips. The approach taken tries
to mimic the implementation of PAMU LIODN setup on booke powerpc.

First 4 patches contain some fixes and add some missing bits & pieces.
Last 3 patches add the actual infrastructure for ICID setup, qman
portal and fman ICID configuration.

Changes in v3:
 - cleaner QMAN_BAR setup
 - moved SoC specific bits from generic ICID arch setup to board code

Changes in v2:
 - drop CONFIG_SYS_ prefix from newly introduced defines in patch [1/7]

Laurentiu Tudor (7):
  armv8: fsl-layerscape: add missing register blocks base address
    defines
  armv8: ls1046a: advertise QMan v3 in configuration
  misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms
  armv8: fsl-layerscape: add missing debug stream ID
  armv8: ls1046a: initial icid setup support
  armv8: ls1046a: add icid setup for qman portals
  armv8: ls1046a: setup fman ports ICIDs and device tree

 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 193 ++++++++++++++++++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  75 +++++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
 .../include/asm/arch-fsl-layerscape/config.h  |   1 +
 .../asm/arch-fsl-layerscape/fsl_icid.h        |  90 ++++++++
 .../asm/arch-fsl-layerscape/fsl_portals.h     |  23 +++
 .../asm/arch-fsl-layerscape/immap_lsch2.h     |   7 +-
 .../asm/arch-fsl-layerscape/stream_id_lsch2.h |   1 +
 board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
 board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
 drivers/misc/fsl_portals.c                    |  45 +++-
 12 files changed, 432 insertions(+), 12 deletions(-)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h

-- 
2.17.1

[U-Boot] [PATCH v3 1/7] armv8: fsl-layerscape: add missing register blocks base address defines

[Laurentiu Tudor]

Add defines for the edma and qdma register block base addresses.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 5b4767e0fe..644a16dd30 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -88,8 +88,12 @@
 
 #define LPUART_BASE				(CONFIG_SYS_IMMR + 0x01950000)
 
+#define EDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x01c00000)
+
 #define AHCI_BASE_ADDR				(CONFIG_SYS_IMMR + 0x02200000)
 
+#define QDMA_BASE_ADDR				(CONFIG_SYS_IMMR + 0x07380000)
+
 #define CONFIG_SYS_PCIE1_PHYS_ADDR		0x4000000000ULL
 #define CONFIG_SYS_PCIE2_PHYS_ADDR		0x4800000000ULL
 #define CONFIG_SYS_PCIE3_PHYS_ADDR		0x5000000000ULL
-- 
2.17.1

[U-Boot] [PATCH v3 2/7] armv8: ls1046a: advertise QMan v3 in configuration

[Laurentiu Tudor]

The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 23faffd9fc..8a05148136 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -257,6 +257,7 @@
 
 #elif defined(CONFIG_ARCH_LS1046A)
 #define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
 #define CONFIG_SYS_NUM_FMAN			1
 #define CONFIG_SYS_NUM_FM1_DTSEC		8
 #define CONFIG_SYS_NUM_FM1_10GEC		2
-- 
2.17.1

[U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms

[Laurentiu Tudor]

QMAN_BAR{E} register setup was disabled on ARM platforms, however the
register does need to be set. Enable the code also on ARMs and fix the
CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the newly
enabled code works.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
 drivers/misc/fsl_portals.c                             | 2 --
 2 files changed, 1 insertion(+), 4 deletions(-)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index 644a16dd30..d22ec70aa5 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -57,8 +57,7 @@
 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
 #define CONFIG_SYS_QMAN_NUM_PORTALS	10
 #define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
-#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
-						CONFIG_SYS_QMAN_MEM_BASE)
+#define CONFIG_SYS_QMAN_MEM_PHYS	CONFIG_SYS_QMAN_MEM_BASE
 #define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 7c22b8d209..22faf16751 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -24,7 +24,6 @@ void setup_qbman_portals(void)
 				CONFIG_SYS_BMAN_SWP_ISDR_REG;
 	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
 				CONFIG_SYS_QMAN_SWP_ISDR_REG;
-#ifdef CONFIG_PPC
 	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
 
 	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */
@@ -32,7 +31,6 @@ void setup_qbman_portals(void)
 	out_be32(&qman->qcsp_bare, (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
 #endif
 	out_be32(&qman->qcsp_bar, (u32)CONFIG_SYS_QMAN_MEM_PHYS);
-#endif
 #ifdef CONFIG_FSL_CORENET
 	int i;
 
-- 
2.17.1

[U-Boot] [PATCH v3 4/7] armv8: fsl-layerscape: add missing debug stream ID

[Laurentiu Tudor]

Add a define with a value for the missing debug stream ID.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
index 61c6e533c6..1b02d484d9 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h
@@ -50,6 +50,7 @@
 #define FSL_QDMA_STREAM_ID		7
 #define FSL_EDMA_STREAM_ID		8
 #define FSL_ETR_STREAM_ID		9
+#define FSL_DEBUG_STREAM_ID		10
 
 /* PCI - programmed in PEXn_LUT */
 #define FSL_PEX_STREAM_ID_START		11
-- 
2.17.1

[U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support

[Laurentiu Tudor]

Add infrastructure for ICID setup and device tree
fixup on ARM platforms. This include basic ICID setup
for several devices.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
 arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 111 ++++++++++++++++++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +++++
 arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
 .../asm/arch-fsl-layerscape/fsl_icid.h        |  80 +++++++++++++
 board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
 board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
 7 files changed, 229 insertions(+)
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
 create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 1e9e4680fe..5d6f68aad6 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -37,6 +37,7 @@ endif
 
 ifneq ($(CONFIG_ARCH_LS1046A),)
 obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
+obj-y += icid.o ls1046_ids.o
 endif
 
 ifneq ($(CONFIG_ARCH_LS1088A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
new file mode 100644
index 0000000000..8694bd6fa1
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -0,0 +1,111 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <linux/libfdt.h>
+#include <fdt_support.h>
+
+#include <asm/io.h>
+#include <asm/processor.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+static void set_icid(struct icid_id_table *tbl, int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++)
+		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
+}
+
+void set_icids(void)
+{
+	/* setup general icid offsets */
+	set_icid(icid_tbl, icid_tbl_sz);
+}
+
+int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
+{
+	int i, ret;
+	u32 prop[8];
+
+	for (i = 0; i < num_ids; i++) {
+		prop[i * 2] = cpu_to_fdt32(smmu_ph);
+		prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
+	}
+	ret = fdt_setprop(blob, off, "iommus",
+			  prop, sizeof(u32) * num_ids * 2);
+	if (ret > 0) {
+		printf("WARNING unable to set iommus: %s\n", fdt_strerror(off));
+		return off;
+	}
+	ret = fdt_setprop_empty(blob, off, "dma-coherent");
+	if (ret > 0) {
+		printf("WARNING unable to set dma-coherent: %s\n",
+		       fdt_strerror(off));
+		return off;
+	}
+
+	return 0;
+}
+
+int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
+		       struct icid_id_table *tbl, int size)
+{
+	int i, err, off;
+
+	for (i = 0; i < size; i++) {
+		if (!tbl[i].compat)
+			continue;
+
+		off = fdt_node_offset_by_compat_reg(blob,
+						    tbl[i].compat,
+						    tbl[i].compat_addr);
+		if (off > 0) {
+			err = fdt_set_iommu_prop(blob, off, smmu_ph,
+						 &tbl[i].id, 1);
+			if (err)
+				return err;
+		} else {
+			printf("WARNING could not find node %s: %s.\n",
+			       tbl[i].compat, fdt_strerror(off));
+		}
+	}
+
+	return 0;
+}
+
+int fdt_get_smmu_phandle(void *blob)
+{
+	int noff, smmu_ph;
+
+	noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
+	if (noff < 0) {
+		printf("WARNING failed to get smmu node: %s\n",
+		       fdt_strerror(noff));
+		return noff;
+	}
+
+	smmu_ph = fdt_get_phandle(blob, noff);
+	if (!smmu_ph) {
+		smmu_ph = fdt_create_phandle(blob, noff);
+		if (!smmu_ph) {
+			printf("WARNING failed to get smmu phandle\n");
+			return -1;
+		}
+	}
+
+	return smmu_ph;
+}
+
+void fdt_fixup_icid(void *blob)
+{
+	int smmu_ph;
+
+	smmu_ph = fdt_get_smmu_phandle(blob);
+	if (smmu_ph < 0)
+		return;
+
+	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+}
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
new file mode 100644
index 0000000000..1c528ab751
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -0,0 +1,29 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+	SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+	SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+	SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
+
+	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+	SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
+
+	SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID),
+	SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID),
+	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+	SET_ETR_ICID(FSL_ETR_STREAM_ID),
+	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index bfd663942a..5c5df5b7ef 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -13,6 +13,7 @@
 #include <asm/io.h>
 #include <asm/global_data.h>
 #include <asm/arch-fsl-layerscape/config.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 #include <fsl_csu.h>
 #endif
@@ -674,6 +675,8 @@ void fsl_lsch2_early_init_f(void)
 	erratum_a009798();
 	erratum_a008997();
 	erratum_a009007();
+
+	set_icids();
 }
 #endif
 
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
new file mode 100644
index 0000000000..249837c78e
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_ICID_H_
+#define _FSL_ICID_H_
+
+#include <asm/types.h>
+#include <fsl_qbman.h>
+
+struct icid_id_table {
+	const char *compat;
+	u32 id;
+	u32 reg;
+	phys_addr_t compat_addr;
+	phys_addr_t reg_addr;
+};
+
+u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
+int fdt_get_smmu_phandle(void *blob);
+int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
+void set_icids(void);
+void fdt_fixup_icid(void *blob);
+
+#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
+	{ .compat = name, \
+	  .id = idA, \
+	  .reg = regA, \
+	  .compat_addr = compataddr, \
+	  .reg_addr = addr, \
+	}
+
+#define SET_SCFG_ICID(compat, icid, name, compataddr) \
+	SET_ICID_ENTRY(compat, icid, (((icid) << 24) | (1 << 23)), \
+		offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \
+		compataddr)
+
+#define SET_USB_ICID(usb_num, compat, icid) \
+	SET_SCFG_ICID(compat, icid, usb##usb_num##_icid,\
+		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
+
+#define SET_SATA_ICID(compat, icid) \
+	SET_SCFG_ICID(compat, icid, sata_icid,\
+		AHCI_BASE_ADDR)
+
+#define SET_SDHC_ICID(icid) \
+	SET_SCFG_ICID("fsl,esdhc", icid, sdhc_icid,\
+		CONFIG_SYS_FSL_ESDHC_ADDR)
+
+#define SET_QDMA_ICID(compat, icid) \
+	SET_SCFG_ICID(compat, icid, dma_icid,\
+		QDMA_BASE_ADDR)
+
+#define SET_EDMA_ICID(icid) \
+	SET_SCFG_ICID("fsl,vf610-edma", icid, edma_icid,\
+		EDMA_BASE_ADDR)
+
+#define SET_ETR_ICID(icid) \
+	SET_SCFG_ICID(NULL, icid, etr_icid, 0)
+
+#define SET_DEBUG_ICID(icid) \
+	SET_SCFG_ICID(NULL, icid, debug_icid, 0)
+
+#define SET_QMAN_ICID(icid) \
+	SET_ICID_ENTRY("fsl,qman", icid, icid, \
+		offsetof(struct ccsr_qman, liodnr) + \
+		CONFIG_SYS_FSL_QMAN_ADDR, \
+		CONFIG_SYS_FSL_QMAN_ADDR)
+
+#define SET_BMAN_ICID(icid) \
+	SET_ICID_ENTRY("fsl,bman", icid, icid, \
+		offsetof(struct ccsr_bman, liodnr) + \
+		CONFIG_SYS_FSL_BMAN_ADDR, \
+		CONFIG_SYS_FSL_BMAN_ADDR)
+
+extern struct icid_id_table icid_tbl[];
+extern int icid_tbl_sz;
+
+#endif
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c
index b765f07f85..072f8c37a5 100644
--- a/board/freescale/ls1046aqds/ls1046aqds.c
+++ b/board/freescale/ls1046aqds/ls1046aqds.c
@@ -309,6 +309,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_board_enet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	reg = QIXIS_READ(brdcfg[0]);
 	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
 
diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c
index feb5c2448a..0a73fe859d 100644
--- a/board/freescale/ls1046ardb/ls1046ardb.c
+++ b/board/freescale/ls1046ardb/ls1046ardb.c
@@ -11,6 +11,7 @@
 #include <asm/arch/fsl_serdes.h>
 #include <asm/arch/ppa.h>
 #include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #include <hwconfig.h>
 #include <ahci.h>
 #include <mmc.h>
@@ -174,6 +175,8 @@ int ft_board_setup(void *blob, bd_t *bd)
 	fdt_fixup_fman_ethernet(blob);
 #endif
 
+	fdt_fixup_icid(blob);
+
 	return 0;
 }
 #endif
-- 
2.17.1

[U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals

[Laurentiu Tudor]

Add support for ICID setting of qman portals and
the required device tree fixups.
Also fix an endiness issue in portal setup code.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++++++
 .../asm/arch-fsl-layerscape/fsl_portals.h     | 23 ++++++++++
 drivers/misc/fsl_portals.c                    | 43 +++++++++++++++----
 3 files changed, 74 insertions(+), 8 deletions(-)
 create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 1c528ab751..80e1ceadc0 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -6,6 +6,22 @@
 #include <common.h>
 #include <asm/arch-fsl-layerscape/immap_lsch2.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
 
 struct icid_id_table icid_tbl[] = {
 #ifdef CONFIG_SYS_DPAA_QBMAN
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
new file mode 100644
index 0000000000..bd8d3fb49a
--- /dev/null
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
@@ -0,0 +1,23 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2018 NXP
+ */
+
+#ifndef _FSL_PORTALS_H_
+#define _FSL_PORTALS_H_
+
+struct qportal_info {
+	u16	dicid;	/* DQRR ICID */
+	u16	ficid;	/* frame data ICID */
+	u16	icid;
+	u8	sdest;
+};
+
+#define SET_QP_INFO(_icid, dest) \
+	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
+
+extern struct qportal_info qp_info[];
+void fdt_portal(void *blob, const char *compat, const char *container,
+		u64 addr, u32 size);
+
+#endif
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index 22faf16751..a524510707 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -13,6 +13,9 @@
 #ifdef CONFIG_PPC
 #include <asm/fsl_portals.h>
 #include <asm/fsl_liodn.h>
+#else
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
 #endif
 #include <fsl_qbman.h>
 
@@ -45,6 +48,22 @@ void setup_qbman_portals(void)
 		/* set frame liodn */
 		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
 	}
+#else
+#ifdef CONFIG_ARM
+	int i;
+
+	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
+		u8 sdest = qp_info[i].sdest;
+		u16 ficid = qp_info[i].ficid;
+		u16 dicid = qp_info[i].dicid;
+		u16 icid = qp_info[i].icid;
+
+		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
+					dicid);
+		/* set frame icid */
+		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
+	}
+#endif
 #endif
 
 	/* Change default state of BMan ISDR portals to all 1s */
@@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
 	char compat[64];
 	int compat_len;
 
+#ifndef CONFIG_PPC
+	int smmu_ph = fdt_get_smmu_phandle(blob);
+#endif
+
 	maj = (rev_1 >> 8) & 0xff;
 	min = rev_1 & 0xff;
 	ip_cfg = rev_2 & 0xff;
@@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
 
 	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
 	while (off != -FDT_ERR_NOTFOUND) {
-#ifdef CONFIG_PPC
 #ifdef CONFIG_FSL_CORENET
 		u32 liodns[2];
 #endif
@@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
 		if (!ci)
 			goto err;
 
-		i = *ci;
-#ifdef CONFIG_SYS_DPAA_FMAN
-		int j;
-#endif
-
-#endif /* CONFIG_PPC */
+		i = fdt32_to_cpu(*ci);
 		err = fdt_setprop(blob, off, "compatible", compat, compat_len);
 		if (err < 0)
 			goto err;
@@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
 #endif
 
 #ifdef CONFIG_SYS_DPAA_FMAN
-		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
+		for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
 			char name[] = "fman@0";
 
 			name[sizeof(name) - 2] = '0' + j;
@@ -251,6 +268,16 @@ void fdt_fixup_qportals(void *blob)
 		if (err < 0)
 			goto err;
 #endif
+#else
+		if (smmu_ph >= 0) {
+			u32 icids[3];
+
+			icids[0] = qp_info[i].icid;
+			icids[1] = qp_info[i].dicid;
+			icids[2] = qp_info[i].ficid;
+
+			fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
+		}
 #endif /* CONFIG_PPC */
 
 err:
-- 
2.17.1

[U-Boot] [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device tree

[Laurentiu Tudor]

Add support for ICID setting of fman ports and
the required device tree fixups.

Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
 arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 82 +++++++++++++++++++
 .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++++++
 .../asm/arch-fsl-layerscape/fsl_icid.h        | 10 +++
 3 files changed, 122 insertions(+)

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
index 8694bd6fa1..9502f83ac8 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
@@ -10,6 +10,7 @@
 #include <asm/io.h>
 #include <asm/processor.h>
 #include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <fsl_fman.h>
 
 static void set_icid(struct icid_id_table *tbl, int size)
 {
@@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size)
 		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
 }
 
+#ifdef CONFIG_SYS_FMAN_V3
+void set_fman_icids(struct fman_icid_id_table *tbl, int size)
+{
+	int i;
+	ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
+
+	for (i = 0; i < size; i++) {
+		out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1],
+			 tbl[i].icid);
+	}
+}
+#endif
+
 void set_icids(void)
 {
 	/* setup general icid offsets */
 	set_icid(icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_FMAN_V3
+	set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
+#endif
 }
 
 int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids)
@@ -76,6 +94,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
 	return 0;
 }
 
+#ifdef CONFIG_SYS_FMAN_V3
+int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
+		       const int size)
+{
+	int i;
+
+	for (i = 0; i < size; i++) {
+		if (tbl[i].port_id == port_id)
+			return tbl[i].icid;
+	}
+
+	return -1;
+}
+
+void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
+					const char *compat)
+{
+	int noff, len, icid;
+	const u32 *prop;
+
+	noff = fdt_node_offset_by_compatible(blob, -1, compat);
+	while (noff > 0) {
+		prop = fdt_getprop(blob, noff, "cell-index", &len);
+		if (!prop) {
+			printf("WARNING missing cell-index for fman port\n");
+			continue;
+		}
+		if (len != 4) {
+			printf("WARNING bad cell-index size for fman port\n");
+			continue;
+		}
+
+		icid = get_fman_port_icid(fdt32_to_cpu(*prop),
+					  fman_icid_tbl, fman_icid_tbl_sz);
+		if (icid < 0) {
+			printf("WARNING unknown ICID for fman port %d\n",
+			       *prop);
+			continue;
+		}
+
+		fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
+
+		noff = fdt_node_offset_by_compatible(blob, noff, compat);
+	}
+}
+
+void fdt_fixup_fman_icids(void *blob, int smmu_ph)
+{
+	static const char * const compats[] = {
+		"fsl,fman-v3-port-oh",
+		"fsl,fman-v3-port-rx",
+		"fsl,fman-v3-port-tx",
+	};
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(compats); i++)
+		fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph, compats[i]);
+}
+#endif
+
 int fdt_get_smmu_phandle(void *blob)
 {
 	int noff, smmu_ph;
@@ -108,4 +186,8 @@ void fdt_fixup_icid(void *blob)
 		return;
 
 	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
+
+#ifdef CONFIG_SYS_FMAN_V3
+	fdt_fixup_fman_icids(blob, smmu_ph);
+#endif
 }
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
index 80e1ceadc0..30c7d8d28a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
@@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = {
 };
 
 int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+	/* port id, icid */
+	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
+	SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
+};
+
+int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
+#endif
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index 249837c78e..7568abc280 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -17,6 +17,11 @@ struct icid_id_table {
 	phys_addr_t reg_addr;
 };
 
+struct fman_icid_id_table {
+	u32 port_id;
+	u32 icid;
+};
+
 u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
 int fdt_get_smmu_phandle(void *blob);
 int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int num_ids);
@@ -74,7 +79,12 @@ void fdt_fixup_icid(void *blob);
 		CONFIG_SYS_FSL_BMAN_ADDR, \
 		CONFIG_SYS_FSL_BMAN_ADDR)
 
+#define SET_FMAN_ICID_ENTRY(_port_id, _icid) \
+	{ .port_id = (_port_id), .icid = (_icid) }
+
 extern struct icid_id_table icid_tbl[];
+extern struct fman_icid_id_table fman_icid_tbl[];
 extern int icid_tbl_sz;
+extern int fman_icid_tbl_sz;
 
 #endif
-- 
2.17.1

[U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> <laurentiu.tudor@nxp.com>
> Subject: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM
> platforms
> 
> QMAN_BAR{E} register setup was disabled on ARM platforms, however the
> register does need to be set. Enable the code also on ARMs and fix the
> CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the
> newly
> enabled code works.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
>  drivers/misc/fsl_portals.c                             | 2 --
>  2 files changed, 1 insertion(+), 4 deletions(-)
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> index 644a16dd30..d22ec70aa5 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> @@ -57,8 +57,7 @@
>  #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
>  #define CONFIG_SYS_QMAN_NUM_PORTALS	10
>  #define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
> -#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
> -
> 	CONFIG_SYS_QMAN_MEM_BASE)
> +#define CONFIG_SYS_QMAN_MEM_PHYS
> 	CONFIG_SYS_QMAN_MEM_BASE

Are you sure that these changes works for PowerPC ?

Thanks
-Bharat

>  #define CONFIG_SYS_QMAN_MEM_SIZE	0x08000000
>  #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x10000
>  #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x10000
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 7c22b8d209..22faf16751 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -24,7 +24,6 @@ void setup_qbman_portals(void)
>  				CONFIG_SYS_BMAN_SWP_ISDR_REG;
>  	void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE +
>  				CONFIG_SYS_QMAN_SWP_ISDR_REG;
> -#ifdef CONFIG_PPC
>  	struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR;
> 
>  	/* Set the Qman initiator BAR to match the LAW (for DQRR stashing)
> */
> @@ -32,7 +31,6 @@ void setup_qbman_portals(void)
>  	out_be32(&qman->qcsp_bare,
> (u32)(CONFIG_SYS_QMAN_MEM_PHYS >> 32));
>  #endif
>  	out_be32(&qman->qcsp_bar,
> (u32)CONFIG_SYS_QMAN_MEM_PHYS);
> -#endif
>  #ifdef CONFIG_FSL_CORENET
>  	int i;
> 
> --
> 2.17.1

[U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> <laurentiu.tudor@nxp.com>
> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> 
> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> This include basic ICID setup for several devices.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
>  arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 111 ++++++++++++++++++
>  .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +++++
>  arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
>  .../asm/arch-fsl-layerscape/fsl_icid.h        |  80 +++++++++++++
>  board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
>  board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
>  7 files changed, 229 insertions(+)
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
>  create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> index 1e9e4680fe..5d6f68aad6 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> @@ -37,6 +37,7 @@ endif
> 
>  ifneq ($(CONFIG_ARCH_LS1046A),)
>  obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> +obj-y += icid.o ls1046_ids.o
>  endif
> 
>  ifneq ($(CONFIG_ARCH_LS1088A),)
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> new file mode 100644
> index 0000000000..8694bd6fa1
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -0,0 +1,111 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <common.h>
> +#include <linux/libfdt.h>
> +#include <fdt_support.h>
> +
> +#include <asm/io.h>
> +#include <asm/processor.h>
> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> +
> +static void set_icid(struct icid_id_table *tbl, int size) {
> +	int i;
> +
> +	for (i = 0; i < size; i++)
> +		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> +
> +void set_icids(void)
> +{
> +	/* setup general icid offsets */
> +	set_icid(icid_tbl, icid_tbl_sz);
> +}
> +
> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> +num_ids) {
> +	int i, ret;
> +	u32 prop[8];
> +
> +	for (i = 0; i < num_ids; i++) {
> +		prop[i * 2] = cpu_to_fdt32(smmu_ph);
> +		prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> +	}
> +	ret = fdt_setprop(blob, off, "iommus",
> +			  prop, sizeof(u32) * num_ids * 2);
> +	if (ret > 0) {
> +		printf("WARNING unable to set iommus: %s\n",
> fdt_strerror(off));
> +		return off;
> +	}
> +	ret = fdt_setprop_empty(blob, off, "dma-coherent");

This forces "dma-coherent" for all SOCs, although there is no current known SOCs which does not support non-coherent but maybe safe not to set from common code.

> +	if (ret > 0) {
> +		printf("WARNING unable to set dma-coherent: %s\n",
> +		       fdt_strerror(off));
> +		return off;
> +	}
> +
> +	return 0;
> +}
> +
> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> +		       struct icid_id_table *tbl, int size) {
> +	int i, err, off;
> +
> +	for (i = 0; i < size; i++) {
> +		if (!tbl[i].compat)
> +			continue;
> +
> +		off = fdt_node_offset_by_compat_reg(blob,
> +						    tbl[i].compat,
> +						    tbl[i].compat_addr);
> +		if (off > 0) {
> +			err = fdt_set_iommu_prop(blob, off, smmu_ph,
> +						 &tbl[i].id, 1);
> +			if (err)
> +				return err;
> +		} else {
> +			printf("WARNING could not find node %s: %s.\n",
> +			       tbl[i].compat, fdt_strerror(off));
> +		}
> +	}
> +
> +	return 0;
> +}
> +
> +int fdt_get_smmu_phandle(void *blob)
> +{
> +	int noff, smmu_ph;
> +
> +	noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> +	if (noff < 0) {
> +		printf("WARNING failed to get smmu node: %s\n",
> +		       fdt_strerror(noff));
> +		return noff;
> +	}
> +
> +	smmu_ph = fdt_get_phandle(blob, noff);
> +	if (!smmu_ph) {
> +		smmu_ph = fdt_create_phandle(blob, noff);
> +		if (!smmu_ph) {
> +			printf("WARNING failed to get smmu phandle\n");
> +			return -1;
> +		}
> +	}
> +
> +	return smmu_ph;
> +}
> +
> +void fdt_fixup_icid(void *blob)
> +{
> +	int smmu_ph;
> +
> +	smmu_ph = fdt_get_smmu_phandle(blob);
> +	if (smmu_ph < 0)
> +		return;
> +
> +	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> new file mode 100644
> index 0000000000..1c528ab751
> --- /dev/null
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -0,0 +1,29 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#include <common.h>
> +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> +
> +struct icid_id_table icid_tbl[] = {
> +#ifdef CONFIG_SYS_DPAA_QBMAN
> +	SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
> +	SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), #endif
> +
> +	SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
> +
> +	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> +	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> +	SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
> +
> +	SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID),
> +	SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID),
> +	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
> +	SET_ETR_ICID(FSL_ETR_STREAM_ID),
> +	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
> +};
> +
> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> index bfd663942a..5c5df5b7ef 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> @@ -13,6 +13,7 @@
>  #include <asm/io.h>
>  #include <asm/global_data.h>
>  #include <asm/arch-fsl-layerscape/config.h>
> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>  #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
>  #include <fsl_csu.h>
>  #endif
> @@ -674,6 +675,8 @@ void fsl_lsch2_early_init_f(void)
>  	erratum_a009798();
>  	erratum_a008997();
>  	erratum_a009007();
> +
> +	set_icids();
>  }
>  #endif
> 
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> new file mode 100644
> index 0000000000..249837c78e
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> @@ -0,0 +1,80 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef _FSL_ICID_H_
> +#define _FSL_ICID_H_
> +
> +#include <asm/types.h>
> +#include <fsl_qbman.h>
> +
> +struct icid_id_table {
> +	const char *compat;
> +	u32 id;
> +	u32 reg;
> +	phys_addr_t compat_addr;
> +	phys_addr_t reg_addr;
> +};
> +
> +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); int
> +fdt_get_smmu_phandle(void *blob); int fdt_set_iommu_prop(void *blob,
> +int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void);
> +void fdt_fixup_icid(void *blob);
> +
> +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
> +	{ .compat = name, \
> +	  .id = idA, \
> +	  .reg = regA, \
> +	  .compat_addr = compataddr, \
> +	  .reg_addr = addr, \
> +	}
> +
> +#define SET_SCFG_ICID(compat, icid, name, compataddr) \
> +	SET_ICID_ENTRY(compat, icid, (((icid) << 24) | (1 << 23)), \
> +		offsetof(struct ccsr_scfg, name) +
> CONFIG_SYS_FSL_SCFG_ADDR, \
> +		compataddr)
> +
> +#define SET_USB_ICID(usb_num, compat, icid) \
> +	SET_SCFG_ICID(compat, icid, usb##usb_num##_icid,\
> +		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
> +
> +#define SET_SATA_ICID(compat, icid) \
> +	SET_SCFG_ICID(compat, icid, sata_icid,\
> +		AHCI_BASE_ADDR)
> +
> +#define SET_SDHC_ICID(icid) \
> +	SET_SCFG_ICID("fsl,esdhc", icid, sdhc_icid,\
> +		CONFIG_SYS_FSL_ESDHC_ADDR)
> +
> +#define SET_QDMA_ICID(compat, icid) \
> +	SET_SCFG_ICID(compat, icid, dma_icid,\
> +		QDMA_BASE_ADDR)
> +
> +#define SET_EDMA_ICID(icid) \
> +	SET_SCFG_ICID("fsl,vf610-edma", icid, edma_icid,\
> +		EDMA_BASE_ADDR)

Is same "edma" version used in all SOCs? Can I call this for any other platform ?

> +
> +#define SET_ETR_ICID(icid) \
> +	SET_SCFG_ICID(NULL, icid, etr_icid, 0)
> +
> +#define SET_DEBUG_ICID(icid) \
> +	SET_SCFG_ICID(NULL, icid, debug_icid, 0)
> +
> +#define SET_QMAN_ICID(icid) \
> +	SET_ICID_ENTRY("fsl,qman", icid, icid, \
> +		offsetof(struct ccsr_qman, liodnr) + \
> +		CONFIG_SYS_FSL_QMAN_ADDR, \
> +		CONFIG_SYS_FSL_QMAN_ADDR)
> +
> +#define SET_BMAN_ICID(icid) \
> +	SET_ICID_ENTRY("fsl,bman", icid, icid, \
> +		offsetof(struct ccsr_bman, liodnr) + \
> +		CONFIG_SYS_FSL_BMAN_ADDR, \
> +		CONFIG_SYS_FSL_BMAN_ADDR)
> +
> +extern struct icid_id_table icid_tbl[]; extern int icid_tbl_sz;
> +
> +#endif
> diff --git a/board/freescale/ls1046aqds/ls1046aqds.c
> b/board/freescale/ls1046aqds/ls1046aqds.c
> index b765f07f85..072f8c37a5 100644
> --- a/board/freescale/ls1046aqds/ls1046aqds.c
> +++ b/board/freescale/ls1046aqds/ls1046aqds.c
> @@ -309,6 +309,8 @@ int ft_board_setup(void *blob, bd_t *bd)
>  	fdt_fixup_board_enet(blob);
>  #endif
> 
> +	fdt_fixup_icid(blob);
> +
>  	reg = QIXIS_READ(brdcfg[0]);
>  	reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
> 
> diff --git a/board/freescale/ls1046ardb/ls1046ardb.c
> b/board/freescale/ls1046ardb/ls1046ardb.c
> index feb5c2448a..0a73fe859d 100644
> --- a/board/freescale/ls1046ardb/ls1046ardb.c
> +++ b/board/freescale/ls1046ardb/ls1046ardb.c
> @@ -11,6 +11,7 @@
>  #include <asm/arch/fsl_serdes.h>
>  #include <asm/arch/ppa.h>
>  #include <asm/arch/soc.h>
> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>  #include <hwconfig.h>
>  #include <ahci.h>
>  #include <mmc.h>
> @@ -174,6 +175,8 @@ int ft_board_setup(void *blob, bd_t *bd)
>  	fdt_fixup_fman_ethernet(blob);
>  #endif
> 
> +	fdt_fixup_icid(blob);
> +
>  	return 0;
>  }
>  #endif
> --
> 2.17.1

[U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> <laurentiu.tudor@nxp.com>
> Subject: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
> 
> Add support for ICID setting of qman portals and
> the required device tree fixups.
> Also fix an endiness issue in portal setup code.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++++++
>  .../asm/arch-fsl-layerscape/fsl_portals.h     | 23 ++++++++++
>  drivers/misc/fsl_portals.c                    | 43 +++++++++++++++----
>  3 files changed, 74 insertions(+), 8 deletions(-)
>  create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 1c528ab751..80e1ceadc0 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -6,6 +6,22 @@
>  #include <common.h>
>  #include <asm/arch-fsl-layerscape/immap_lsch2.h>
>  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
> +
> +#ifdef CONFIG_SYS_DPAA_QBMAN
> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),

FSL_DPAA1_STREAM_ID_END is "Stream-ID" while SET_QP_INFO is defined as

 #define SET_QP_INFO(_icid, dest) \
 	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
 
It expects "icid"

Can we use consistent names, either "streamed" or "icid" at both places. 
In fact this structure is used to finally program the h/w, so we should use same name as in h/w to avoid any confusion.

Thanks
-Bharat

> +};
> +#endif
> 
>  struct icid_id_table icid_tbl[] = {
>  #ifdef CONFIG_SYS_DPAA_QBMAN
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> new file mode 100644
> index 0000000000..bd8d3fb49a
> --- /dev/null
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> @@ -0,0 +1,23 @@
> +/* SPDX-License-Identifier: GPL-2.0+ */
> +/*
> + * Copyright 2018 NXP
> + */
> +
> +#ifndef _FSL_PORTALS_H_
> +#define _FSL_PORTALS_H_
> +
> +struct qportal_info {
> +	u16	dicid;	/* DQRR ICID */
> +	u16	ficid;	/* frame data ICID */
> +	u16	icid;
> +	u8	sdest;
> +};
> +
> +#define SET_QP_INFO(_icid, dest) \
> +	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
> +
> +extern struct qportal_info qp_info[];
> +void fdt_portal(void *blob, const char *compat, const char *container,
> +		u64 addr, u32 size);
> +
> +#endif
> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> index 22faf16751..a524510707 100644
> --- a/drivers/misc/fsl_portals.c
> +++ b/drivers/misc/fsl_portals.c
> @@ -13,6 +13,9 @@
>  #ifdef CONFIG_PPC
>  #include <asm/fsl_portals.h>
>  #include <asm/fsl_liodn.h>
> +#else
> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>  #endif
>  #include <fsl_qbman.h>
> 
> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
>  		/* set frame liodn */
>  		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) |
> fliodn);
>  	}
> +#else
> +#ifdef CONFIG_ARM
> +	int i;
> +
> +	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
> +		u8 sdest = qp_info[i].sdest;
> +		u16 ficid = qp_info[i].ficid;
> +		u16 dicid = qp_info[i].dicid;
> +		u16 icid = qp_info[i].icid;
> +
> +		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
> +					dicid);
> +		/* set frame icid */
> +		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
> +	}
> +#endif
>  #endif
> 
>  	/* Change default state of BMan ISDR portals to all 1s */
> @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
>  	char compat[64];
>  	int compat_len;
> 
> +#ifndef CONFIG_PPC
> +	int smmu_ph = fdt_get_smmu_phandle(blob);
> +#endif
> +
>  	maj = (rev_1 >> 8) & 0xff;
>  	min = rev_1 & 0xff;
>  	ip_cfg = rev_2 & 0xff;
> @@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
> 
>  	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
>  	while (off != -FDT_ERR_NOTFOUND) {
> -#ifdef CONFIG_PPC
>  #ifdef CONFIG_FSL_CORENET
>  		u32 liodns[2];
>  #endif
> @@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
>  		if (!ci)
>  			goto err;
> 
> -		i = *ci;
> -#ifdef CONFIG_SYS_DPAA_FMAN
> -		int j;
> -#endif
> -
> -#endif /* CONFIG_PPC */
> +		i = fdt32_to_cpu(*ci);
>  		err = fdt_setprop(blob, off, "compatible", compat,
> compat_len);
>  		if (err < 0)
>  			goto err;
> @@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
>  #endif
> 
>  #ifdef CONFIG_SYS_DPAA_FMAN
> -		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
> +		for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
>  			char name[] = "fman at 0";
> 
>  			name[sizeof(name) - 2] = '0' + j;
> @@ -251,6 +268,16 @@ void fdt_fixup_qportals(void *blob)
>  		if (err < 0)
>  			goto err;
>  #endif
> +#else
> +		if (smmu_ph >= 0) {
> +			u32 icids[3];
> +
> +			icids[0] = qp_info[i].icid;
> +			icids[1] = qp_info[i].dicid;
> +			icids[2] = qp_info[i].ficid;
> +
> +			fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
> +		}
>  #endif /* CONFIG_PPC */
> 
>  err:
> --
> 2.17.1

[U-Boot] [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device tree

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> Sent: Wednesday, July 4, 2018 7:44 PM
> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> <laurentiu.tudor@nxp.com>
> Subject: [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device
> tree
> 
> Add support for ICID setting of fman ports and
> the required device tree fixups.
> 
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
>  arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 82 +++++++++++++++++++
>  .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 30 +++++++
>  .../asm/arch-fsl-layerscape/fsl_icid.h        | 10 +++
>  3 files changed, 122 insertions(+)
> 
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> index 8694bd6fa1..9502f83ac8 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> @@ -10,6 +10,7 @@
>  #include <asm/io.h>
>  #include <asm/processor.h>
>  #include <asm/arch-fsl-layerscape/fsl_icid.h>
> +#include <fsl_fman.h>
> 
>  static void set_icid(struct icid_id_table *tbl, int size)
>  {
> @@ -19,10 +20,27 @@ static void set_icid(struct icid_id_table *tbl, int size)
>  		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg);
>  }
> 
> +#ifdef CONFIG_SYS_FMAN_V3
> +void set_fman_icids(struct fman_icid_id_table *tbl, int size)
> +{
> +	int i;
> +	ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR;
> +
> +	for (i = 0; i < size; i++) {
> +		out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id
> - 1],
> +			 tbl[i].icid);
> +	}
> +}
> +#endif
> +
>  void set_icids(void)
>  {
>  	/* setup general icid offsets */
>  	set_icid(icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_FMAN_V3
> +	set_fman_icids(fman_icid_tbl, fman_icid_tbl_sz);
> +#endif
>  }
> 
>  int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids)
> @@ -76,6 +94,66 @@ int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
>  	return 0;
>  }
> 
> +#ifdef CONFIG_SYS_FMAN_V3
> +int get_fman_port_icid(int port_id, struct fman_icid_id_table *tbl,
> +		       const int size)
> +{
> +	int i;
> +
> +	for (i = 0; i < size; i++) {
> +		if (tbl[i].port_id == port_id)
> +			return tbl[i].icid;
> +	}
> +
> +	return -1;
> +}
> +
> +void fdt_fixup_fman_port_icid_by_compat(void *blob, int smmu_ph,
> +					const char *compat)
> +{
> +	int noff, len, icid;
> +	const u32 *prop;
> +
> +	noff = fdt_node_offset_by_compatible(blob, -1, compat);
> +	while (noff > 0) {
> +		prop = fdt_getprop(blob, noff, "cell-index", &len);
> +		if (!prop) {
> +			printf("WARNING missing cell-index for fman
> port\n");
> +			continue;
> +		}
> +		if (len != 4) {
> +			printf("WARNING bad cell-index size for fman
> port\n");
> +			continue;
> +		}
> +
> +		icid = get_fman_port_icid(fdt32_to_cpu(*prop),
> +					  fman_icid_tbl, fman_icid_tbl_sz);
> +		if (icid < 0) {
> +			printf("WARNING unknown ICID for fman port
> %d\n",
> +			       *prop);
> +			continue;
> +		}
> +
> +		fdt_set_iommu_prop(blob, noff, smmu_ph, (u32 *)&icid, 1);
> +
> +		noff = fdt_node_offset_by_compatible(blob, noff, compat);
> +	}
> +}
> +
> +void fdt_fixup_fman_icids(void *blob, int smmu_ph)
> +{
> +	static const char * const compats[] = {
> +		"fsl,fman-v3-port-oh",
> +		"fsl,fman-v3-port-rx",
> +		"fsl,fman-v3-port-tx",
> +	};
> +	int i;
> +
> +	for (i = 0; i < ARRAY_SIZE(compats); i++)
> +		fdt_fixup_fman_port_icid_by_compat(blob, smmu_ph,
> compats[i]);
> +}
> +#endif
> +
>  int fdt_get_smmu_phandle(void *blob)
>  {
>  	int noff, smmu_ph;
> @@ -108,4 +186,8 @@ void fdt_fixup_icid(void *blob)
>  		return;
> 
>  	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz);
> +
> +#ifdef CONFIG_SYS_FMAN_V3
> +	fdt_fixup_fman_icids(blob, smmu_ph);
> +#endif
>  }
> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> index 80e1ceadc0..30c7d8d28a 100644
> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> @@ -43,3 +43,33 @@ struct icid_id_table icid_tbl[] = {
>  };
> 
>  int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> +
> +#ifdef CONFIG_SYS_DPAA_FMAN
> +struct fman_icid_id_table fman_icid_tbl[] = {
> +	/* port id, icid */
> +	SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
> +	SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
> +};
> +
> +int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
> +#endif
> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> index 249837c78e..7568abc280 100644
> --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> @@ -17,6 +17,11 @@ struct icid_id_table {
>  	phys_addr_t reg_addr;
>  };
> 
> +struct fman_icid_id_table {
> +	u32 port_id;
> +	u32 icid;
> +};
> +
>  u32 get_ppid_icid(int ppid_tbl_idx, int ppid);
>  int fdt_get_smmu_phandle(void *blob);
>  int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
> num_ids);
> @@ -74,7 +79,12 @@ void fdt_fixup_icid(void *blob);
>  		CONFIG_SYS_FSL_BMAN_ADDR, \
>  		CONFIG_SYS_FSL_BMAN_ADDR)
> 
> +#define SET_FMAN_ICID_ENTRY(_port_id, _icid) \
> +	{ .port_id = (_port_id), .icid = (_icid) }

Same comment as in 6/7 patch applies here also, use "streamed" or "icid" consistent with h/w or devicetree.

Thanks
-Bharat

> +
>  extern struct icid_id_table icid_tbl[];
> +extern struct fman_icid_id_table fman_icid_tbl[];
>  extern int icid_tbl_sz;
> +extern int fman_icid_tbl_sz;
> 
>  #endif
> --
> 2.17.1

[U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms

[Laurentiu Tudor]

Hi Bharat,

On 09.07.2018 15:06, Bharat Bhushan wrote:
> 
> 
>> -----Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
>> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
>> <laurentiu.tudor@nxp.com>
>> Subject: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM
>> platforms
>>
>> QMAN_BAR{E} register setup was disabled on ARM platforms, however the
>> register does need to be set. Enable the code also on ARMs and fix the
>> CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that the
>> newly
>> enabled code works.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>>   arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
>>   drivers/misc/fsl_portals.c                             | 2 --
>>   2 files changed, 1 insertion(+), 4 deletions(-)
>>
>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>> index 644a16dd30..d22ec70aa5 100644
>> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
>> @@ -57,8 +57,7 @@
>>   #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
>>   #define CONFIG_SYS_QMAN_NUM_PORTALS	10
>>   #define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
>> -#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
>> -
>> 	CONFIG_SYS_QMAN_MEM_BASE)
>> +#define CONFIG_SYS_QMAN_MEM_PHYS
>> 	CONFIG_SYS_QMAN_MEM_BASE
> 
> Are you sure that these changes works for PowerPC ?
> 

Can't imagine how it could happen. immap_lsch2.h is a ls104xa specific file.

---
Thanks & Best Regards, Laurentiu

[U-Boot] [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on ARM platforms

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 6:10 PM
> To: Bharat Bhushan <bharat.bhushan@nxp.com>; York Sun
> <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on
> ARM platforms
> 
> Hi Bharat,
> 
> On 09.07.2018 15:06, Bharat Bhushan wrote:
> >
> >
> >> -----Original Message-----
> >> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> >> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> >> <laurentiu.tudor@nxp.com>
> >> Subject: [PATCH v3 3/7] misc: fsl_portals: setup QMAN_BAR{E} also on
> >> ARM platforms
> >>
> >> QMAN_BAR{E} register setup was disabled on ARM platforms, however
> the
> >> register does need to be set. Enable the code also on ARMs and fix
> >> the CONFIG_SYS_QMAN_MEM_PHYS define to the correct value so that
> the
> >> newly enabled code works.
> >>
> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> >> ---
> >>   arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 3 +--
> >>   drivers/misc/fsl_portals.c                             | 2 --
> >>   2 files changed, 1 insertion(+), 4 deletions(-)
> >>
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> index 644a16dd30..d22ec70aa5 100644
> >> --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
> >> @@ -57,8 +57,7 @@
> >>   #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0x3E80
> >>   #define CONFIG_SYS_QMAN_NUM_PORTALS	10
> >>   #define CONFIG_SYS_QMAN_MEM_BASE	0x500000000
> >> -#define CONFIG_SYS_QMAN_MEM_PHYS	(0xf00000000ull + \
> >> -
> >> 	CONFIG_SYS_QMAN_MEM_BASE)
> >> +#define CONFIG_SYS_QMAN_MEM_PHYS
> >> 	CONFIG_SYS_QMAN_MEM_BASE
> >
> > Are you sure that these changes works for PowerPC ?
> >
> 
> Can't imagine how it could happen. immap_lsch2.h is a ls104xa specific file.

Ahh yes, just missed 😊

Thanks
-Bharat


> 
> ---
> Thanks & Best Regards, Laurentiu

[U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support

[Laurentiu Tudor]

Hi Bharat,

On 09.07.2018 15:13, Bharat Bhushan wrote:
> 
> 
>> -----Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
>> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
>> <laurentiu.tudor@nxp.com>
>> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
>>
>> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
>> This include basic ICID setup for several devices.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>>   arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
>>   arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 111 ++++++++++++++++++
>>   .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +++++
>>   arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
>>   .../asm/arch-fsl-layerscape/fsl_icid.h        |  80 +++++++++++++
>>   board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
>>   board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
>>   7 files changed, 229 insertions(+)
>>   create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
>>   create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>>   create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> index 1e9e4680fe..5d6f68aad6 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>> @@ -37,6 +37,7 @@ endif
>>
>>   ifneq ($(CONFIG_ARCH_LS1046A),)
>>   obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
>> +obj-y += icid.o ls1046_ids.o
>>   endif
>>
>>   ifneq ($(CONFIG_ARCH_LS1088A),)
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>> new file mode 100644
>> index 0000000000..8694bd6fa1
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>> @@ -0,0 +1,111 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2018 NXP
>> + */
>> +
>> +#include <common.h>
>> +#include <linux/libfdt.h>
>> +#include <fdt_support.h>
>> +
>> +#include <asm/io.h>
>> +#include <asm/processor.h>
>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>> +
>> +static void set_icid(struct icid_id_table *tbl, int size) {
>> +	int i;
>> +
>> +	for (i = 0; i < size; i++)
>> +		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
>> +
>> +void set_icids(void)
>> +{
>> +	/* setup general icid offsets */
>> +	set_icid(icid_tbl, icid_tbl_sz);
>> +}
>> +
>> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids, int
>> +num_ids) {
>> +	int i, ret;
>> +	u32 prop[8];
>> +
>> +	for (i = 0; i < num_ids; i++) {
>> +		prop[i * 2] = cpu_to_fdt32(smmu_ph);
>> +		prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
>> +	}
>> +	ret = fdt_setprop(blob, off, "iommus",
>> +			  prop, sizeof(u32) * num_ids * 2);
>> +	if (ret > 0) {
>> +		printf("WARNING unable to set iommus: %s\n",
>> fdt_strerror(off));
>> +		return off;
>> +	}
>> +	ret = fdt_setprop_empty(blob, off, "dma-coherent");
> 
> This forces "dma-coherent" for all SOCs, although there is no current known SOCs which does not support non-coherent but maybe safe not to set from common code.

I see your point and will drop this.
Now, regarding a replacement solution, I don't have any other idea than 
updating the device trees directly. Thoughts?

>> +	if (ret > 0) {
>> +		printf("WARNING unable to set dma-coherent: %s\n",
>> +		       fdt_strerror(off));
>> +		return off;
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
>> +		       struct icid_id_table *tbl, int size) {
>> +	int i, err, off;
>> +
>> +	for (i = 0; i < size; i++) {
>> +		if (!tbl[i].compat)
>> +			continue;
>> +
>> +		off = fdt_node_offset_by_compat_reg(blob,
>> +						    tbl[i].compat,
>> +						    tbl[i].compat_addr);
>> +		if (off > 0) {
>> +			err = fdt_set_iommu_prop(blob, off, smmu_ph,
>> +						 &tbl[i].id, 1);
>> +			if (err)
>> +				return err;
>> +		} else {
>> +			printf("WARNING could not find node %s: %s.\n",
>> +			       tbl[i].compat, fdt_strerror(off));
>> +		}
>> +	}
>> +
>> +	return 0;
>> +}
>> +
>> +int fdt_get_smmu_phandle(void *blob)
>> +{
>> +	int noff, smmu_ph;
>> +
>> +	noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
>> +	if (noff < 0) {
>> +		printf("WARNING failed to get smmu node: %s\n",
>> +		       fdt_strerror(noff));
>> +		return noff;
>> +	}
>> +
>> +	smmu_ph = fdt_get_phandle(blob, noff);
>> +	if (!smmu_ph) {
>> +		smmu_ph = fdt_create_phandle(blob, noff);
>> +		if (!smmu_ph) {
>> +			printf("WARNING failed to get smmu phandle\n");
>> +			return -1;
>> +		}
>> +	}
>> +
>> +	return smmu_ph;
>> +}
>> +
>> +void fdt_fixup_icid(void *blob)
>> +{
>> +	int smmu_ph;
>> +
>> +	smmu_ph = fdt_get_smmu_phandle(blob);
>> +	if (smmu_ph < 0)
>> +		return;
>> +
>> +	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); }
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> new file mode 100644
>> index 0000000000..1c528ab751
>> --- /dev/null
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> @@ -0,0 +1,29 @@
>> +// SPDX-License-Identifier: GPL-2.0+
>> +/*
>> + * Copyright 2018 NXP
>> + */
>> +
>> +#include <common.h>
>> +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>> +
>> +struct icid_id_table icid_tbl[] = {
>> +#ifdef CONFIG_SYS_DPAA_QBMAN
>> +	SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
>> +	SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), #endif
>> +
>> +	SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
>> +
>> +	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
>> +	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
>> +	SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
>> +
>> +	SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID),
>> +	SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID),
>> +	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
>> +	SET_ETR_ICID(FSL_ETR_STREAM_ID),
>> +	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
>> +};
>> +
>> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> index bfd663942a..5c5df5b7ef 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
>> @@ -13,6 +13,7 @@
>>   #include <asm/io.h>
>>   #include <asm/global_data.h>
>>   #include <asm/arch-fsl-layerscape/config.h>
>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>>   #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
>>   #include <fsl_csu.h>
>>   #endif
>> @@ -674,6 +675,8 @@ void fsl_lsch2_early_init_f(void)
>>   	erratum_a009798();
>>   	erratum_a008997();
>>   	erratum_a009007();
>> +
>> +	set_icids();
>>   }
>>   #endif
>>
>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>> new file mode 100644
>> index 0000000000..249837c78e
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>> @@ -0,0 +1,80 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2018 NXP
>> + */
>> +
>> +#ifndef _FSL_ICID_H_
>> +#define _FSL_ICID_H_
>> +
>> +#include <asm/types.h>
>> +#include <fsl_qbman.h>
>> +
>> +struct icid_id_table {
>> +	const char *compat;
>> +	u32 id;
>> +	u32 reg;
>> +	phys_addr_t compat_addr;
>> +	phys_addr_t reg_addr;
>> +};
>> +
>> +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); int
>> +fdt_get_smmu_phandle(void *blob); int fdt_set_iommu_prop(void *blob,
>> +int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void);
>> +void fdt_fixup_icid(void *blob);
>> +
>> +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
>> +	{ .compat = name, \
>> +	  .id = idA, \
>> +	  .reg = regA, \
>> +	  .compat_addr = compataddr, \
>> +	  .reg_addr = addr, \
>> +	}
>> +
>> +#define SET_SCFG_ICID(compat, icid, name, compataddr) \
>> +	SET_ICID_ENTRY(compat, icid, (((icid) << 24) | (1 << 23)), \
>> +		offsetof(struct ccsr_scfg, name) +
>> CONFIG_SYS_FSL_SCFG_ADDR, \
>> +		compataddr)
>> +
>> +#define SET_USB_ICID(usb_num, compat, icid) \
>> +	SET_SCFG_ICID(compat, icid, usb##usb_num##_icid,\
>> +		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
>> +
>> +#define SET_SATA_ICID(compat, icid) \
>> +	SET_SCFG_ICID(compat, icid, sata_icid,\
>> +		AHCI_BASE_ADDR)
>> +
>> +#define SET_SDHC_ICID(icid) \
>> +	SET_SCFG_ICID("fsl,esdhc", icid, sdhc_icid,\
>> +		CONFIG_SYS_FSL_ESDHC_ADDR)
>> +
>> +#define SET_QDMA_ICID(compat, icid) \
>> +	SET_SCFG_ICID(compat, icid, dma_icid,\
>> +		QDMA_BASE_ADDR)
>> +
>> +#define SET_EDMA_ICID(icid) \
>> +	SET_SCFG_ICID("fsl,vf610-edma", icid, edma_icid,\
>> +		EDMA_BASE_ADDR)
> 
> Is same "edma" version used in all SOCs? Can I call this for any other platform ?

I grep-ed the device trees and it's the only existing compatible. I 
propose that for now leave it like this for now, and if a new edma 
compatible shows up we can update at that time.

---
Thanks & Best Regards, Laurentiu

[U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals

[Laurentiu Tudor]

Hi Bharat,

On 09.07.2018 15:21, Bharat Bhushan wrote:
> 
> 
>> -----Original Message-----
>> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
>> Sent: Wednesday, July 4, 2018 7:44 PM
>> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
>> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
>> <laurentiu.tudor@nxp.com>
>> Subject: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
>>
>> Add support for ICID setting of qman portals and
>> the required device tree fixups.
>> Also fix an endiness issue in portal setup code.
>>
>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>> ---
>>   .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++++++
>>   .../asm/arch-fsl-layerscape/fsl_portals.h     | 23 ++++++++++
>>   drivers/misc/fsl_portals.c                    | 43 +++++++++++++++----
>>   3 files changed, 74 insertions(+), 8 deletions(-)
>>   create mode 100644 arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>>
>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> index 1c528ab751..80e1ceadc0 100644
>> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>> @@ -6,6 +6,22 @@
>>   #include <common.h>
>>   #include <asm/arch-fsl-layerscape/immap_lsch2.h>
>>   #include <asm/arch-fsl-layerscape/fsl_icid.h>
>> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
>> +
>> +#ifdef CONFIG_SYS_DPAA_QBMAN
>> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
>> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> 
> FSL_DPAA1_STREAM_ID_END is "Stream-ID" while SET_QP_INFO is defined as
> 
>   #define SET_QP_INFO(_icid, dest) \
>   	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
>   
> It expects "icid"
> 
> Can we use consistent names, either "streamed" or "icid" at both places.

The problem is that the streamid defines where defined some time ago 
(see file ./arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h).

> In fact this structure is used to finally program the h/w, so we should use same name as in h/w to avoid any confusion.

The RefMan uses the term "icid" so i'd stick with it.

In order to make this consistent I think i should rename the existing 
*_STREAM_ID_* defines to *_ICID_* but also the header that contains them 
from stream_id_lsch2.h to something like icid_lsch2.h. This implies that 
also the PCI related defines would be renamed. Is that ok?
Let me know what you think.

---
Best Regards, Laurentiu

> 
> Thanks
> -Bharat
> 
>> +};
>> +#endif
>>
>>   struct icid_id_table icid_tbl[] = {
>>   #ifdef CONFIG_SYS_DPAA_QBMAN
>> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>> new file mode 100644
>> index 0000000000..bd8d3fb49a
>> --- /dev/null
>> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
>> @@ -0,0 +1,23 @@
>> +/* SPDX-License-Identifier: GPL-2.0+ */
>> +/*
>> + * Copyright 2018 NXP
>> + */
>> +
>> +#ifndef _FSL_PORTALS_H_
>> +#define _FSL_PORTALS_H_
>> +
>> +struct qportal_info {
>> +	u16	dicid;	/* DQRR ICID */
>> +	u16	ficid;	/* frame data ICID */
>> +	u16	icid;
>> +	u8	sdest;
>> +};
>> +
>> +#define SET_QP_INFO(_icid, dest) \
>> +	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
>> +
>> +extern struct qportal_info qp_info[];
>> +void fdt_portal(void *blob, const char *compat, const char *container,
>> +		u64 addr, u32 size);
>> +
>> +#endif
>> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
>> index 22faf16751..a524510707 100644
>> --- a/drivers/misc/fsl_portals.c
>> +++ b/drivers/misc/fsl_portals.c
>> @@ -13,6 +13,9 @@
>>   #ifdef CONFIG_PPC
>>   #include <asm/fsl_portals.h>
>>   #include <asm/fsl_liodn.h>
>> +#else
>> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>>   #endif
>>   #include <fsl_qbman.h>
>>
>> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
>>   		/* set frame liodn */
>>   		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) |
>> fliodn);
>>   	}
>> +#else
>> +#ifdef CONFIG_ARM
>> +	int i;
>> +
>> +	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
>> +		u8 sdest = qp_info[i].sdest;
>> +		u16 ficid = qp_info[i].ficid;
>> +		u16 dicid = qp_info[i].dicid;
>> +		u16 icid = qp_info[i].icid;
>> +
>> +		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
>> +					dicid);
>> +		/* set frame icid */
>> +		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
>> +	}
>> +#endif
>>   #endif
>>
>>   	/* Change default state of BMan ISDR portals to all 1s */
>> @@ -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
>>   	char compat[64];
>>   	int compat_len;
>>
>> +#ifndef CONFIG_PPC
>> +	int smmu_ph = fdt_get_smmu_phandle(blob);
>> +#endif
>> +
>>   	maj = (rev_1 >> 8) & 0xff;
>>   	min = rev_1 & 0xff;
>>   	ip_cfg = rev_2 & 0xff;
>> @@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
>>
>>   	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
>>   	while (off != -FDT_ERR_NOTFOUND) {
>> -#ifdef CONFIG_PPC
>>   #ifdef CONFIG_FSL_CORENET
>>   		u32 liodns[2];
>>   #endif
>> @@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
>>   		if (!ci)
>>   			goto err;
>>
>> -		i = *ci;
>> -#ifdef CONFIG_SYS_DPAA_FMAN
>> -		int j;
>> -#endif
>> -
>> -#endif /* CONFIG_PPC */
>> +		i = fdt32_to_cpu(*ci);
>>   		err = fdt_setprop(blob, off, "compatible", compat,
>> compat_len);
>>   		if (err < 0)
>>   			goto err;
>> @@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
>>   #endif
>>
>>   #ifdef CONFIG_SYS_DPAA_FMAN
>> -		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
>> +		for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
>>   			char name[] = "fman at 0";
>>
>>   			name[sizeof(name) - 2] = '0' + j;
>> @@ -251,6 +268,16 @@ void fdt_fixup_qportals(void *blob)
>>   		if (err < 0)
>>   			goto err;
>>   #endif
>> +#else
>> +		if (smmu_ph >= 0) {
>> +			u32 icids[3];
>> +
>> +			icids[0] = qp_info[i].icid;
>> +			icids[1] = qp_info[i].dicid;
>> +			icids[2] = qp_info[i].ficid;
>> +
>> +			fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
>> +		}
>>   #endif /* CONFIG_PPC */
>>
>>   err:
>> --
>> 2.17.1
> 

[U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 6:42 PM
> To: Bharat Bhushan <bharat.bhushan@nxp.com>; York Sun
> <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> 
> Hi Bharat,
> 
> On 09.07.2018 15:13, Bharat Bhushan wrote:
> >
> >
> >> -----Original Message-----
> >> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> >> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> >> <laurentiu.tudor@nxp.com>
> >> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
> >>
> >> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
> >> This include basic ICID setup for several devices.
> >>
> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> >> ---
> >>   arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
> >>   arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 111
> ++++++++++++++++++
> >>   .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +++++
> >>   arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
> >>   .../asm/arch-fsl-layerscape/fsl_icid.h        |  80 +++++++++++++
> >>   board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
> >>   board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
> >>   7 files changed, 229 insertions(+)
> >>   create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >>   create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >>   create mode 100644
> >> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> index 1e9e4680fe..5d6f68aad6 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
> >> @@ -37,6 +37,7 @@ endif
> >>
> >>   ifneq ($(CONFIG_ARCH_LS1046A),)
> >>   obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
> >> +obj-y += icid.o ls1046_ids.o
> >>   endif
> >>
> >>   ifneq ($(CONFIG_ARCH_LS1088A),)
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> new file mode 100644
> >> index 0000000000..8694bd6fa1
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
> >> @@ -0,0 +1,111 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#include <common.h>
> >> +#include <linux/libfdt.h>
> >> +#include <fdt_support.h>
> >> +
> >> +#include <asm/io.h>
> >> +#include <asm/processor.h>
> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> >> +
> >> +static void set_icid(struct icid_id_table *tbl, int size) {
> >> +	int i;
> >> +
> >> +	for (i = 0; i < size; i++)
> >> +		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
> >> +
> >> +void set_icids(void)
> >> +{
> >> +	/* setup general icid offsets */
> >> +	set_icid(icid_tbl, icid_tbl_sz);
> >> +}
> >> +
> >> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids,
> >> +int
> >> +num_ids) {
> >> +	int i, ret;
> >> +	u32 prop[8];
> >> +
> >> +	for (i = 0; i < num_ids; i++) {
> >> +		prop[i * 2] = cpu_to_fdt32(smmu_ph);
> >> +		prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
> >> +	}
> >> +	ret = fdt_setprop(blob, off, "iommus",
> >> +			  prop, sizeof(u32) * num_ids * 2);
> >> +	if (ret > 0) {
> >> +		printf("WARNING unable to set iommus: %s\n",
> >> fdt_strerror(off));
> >> +		return off;
> >> +	}
> >> +	ret = fdt_setprop_empty(blob, off, "dma-coherent");
> >
> > This forces "dma-coherent" for all SOCs, although there is no current
> known SOCs which does not support non-coherent but maybe safe not to
> set from common code.
> 
> I see your point and will drop this.
> Now, regarding a replacement solution, I don't have any other idea than
> updating the device trees directly. Thoughts?

dma-coherent will be default in device tree and u-boot code should check if dma-coherent already set.
Have another function exposed from generic code which set "dma-coherent" and platforms code will call that function if it is coherent. 

> 
> >> +	if (ret > 0) {
> >> +		printf("WARNING unable to set dma-coherent: %s\n",
> >> +		       fdt_strerror(off));
> >> +		return off;
> >> +	}
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +int fdt_fixup_icid_tbl(void *blob, int smmu_ph,
> >> +		       struct icid_id_table *tbl, int size) {
> >> +	int i, err, off;
> >> +
> >> +	for (i = 0; i < size; i++) {
> >> +		if (!tbl[i].compat)
> >> +			continue;
> >> +
> >> +		off = fdt_node_offset_by_compat_reg(blob,
> >> +						    tbl[i].compat,
> >> +						    tbl[i].compat_addr);
> >> +		if (off > 0) {
> >> +			err = fdt_set_iommu_prop(blob, off, smmu_ph,
> >> +						 &tbl[i].id, 1);
> >> +			if (err)
> >> +				return err;
> >> +		} else {
> >> +			printf("WARNING could not find node %s: %s.\n",
> >> +			       tbl[i].compat, fdt_strerror(off));
> >> +		}
> >> +	}
> >> +
> >> +	return 0;
> >> +}
> >> +
> >> +int fdt_get_smmu_phandle(void *blob) {
> >> +	int noff, smmu_ph;
> >> +
> >> +	noff = fdt_node_offset_by_compatible(blob, -1, "arm,mmu-500");
> >> +	if (noff < 0) {
> >> +		printf("WARNING failed to get smmu node: %s\n",
> >> +		       fdt_strerror(noff));
> >> +		return noff;
> >> +	}
> >> +
> >> +	smmu_ph = fdt_get_phandle(blob, noff);
> >> +	if (!smmu_ph) {
> >> +		smmu_ph = fdt_create_phandle(blob, noff);
> >> +		if (!smmu_ph) {
> >> +			printf("WARNING failed to get smmu phandle\n");
> >> +			return -1;
> >> +		}
> >> +	}
> >> +
> >> +	return smmu_ph;
> >> +}
> >> +
> >> +void fdt_fixup_icid(void *blob)
> >> +{
> >> +	int smmu_ph;
> >> +
> >> +	smmu_ph = fdt_get_smmu_phandle(blob);
> >> +	if (smmu_ph < 0)
> >> +		return;
> >> +
> >> +	fdt_fixup_icid_tbl(blob, smmu_ph, icid_tbl, icid_tbl_sz); }
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> new file mode 100644
> >> index 0000000000..1c528ab751
> >> --- /dev/null
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> @@ -0,0 +1,29 @@
> >> +// SPDX-License-Identifier: GPL-2.0+
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#include <common.h>
> >> +#include <asm/arch-fsl-layerscape/immap_lsch2.h>
> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> >> +
> >> +struct icid_id_table icid_tbl[] = {
> >> +#ifdef CONFIG_SYS_DPAA_QBMAN
> >> +	SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
> >> +	SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1), #endif
> >> +
> >> +	SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
> >> +
> >> +	SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> >> +	SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> >> +	SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
> >> +
> >> +	SET_SATA_ICID("fsl,ls1046a-ahci", FSL_SATA_STREAM_ID),
> >> +	SET_QDMA_ICID("fsl,ls1046a-qdma", FSL_QDMA_STREAM_ID),
> >> +	SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
> >> +	SET_ETR_ICID(FSL_ETR_STREAM_ID),
> >> +	SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
> >> +};
> >> +
> >> +int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> index bfd663942a..5c5df5b7ef 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
> >> @@ -13,6 +13,7 @@
> >>   #include <asm/io.h>
> >>   #include <asm/global_data.h>
> >>   #include <asm/arch-fsl-layerscape/config.h>
> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> >>   #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
> >>   #include <fsl_csu.h>
> >>   #endif
> >> @@ -674,6 +675,8 @@ void fsl_lsch2_early_init_f(void)
> >>   	erratum_a009798();
> >>   	erratum_a008997();
> >>   	erratum_a009007();
> >> +
> >> +	set_icids();
> >>   }
> >>   #endif
> >>
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> >> new file mode 100644
> >> index 0000000000..249837c78e
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
> >> @@ -0,0 +1,80 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#ifndef _FSL_ICID_H_
> >> +#define _FSL_ICID_H_
> >> +
> >> +#include <asm/types.h>
> >> +#include <fsl_qbman.h>
> >> +
> >> +struct icid_id_table {
> >> +	const char *compat;
> >> +	u32 id;
> >> +	u32 reg;
> >> +	phys_addr_t compat_addr;
> >> +	phys_addr_t reg_addr;
> >> +};
> >> +
> >> +u32 get_ppid_icid(int ppid_tbl_idx, int ppid); int
> >> +fdt_get_smmu_phandle(void *blob); int fdt_set_iommu_prop(void
> *blob,
> >> +int off, int smmu_ph, u32 *ids, int num_ids); void set_icids(void);
> >> +void fdt_fixup_icid(void *blob);
> >> +
> >> +#define SET_ICID_ENTRY(name, idA, regA, addr, compataddr) \
> >> +	{ .compat = name, \
> >> +	  .id = idA, \
> >> +	  .reg = regA, \
> >> +	  .compat_addr = compataddr, \
> >> +	  .reg_addr = addr, \
> >> +	}
> >> +
> >> +#define SET_SCFG_ICID(compat, icid, name, compataddr) \
> >> +	SET_ICID_ENTRY(compat, icid, (((icid) << 24) | (1 << 23)), \
> >> +		offsetof(struct ccsr_scfg, name) +
> >> CONFIG_SYS_FSL_SCFG_ADDR, \
> >> +		compataddr)
> >> +
> >> +#define SET_USB_ICID(usb_num, compat, icid) \
> >> +	SET_SCFG_ICID(compat, icid, usb##usb_num##_icid,\
> >> +		CONFIG_SYS_XHCI_USB##usb_num##_ADDR)
> >> +
> >> +#define SET_SATA_ICID(compat, icid) \
> >> +	SET_SCFG_ICID(compat, icid, sata_icid,\
> >> +		AHCI_BASE_ADDR)
> >> +
> >> +#define SET_SDHC_ICID(icid) \
> >> +	SET_SCFG_ICID("fsl,esdhc", icid, sdhc_icid,\
> >> +		CONFIG_SYS_FSL_ESDHC_ADDR)
> >> +
> >> +#define SET_QDMA_ICID(compat, icid) \
> >> +	SET_SCFG_ICID(compat, icid, dma_icid,\
> >> +		QDMA_BASE_ADDR)
> >> +
> >> +#define SET_EDMA_ICID(icid) \
> >> +	SET_SCFG_ICID("fsl,vf610-edma", icid, edma_icid,\
> >> +		EDMA_BASE_ADDR)
> >
> > Is same "edma" version used in all SOCs? Can I call this for any other
> platform ?
> 
> I grep-ed the device trees and it's the only existing compatible. I propose
> that for now leave it like this for now, and if a new edma compatible shows
> up we can update at that time.

Ok for now;

Thanks
-Bharat

> 
> ---
> Thanks & Best Regards, Laurentiu

[U-Boot] [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals

[Bharat Bhushan]

> -----Original Message-----
> From: Laurentiu Tudor
> Sent: Monday, July 9, 2018 7:23 PM
> To: Bharat Bhushan <bharat.bhushan@nxp.com>; York Sun
> <york.sun@nxp.com>; Prabhakar Kushwaha
> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> Subject: Re: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman portals
> 
> Hi Bharat,
> 
> On 09.07.2018 15:21, Bharat Bhushan wrote:
> >
> >
> >> -----Original Message-----
> >> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
> >> Sent: Wednesday, July 4, 2018 7:44 PM
> >> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
> >> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
> >> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
> >> <laurentiu.tudor@nxp.com>
> >> Subject: [PATCH v3 6/7] armv8: ls1046a: add icid setup for qman
> >> portals
> >>
> >> Add support for ICID setting of qman portals and the required device
> >> tree fixups.
> >> Also fix an endiness issue in portal setup code.
> >>
> >> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> >> ---
> >>   .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c | 16 +++++++
> >>   .../asm/arch-fsl-layerscape/fsl_portals.h     | 23 ++++++++++
> >>   drivers/misc/fsl_portals.c                    | 43 +++++++++++++++----
> >>   3 files changed, 74 insertions(+), 8 deletions(-)
> >>   create mode 100644
> >> arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >>
> >> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> index 1c528ab751..80e1ceadc0 100644
> >> --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
> >> @@ -6,6 +6,22 @@
> >>   #include <common.h>
> >>   #include <asm/arch-fsl-layerscape/immap_lsch2.h>
> >>   #include <asm/arch-fsl-layerscape/fsl_icid.h>
> >> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
> >> +
> >> +#ifdef CONFIG_SYS_DPAA_QBMAN
> >> +struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >> +	SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
> >
> > FSL_DPAA1_STREAM_ID_END is "Stream-ID" while SET_QP_INFO is
> defined as
> >
> >   #define SET_QP_INFO(_icid, dest) \
> >   	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
> >
> > It expects "icid"
> >
> > Can we use consistent names, either "streamed" or "icid" at both places.
> 
> The problem is that the streamid defines where defined some time ago (see
> file ./arch/arm/include/asm/arch-fsl-layerscape/stream_id_lsch2.h).
> 
> > In fact this structure is used to finally program the h/w, so we should use
> same name as in h/w to avoid any confusion.
> 
> The RefMan uses the term "icid" so i'd stick with it.
> 
> In order to make this consistent I think i should rename the existing
> *_STREAM_ID_* defines to *_ICID_* but also the header that contains them
> from stream_id_lsch2.h to something like icid_lsch2.h. This implies that also
> the PCI related defines would be renamed. Is that ok?
> Let me know what you think.

Other way is 
 - use stream-id in common code (header files etc)
 - above is used to update the device-tree and device tree should use stream-id and not icid
 - pass stream-id to platform/device init code
 - finally when programming to h/w convert them to ICID, STREAMUID_TO_ICID(), which is one-o-one.
   In this ICID is limited to h/w definition/programming while remaining common framework use streamed.

   Does that look ok?

Thanks
-Bharat
  
> 
> ---
> Best Regards, Laurentiu
> 
> >
> > Thanks
> > -Bharat
> >
> >> +};
> >> +#endif
> >>
> >>   struct icid_id_table icid_tbl[] = {
> >>   #ifdef CONFIG_SYS_DPAA_QBMAN
> >> diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> new file mode 100644
> >> index 0000000000..bd8d3fb49a
> >> --- /dev/null
> >> +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_portals.h
> >> @@ -0,0 +1,23 @@
> >> +/* SPDX-License-Identifier: GPL-2.0+ */
> >> +/*
> >> + * Copyright 2018 NXP
> >> + */
> >> +
> >> +#ifndef _FSL_PORTALS_H_
> >> +#define _FSL_PORTALS_H_
> >> +
> >> +struct qportal_info {
> >> +	u16	dicid;	/* DQRR ICID */
> >> +	u16	ficid;	/* frame data ICID */
> >> +	u16	icid;
> >> +	u8	sdest;
> >> +};
> >> +
> >> +#define SET_QP_INFO(_icid, dest) \
> >> +	{ .dicid = _icid, .ficid = _icid, .icid = _icid, .sdest = dest }
> >> +
> >> +extern struct qportal_info qp_info[]; void fdt_portal(void *blob,
> >> +const char *compat, const char *container,
> >> +		u64 addr, u32 size);
> >> +
> >> +#endif
> >> diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
> >> index 22faf16751..a524510707 100644
> >> --- a/drivers/misc/fsl_portals.c
> >> +++ b/drivers/misc/fsl_portals.c
> >> @@ -13,6 +13,9 @@
> >>   #ifdef CONFIG_PPC
> >>   #include <asm/fsl_portals.h>
> >>   #include <asm/fsl_liodn.h>
> >> +#else
> >> +#include <asm/arch-fsl-layerscape/fsl_portals.h>
> >> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
> >>   #endif
> >>   #include <fsl_qbman.h>
> >>
> >> @@ -45,6 +48,22 @@ void setup_qbman_portals(void)
> >>   		/* set frame liodn */
> >>   		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) |
> fliodn);
> >>   	}
> >> +#else
> >> +#ifdef CONFIG_ARM
> >> +	int i;
> >> +
> >> +	for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
> >> +		u8 sdest = qp_info[i].sdest;
> >> +		u16 ficid = qp_info[i].ficid;
> >> +		u16 dicid = qp_info[i].dicid;
> >> +		u16 icid = qp_info[i].icid;
> >> +
> >> +		out_be32(&qman->qcsp[i].qcsp_lio_cfg, (icid << 16) |
> >> +					dicid);
> >> +		/* set frame icid */
> >> +		out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | ficid);
> >> +	}
> >> +#endif
> >>   #endif
> >>
> >>   	/* Change default state of BMan ISDR portals to all 1s */ @@
> >> -178,6 +197,10 @@ void fdt_fixup_qportals(void *blob)
> >>   	char compat[64];
> >>   	int compat_len;
> >>
> >> +#ifndef CONFIG_PPC
> >> +	int smmu_ph = fdt_get_smmu_phandle(blob); #endif
> >> +
> >>   	maj = (rev_1 >> 8) & 0xff;
> >>   	min = rev_1 & 0xff;
> >>   	ip_cfg = rev_2 & 0xff;
> >> @@ -188,7 +211,6 @@ void fdt_fixup_qportals(void *blob)
> >>
> >>   	off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
> >>   	while (off != -FDT_ERR_NOTFOUND) { -#ifdef CONFIG_PPC
> >>   #ifdef CONFIG_FSL_CORENET
> >>   		u32 liodns[2];
> >>   #endif
> >> @@ -198,12 +220,7 @@ void fdt_fixup_qportals(void *blob)
> >>   		if (!ci)
> >>   			goto err;
> >>
> >> -		i = *ci;
> >> -#ifdef CONFIG_SYS_DPAA_FMAN
> >> -		int j;
> >> -#endif
> >> -
> >> -#endif /* CONFIG_PPC */
> >> +		i = fdt32_to_cpu(*ci);
> >>   		err = fdt_setprop(blob, off, "compatible", compat,
> compat_len);
> >>   		if (err < 0)
> >>   			goto err;
> >> @@ -235,7 +252,7 @@ void fdt_fixup_qportals(void *blob)
> >>   #endif
> >>
> >>   #ifdef CONFIG_SYS_DPAA_FMAN
> >> -		for (j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
> >> +		for (int j = 0; j < CONFIG_SYS_NUM_FMAN; j++) {
> >>   			char name[] = "fman at 0";
> >>
> >>   			name[sizeof(name) - 2] = '0' + j; @@ -251,6 +268,16
> @@ void
> >> fdt_fixup_qportals(void *blob)
> >>   		if (err < 0)
> >>   			goto err;
> >>   #endif
> >> +#else
> >> +		if (smmu_ph >= 0) {
> >> +			u32 icids[3];
> >> +
> >> +			icids[0] = qp_info[i].icid;
> >> +			icids[1] = qp_info[i].dicid;
> >> +			icids[2] = qp_info[i].ficid;
> >> +
> >> +			fdt_set_iommu_prop(blob, off, smmu_ph, icids, 3);
> >> +		}
> >>   #endif /* CONFIG_PPC */
> >>
> >>   err:
> >> --
> >> 2.17.1
> >

[U-Boot] [PATCH v3 5/7] armv8: ls1046a: initial icid setup support

[Laurentiu Tudor]

Hi Bharat,

On 10.07.2018 08:14, Bharat Bhushan wrote:
> 
> 
>> -----Original Message-----
>> From: Laurentiu Tudor
>> Sent: Monday, July 9, 2018 6:42 PM
>> To: Bharat Bhushan <bharat.bhushan@nxp.com>; York Sun
>> <york.sun@nxp.com>; Prabhakar Kushwaha
>> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
>> Subject: Re: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
>>
>> Hi Bharat,
>>
>> On 09.07.2018 15:13, Bharat Bhushan wrote:
>>>
>>>
>>>> -----Original Message-----
>>>> From: Laurentiu Tudor [mailto:laurentiu.tudor at nxp.com]
>>>> Sent: Wednesday, July 4, 2018 7:44 PM
>>>> To: York Sun <york.sun@nxp.com>; Prabhakar Kushwaha
>>>> <prabhakar.kushwaha@nxp.com>; u-boot at lists.denx.de
>>>> Cc: Bharat Bhushan <bharat.bhushan@nxp.com>; Laurentiu Tudor
>>>> <laurentiu.tudor@nxp.com>
>>>> Subject: [PATCH v3 5/7] armv8: ls1046a: initial icid setup support
>>>>
>>>> Add infrastructure for ICID setup and device tree fixup on ARM platforms.
>>>> This include basic ICID setup for several devices.
>>>>
>>>> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>>>> ---
>>>>    arch/arm/cpu/armv8/fsl-layerscape/Makefile    |   1 +
>>>>    arch/arm/cpu/armv8/fsl-layerscape/icid.c      | 111
>> ++++++++++++++++++
>>>>    .../arm/cpu/armv8/fsl-layerscape/ls1046_ids.c |  29 +++++
>>>>    arch/arm/cpu/armv8/fsl-layerscape/soc.c       |   3 +
>>>>    .../asm/arch-fsl-layerscape/fsl_icid.h        |  80 +++++++++++++
>>>>    board/freescale/ls1046aqds/ls1046aqds.c       |   2 +
>>>>    board/freescale/ls1046ardb/ls1046ardb.c       |   3 +
>>>>    7 files changed, 229 insertions(+)
>>>>    create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/icid.c
>>>>    create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1046_ids.c
>>>>    create mode 100644
>>>> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
>>>>
>>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>>>> b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>>>> index 1e9e4680fe..5d6f68aad6 100644
>>>> --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
>>>> @@ -37,6 +37,7 @@ endif
>>>>
>>>>    ifneq ($(CONFIG_ARCH_LS1046A),)
>>>>    obj-$(CONFIG_SYS_HAS_SERDES) += ls1046a_serdes.o
>>>> +obj-y += icid.o ls1046_ids.o
>>>>    endif
>>>>
>>>>    ifneq ($(CONFIG_ARCH_LS1088A),)
>>>> diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>>>> b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>>>> new file mode 100644
>>>> index 0000000000..8694bd6fa1
>>>> --- /dev/null
>>>> +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c
>>>> @@ -0,0 +1,111 @@
>>>> +// SPDX-License-Identifier: GPL-2.0+
>>>> +/*
>>>> + * Copyright 2018 NXP
>>>> + */
>>>> +
>>>> +#include <common.h>
>>>> +#include <linux/libfdt.h>
>>>> +#include <fdt_support.h>
>>>> +
>>>> +#include <asm/io.h>
>>>> +#include <asm/processor.h>
>>>> +#include <asm/arch-fsl-layerscape/fsl_icid.h>
>>>> +
>>>> +static void set_icid(struct icid_id_table *tbl, int size) {
>>>> +	int i;
>>>> +
>>>> +	for (i = 0; i < size; i++)
>>>> +		out_be32((u32 *)(tbl[i].reg_addr), tbl[i].reg); }
>>>> +
>>>> +void set_icids(void)
>>>> +{
>>>> +	/* setup general icid offsets */
>>>> +	set_icid(icid_tbl, icid_tbl_sz);
>>>> +}
>>>> +
>>>> +int fdt_set_iommu_prop(void *blob, int off, int smmu_ph, u32 *ids,
>>>> +int
>>>> +num_ids) {
>>>> +	int i, ret;
>>>> +	u32 prop[8];
>>>> +
>>>> +	for (i = 0; i < num_ids; i++) {
>>>> +		prop[i * 2] = cpu_to_fdt32(smmu_ph);
>>>> +		prop[i * 2 + 1] = cpu_to_fdt32(ids[i]);
>>>> +	}
>>>> +	ret = fdt_setprop(blob, off, "iommus",
>>>> +			  prop, sizeof(u32) * num_ids * 2);
>>>> +	if (ret > 0) {
>>>> +		printf("WARNING unable to set iommus: %s\n",
>>>> fdt_strerror(off));
>>>> +		return off;
>>>> +	}
>>>> +	ret = fdt_setprop_empty(blob, off, "dma-coherent");
>>>
>>> This forces "dma-coherent" for all SOCs, although there is no current
>> known SOCs which does not support non-coherent but maybe safe not to
>> set from common code.
>>
>> I see your point and will drop this.
>> Now, regarding a replacement solution, I don't have any other idea than
>> updating the device trees directly. Thoughts?
> 
> dma-coherent will be default in device tree and u-boot code should check if dma-coherent already set.

You mean add a check that dma-coherent isn't already there?

> Have another function exposed from generic code which set "dma-coherent" and platforms code will call that function if it is coherent.

Who would call such a function in the current design? Not sure I 
understand where this would fit in the current implementation.

On the other hand, I think that the dma coherency of a device is a hw 
property and it really makes sense to sit in the device tree.

---
Best Regards, Laurentiu

[U-Boot] [PATCH v3 7/7] armv8: ls1046a: setup fman ports ICIDs and device tree

[York Sun]

On 07/09/2018 05:26 AM, Bharat Bhushan wrote:

<snip>

>> @@ -74,7 +79,12 @@ void fdt_fixup_icid(void *blob);
>>  		CONFIG_SYS_FSL_BMAN_ADDR, \
>>  		CONFIG_SYS_FSL_BMAN_ADDR)
>>
>> +#define SET_FMAN_ICID_ENTRY(_port_id, _icid) \
>> +	{ .port_id = (_port_id), .icid = (_icid) }
> 
> Same comment as in 6/7 patch applies here also, use "streamed" or "icid" consistent with h/w or devicetree.
> 

Guys,

The discussion is healthy. Please trim the quoted messages to keep only
relevant context to make the comments easy to read. Thanks.

York