* [PATCH 0/3] clk: meson: add gen_clk
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: Jerome Brunet, linux-amlogic, linux-clk, linux-kernel
This patch adds GEN_CLK, which a very useful clock for debugging.
It allows to output most of the SoC plls through one of the SoC pad.
In the future, we could even use clk_measure with it to access the
vast majority of the SoC clocks.
Jerome Brunet (3):
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson: expose GEN_CLK clkid
clk: meson: add gen_clk
drivers/clk/meson/axg.c | 64 ++++++++++++++++++++++++++++++++-
drivers/clk/meson/axg.h | 4 ++-
drivers/clk/meson/gxbb.c | 66 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 5 +--
include/dt-bindings/clock/axg-clkc.h | 1 +
include/dt-bindings/clock/gxbb-clkc.h | 1 +
6 files changed, 137 insertions(+), 4 deletions(-)
--
2.14.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/3] clk: meson: add gen_clk
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: linus-amlogic
This patch adds GEN_CLK, which a very useful clock for debugging.
It allows to output most of the SoC plls through one of the SoC pad.
In the future, we could even use clk_measure with it to access the
vast majority of the SoC clocks.
Jerome Brunet (3):
clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
clk: meson: expose GEN_CLK clkid
clk: meson: add gen_clk
drivers/clk/meson/axg.c | 64 ++++++++++++++++++++++++++++++++-
drivers/clk/meson/axg.h | 4 ++-
drivers/clk/meson/gxbb.c | 66 +++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 5 +--
include/dt-bindings/clock/axg-clkc.h | 1 +
include/dt-bindings/clock/gxbb-clkc.h | 1 +
6 files changed, 137 insertions(+), 4 deletions(-)
--
2.14.4
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
2018-07-04 16:54 ` Jerome Brunet
(?)
@ 2018-07-04 16:54 ` Jerome Brunet
-1 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: Jerome Brunet, linux-amlogic, linux-clk, linux-kernel
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index ec1a812bf1fd..df6c21d368c6 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -66,7 +66,6 @@
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
-#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: linux-amlogic, linux-clk, linux-kernel, Jerome Brunet
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index ec1a812bf1fd..df6c21d368c6 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -66,7 +66,6 @@
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
-#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
--
2.14.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: linus-amlogic
HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition
Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.h | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index ec1a812bf1fd..df6c21d368c6 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -66,7 +66,6 @@
#define HHI_USB_CLK_CNTL 0x220 /* 0x88 offset in data sheet */
#define HHI_32K_CLK_CNTL 0x224 /* 0x89 offset in data sheet */
#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
-#define HHI_GEN_CLK_CNTL 0x228 /* 0x8a offset in data sheet */
#define HHI_PCM_CLK_CNTL 0x258 /* 0x96 offset in data sheet */
#define HHI_NAND_CLK_CNTL 0x25C /* 0x97 offset in data sheet */
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] clk: meson: expose GEN_CLK clkid
2018-07-04 16:54 ` Jerome Brunet
(?)
@ 2018-07-04 16:54 ` Jerome Brunet
-1 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: Jerome Brunet, linux-amlogic, linux-clk, linux-kernel
Expose GEN_CLK clock id
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
include/dt-bindings/clock/axg-clkc.h | 1 +
include/dt-bindings/clock/gxbb-clkc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 70371228b7e0..fd1f938c38d1 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -71,5 +71,6 @@
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
+#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 7a892be90549..3979d48c025f 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -127,5 +127,6 @@
#define CLKID_VAPB 140
#define CLKID_VDEC_1 153
#define CLKID_VDEC_HEVC 156
+#define CLKID_GEN_CLK 159
#endif /* __GXBB_CLKC_H */
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] clk: meson: expose GEN_CLK clkid
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: linux-amlogic, linux-clk, linux-kernel, Jerome Brunet
Expose GEN_CLK clock id
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
include/dt-bindings/clock/axg-clkc.h | 1 +
include/dt-bindings/clock/gxbb-clkc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 70371228b7e0..fd1f938c38d1 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -71,5 +71,6 @@
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
+#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 7a892be90549..3979d48c025f 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -127,5 +127,6 @@
#define CLKID_VAPB 140
#define CLKID_VDEC_1 153
#define CLKID_VDEC_HEVC 156
+#define CLKID_GEN_CLK 159
#endif /* __GXBB_CLKC_H */
--
2.14.4
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/3] clk: meson: expose GEN_CLK clkid
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: linus-amlogic
Expose GEN_CLK clock id
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
include/dt-bindings/clock/axg-clkc.h | 1 +
include/dt-bindings/clock/gxbb-clkc.h | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/dt-bindings/clock/axg-clkc.h b/include/dt-bindings/clock/axg-clkc.h
index 70371228b7e0..fd1f938c38d1 100644
--- a/include/dt-bindings/clock/axg-clkc.h
+++ b/include/dt-bindings/clock/axg-clkc.h
@@ -71,5 +71,6 @@
#define CLKID_PCIE_CML_EN0 79
#define CLKID_PCIE_CML_EN1 80
#define CLKID_MIPI_ENABLE 81
+#define CLKID_GEN_CLK 84
#endif /* __AXG_CLKC_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index 7a892be90549..3979d48c025f 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -127,5 +127,6 @@
#define CLKID_VAPB 140
#define CLKID_VDEC_1 153
#define CLKID_VDEC_HEVC 156
+#define CLKID_GEN_CLK 159
#endif /* __GXBB_CLKC_H */
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/3] clk: meson: add gen_clk
2018-07-04 16:54 ` Jerome Brunet
@ 2018-07-04 16:54 ` Jerome Brunet
-1 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: Jerome Brunet, linux-amlogic, linux-clk, linux-kernel
GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/axg.c | 64 +++++++++++++++++++++++++++++++++++++++++++++-
drivers/clk/meson/axg.h | 4 ++-
drivers/clk/meson/gxbb.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 4 ++-
4 files changed, 135 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2d458092884a..00ce62ad6416 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -909,6 +909,63 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
},
};
+static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
+ 9, 10, 11, 13, 14, };
+static const char * const gen_clk_parent_names[] = {
+ "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+};
+
+static struct clk_regmap axg_gen_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .mask = 0xf,
+ .shift = 12,
+ .table = mux_table_gen_clk,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ /*
+ * bits 15:12 selects from 14 possible parents:
+ * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
+ * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
+ * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
+ */
+ .parent_names = gen_clk_parent_names,
+ .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+ },
+};
+
+static struct clk_regmap axg_gen_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "gen_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap axg_gen_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "gen_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
@@ -1047,7 +1104,9 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
[CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
-
+ [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &axg_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1132,6 +1191,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_pcie_cml_en0,
&axg_pcie_cml_en1,
&axg_mipi_enable,
+ &axg_gen_clk_sel,
+ &axg_gen_clk_div,
+ &axg_gen_clk,
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 6e55ebd6c77d..1d04144a1b2c 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -131,8 +131,10 @@
#define CLKID_PCIE_PLL 76
#define CLKID_PCIE_MUX 77
#define CLKID_PCIE_REF 78
+#define CLKID_GEN_CLK_SEL 82
+#define CLKID_GEN_CLK_DIV 83
-#define NR_CLKS 82
+#define NR_CLKS 85
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 894a6adaa17a..86d3ae58e84c 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1624,6 +1624,63 @@ static struct clk_regmap gxbb_vdec_hevc = {
},
};
+static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
+ 9, 10, 11, 13, 14, };
+static const char * const gen_clk_parent_names[] = {
+ "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+};
+
+static struct clk_regmap gxbb_gen_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .mask = 0xf,
+ .shift = 12,
+ .table = mux_table_gen_clk,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ /*
+ * bits 15:12 selects from 14 possible parents:
+ * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
+ * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
+ * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
+ */
+ .parent_names = gen_clk_parent_names,
+ .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+ },
+};
+
+static struct clk_regmap gxbb_gen_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "gen_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_gen_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "gen_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1873,6 +1930,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2035,6 +2095,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2199,6 +2262,9 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_vdec_hevc_sel,
&gxbb_vdec_hevc_div,
&gxbb_vdec_hevc,
+ &gxbb_gen_clk_sel,
+ &gxbb_gen_clk_div,
+ &gxbb_gen_clk,
};
struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index df6c21d368c6..20dfb1daf5b8 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -157,8 +157,10 @@
#define CLKID_VDEC_1_DIV 152
#define CLKID_VDEC_HEVC_SEL 154
#define CLKID_VDEC_HEVC_DIV 155
+#define CLKID_GEN_CLK_SEL 157
+#define CLKID_GEN_CLK_DIV 158
-#define NR_CLKS 157
+#define NR_CLKS 160
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 3/3] clk: meson: add gen_clk
@ 2018-07-04 16:54 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-04 16:54 UTC (permalink / raw)
To: linus-amlogic
GEN_CLK is able to route several internal clocks to one of the SoC
pads. In the future, even more clocks could be made accessible using
cts_msr_clk - the clock measure block.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/axg.c | 64 +++++++++++++++++++++++++++++++++++++++++++++-
drivers/clk/meson/axg.h | 4 ++-
drivers/clk/meson/gxbb.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++++
drivers/clk/meson/gxbb.h | 4 ++-
4 files changed, 135 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 2d458092884a..00ce62ad6416 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -909,6 +909,63 @@ static struct clk_regmap axg_sd_emmc_c_clk0 = {
},
};
+static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
+ 9, 10, 11, 13, 14, };
+static const char * const gen_clk_parent_names[] = {
+ "xtal", "hifi_pll", "mpll0", "mpll1", "mpll2", "mpll3",
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+};
+
+static struct clk_regmap axg_gen_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .mask = 0xf,
+ .shift = 12,
+ .table = mux_table_gen_clk,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ /*
+ * bits 15:12 selects from 14 possible parents:
+ * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
+ * hifi_pll, mpll0, mpll1, mpll2, mpll3, fdiv4,
+ * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
+ */
+ .parent_names = gen_clk_parent_names,
+ .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+ },
+};
+
+static struct clk_regmap axg_gen_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "gen_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap axg_gen_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "gen_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(axg_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(axg_audio_locker, HHI_GCLK_MPEG0, 2);
@@ -1047,7 +1104,9 @@ static struct clk_hw_onecell_data axg_hw_onecell_data = {
[CLKID_PCIE_CML_EN0] = &axg_pcie_cml_en0.hw,
[CLKID_PCIE_CML_EN1] = &axg_pcie_cml_en1.hw,
[CLKID_MIPI_ENABLE] = &axg_mipi_enable.hw,
-
+ [CLKID_GEN_CLK_SEL] = &axg_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &axg_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &axg_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -1132,6 +1191,9 @@ static struct clk_regmap *const axg_clk_regmaps[] = {
&axg_pcie_cml_en0,
&axg_pcie_cml_en1,
&axg_mipi_enable,
+ &axg_gen_clk_sel,
+ &axg_gen_clk_div,
+ &axg_gen_clk,
};
static const struct of_device_id clkc_match_table[] = {
diff --git a/drivers/clk/meson/axg.h b/drivers/clk/meson/axg.h
index 6e55ebd6c77d..1d04144a1b2c 100644
--- a/drivers/clk/meson/axg.h
+++ b/drivers/clk/meson/axg.h
@@ -131,8 +131,10 @@
#define CLKID_PCIE_PLL 76
#define CLKID_PCIE_MUX 77
#define CLKID_PCIE_REF 78
+#define CLKID_GEN_CLK_SEL 82
+#define CLKID_GEN_CLK_DIV 83
-#define NR_CLKS 82
+#define NR_CLKS 85
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/axg-clkc.h>
diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c
index 894a6adaa17a..86d3ae58e84c 100644
--- a/drivers/clk/meson/gxbb.c
+++ b/drivers/clk/meson/gxbb.c
@@ -1624,6 +1624,63 @@ static struct clk_regmap gxbb_vdec_hevc = {
},
};
+static u32 mux_table_gen_clk[] = { 0, 4, 5, 6, 7, 8,
+ 9, 10, 11, 13, 14, };
+static const char * const gen_clk_parent_names[] = {
+ "xtal", "vdec_1", "vdec_hevc", "mpll0", "mpll1", "mpll2",
+ "fclk_div4", "fclk_div3", "fclk_div5", "fclk_div7", "gp0_pll",
+};
+
+static struct clk_regmap gxbb_gen_clk_sel = {
+ .data = &(struct clk_regmap_mux_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .mask = 0xf,
+ .shift = 12,
+ .table = mux_table_gen_clk,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_sel",
+ .ops = &clk_regmap_mux_ops,
+ /*
+ * bits 15:12 selects from 14 possible parents:
+ * xtal, [rtc_oscin_i], [sys_cpu_div16], [ddr_dpll_pt],
+ * vid_pll, vid2_pll (hevc), mpll0, mpll1, mpll2, fdiv4,
+ * fdiv3, fdiv5, [cts_msr_clk], fdiv7, gp0_pll
+ */
+ .parent_names = gen_clk_parent_names,
+ .num_parents = ARRAY_SIZE(gen_clk_parent_names),
+ },
+};
+
+static struct clk_regmap gxbb_gen_clk_div = {
+ .data = &(struct clk_regmap_div_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .shift = 0,
+ .width = 11,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk_div",
+ .ops = &clk_regmap_divider_ops,
+ .parent_names = (const char *[]){ "gen_clk_sel" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
+static struct clk_regmap gxbb_gen_clk = {
+ .data = &(struct clk_regmap_gate_data){
+ .offset = HHI_GEN_CLK_CNTL,
+ .bit_idx = 7,
+ },
+ .hw.init = &(struct clk_init_data){
+ .name = "gen_clk",
+ .ops = &clk_regmap_gate_ops,
+ .parent_names = (const char *[]){ "gen_clk_div" },
+ .num_parents = 1,
+ .flags = CLK_SET_RATE_PARENT,
+ },
+};
+
/* Everything Else (EE) domain gates */
static MESON_GATE(gxbb_ddr, HHI_GCLK_MPEG0, 0);
static MESON_GATE(gxbb_dos, HHI_GCLK_MPEG0, 1);
@@ -1873,6 +1930,9 @@ static struct clk_hw_onecell_data gxbb_hw_onecell_data = {
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2035,6 +2095,9 @@ static struct clk_hw_onecell_data gxl_hw_onecell_data = {
[CLKID_VDEC_HEVC_SEL] = &gxbb_vdec_hevc_sel.hw,
[CLKID_VDEC_HEVC_DIV] = &gxbb_vdec_hevc_div.hw,
[CLKID_VDEC_HEVC] = &gxbb_vdec_hevc.hw,
+ [CLKID_GEN_CLK_SEL] = &gxbb_gen_clk_sel.hw,
+ [CLKID_GEN_CLK_DIV] = &gxbb_gen_clk_div.hw,
+ [CLKID_GEN_CLK] = &gxbb_gen_clk.hw,
[NR_CLKS] = NULL,
},
.num = NR_CLKS,
@@ -2199,6 +2262,9 @@ static struct clk_regmap *const gx_clk_regmaps[] = {
&gxbb_vdec_hevc_sel,
&gxbb_vdec_hevc_div,
&gxbb_vdec_hevc,
+ &gxbb_gen_clk_sel,
+ &gxbb_gen_clk_div,
+ &gxbb_gen_clk,
};
struct clkc_data {
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index df6c21d368c6..20dfb1daf5b8 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -157,8 +157,10 @@
#define CLKID_VDEC_1_DIV 152
#define CLKID_VDEC_HEVC_SEL 154
#define CLKID_VDEC_HEVC_DIV 155
+#define CLKID_GEN_CLK_SEL 157
+#define CLKID_GEN_CLK_DIV 158
-#define NR_CLKS 157
+#define NR_CLKS 160
/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
--
2.14.4
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
2018-07-04 16:54 ` Jerome Brunet
@ 2018-07-04 17:34 ` Martin Blumenstingl
-1 siblings, 0 replies; 15+ messages in thread
From: Martin Blumenstingl @ 2018-07-04 17:34 UTC (permalink / raw)
To: jbrunet
Cc: Neil Armstrong, khilman, carlo, linux-amlogic, linux-clk, linux-kernel
On Wed, Jul 4, 2018 at 6:55 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition
>
> Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
good catch Jerome!
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
@ 2018-07-04 17:34 ` Martin Blumenstingl
0 siblings, 0 replies; 15+ messages in thread
From: Martin Blumenstingl @ 2018-07-04 17:34 UTC (permalink / raw)
To: linus-amlogic
On Wed, Jul 4, 2018 at 6:55 PM Jerome Brunet <jbrunet@baylibre.com> wrote:
>
> HHI_GEN_CLK_CTNL is defined twice, just remove the duplicate definition
>
> Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver")
> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
good catch Jerome!
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/3] clk: meson: add gen_clk
2018-07-04 16:54 ` Jerome Brunet
(?)
@ 2018-07-09 12:55 ` Jerome Brunet
-1 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-09 12:55 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: linux-amlogic, linux-clk, linux-kernel
On Wed, 2018-07-04 at 18:54 +0200, Jerome Brunet wrote:
> Jerome Brunet (3):
> clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
> clk: meson: expose GEN_CLK clkid
> clk: meson: add gen_clk
Applied
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/3] clk: meson: add gen_clk
@ 2018-07-09 12:55 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-09 12:55 UTC (permalink / raw)
To: Neil Armstrong, Kevin Hilman, Carlo Caione
Cc: linux-amlogic, linux-clk, linux-kernel
On Wed, 2018-07-04 at 18:54 +0200, Jerome Brunet wrote:
> Jerome Brunet (3):
> clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
> clk: meson: expose GEN_CLK clkid
> clk: meson: add gen_clk
Applied
_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic
^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 0/3] clk: meson: add gen_clk
@ 2018-07-09 12:55 ` Jerome Brunet
0 siblings, 0 replies; 15+ messages in thread
From: Jerome Brunet @ 2018-07-09 12:55 UTC (permalink / raw)
To: linus-amlogic
On Wed, 2018-07-04 at 18:54 +0200, Jerome Brunet wrote:
> Jerome Brunet (3):
> clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition
> clk: meson: expose GEN_CLK clkid
> clk: meson: add gen_clk
Applied
^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2018-07-09 12:56 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-04 16:54 [PATCH 0/3] clk: meson: add gen_clk Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-04 16:54 ` [PATCH 1/3] clk: meson: gxbb: remove HHI_GEN_CLK_CTNL duplicate definition Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-04 17:34 ` Martin Blumenstingl
2018-07-04 17:34 ` Martin Blumenstingl
2018-07-04 16:54 ` [PATCH 2/3] clk: meson: expose GEN_CLK clkid Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-04 16:54 ` [PATCH 3/3] clk: meson: add gen_clk Jerome Brunet
2018-07-04 16:54 ` Jerome Brunet
2018-07-09 12:55 ` [PATCH 0/3] " Jerome Brunet
2018-07-09 12:55 ` Jerome Brunet
2018-07-09 12:55 ` Jerome Brunet
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.