[PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[Chris Wilson]

As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index 39779dbed..0b4972e37 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
 	}
 }
 
+static bool known_swizzling(uint32_t handle)
+{
+	struct drm_i915_gem_get_tiling arg = {
+		.handle = handle,
+	};
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
+		return false;
+
+	return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
 igt_main
 {
 	uint32_t tiling_mode = I915_TILING_X;
@@ -272,6 +284,12 @@ igt_main
 						      &tiling_mode, &scratch_pitch, 0);
 		igt_assert(tiling_mode == I915_TILING_X);
 		igt_assert(scratch_pitch == 4096);
+
+		/*
+		 * As we want to compare our template tiled pattern against
+		 * the target bo, we need consistent swizzling on both.
+		 */
+		igt_require(known_swizzling(scratch_bo->handle));
 		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
 							    BO_SIZE/4096, 4,
-- 
2.18.0

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[Intel-gfx] [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[Chris Wilson]

As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
---
 tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
 1 file changed, 18 insertions(+)

diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index 39779dbed..0b4972e37 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
 	}
 }
 
+static bool known_swizzling(uint32_t handle)
+{
+	struct drm_i915_gem_get_tiling arg = {
+		.handle = handle,
+	};
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
+		return false;
+
+	return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
 igt_main
 {
 	uint32_t tiling_mode = I915_TILING_X;
@@ -272,6 +284,12 @@ igt_main
 						      &tiling_mode, &scratch_pitch, 0);
 		igt_assert(tiling_mode == I915_TILING_X);
 		igt_assert(scratch_pitch == 4096);
+
+		/*
+		 * As we want to compare our template tiled pattern against
+		 * the target bo, we need consistent swizzling on both.
+		 */
+		igt_require(known_swizzling(scratch_bo->handle));
 		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
 							    BO_SIZE/4096, 4,
-- 
2.18.0

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[igt-dev] ✓ Fi.CI.BAT: success for igt/gem_tiled_partial_pwrite_pread: Check for known swizzling (rev2)

[Patchwork]

== Series Details ==

Series: igt/gem_tiled_partial_pwrite_pread: Check for known swizzling (rev2)
URL   : https://patchwork.freedesktop.org/series/44830/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4434 -> IGTPW_1539 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44830/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1539:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_suspend@basic-s4-devices:
      {fi-kbl-8809g}:     INCOMPLETE -> DMESG-WARN

    
== Known issues ==

  Here are the changes found in IGTPW_1539 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@read-crc-pipe-a:
      fi-skl-6700k2:      FAIL (fdo#103191) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191


== Participating hosts (46 -> 42) ==

  Additional (1): fi-skl-guc 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * IGT: IGT_4538 -> IGTPW_1539

  CI_DRM_4434: 2fa1923491b6f391b5048d74f54a9450ee8ba673 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1539: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1539/
  IGT_4538: 9b3f41a6c6da7d767516a93dccf17469a551e942 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1539/issues.html
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Re: [igt-dev] [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[Tvrtko Ursulin]

On 05/07/2018 20:26, Chris Wilson wrote:
> As we want to compare a templated tiling pattern against the target_bo,
> we need to know that the swizzling is compatible. Or else the two
> tiling pattern may differ due to underlying page address that we cannot
> know, and so the test may sporadically fail.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
> index 39779dbed..0b4972e37 100644
> --- a/tests/gem_tiled_partial_pwrite_pread.c
> +++ b/tests/gem_tiled_partial_pwrite_pread.c
> @@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
>   	}
>   }
>   
> +static bool known_swizzling(uint32_t handle)
> +{
> +	struct drm_i915_gem_get_tiling arg = {
> +		.handle = handle,
> +	};
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
> +		return false;
> +
> +	return arg.phys_swizzle_mode == arg.swizzle_mode;
> +}
> +
>   igt_main
>   {
>   	uint32_t tiling_mode = I915_TILING_X;
> @@ -272,6 +284,12 @@ igt_main
>   						      &tiling_mode, &scratch_pitch, 0);
>   		igt_assert(tiling_mode == I915_TILING_X);
>   		igt_assert(scratch_pitch == 4096);
> +
> +		/*
> +		 * As we want to compare our template tiled pattern against
> +		 * the target bo, we need consistent swizzling on both.
> +		 */
> +		igt_require(known_swizzling(scratch_bo->handle));
>   		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
>   		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
>   							    BO_SIZE/4096, 4,
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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Re: [Intel-gfx] [igt-dev] [PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[Tvrtko Ursulin]

On 05/07/2018 20:26, Chris Wilson wrote:
> As we want to compare a templated tiling pattern against the target_bo,
> we need to know that the swizzling is compatible. Or else the two
> tiling pattern may differ due to underlying page address that we cannot
> know, and so the test may sporadically fail.
> 
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> ---
>   tests/gem_tiled_partial_pwrite_pread.c | 18 ++++++++++++++++++
>   1 file changed, 18 insertions(+)
> 
> diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
> index 39779dbed..0b4972e37 100644
> --- a/tests/gem_tiled_partial_pwrite_pread.c
> +++ b/tests/gem_tiled_partial_pwrite_pread.c
> @@ -249,6 +249,18 @@ static void test_partial_read_writes(void)
>   	}
>   }
>   
> +static bool known_swizzling(uint32_t handle)
> +{
> +	struct drm_i915_gem_get_tiling arg = {
> +		.handle = handle,
> +	};
> +
> +	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING, &arg))
> +		return false;
> +
> +	return arg.phys_swizzle_mode == arg.swizzle_mode;
> +}
> +
>   igt_main
>   {
>   	uint32_t tiling_mode = I915_TILING_X;
> @@ -272,6 +284,12 @@ igt_main
>   						      &tiling_mode, &scratch_pitch, 0);
>   		igt_assert(tiling_mode == I915_TILING_X);
>   		igt_assert(scratch_pitch == 4096);
> +
> +		/*
> +		 * As we want to compare our template tiled pattern against
> +		 * the target bo, we need consistent swizzling on both.
> +		 */
> +		igt_require(known_swizzling(scratch_bo->handle));
>   		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
>   		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
>   							    BO_SIZE/4096, 4,
> 

Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>

Regards,

Tvrtko
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[igt-dev] ✗ Fi.CI.IGT: failure for igt/gem_tiled_partial_pwrite_pread: Check for known swizzling (rev2)

[Patchwork]

== Series Details ==

Series: igt/gem_tiled_partial_pwrite_pread: Check for known swizzling (rev2)
URL   : https://patchwork.freedesktop.org/series/44830/
State : failure

== Summary ==

= CI Bug Log - changes from IGT_4538_full -> IGTPW_1539_full =

== Summary - FAILURE ==

  Serious unknown changes coming with IGTPW_1539_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in IGTPW_1539_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/44830/revisions/2/mbox/

== Possible new issues ==

  Here are the unknown changes that may have been introduced in IGTPW_1539_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@kms_flip_tiling@flip-x-tiled:
      shard-glk:          PASS -> FAIL

    
    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          PASS -> SKIP +5

    
== Known issues ==

  Here are the changes found in IGTPW_1539_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_gtt:
      shard-kbl:          PASS -> FAIL (fdo#107127, fdo#105347)

    igt@kms_flip@plain-flip-fb-recreate-interruptible:
      shard-glk:          PASS -> FAIL (fdo#100368)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@kms_vblank@pipe-b-ts-continuation-suspend:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665)

    igt@testdisplay:
      shard-glk:          PASS -> INCOMPLETE (fdo#103359, k.org#198133)

    
    ==== Possible fixes ====

    igt@kms_flip@2x-wf_vblank-ts-check:
      shard-glk:          FAIL (fdo#100368) -> PASS +1

    igt@kms_flip_tiling@flip-to-x-tiled:
      shard-glk:          FAIL (fdo#103822) -> PASS +1

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
      shard-snb:          DMESG-WARN (fdo#102365) -> PASS

    igt@kms_plane_multiple@atomic-pipe-a-tiling-x:
      shard-snb:          FAIL (fdo#103166) -> PASS

    igt@kms_rotation_crc@sprite-rotation-180:
      shard-snb:          FAIL (fdo#103925) -> PASS

    
    ==== Warnings ====

    igt@drv_selftest@live_gtt:
      shard-apl:          INCOMPLETE (fdo#107127, fdo#103927) -> FAIL (fdo#107127, fdo#105347)

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102365 https://bugs.freedesktop.org/show_bug.cgi?id=102365
  fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103822 https://bugs.freedesktop.org/show_bug.cgi?id=103822
  fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105347 https://bugs.freedesktop.org/show_bug.cgi?id=105347
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#107127 https://bugs.freedesktop.org/show_bug.cgi?id=107127
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * IGT: IGT_4538 -> IGTPW_1539
    * Linux: CI_DRM_4431 -> CI_DRM_4434

  CI_DRM_4431: b9bf725e2d248638a834b4b4db5b684098216b86 @ git://anongit.freedesktop.org/gfx-ci/linux
  CI_DRM_4434: 2fa1923491b6f391b5048d74f54a9450ee8ba673 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGTPW_1539: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1539/
  IGT_4538: 9b3f41a6c6da7d767516a93dccf17469a551e942 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/IGTPW_1539/shards.html
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[PATCH i-g-t] igt/gem_tiled_partial_pwrite_pread: Check for known swizzling

[Chris Wilson]

As we want to compare a templated tiling pattern against the target_bo,
we need to know that the swizzling is compatible. Or else the two
tiling pattern may differ due to underlying page address that we cannot
know, and so the test may sporadically fail.

References: https://bugs.freedesktop.org/show_bug.cgi?id=102575
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
 tests/gem_tiled_partial_pwrite_pread.c | 24 ++++++++++++++++++++++++
 1 file changed, 24 insertions(+)

diff --git a/tests/gem_tiled_partial_pwrite_pread.c b/tests/gem_tiled_partial_pwrite_pread.c
index fe573c37c..83c57c07d 100644
--- a/tests/gem_tiled_partial_pwrite_pread.c
+++ b/tests/gem_tiled_partial_pwrite_pread.c
@@ -249,6 +249,24 @@ static void test_partial_read_writes(void)
 	}
 }
 
+static bool known_swizzling(uint32_t handle)
+{
+	struct drm_i915_gem_get_tiling2 {
+		uint32_t handle;
+		uint32_t tiling_mode;
+		uint32_t swizzle_mode;
+		uint32_t phys_swizzle_mode;
+	} arg = {
+		.handle = handle,
+	};
+#define DRM_IOCTL_I915_GEM_GET_TILING2	DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling2)
+
+	if (igt_ioctl(fd, DRM_IOCTL_I915_GEM_GET_TILING2, &arg))
+		return false;
+
+	return arg.phys_swizzle_mode == arg.swizzle_mode;
+}
+
 igt_main
 {
 	uint32_t tiling_mode = I915_TILING_X;
@@ -271,6 +289,12 @@ igt_main
 						      &tiling_mode, &scratch_pitch, 0);
 		igt_assert(tiling_mode == I915_TILING_X);
 		igt_assert(scratch_pitch == 4096);
+
+		/*
+		 * As we want to compare our template tiled pattern against
+		 * the target bo, we need consistent swizzling on both.
+		 */
+		igt_require(known_swizzling(scratch_bo->handle));
 		staging_bo = drm_intel_bo_alloc(bufmgr, "staging bo", BO_SIZE, 4096);
 		tiled_staging_bo = drm_intel_bo_alloc_tiled(bufmgr, "scratch bo", 1024,
 							    BO_SIZE/4096, 4,
-- 
2.17.1

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