* [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-03 19:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: Shawn Guo, Fabio Estevam, Sascha Hauer Cc: linux-arm-kernel, devicetree, Rob Herring, NXP Linux Team, Pengutronix Kernel Team The changeset combines a number of essential updates to support device tree on Freescale i.MX31 powered boards: * removal of bogus RNGA registration for i.MX31 (device tree only), * the core controllers on the i.MX31 SoC are now properly described, * for reference and testing I add basic support of LogicPD MX31Lite board. There are some missing compatibles in the change 2/3, however at the moment I assume that either adding the values can be omitted or deferred, here is the exact list: * "fsl,imx31-pata" * "fsl,imx31-rtc" * "fsl,imx31-nand" * "fsl,imx31-weim" To test the changes I used a LogicPD reference board, however note that still I have to add a workaround to the old known issue within imx-wdt driver, also I perform testing with my own and not yet shared imx31 pinctrl driver, but obviously the device tree pinctrl changes are irrelevant to the code from this series. Vladimir Zapolskiy (3): ARM: i.MX31: remove rnga registration as a platform device ARM: dts: imx31: add device tree description of basic controllers ARM: dts: imx31: add LogicPD MX31Lite board description arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx31.dtsi | 222 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx31-dt.c | 18 ---- 4 files changed, 401 insertions(+), 19 deletions(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts -- 2.10.2 ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-03 19:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: linux-arm-kernel The changeset combines a number of essential updates to support device tree on Freescale i.MX31 powered boards: * removal of bogus RNGA registration for i.MX31 (device tree only), * the core controllers on the i.MX31 SoC are now properly described, * for reference and testing I add basic support of LogicPD MX31Lite board. There are some missing compatibles in the change 2/3, however at the moment I assume that either adding the values can be omitted or deferred, here is the exact list: * "fsl,imx31-pata" * "fsl,imx31-rtc" * "fsl,imx31-nand" * "fsl,imx31-weim" To test the changes I used a LogicPD reference board, however note that still I have to add a workaround to the old known issue within imx-wdt driver, also I perform testing with my own and not yet shared imx31 pinctrl driver, but obviously the device tree pinctrl changes are irrelevant to the code from this series. Vladimir Zapolskiy (3): ARM: i.MX31: remove rnga registration as a platform device ARM: dts: imx31: add device tree description of basic controllers ARM: dts: imx31: add LogicPD MX31Lite board description arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++ arch/arm/boot/dts/imx31.dtsi | 222 +++++++++++++++++++++++++++++++++++++++ arch/arm/mach-imx/imx31-dt.c | 18 ---- 4 files changed, 401 insertions(+), 19 deletions(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts -- 2.10.2 ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/3] ARM: i.MX31: remove rnga registration as a platform device 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-03 19:29 ` Vladimir Zapolskiy -1 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: Shawn Guo, Fabio Estevam, Sascha Hauer Cc: linux-arm-kernel, devicetree, Rob Herring, NXP Linux Team, Pengutronix Kernel Team On i.MX31 powered boards with OF support Security Random Number Generator Accelerator RNGA controller is initialized from device tree, its registration as a platform device is redundant and actually it is broken due to missing clock information: mxc_rnga mxc_rnga: Could not get rng_clk! mxc_rnga: probe of mxc_rnga failed with error -2 Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/mach-imx/imx31-dt.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 668d74b..9d9640a 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -9,35 +9,17 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/mach/time.h> - #include "common.h" -#include "mx31.h" static const char * const imx31_dt_board_compat[] __initconst = { "fsl,imx31", NULL }; -/* FIXME: replace with DT binding */ -static const struct resource imx31_rnga_res[] __initconst = { - DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), -}; - -static void __init imx31_dt_mach_init(void) -{ - platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, - ARRAY_SIZE(imx31_rnga_res)); -} - DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, - .init_machine = imx31_dt_mach_init, .dt_compat = imx31_dt_board_compat, MACHINE_END -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 1/3] ARM: i.MX31: remove rnga registration as a platform device @ 2018-07-03 19:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: linux-arm-kernel On i.MX31 powered boards with OF support Security Random Number Generator Accelerator RNGA controller is initialized from device tree, its registration as a platform device is redundant and actually it is broken due to missing clock information: mxc_rnga mxc_rnga: Could not get rng_clk! mxc_rnga: probe of mxc_rnga failed with error -2 Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/mach-imx/imx31-dt.c | 18 ------------------ 1 file changed, 18 deletions(-) diff --git a/arch/arm/mach-imx/imx31-dt.c b/arch/arm/mach-imx/imx31-dt.c index 668d74b..9d9640a 100644 --- a/arch/arm/mach-imx/imx31-dt.c +++ b/arch/arm/mach-imx/imx31-dt.c @@ -9,35 +9,17 @@ * http://www.gnu.org/copyleft/gpl.html */ -#include <linux/irq.h> -#include <linux/of_irq.h> -#include <linux/of_platform.h> #include <asm/mach/arch.h> -#include <asm/mach/time.h> - #include "common.h" -#include "mx31.h" static const char * const imx31_dt_board_compat[] __initconst = { "fsl,imx31", NULL }; -/* FIXME: replace with DT binding */ -static const struct resource imx31_rnga_res[] __initconst = { - DEFINE_RES_MEM(MX31_RNGA_BASE_ADDR, SZ_16K), -}; - -static void __init imx31_dt_mach_init(void) -{ - platform_device_register_simple("mxc_rnga", -1, imx31_rnga_res, - ARRAY_SIZE(imx31_rnga_res)); -} - DT_MACHINE_START(IMX31_DT, "Freescale i.MX31 (Device Tree Support)") .map_io = mx31_map_io, .init_early = imx31_init_early, .init_irq = mx31_init_irq, - .init_machine = imx31_dt_mach_init, .dt_compat = imx31_dt_board_compat, MACHINE_END -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 1/3] ARM: i.MX31: remove rnga registration as a platform device 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-05 0:55 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 0:55 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > On i.MX31 powered boards with OF support Security Random Number > Generator Accelerator RNGA controller is initialized from device tree, > its registration as a platform device is redundant and actually it is > broken due to missing clock information: > > mxc_rnga mxc_rnga: Could not get rng_clk! > mxc_rnga: probe of mxc_rnga failed with error -2 > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 1/3] ARM: i.MX31: remove rnga registration as a platform device @ 2018-07-05 0:55 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 0:55 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > On i.MX31 powered boards with OF support Security Random Number > Generator Accelerator RNGA controller is initialized from device tree, > its registration as a platform device is redundant and actually it is > broken due to missing clock information: > > mxc_rnga mxc_rnga: Could not get rng_clk! > mxc_rnga: probe of mxc_rnga failed with error -2 > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-03 19:29 ` Vladimir Zapolskiy -1 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: Shawn Guo, Fabio Estevam, Sascha Hauer Cc: linux-arm-kernel, devicetree, Rob Herring, NXP Linux Team, Pengutronix Kernel Team The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/imx31.dtsi | 222 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 222 insertions(+) diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c81..62bafa6 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> / { @@ -15,11 +16,22 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &sdhci1; + mmc1 = &sdhci2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +59,11 @@ interrupt-parent = <&avic>; ranges; + iram: iram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + }; + aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +71,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +117,29 @@ status = "disabled"; }; + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +174,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +205,19 @@ status = "disabled"; }; + spi2: cspi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +240,19 @@ #clock-cells = <1>; }; + spi3: cspi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +260,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-03 19:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: linux-arm-kernel The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/imx31.dtsi | 222 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 222 insertions(+) diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c81..62bafa6 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> / { @@ -15,11 +16,22 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; + mmc0 = &sdhci1; + mmc1 = &sdhci2; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +59,11 @@ interrupt-parent = <&avic>; ranges; + iram: iram at 1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + }; + aips at 43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +71,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c at 43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c at 43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata at 43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial at 43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +117,29 @@ status = "disabled"; }; + i2c2: i2c at 43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi at 43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp at 43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +174,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci at 50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci at 50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial at 5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +205,19 @@ status = "disabled"; }; + spi2: cspi at 50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim at 5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +240,19 @@ #clock-cells = <1>; }; + spi3: cspi at 53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer at 53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +260,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio at 53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng at 53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio at 53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma at 53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc at 53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog at 53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm at 53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi at b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand at b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim at b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-05 1:01 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:01 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The change adds a number of basic peripherals found on i.MX31 SoC: > * GPIO controllers, > * I2C master controllers, > * SPI master controllers, > * ATA controller, > * SDHC controllers, > * RTC, watchdog and PWM contollers, > * SDMA, > * IRAM, > * NAND and WEIM controllers on EMI. > > The added controller devices were tested on Freescale i.MX31 powered > LogicPD Lite SoM and baseboard. > > DMA functionality was tested on SDHC and SPI controllers so far, > thus dmas properties are added to those device nodes only. > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-05 1:01 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:01 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The change adds a number of basic peripherals found on i.MX31 SoC: > * GPIO controllers, > * I2C master controllers, > * SPI master controllers, > * ATA controller, > * SDHC controllers, > * RTC, watchdog and PWM contollers, > * SDMA, > * IRAM, > * NAND and WEIM controllers on EMI. > > The added controller devices were tested on Freescale i.MX31 powered > LogicPD Lite SoM and baseboard. > > DMA functionality was tested on SDHC and SPI controllers so far, > thus dmas properties are added to those device nodes only. > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-05 1:01 ` Fabio Estevam @ 2018-07-05 19:09 ` Vladimir Zapolskiy -1 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-05 19:09 UTC (permalink / raw) To: Fabio Estevam Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Fabio, On 07/05/2018 04:01 AM, Fabio Estevam wrote: > On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: >> The change adds a number of basic peripherals found on i.MX31 SoC: >> * GPIO controllers, >> * I2C master controllers, >> * SPI master controllers, >> * ATA controller, >> * SDHC controllers, >> * RTC, watchdog and PWM contollers, >> * SDMA, >> * IRAM, >> * NAND and WEIM controllers on EMI. >> >> The added controller devices were tested on Freescale i.MX31 powered >> LogicPD Lite SoM and baseboard. >> >> DMA functionality was tested on SDHC and SPI controllers so far, >> thus dmas properties are added to those device nodes only. >> >> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> thank you for review, please note that I've just sent v2 with a couple of minor fixes as a reply to v1 2/3, I hope that I didn't introduce a mess to the series. And again I hope that a number of missing SoC specific compatibles could be added to the documentation later on, at the moment generic variants are good enough to run the corresponding drivers. -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-05 19:09 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-05 19:09 UTC (permalink / raw) To: linux-arm-kernel Hi Fabio, On 07/05/2018 04:01 AM, Fabio Estevam wrote: > On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: >> The change adds a number of basic peripherals found on i.MX31 SoC: >> * GPIO controllers, >> * I2C master controllers, >> * SPI master controllers, >> * ATA controller, >> * SDHC controllers, >> * RTC, watchdog and PWM contollers, >> * SDMA, >> * IRAM, >> * NAND and WEIM controllers on EMI. >> >> The added controller devices were tested on Freescale i.MX31 powered >> LogicPD Lite SoM and baseboard. >> >> DMA functionality was tested on SDHC and SPI controllers so far, >> thus dmas properties are added to those device nodes only. >> >> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> > > Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> thank you for review, please note that I've just sent v2 with a couple of minor fixes as a reply to v1 2/3, I hope that I didn't introduce a mess to the series. And again I hope that a number of missing SoC specific compatibles could be added to the documentation later on, at the moment generic variants are good enough to run the corresponding drivers. -- Best wishes, Vladimir ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-05 19:09 ` Vladimir Zapolskiy @ 2018-07-11 16:21 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-11 16:21 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Vladimir, On Thu, Jul 5, 2018 at 4:09 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > thank you for review, please note that I've just sent v2 with a couple > of minor fixes as a reply to v1 2/3, I hope that I didn't introduce > a mess to the series. It seems that Shawn has already applied the first version of your series, so please send any changes as incremental patches. Thanks ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-11 16:21 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-11 16:21 UTC (permalink / raw) To: linux-arm-kernel Hi Vladimir, On Thu, Jul 5, 2018 at 4:09 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > thank you for review, please note that I've just sent v2 with a couple > of minor fixes as a reply to v1 2/3, I hope that I didn't introduce > a mess to the series. It seems that Shawn has already applied the first version of your series, so please send any changes as incremental patches. Thanks ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-11 16:21 ` Fabio Estevam @ 2018-07-12 1:07 ` Shawn Guo -1 siblings, 0 replies; 28+ messages in thread From: Shawn Guo @ 2018-07-12 1:07 UTC (permalink / raw) To: Fabio Estevam Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Vladimir Zapolskiy, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Wed, Jul 11, 2018 at 01:21:09PM -0300, Fabio Estevam wrote: > Hi Vladimir, > > On Thu, Jul 5, 2018 at 4:09 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > > > thank you for review, please note that I've just sent v2 with a couple > > of minor fixes as a reply to v1 2/3, I hope that I didn't introduce > > a mess to the series. > > It seems that Shawn has already applied the first version of your > series, so please send any changes as incremental patches. No. I picked up the v2 of this patch. Shawn ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-12 1:07 ` Shawn Guo 0 siblings, 0 replies; 28+ messages in thread From: Shawn Guo @ 2018-07-12 1:07 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jul 11, 2018 at 01:21:09PM -0300, Fabio Estevam wrote: > Hi Vladimir, > > On Thu, Jul 5, 2018 at 4:09 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > > > thank you for review, please note that I've just sent v2 with a couple > > of minor fixes as a reply to v1 2/3, I hope that I didn't introduce > > a mess to the series. > > It seems that Shawn has already applied the first version of your > series, so please send any changes as incremental patches. No. I picked up the v2 of this patch. Shawn ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-12 1:07 ` Shawn Guo @ 2018-07-12 1:09 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-12 1:09 UTC (permalink / raw) To: Shawn Guo Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Vladimir Zapolskiy, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Wed, Jul 11, 2018 at 10:07 PM, Shawn Guo <shawnguo@kernel.org> wrote: > No. I picked up the v2 of this patch. Excellent, thanks! ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-12 1:09 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-12 1:09 UTC (permalink / raw) To: linux-arm-kernel On Wed, Jul 11, 2018 at 10:07 PM, Shawn Guo <shawnguo@kernel.org> wrote: > No. I picked up the v2 of this patch. Excellent, thanks! ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v2 2/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-05 19:05 ` Vladimir Zapolskiy -1 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-05 19:05 UTC (permalink / raw) To: Shawn Guo, Fabio Estevam, Sascha Hauer Cc: linux-arm-kernel, devicetree, Rob Herring, NXP Linux Team, Pengutronix Kernel Team The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- Changes from v1 to v2: * removed mmc0 and mmc1 aliases, * added #address-cells, #size-cells and ranges properties to iram device node arch/arm/boot/dts/imx31.dtsi | 223 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c81..ca1419c 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> / { @@ -15,11 +16,20 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +57,14 @@ interrupt-parent = <&avic>; ranges; + iram: iram@1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + aips@43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +72,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c@43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c@43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata@43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial@43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +118,29 @@ status = "disabled"; }; + i2c2: i2c@43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi@43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp@43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +175,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci@50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci@50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial@5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +206,19 @@ status = "disabled"; }; + spi2: cspi@50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim@5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +241,19 @@ #clock-cells = <1>; }; + spi3: cspi@53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer@53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +261,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio@53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng@53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio@53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio@53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma@53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc@53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog@53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm@53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi@b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand@b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim@b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v2 2/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-05 19:05 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-05 19:05 UTC (permalink / raw) To: linux-arm-kernel The change adds a number of basic peripherals found on i.MX31 SoC: * GPIO controllers, * I2C master controllers, * SPI master controllers, * ATA controller, * SDHC controllers, * RTC, watchdog and PWM contollers, * SDMA, * IRAM, * NAND and WEIM controllers on EMI. The added controller devices were tested on Freescale i.MX31 powered LogicPD Lite SoM and baseboard. DMA functionality was tested on SDHC and SPI controllers so far, thus dmas properties are added to those device nodes only. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- Changes from v1 to v2: * removed mmc0 and mmc1 aliases, * added #address-cells, #size-cells and ranges properties to iram device node arch/arm/boot/dts/imx31.dtsi | 223 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 223 insertions(+) diff --git a/arch/arm/boot/dts/imx31.dtsi b/arch/arm/boot/dts/imx31.dtsi index 4642c81..ca1419c 100644 --- a/arch/arm/boot/dts/imx31.dtsi +++ b/arch/arm/boot/dts/imx31.dtsi @@ -1,5 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ // +// Copyright 2016-2018 Vladimir Zapolskiy <vz@mleia.com> // Copyright 2012 Denis 'GNUtoo' Carikli <GNUtoo@no-log.org> / { @@ -15,11 +16,20 @@ memory { device_type = "memory"; }; aliases { + gpio0 = &gpio1; + gpio1 = &gpio2; + gpio2 = &gpio3; + i2c0 = &i2c1; + i2c1 = &i2c2; + i2c2 = &i2c3; serial0 = &uart1; serial1 = &uart2; serial2 = &uart3; serial3 = &uart4; serial4 = &uart5; + spi0 = &spi1; + spi1 = &spi2; + spi2 = &spi3; }; cpus { @@ -47,6 +57,14 @@ interrupt-parent = <&avic>; ranges; + iram: iram at 1fffc000 { + compatible = "mmio-sram"; + reg = <0x1fffc000 0x4000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x1fffc000 0x4000>; + }; + aips at 43f00000 { /* AIPS1 */ compatible = "fsl,aips-bus", "simple-bus"; #address-cells = <1>; @@ -54,6 +72,34 @@ reg = <0x43f00000 0x100000>; ranges; + i2c1: i2c at 43f80000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f80000 0x4000>; + interrupts = <10>; + clocks = <&clks 33>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + i2c3: i2c at 43f84000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f84000 0x4000>; + interrupts = <3>; + clocks = <&clks 35>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + ata: ata at 43f8c000 { + compatible = "fsl,imx31-pata", "fsl,imx27-pata"; + reg = <0x43f8c000 0x4000>; + interrupts = <15>; + clocks = <&clks 26>; + status = "disabled"; + }; + uart1: serial at 43f90000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x43f90000 0x4000>; @@ -72,6 +118,29 @@ status = "disabled"; }; + i2c2: i2c at 43f98000 { + compatible = "fsl,imx31-i2c", "fsl,imx21-i2c"; + reg = <0x43f98000 0x4000>; + interrupts = <4>; + clocks = <&clks 34>; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + spi1: spi at 43fa4000 { + compatible = "fsl,imx31-cspi"; + reg = <0x43fa4000 0x4000>; + interrupts = <14>; + clocks = <&clks 10>, <&clks 53>; + clock-names = "ipg", "per"; + dmas = <&sdma 8 8 0>, <&sdma 9 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + kpp: kpp at 43fa8000 { compatible = "fsl,imx31-kpp", "fsl,imx21-kpp"; reg = <0x43fa8000 0x4000>; @@ -106,6 +175,28 @@ reg = <0x50000000 0x100000>; ranges; + sdhci1: sdhci at 50004000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50004000 0x4000>; + interrupts = <9>; + clocks = <&clks 10>, <&clks 20>; + clock-names = "ipg", "per"; + dmas = <&sdma 20 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + + sdhci2: sdhci at 50008000 { + compatible = "fsl,imx31-mmc"; + reg = <0x50008000 0x4000>; + interrupts = <8>; + clocks = <&clks 10>, <&clks 21>; + clock-names = "ipg", "per"; + dmas = <&sdma 21 3 0>; + dma-names = "rx-tx"; + status = "disabled"; + }; + uart3: serial at 5000c000 { compatible = "fsl,imx31-uart", "fsl,imx21-uart"; reg = <0x5000c000 0x4000>; @@ -115,6 +206,19 @@ status = "disabled"; }; + spi2: cspi at 50010000 { + compatible = "fsl,imx31-cspi"; + reg = <0x50010000 0x4000>; + interrupts = <13>; + clocks = <&clks 10>, <&clks 54>; + clock-names = "ipg", "per"; + dmas = <&sdma 6 8 0>, <&sdma 7 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + iim: iim at 5001c000 { compatible = "fsl,imx31-iim", "fsl,imx27-iim"; reg = <0x5001c000 0x1000>; @@ -137,6 +241,19 @@ #clock-cells = <1>; }; + spi3: cspi at 53f84000 { + compatible = "fsl,imx31-cspi"; + reg = <0x53f84000 0x4000>; + interrupts = <17>; + clocks = <&clks 10>, <&clks 28>; + clock-names = "ipg", "per"; + dmas = <&sdma 10 8 0>, <&sdma 11 8 0>; + dma-names = "rx", "tx"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + gpt: timer at 53f90000 { compatible = "fsl,imx31-gpt"; reg = <0x53f90000 0x4000>; @@ -144,6 +261,112 @@ clocks = <&clks 10>, <&clks 22>; clock-names = "ipg", "per"; }; + + gpio3: gpio at 53fa4000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fa4000 0x4000>; + interrupts = <56>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + rng at 53fb0000 { + compatible = "fsl,imx31-rnga"; + reg = <0x53fb0000 0x4000>; + interrupts = <22>; + clocks = <&clks 29>; + }; + + gpio1: gpio at 53fcc000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fcc000 0x4000>; + interrupts = <52>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + gpio2: gpio at 53fd0000 { + compatible = "fsl,imx31-gpio"; + reg = <0x53fd0000 0x4000>; + interrupts = <51>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + }; + + sdma: sdma at 53fd4000 { + compatible = "fsl,imx31-sdma"; + reg = <0x53fd4000 0x4000>; + interrupts = <34>; + clocks = <&clks 10>, <&clks 27>; + clock-names = "ipg", "ahb"; + #dma-cells = <3>; + fsl,sdma-ram-script-name = "imx/sdma/sdma-imx31.bin"; + }; + + rtc: rtc at 53fd8000 { + compatible = "fsl,imx31-rtc", "fsl,imx21-rtc"; + reg = <0x53fd8000 0x4000>; + interrupts = <25>; + clocks = <&clks 2>, <&clks 40>; + clock-names = "ref", "ipg"; + }; + + wdog: wdog at 53fdc000 { + compatible = "fsl,imx31-wdt", "fsl,imx21-wdt"; + reg = <0x53fdc000 0x4000>; + clocks = <&clks 41>; + }; + + pwm: pwm at 53fe0000 { + compatible = "fsl,imx31-pwm", "fsl,imx27-pwm"; + reg = <0x53fe0000 0x4000>; + interrupts = <26>; + clocks = <&clks 10>, <&clks 42>; + clock-names = "ipg", "per"; + #pwm-cells = <2>; + status = "disabled"; + }; + }; + + emi at b8000000 { /* External Memory Interface */ + compatible = "simple-bus"; + reg = <0xb8000000 0x5000>; + ranges; + #address-cells = <1>; + #size-cells = <1>; + + nfc: nand at b8000000 { + compatible = "fsl,imx31-nand", "fsl,imx27-nand"; + reg = <0xb8000000 0x1000>; + interrupts = <33>; + clocks = <&clks 9>; + dmas = <&sdma 30 17 0>; + dma-names = "rx-tx"; + #address-cells = <1>; + #size-cells = <1>; + status = "disabled"; + }; + + weim: weim at b8002000 { + compatible = "fsl,imx31-weim", "fsl,imx27-weim"; + reg = <0xb8002000 0x1000>; + clocks = <&clks 56>; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0 0xa0000000 0x08000000 + 1 0 0xa8000000 0x08000000 + 2 0 0xb0000000 0x02000000 + 3 0 0xb2000000 0x02000000 + 4 0 0xb4000000 0x02000000 + 5 0 0xb6000000 0x02000000>; + status = "disabled"; + }; }; }; }; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/3] ARM: dts: imx31: add LogicPD MX31Lite board description 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-03 19:29 ` Vladimir Zapolskiy -1 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: Shawn Guo, Fabio Estevam, Sascha Hauer Cc: linux-arm-kernel, devicetree, Rob Herring, NXP Linux Team, Pengutronix Kernel Team The added DTS contains a combined description of LogicPD MX31 Lite SoM devices, peripherals are routed to ports on a baseboard: * PATA controller, * SD/MMC controller, * 2 GPIO LEDs, * UART controllers, * Freescale MC13783 MFD connected over SPI, * SMSC LAN9117, * ST Micro NAND SLC, 64 MiB, * Intel NOR flash, 16 MiB. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de7..2210b73 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -345,7 +345,8 @@ dtb-$(CONFIG_SOC_IMX27) += \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb + imx31-bug.dtb \ + imx31-lite.dtb dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts new file mode 100644 index 0000000..db52ddc --- /dev/null +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com> + +/dts-v1/; + +#include "imx31.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory@80000000 { + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic@0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor@0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet@4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH 3/3] ARM: dts: imx31: add LogicPD MX31Lite board description @ 2018-07-03 19:29 ` Vladimir Zapolskiy 0 siblings, 0 replies; 28+ messages in thread From: Vladimir Zapolskiy @ 2018-07-03 19:29 UTC (permalink / raw) To: linux-arm-kernel The added DTS contains a combined description of LogicPD MX31 Lite SoM devices, peripherals are routed to ports on a baseboard: * PATA controller, * SD/MMC controller, * 2 GPIO LEDs, * UART controllers, * Freescale MC13783 MFD connected over SPI, * SMSC LAN9117, * ST Micro NAND SLC, 64 MiB, * Intel NOR flash, 16 MiB. Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/imx31-lite.dts | 177 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 179 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/imx31-lite.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 37a3de7..2210b73 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -345,7 +345,8 @@ dtb-$(CONFIG_SOC_IMX27) += \ imx27-phytec-phycore-rdk.dtb \ imx27-phytec-phycard-s-rdk.dtb dtb-$(CONFIG_SOC_IMX31) += \ - imx31-bug.dtb + imx31-bug.dtb \ + imx31-lite.dtb dtb-$(CONFIG_SOC_IMX35) += \ imx35-eukrea-mbimxsd35-baseboard.dtb \ imx35-pdk.dtb diff --git a/arch/arm/boot/dts/imx31-lite.dts b/arch/arm/boot/dts/imx31-lite.dts new file mode 100644 index 0000000..db52ddc --- /dev/null +++ b/arch/arm/boot/dts/imx31-lite.dts @@ -0,0 +1,177 @@ +// SPDX-License-Identifier: GPL-2.0+ +// +// Copyright (C) 2016-2018 Vladimir Zapolskiy <vz@mleia.com> + +/dts-v1/; + +#include "imx31.dtsi" + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> + +/ { + model = "LogicPD i.MX31 Lite"; + compatible = "logicpd,imx31-lite", "fsl,imx31"; + + chosen { + stdout-path = &uart1; + }; + + memory at 80000000 { + reg = <0x80000000 0x8000000>; + }; + + leds { + compatible = "gpio-leds"; + + led0 { + gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + }; + + led1 { + gpios = <&gpio1 7 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ata { + status = "okay"; +}; + +&nfc { + nand-bus-width = <8>; + nand-ecc-mode = "hw"; + nand-on-flash-bbt; + status = "okay"; +}; + +&sdhci1 { + bus-width = <4>; + cd-gpios = <&gpio2 11 GPIO_ACTIVE_HIGH>; + wp-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&spi2 { + status = "okay"; + + pmic at 0 { + compatible = "fsl,mc13783"; + reg = <0>; + spi-cs-high; + spi-max-frequency = <1000000>; + interrupt-parent = <&gpio1>; + interrupts = <3 IRQ_TYPE_EDGE_RISING>; + + fsl,mc13xxx-uses-adc; + fsl,mc13xxx-uses-rtc; + + regulators { + sw1a { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw1b { /* QVCC */ + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1500000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2a { /* 1.8V_DDR, NVCC2, NVCC21 and NVCC22 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + sw2b { /* NVCC10 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + violo { /* NVCC1 and NVCC7 */ + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + regulator-boot-on; + }; + + viohi { /* VIOHI */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vaudio { /* VAUDIO */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + }; + + vcam { /* NVCC4 */ + regulator-min-microvolt = <2800000>; + regulator-max-microvolt = <2800000>; + }; + + vgen { /* NVCC5 / NVCC8 and NVCC6 / NVCC9 */ + regulator-min-microvolt = <2775000>; + regulator-max-microvolt = <2775000>; + regulator-always-on; + regulator-boot-on; + }; + + vmmc2 { /* NVCC3 */ + regulator-min-microvolt = <1600000>; + regulator-max-microvolt = <3000000>; + regulator-always-on; + regulator-boot-on; + }; + }; + }; +}; + +&uart1 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart2 { + uart-has-rtscts; + status = "okay"; +}; + +/* Routed to the extension board */ +&uart3 { + uart-has-rtscts; + status = "okay"; +}; + +&weim { + status = "okay"; + + nor at 0,0 { + compatible = "cfi-flash"; + reg = <0 0x0 0x200000>; + bank-width = <2>; + linux,mtd-name = "physmap-flash.0"; + fsl,weim-cs-timing = <0x0000cf03 0xa0330d01 0x00220800>; + }; + + ethernet at 4,0 { + compatible = "smsc,lan9117", "smsc,lan9115"; + reg = <4 0x0 0x100>; + interrupt-parent = <&gpio1>; + interrupts = <26 IRQ_TYPE_EDGE_FALLING>; + phy-mode = "mii"; + reg-io-width = <2>; + smsc,irq-push-pull; + fsl,weim-cs-timing = <0x00008701 0x04000541 0x00010000>; + }; +}; -- 2.10.2 ^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH 3/3] ARM: dts: imx31: add LogicPD MX31Lite board description 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-05 1:03 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:03 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The added DTS contains a combined description of LogicPD MX31 Lite > SoM devices, peripherals are routed to ports on a baseboard: > * PATA controller, > * SD/MMC controller, > * 2 GPIO LEDs, > * UART controllers, > * Freescale MC13783 MFD connected over SPI, > * SMSC LAN9117, > * ST Micro NAND SLC, 64 MiB, > * Intel NOR flash, 16 MiB. > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 3/3] ARM: dts: imx31: add LogicPD MX31Lite board description @ 2018-07-05 1:03 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:03 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The added DTS contains a combined description of LogicPD MX31 Lite > SoM devices, peripherals are routed to ports on a baseboard: > * PATA controller, > * SD/MMC controller, > * 2 GPIO LEDs, > * UART controllers, > * Freescale MC13783 MFD connected over SPI, > * SMSC LAN9117, > * ST Micro NAND SLC, 64 MiB, > * Intel NOR flash, 16 MiB. > > Signed-off-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Fabio Estevam <fabio.estevam@nxp.com> ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-05 1:05 ` Fabio Estevam -1 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:05 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, Shawn Guo, moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE Hi Vladimir, On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The changeset combines a number of essential updates to support device tree > on Freescale i.MX31 powered boards: > * removal of bogus RNGA registration for i.MX31 (device tree only), > * the core controllers on the i.MX31 SoC are now properly described, > * for reference and testing I add basic support of LogicPD MX31Lite board. > > There are some missing compatibles in the change 2/3, however at the moment > I assume that either adding the values can be omitted or deferred, here is > the exact list: > * "fsl,imx31-pata" > * "fsl,imx31-rtc" > * "fsl,imx31-nand" > * "fsl,imx31-weim" > > To test the changes I used a LogicPD reference board, however note that > still I have to add a workaround to the old known issue within imx-wdt Hopefully you and Uwe can reach an agreement on the imx31 watchdog fix :-) ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-05 1:05 ` Fabio Estevam 0 siblings, 0 replies; 28+ messages in thread From: Fabio Estevam @ 2018-07-05 1:05 UTC (permalink / raw) To: linux-arm-kernel Hi Vladimir, On Tue, Jul 3, 2018 at 4:29 PM, Vladimir Zapolskiy <vz@mleia.com> wrote: > The changeset combines a number of essential updates to support device tree > on Freescale i.MX31 powered boards: > * removal of bogus RNGA registration for i.MX31 (device tree only), > * the core controllers on the i.MX31 SoC are now properly described, > * for reference and testing I add basic support of LogicPD MX31Lite board. > > There are some missing compatibles in the change 2/3, however at the moment > I assume that either adding the values can be omitted or deferred, here is > the exact list: > * "fsl,imx31-pata" > * "fsl,imx31-rtc" > * "fsl,imx31-nand" > * "fsl,imx31-weim" > > To test the changes I used a LogicPD reference board, however note that > still I have to add a workaround to the old known issue within imx-wdt Hopefully you and Uwe can reach an agreement on the imx31 watchdog fix :-) ^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers 2018-07-03 19:29 ` Vladimir Zapolskiy @ 2018-07-11 12:26 ` Shawn Guo -1 siblings, 0 replies; 28+ messages in thread From: Shawn Guo @ 2018-07-11 12:26 UTC (permalink / raw) To: Vladimir Zapolskiy Cc: devicetree, Sascha Hauer, Rob Herring, NXP Linux Team, Pengutronix Kernel Team, Fabio Estevam, linux-arm-kernel On Tue, Jul 03, 2018 at 10:29:31PM +0300, Vladimir Zapolskiy wrote: > Vladimir Zapolskiy (3): > ARM: i.MX31: remove rnga registration as a platform device > ARM: dts: imx31: add device tree description of basic controllers > ARM: dts: imx31: add LogicPD MX31Lite board description Applied all, thanks. ^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers @ 2018-07-11 12:26 ` Shawn Guo 0 siblings, 0 replies; 28+ messages in thread From: Shawn Guo @ 2018-07-11 12:26 UTC (permalink / raw) To: linux-arm-kernel On Tue, Jul 03, 2018 at 10:29:31PM +0300, Vladimir Zapolskiy wrote: > Vladimir Zapolskiy (3): > ARM: i.MX31: remove rnga registration as a platform device > ARM: dts: imx31: add device tree description of basic controllers > ARM: dts: imx31: add LogicPD MX31Lite board description Applied all, thanks. ^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2018-07-12 1:09 UTC | newest] Thread overview: 28+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-07-03 19:29 [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers Vladimir Zapolskiy 2018-07-03 19:29 ` Vladimir Zapolskiy 2018-07-03 19:29 ` [PATCH 1/3] ARM: i.MX31: remove rnga registration as a platform device Vladimir Zapolskiy 2018-07-03 19:29 ` Vladimir Zapolskiy 2018-07-05 0:55 ` Fabio Estevam 2018-07-05 0:55 ` Fabio Estevam 2018-07-03 19:29 ` [PATCH 2/3] ARM: dts: imx31: add device tree description of basic controllers Vladimir Zapolskiy 2018-07-03 19:29 ` Vladimir Zapolskiy 2018-07-05 1:01 ` Fabio Estevam 2018-07-05 1:01 ` Fabio Estevam 2018-07-05 19:09 ` Vladimir Zapolskiy 2018-07-05 19:09 ` Vladimir Zapolskiy 2018-07-11 16:21 ` Fabio Estevam 2018-07-11 16:21 ` Fabio Estevam 2018-07-12 1:07 ` Shawn Guo 2018-07-12 1:07 ` Shawn Guo 2018-07-12 1:09 ` Fabio Estevam 2018-07-12 1:09 ` Fabio Estevam 2018-07-05 19:05 ` [PATCH v2 " Vladimir Zapolskiy 2018-07-05 19:05 ` Vladimir Zapolskiy 2018-07-03 19:29 ` [PATCH 3/3] ARM: dts: imx31: add LogicPD MX31Lite board description Vladimir Zapolskiy 2018-07-03 19:29 ` Vladimir Zapolskiy 2018-07-05 1:03 ` Fabio Estevam 2018-07-05 1:03 ` Fabio Estevam 2018-07-05 1:05 ` [PATCH 0/3] ARM: dts: imx31: add device tree description of basic controllers Fabio Estevam 2018-07-05 1:05 ` Fabio Estevam 2018-07-11 12:26 ` Shawn Guo 2018-07-11 12:26 ` Shawn Guo
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