* [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support
@ 2018-07-14 17:15 Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor Luc Michel
` (20 more replies)
0 siblings, 21 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
v2:
- Add VMSTATE_UINT16_SUB_ARRAY to vmstate.h
- Keep backward compatibility on the GIC VMState by storing vCPUs
state in the virt VMState subsection.
- Use h_apr to store APR value for vCPUs, instead of increasing apr 2D
array. This adds a little complexity to the implementation (a bunch
of `if (gic_is_vcpu(cpu))'), but avoid ugly VMState description for
the apr array.
v3:
- Remove the LR caching mechanism as it is probably not worse it.
- Remove the forced secure access hack and replace it with a proper
check (commit 8, function gic_cpu_ns_access()).
- Split the Implementation patch for easier review.
- Misc modifications following the review from Peter on v2.
- Add GICv2 virt extensions support to the arm virt machine.
- Fix vCPU running prio not being recomputed after a write to H_APR.
- Fix group0 hw interrupts deactivation request not being forwarded to
distributor when the GIC is not secure.
- Implement GICD_ISACTIVERn and GICD_ICACTIVERn because KVM uses them.
v4:
- Patch 2: check GICD_ISACTIVERn and GICD_ICACTIVERn access (exist
only in GICv2) [Peter]
- Patch 2: moved after patch 1 to ensure compilation success across
patches [Peter]
- Patch 2: implement GICD_ICACTIVERn reads on GICv2 [Peter]
- Patch 7: Integrated Peter rational about LRs helpers, added
comments to explain what's going on [Peter]
- Patch 9: gic_clear_active(): check that the given PhysicalID is a
valid IRQ [Peter]
- Patch 10: refactor to move out the virt cases for more clarity [Peter]
- Patch 12: Add a validity check on the given vIRQ [Peter]
- Patch 14: Fix a comment on memory region creation [Peter]
- Patch 14: Fix per-core alias creation, that should target the
virtual interfaces, and not the vCPU interfaces [Peter]
- Patch 16: gic_update_internal(): Move the CPU interface enable test
in gic_irq_signaling_enabled() [Peter]
- Patch 17: Stylistic [Peter]
- Patch 20: Rebase onto master
- Patch 20: Merge the two GIC maintenance IRQ constants into one
[Peter]
- Patch 20: Fix Memory region size for GICv2 virtual interface and
vCPU iface. [Peter]
Luc Michel (20):
intc/arm_gic: Refactor operations on the distributor
intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
intc/arm_gic: Remove some dead code and put some functions static
vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY
intc/arm_gic: Add the virtualization extensions to the GIC state
intc/arm_gic: Add virtual interface register definitions
intc/arm_gic: Add virtualization extensions helper macros and
functions
intc/arm_gic: Refactor secure/ns access check in the CPU interface
intc/arm_gic: Add virtualization enabled IRQ helper functions
intc/arm_gic: Implement virtualization extensions in
gic_(activate_irq|drop_prio)
intc/arm_gic: Implement virtualization extensions in
gic_acknowledge_irq
intc/arm_gic: Implement virtualization extensions in
gic_(deactivate|complete_irq)
intc/arm_gic: Implement virtualization extensions in
gic_cpu_(read|write)
intc/arm_gic: Wire the vCPU interface
intc/arm_gic: Implement the virtual interface registers
intc/arm_gic: Implement gic_update_virt() function
intc/arm_gic: Implement maintenance interrupt generation
intc/arm_gic: Improve traces
xlnx-zynqmp: Improve GIC wiring and MMIO mapping
arm/virt: Add support for GICv2 virtualization extensions
hw/arm/virt-acpi-build.c | 6 +-
hw/arm/virt.c | 52 +-
hw/arm/xlnx-zynqmp.c | 92 ++-
hw/intc/arm_gic.c | 967 +++++++++++++++++++++++++------
hw/intc/arm_gic_common.c | 154 ++++-
hw/intc/arm_gic_kvm.c | 31 +-
hw/intc/gic_internal.h | 283 ++++++++-
hw/intc/trace-events | 12 +-
include/hw/arm/virt.h | 4 +-
include/hw/arm/xlnx-zynqmp.h | 4 +-
include/hw/intc/arm_gic_common.h | 43 +-
include/migration/vmstate.h | 3 +
12 files changed, 1370 insertions(+), 281 deletions(-)
--
2.18.0
^ permalink raw reply [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Luc Michel
` (19 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
In preparation for the virtualization extensions implementation,
refactor the name of the functions and macros that act on the GIC
distributor to make that fact explicit. It will be useful to
differentiate them from the ones that will act on the virtual
interfaces.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 163 +++++++++++++++++++++------------------
hw/intc/arm_gic_common.c | 6 +-
hw/intc/arm_gic_kvm.c | 23 +++---
hw/intc/gic_internal.h | 51 ++++++------
4 files changed, 127 insertions(+), 116 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index ea0323f969..6f3074ba88 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -92,11 +92,12 @@ void gic_update(GICState *s)
best_prio = 0x100;
best_irq = 1023;
for (irq = 0; irq < s->num_irq; irq++) {
- if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
- (!GIC_TEST_ACTIVE(irq, cm)) &&
- (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) {
- if (GIC_GET_PRIORITY(irq, cpu) < best_prio) {
- best_prio = GIC_GET_PRIORITY(irq, cpu);
+ if (GIC_DIST_TEST_ENABLED(irq, cm) &&
+ gic_test_pending(s, irq, cm) &&
+ (!GIC_DIST_TEST_ACTIVE(irq, cm)) &&
+ (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) {
+ if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) {
+ best_prio = GIC_DIST_GET_PRIORITY(irq, cpu);
best_irq = irq;
}
}
@@ -112,7 +113,7 @@ void gic_update(GICState *s)
if (best_prio < s->priority_mask[cpu]) {
s->current_pending[cpu] = best_irq;
if (best_prio < s->running_priority[cpu]) {
- int group = GIC_TEST_GROUP(best_irq, cm);
+ int group = GIC_DIST_TEST_GROUP(best_irq, cm);
if (extract32(s->ctlr, group, 1) &&
extract32(s->cpu_ctlr[cpu], group, 1)) {
@@ -145,7 +146,7 @@ void gic_set_pending_private(GICState *s, int cpu, int irq)
}
DPRINTF("Set %d pending cpu %d\n", irq, cpu);
- GIC_SET_PENDING(irq, cm);
+ GIC_DIST_SET_PENDING(irq, cm);
gic_update(s);
}
@@ -153,13 +154,13 @@ static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
if (level) {
- GIC_SET_LEVEL(irq, cm);
- if (GIC_TEST_EDGE_TRIGGER(irq) || GIC_TEST_ENABLED(irq, cm)) {
+ GIC_DIST_SET_LEVEL(irq, cm);
+ if (GIC_DIST_TEST_EDGE_TRIGGER(irq) || GIC_DIST_TEST_ENABLED(irq, cm)) {
DPRINTF("Set %d pending mask %x\n", irq, target);
- GIC_SET_PENDING(irq, target);
+ GIC_DIST_SET_PENDING(irq, target);
}
} else {
- GIC_CLEAR_LEVEL(irq, cm);
+ GIC_DIST_CLEAR_LEVEL(irq, cm);
}
}
@@ -167,13 +168,13 @@ static void gic_set_irq_generic(GICState *s, int irq, int level,
int cm, int target)
{
if (level) {
- GIC_SET_LEVEL(irq, cm);
+ GIC_DIST_SET_LEVEL(irq, cm);
DPRINTF("Set %d pending mask %x\n", irq, target);
- if (GIC_TEST_EDGE_TRIGGER(irq)) {
- GIC_SET_PENDING(irq, target);
+ if (GIC_DIST_TEST_EDGE_TRIGGER(irq)) {
+ GIC_DIST_SET_PENDING(irq, target);
}
} else {
- GIC_CLEAR_LEVEL(irq, cm);
+ GIC_DIST_CLEAR_LEVEL(irq, cm);
}
}
@@ -192,7 +193,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
/* The first external input line is internal interrupt 32. */
cm = ALL_CPU_MASK;
irq += GIC_INTERNAL;
- target = GIC_TARGET(irq);
+ target = GIC_DIST_TARGET(irq);
} else {
int cpu;
irq -= (s->num_irq - GIC_INTERNAL);
@@ -204,7 +205,7 @@ static void gic_set_irq(void *opaque, int irq, int level)
assert(irq >= GIC_NR_SGIS);
- if (level == GIC_TEST_LEVEL(irq, cm)) {
+ if (level == GIC_DIST_TEST_LEVEL(irq, cm)) {
return;
}
@@ -224,7 +225,7 @@ static uint16_t gic_get_current_pending_irq(GICState *s, int cpu,
uint16_t pending_irq = s->current_pending[cpu];
if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) {
- int group = GIC_TEST_GROUP(pending_irq, (1 << cpu));
+ int group = GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu));
/* On a GIC without the security extensions, reading this register
* behaves in the same way as a secure access to a GIC with them.
*/
@@ -255,7 +256,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
if (gic_has_groups(s) &&
!(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
- GIC_TEST_GROUP(irq, (1 << cpu))) {
+ GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
bpr = s->abpr[cpu] - 1;
assert(bpr >= 0);
} else {
@@ -268,7 +269,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
*/
mask = ~0U << ((bpr & 7) + 1);
- return GIC_GET_PRIORITY(irq, cpu) & mask;
+ return GIC_DIST_GET_PRIORITY(irq, cpu) & mask;
}
static void gic_activate_irq(GICState *s, int cpu, int irq)
@@ -281,14 +282,14 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
int regno = preemption_level / 32;
int bitno = preemption_level % 32;
- if (gic_has_groups(s) && GIC_TEST_GROUP(irq, (1 << cpu))) {
+ if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
s->nsapr[regno][cpu] |= (1 << bitno);
} else {
s->apr[regno][cpu] |= (1 << bitno);
}
s->running_priority[cpu] = prio;
- GIC_SET_ACTIVE(irq, 1 << cpu);
+ GIC_DIST_SET_ACTIVE(irq, 1 << cpu);
}
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -357,7 +358,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return irq;
}
- if (GIC_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
+ if (GIC_DIST_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq);
return 1023;
}
@@ -366,7 +367,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
- GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
+ GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
+ : cm);
ret = irq;
} else {
if (irq < GIC_NR_SGIS) {
@@ -378,7 +380,9 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
src = ctz32(s->sgi_pending[irq][cpu]);
s->sgi_pending[irq][cpu] &= ~(1 << src);
if (s->sgi_pending[irq][cpu] == 0) {
- GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
+ GIC_DIST_CLEAR_PENDING(irq,
+ GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
+ : cm);
}
ret = irq | ((src & 0x7) << 10);
} else {
@@ -386,7 +390,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
* interrupts. (level triggered interrupts with an active line
* remain pending, see gic_test_pending)
*/
- GIC_CLEAR_PENDING(irq, GIC_TEST_MODEL(irq) ? ALL_CPU_MASK : cm);
+ GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
+ : cm);
ret = irq;
}
}
@@ -397,11 +402,11 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return ret;
}
-void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
+void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs)
{
if (s->security_extn && !attrs.secure) {
- if (!GIC_TEST_GROUP(irq, (1 << cpu))) {
+ if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
return; /* Ignore Non-secure access of Group0 IRQ */
}
val = 0x80 | (val >> 1); /* Non-secure view */
@@ -414,13 +419,13 @@ void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
}
}
-static uint32_t gic_get_priority(GICState *s, int cpu, int irq,
+static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
MemTxAttrs attrs)
{
- uint32_t prio = GIC_GET_PRIORITY(irq, cpu);
+ uint32_t prio = GIC_DIST_GET_PRIORITY(irq, cpu);
if (s->security_extn && !attrs.secure) {
- if (!GIC_TEST_GROUP(irq, (1 << cpu))) {
+ if (!GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
return 0; /* Non-secure access cannot read priority of Group0 IRQ */
}
prio = (prio << 1) & 0xff; /* Non-secure view */
@@ -543,7 +548,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
int cm = 1 << cpu;
- int group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
+ int group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm);
if (!gic_eoi_split(s, cpu, attrs)) {
/* This is UNPREDICTABLE; we choose to ignore it */
@@ -557,7 +562,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
return;
}
- GIC_CLEAR_ACTIVE(irq, cm);
+ GIC_DIST_CLEAR_ACTIVE(irq, cm);
}
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
@@ -584,14 +589,15 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
if (s->revision == REV_11MPCORE) {
/* Mark level triggered interrupts as pending if they are still
raised. */
- if (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_ENABLED(irq, cm)
- && GIC_TEST_LEVEL(irq, cm) && (GIC_TARGET(irq) & cm) != 0) {
+ if (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_ENABLED(irq, cm)
+ && GIC_DIST_TEST_LEVEL(irq, cm)
+ && (GIC_DIST_TARGET(irq) & cm) != 0) {
DPRINTF("Set %d pending mask %x\n", irq, cm);
- GIC_SET_PENDING(irq, cm);
+ GIC_DIST_SET_PENDING(irq, cm);
}
}
- group = gic_has_groups(s) && GIC_TEST_GROUP(irq, cm);
+ group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm);
if (s->security_extn && !attrs.secure && !group) {
DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
@@ -607,7 +613,7 @@ void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
/* In GICv2 the guest can choose to split priority-drop and deactivate */
if (!gic_eoi_split(s, cpu, attrs)) {
- GIC_CLEAR_ACTIVE(irq, cm);
+ GIC_DIST_CLEAR_ACTIVE(irq, cm);
}
gic_update(s);
}
@@ -655,7 +661,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
goto bad_reg;
}
for (i = 0; i < 8; i++) {
- if (GIC_TEST_GROUP(irq + i, cm)) {
+ if (GIC_DIST_TEST_GROUP(irq + i, cm)) {
res |= (1 << i);
}
}
@@ -675,11 +681,11 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
res = 0;
for (i = 0; i < 8; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (GIC_TEST_ENABLED(irq + i, cm)) {
+ if (GIC_DIST_TEST_ENABLED(irq + i, cm)) {
res |= (1 << i);
}
}
@@ -696,7 +702,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
for (i = 0; i < 8; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
@@ -713,11 +719,11 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
mask = (irq < GIC_INTERNAL) ? cm : ALL_CPU_MASK;
for (i = 0; i < 8; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (GIC_TEST_ACTIVE(irq + i, mask)) {
+ if (GIC_DIST_TEST_ACTIVE(irq + i, mask)) {
res |= (1 << i);
}
}
@@ -726,7 +732,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
irq = (offset - 0x400) + GIC_BASE_IRQ;
if (irq >= s->num_irq)
goto bad_reg;
- res = gic_get_priority(s, cpu, irq, attrs);
+ res = gic_dist_get_priority(s, cpu, irq, attrs);
} else if (offset < 0xc00) {
/* Interrupt CPU Target. */
if (s->num_cpu == 1 && s->revision != REV_11MPCORE) {
@@ -740,7 +746,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
if (irq >= 29 && irq <= 31) {
res = cm;
} else {
- res = GIC_TARGET(irq);
+ res = GIC_DIST_TARGET(irq);
}
}
} else if (offset < 0xf00) {
@@ -751,14 +757,16 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
res = 0;
for (i = 0; i < 4; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (GIC_TEST_MODEL(irq + i))
+ if (GIC_DIST_TEST_MODEL(irq + i)) {
res |= (1 << (i * 2));
- if (GIC_TEST_EDGE_TRIGGER(irq + i))
+ }
+ if (GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) {
res |= (2 << (i * 2));
+ }
}
} else if (offset < 0xf10) {
goto bad_reg;
@@ -776,7 +784,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
}
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
res = 0; /* Ignore Non-secure access of Group0 IRQ */
} else {
res = s->sgi_pending[irq][cpu];
@@ -872,10 +880,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (value & (1 << i)) {
/* Group1 (Non-secure) */
- GIC_SET_GROUP(irq + i, cm);
+ GIC_DIST_SET_GROUP(irq + i, cm);
} else {
/* Group0 (Secure) */
- GIC_CLEAR_GROUP(irq + i, cm);
+ GIC_DIST_CLEAR_GROUP(irq + i, cm);
}
}
}
@@ -894,25 +902,26 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for (i = 0; i < 8; i++) {
if (value & (1 << i)) {
int mask =
- (irq < GIC_INTERNAL) ? (1 << cpu) : GIC_TARGET(irq + i);
+ (irq < GIC_INTERNAL) ? (1 << cpu)
+ : GIC_DIST_TARGET(irq + i);
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (!GIC_TEST_ENABLED(irq + i, cm)) {
+ if (!GIC_DIST_TEST_ENABLED(irq + i, cm)) {
DPRINTF("Enabled IRQ %d\n", irq + i);
trace_gic_enable_irq(irq + i);
}
- GIC_SET_ENABLED(irq + i, cm);
+ GIC_DIST_SET_ENABLED(irq + i, cm);
/* If a raised level triggered IRQ enabled then mark
is as pending. */
- if (GIC_TEST_LEVEL(irq + i, mask)
- && !GIC_TEST_EDGE_TRIGGER(irq + i)) {
+ if (GIC_DIST_TEST_LEVEL(irq + i, mask)
+ && !GIC_DIST_TEST_EDGE_TRIGGER(irq + i)) {
DPRINTF("Set %d pending mask %x\n", irq + i, mask);
- GIC_SET_PENDING(irq + i, mask);
+ GIC_DIST_SET_PENDING(irq + i, mask);
}
}
}
@@ -930,15 +939,15 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- if (GIC_TEST_ENABLED(irq + i, cm)) {
+ if (GIC_DIST_TEST_ENABLED(irq + i, cm)) {
DPRINTF("Disabled IRQ %d\n", irq + i);
trace_gic_disable_irq(irq + i);
}
- GIC_CLEAR_ENABLED(irq + i, cm);
+ GIC_DIST_CLEAR_ENABLED(irq + i, cm);
}
}
} else if (offset < 0x280) {
@@ -953,11 +962,11 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for (i = 0; i < 8; i++) {
if (value & (1 << i)) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
- GIC_SET_PENDING(irq + i, GIC_TARGET(irq + i));
+ GIC_DIST_SET_PENDING(irq + i, GIC_DIST_TARGET(irq + i));
}
}
} else if (offset < 0x300) {
@@ -971,7 +980,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for (i = 0; i < 8; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
@@ -979,7 +988,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
for per-CPU interrupts. It's unclear whether this is the
corect behavior. */
if (value & (1 << i)) {
- GIC_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
+ GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
}
}
} else if (offset < 0x400) {
@@ -990,7 +999,7 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
irq = (offset - 0x400) + GIC_BASE_IRQ;
if (irq >= s->num_irq)
goto bad_reg;
- gic_set_priority(s, cpu, irq, value, attrs);
+ gic_dist_set_priority(s, cpu, irq, value, attrs);
} else if (offset < 0xc00) {
/* Interrupt CPU Target. RAZ/WI on uniprocessor GICs, with the
* annoying exception of the 11MPCore's GIC.
@@ -1016,21 +1025,21 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
value |= 0xaa;
for (i = 0; i < 4; i++) {
if (s->security_extn && !attrs.secure &&
- !GIC_TEST_GROUP(irq + i, 1 << cpu)) {
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
continue; /* Ignore Non-secure access of Group0 IRQ */
}
if (s->revision == REV_11MPCORE) {
if (value & (1 << (i * 2))) {
- GIC_SET_MODEL(irq + i);
+ GIC_DIST_SET_MODEL(irq + i);
} else {
- GIC_CLEAR_MODEL(irq + i);
+ GIC_DIST_CLEAR_MODEL(irq + i);
}
}
if (value & (2 << (i * 2))) {
- GIC_SET_EDGE_TRIGGER(irq + i);
+ GIC_DIST_SET_EDGE_TRIGGER(irq + i);
} else {
- GIC_CLEAR_EDGE_TRIGGER(irq + i);
+ GIC_DIST_CLEAR_EDGE_TRIGGER(irq + i);
}
}
} else if (offset < 0xf10) {
@@ -1044,10 +1053,10 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
irq = (offset - 0xf10);
if (!s->security_extn || attrs.secure ||
- GIC_TEST_GROUP(irq, 1 << cpu)) {
+ GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
s->sgi_pending[irq][cpu] &= ~value;
if (s->sgi_pending[irq][cpu] == 0) {
- GIC_CLEAR_PENDING(irq, 1 << cpu);
+ GIC_DIST_CLEAR_PENDING(irq, 1 << cpu);
}
}
} else if (offset < 0xf30) {
@@ -1058,8 +1067,8 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
irq = (offset - 0xf20);
if (!s->security_extn || attrs.secure ||
- GIC_TEST_GROUP(irq, 1 << cpu)) {
- GIC_SET_PENDING(irq, 1 << cpu);
+ GIC_DIST_TEST_GROUP(irq, 1 << cpu)) {
+ GIC_DIST_SET_PENDING(irq, 1 << cpu);
s->sgi_pending[irq][cpu] |= value;
}
} else {
@@ -1106,7 +1115,7 @@ static void gic_dist_writel(void *opaque, hwaddr offset,
mask = ALL_CPU_MASK;
break;
}
- GIC_SET_PENDING(irq, mask);
+ GIC_DIST_SET_PENDING(irq, mask);
target_cpu = ctz32(mask);
while (target_cpu < GIC_NCPU) {
s->sgi_pending[irq][target_cpu] |= (1 << cpu);
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index aee50a20e0..295ee9cc5e 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -204,8 +204,8 @@ static void arm_gic_common_reset(DeviceState *dev)
}
}
for (i = 0; i < GIC_NR_SGIS; i++) {
- GIC_SET_ENABLED(i, ALL_CPU_MASK);
- GIC_SET_EDGE_TRIGGER(i);
+ GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
+ GIC_DIST_SET_EDGE_TRIGGER(i);
}
for (i = 0; i < ARRAY_SIZE(s->priority2); i++) {
@@ -222,7 +222,7 @@ static void arm_gic_common_reset(DeviceState *dev)
}
if (s->security_extn && s->irq_reset_nonsecure) {
for (i = 0; i < GIC_MAXIRQ; i++) {
- GIC_SET_GROUP(i, ALL_CPU_MASK);
+ GIC_DIST_SET_GROUP(i, ALL_CPU_MASK);
}
}
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 86665080bd..4b611c8d6d 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -140,10 +140,10 @@ static void translate_group(GICState *s, int irq, int cpu,
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (to_kernel) {
- *field = GIC_TEST_GROUP(irq, cm);
+ *field = GIC_DIST_TEST_GROUP(irq, cm);
} else {
if (*field & 1) {
- GIC_SET_GROUP(irq, cm);
+ GIC_DIST_SET_GROUP(irq, cm);
}
}
}
@@ -154,10 +154,10 @@ static void translate_enabled(GICState *s, int irq, int cpu,
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (to_kernel) {
- *field = GIC_TEST_ENABLED(irq, cm);
+ *field = GIC_DIST_TEST_ENABLED(irq, cm);
} else {
if (*field & 1) {
- GIC_SET_ENABLED(irq, cm);
+ GIC_DIST_SET_ENABLED(irq, cm);
}
}
}
@@ -171,7 +171,7 @@ static void translate_pending(GICState *s, int irq, int cpu,
*field = gic_test_pending(s, irq, cm);
} else {
if (*field & 1) {
- GIC_SET_PENDING(irq, cm);
+ GIC_DIST_SET_PENDING(irq, cm);
/* TODO: Capture is level-line is held high in the kernel */
}
}
@@ -183,10 +183,10 @@ static void translate_active(GICState *s, int irq, int cpu,
int cm = (irq < GIC_INTERNAL) ? (1 << cpu) : ALL_CPU_MASK;
if (to_kernel) {
- *field = GIC_TEST_ACTIVE(irq, cm);
+ *field = GIC_DIST_TEST_ACTIVE(irq, cm);
} else {
if (*field & 1) {
- GIC_SET_ACTIVE(irq, cm);
+ GIC_DIST_SET_ACTIVE(irq, cm);
}
}
}
@@ -195,10 +195,10 @@ static void translate_trigger(GICState *s, int irq, int cpu,
uint32_t *field, bool to_kernel)
{
if (to_kernel) {
- *field = (GIC_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
+ *field = (GIC_DIST_TEST_EDGE_TRIGGER(irq)) ? 0x2 : 0x0;
} else {
if (*field & 0x2) {
- GIC_SET_EDGE_TRIGGER(irq);
+ GIC_DIST_SET_EDGE_TRIGGER(irq);
}
}
}
@@ -207,9 +207,10 @@ static void translate_priority(GICState *s, int irq, int cpu,
uint32_t *field, bool to_kernel)
{
if (to_kernel) {
- *field = GIC_GET_PRIORITY(irq, cpu) & 0xff;
+ *field = GIC_DIST_GET_PRIORITY(irq, cpu) & 0xff;
} else {
- gic_set_priority(s, cpu, irq, *field & 0xff, MEMTXATTRS_UNSPECIFIED);
+ gic_dist_set_priority(s, cpu, irq,
+ *field & 0xff, MEMTXATTRS_UNSPECIFIED);
}
}
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 7fe87b13de..6f8d242904 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -27,30 +27,31 @@
#define GIC_BASE_IRQ 0
-#define GIC_SET_ENABLED(irq, cm) s->irq_state[irq].enabled |= (cm)
-#define GIC_CLEAR_ENABLED(irq, cm) s->irq_state[irq].enabled &= ~(cm)
-#define GIC_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
-#define GIC_SET_PENDING(irq, cm) s->irq_state[irq].pending |= (cm)
-#define GIC_CLEAR_PENDING(irq, cm) s->irq_state[irq].pending &= ~(cm)
-#define GIC_SET_ACTIVE(irq, cm) s->irq_state[irq].active |= (cm)
-#define GIC_CLEAR_ACTIVE(irq, cm) s->irq_state[irq].active &= ~(cm)
-#define GIC_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
-#define GIC_SET_MODEL(irq) s->irq_state[irq].model = true
-#define GIC_CLEAR_MODEL(irq) s->irq_state[irq].model = false
-#define GIC_TEST_MODEL(irq) s->irq_state[irq].model
-#define GIC_SET_LEVEL(irq, cm) s->irq_state[irq].level |= (cm)
-#define GIC_CLEAR_LEVEL(irq, cm) s->irq_state[irq].level &= ~(cm)
-#define GIC_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
-#define GIC_SET_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = true
-#define GIC_CLEAR_EDGE_TRIGGER(irq) s->irq_state[irq].edge_trigger = false
-#define GIC_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
-#define GIC_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
+#define GIC_DIST_SET_ENABLED(irq, cm) (s->irq_state[irq].enabled |= (cm))
+#define GIC_DIST_CLEAR_ENABLED(irq, cm) (s->irq_state[irq].enabled &= ~(cm))
+#define GIC_DIST_TEST_ENABLED(irq, cm) ((s->irq_state[irq].enabled & (cm)) != 0)
+#define GIC_DIST_SET_PENDING(irq, cm) (s->irq_state[irq].pending |= (cm))
+#define GIC_DIST_CLEAR_PENDING(irq, cm) (s->irq_state[irq].pending &= ~(cm))
+#define GIC_DIST_SET_ACTIVE(irq, cm) (s->irq_state[irq].active |= (cm))
+#define GIC_DIST_CLEAR_ACTIVE(irq, cm) (s->irq_state[irq].active &= ~(cm))
+#define GIC_DIST_TEST_ACTIVE(irq, cm) ((s->irq_state[irq].active & (cm)) != 0)
+#define GIC_DIST_SET_MODEL(irq) (s->irq_state[irq].model = true)
+#define GIC_DIST_CLEAR_MODEL(irq) (s->irq_state[irq].model = false)
+#define GIC_DIST_TEST_MODEL(irq) (s->irq_state[irq].model)
+#define GIC_DIST_SET_LEVEL(irq, cm) (s->irq_state[irq].level |= (cm))
+#define GIC_DIST_CLEAR_LEVEL(irq, cm) (s->irq_state[irq].level &= ~(cm))
+#define GIC_DIST_TEST_LEVEL(irq, cm) ((s->irq_state[irq].level & (cm)) != 0)
+#define GIC_DIST_SET_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger = true)
+#define GIC_DIST_CLEAR_EDGE_TRIGGER(irq) \
+ (s->irq_state[irq].edge_trigger = false)
+#define GIC_DIST_TEST_EDGE_TRIGGER(irq) (s->irq_state[irq].edge_trigger)
+#define GIC_DIST_GET_PRIORITY(irq, cpu) (((irq) < GIC_INTERNAL) ? \
s->priority1[irq][cpu] : \
s->priority2[(irq) - GIC_INTERNAL])
-#define GIC_TARGET(irq) s->irq_target[irq]
-#define GIC_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
-#define GIC_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
-#define GIC_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
+#define GIC_DIST_TARGET(irq) (s->irq_target[irq])
+#define GIC_DIST_CLEAR_GROUP(irq, cm) (s->irq_state[irq].group &= ~(cm))
+#define GIC_DIST_SET_GROUP(irq, cm) (s->irq_state[irq].group |= (cm))
+#define GIC_DIST_TEST_GROUP(irq, cm) ((s->irq_state[irq].group & (cm)) != 0)
#define GICD_CTLR_EN_GRP0 (1U << 0)
#define GICD_CTLR_EN_GRP1 (1U << 1)
@@ -79,8 +80,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
void gic_update(GICState *s);
void gic_init_irqs_and_distributor(GICState *s);
-void gic_set_priority(GICState *s, int cpu, int irq, uint8_t val,
- MemTxAttrs attrs);
+void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
+ MemTxAttrs attrs);
static inline bool gic_test_pending(GICState *s, int irq, int cm)
{
@@ -93,7 +94,7 @@ static inline bool gic_test_pending(GICState *s, int irq, int cm)
* GICD_ISPENDR to set the state pending.
*/
return (s->irq_state[irq].pending & cm) ||
- (!GIC_TEST_EDGE_TRIGGER(irq) && GIC_TEST_LEVEL(irq, cm));
+ (!GIC_DIST_TEST_EDGE_TRIGGER(irq) && GIC_DIST_TEST_LEVEL(irq, cm));
}
}
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:15 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static Luc Michel
` (18 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
Those registers allow to set or clear the active state of an IRQ in the
distributor.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 61 +++++++++++++++++++++++++++++++++++++++++++----
1 file changed, 57 insertions(+), 4 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 6f3074ba88..accc03523b 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -711,8 +711,16 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
}
}
} else if (offset < 0x400) {
- /* Interrupt Active. */
- irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
+ /* Interrupt Set/Clear Active. */
+ if (offset < 0x380) {
+ irq = (offset - 0x300) * 8;
+ } else if (s->revision == 2) {
+ irq = (offset - 0x380) * 8;
+ } else {
+ goto bad_reg;
+ }
+
+ irq += GIC_BASE_IRQ;
if (irq >= s->num_irq)
goto bad_reg;
res = 0;
@@ -991,9 +999,54 @@ static void gic_dist_writeb(void *opaque, hwaddr offset,
GIC_DIST_CLEAR_PENDING(irq + i, ALL_CPU_MASK);
}
}
+ } else if (offset < 0x380) {
+ /* Interrupt Set Active. */
+ if (s->revision != 2) {
+ goto bad_reg;
+ }
+
+ irq = (offset - 0x300) * 8 + GIC_BASE_IRQ;
+ if (irq >= s->num_irq) {
+ goto bad_reg;
+ }
+
+ /* This register is banked per-cpu for PPIs */
+ int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK;
+
+ for (i = 0; i < 8; i++) {
+ if (s->security_extn && !attrs.secure &&
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
+ continue; /* Ignore Non-secure access of Group0 IRQ */
+ }
+
+ if (value & (1 << i)) {
+ GIC_DIST_SET_ACTIVE(irq + i, cm);
+ }
+ }
} else if (offset < 0x400) {
- /* Interrupt Active. */
- goto bad_reg;
+ /* Interrupt Clear Active. */
+ if (s->revision != 2) {
+ goto bad_reg;
+ }
+
+ irq = (offset - 0x380) * 8 + GIC_BASE_IRQ;
+ if (irq >= s->num_irq) {
+ goto bad_reg;
+ }
+
+ /* This register is banked per-cpu for PPIs */
+ int cm = irq < GIC_INTERNAL ? (1 << cpu) : ALL_CPU_MASK;
+
+ for (i = 0; i < 8; i++) {
+ if (s->security_extn && !attrs.secure &&
+ !GIC_DIST_TEST_GROUP(irq + i, 1 << cpu)) {
+ continue; /* Ignore Non-secure access of Group0 IRQ */
+ }
+
+ if (value & (1 << i)) {
+ GIC_DIST_CLEAR_ACTIVE(irq + i, cm);
+ }
+ }
} else if (offset < 0x800) {
/* Interrupt Priority. */
irq = (offset - 0x400) + GIC_BASE_IRQ;
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY Luc Michel
` (17 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Some functions are now only used in arm_gic.c, put them static. Some of
them where only used by the NVIC implementation and are not used
anymore, so remove them.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 23 ++---------------------
hw/intc/gic_internal.h | 4 ----
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index accc03523b..9fe70e5519 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -71,7 +71,7 @@ static inline bool gic_has_groups(GICState *s)
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
-void gic_update(GICState *s)
+static void gic_update(GICState *s)
{
int best_irq;
int best_prio;
@@ -137,19 +137,6 @@ void gic_update(GICState *s)
}
}
-void gic_set_pending_private(GICState *s, int cpu, int irq)
-{
- int cm = 1 << cpu;
-
- if (gic_test_pending(s, irq, cm)) {
- return;
- }
-
- DPRINTF("Set %d pending cpu %d\n", irq, cpu);
- GIC_DIST_SET_PENDING(irq, cm);
- gic_update(s);
-}
-
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
@@ -565,7 +552,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
GIC_DIST_CLEAR_ACTIVE(irq, cm);
}
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
+static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
int cm = 1 << cpu;
int group;
@@ -1472,12 +1459,6 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
-/* This function is used by nvic model */
-void gic_init_irqs_and_distributor(GICState *s)
-{
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
-}
-
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 6f8d242904..a2075a94db 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -75,11 +75,7 @@
/* The special cases for the revision property: */
#define REV_11MPCORE 0
-void gic_set_pending_private(GICState *s, int cpu, int irq);
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs);
-void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs);
-void gic_update(GICState *s);
-void gic_init_irqs_and_distributor(GICState *s);
void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val,
MemTxAttrs attrs);
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (2 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state Luc Michel
` (16 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Provide a VMSTATE_UINT16_SUB_ARRAY macro to save a uint16_t sub-array in
a VMState.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
include/migration/vmstate.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h
index 42b946ce90..2b501d0466 100644
--- a/include/migration/vmstate.h
+++ b/include/migration/vmstate.h
@@ -923,6 +923,9 @@ extern const VMStateInfo vmstate_info_qtailq;
#define VMSTATE_UINT16_ARRAY(_f, _s, _n) \
VMSTATE_UINT16_ARRAY_V(_f, _s, _n, 0)
+#define VMSTATE_UINT16_SUB_ARRAY(_f, _s, _start, _num) \
+ VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint16, uint16_t)
+
#define VMSTATE_UINT16_2DARRAY(_f, _s, _n1, _n2) \
VMSTATE_UINT16_2DARRAY_V(_f, _s, _n1, _n2, 0)
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (3 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 06/20] intc/arm_gic: Add virtual interface register definitions Luc Michel
` (15 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add the necessary parts of the virtualization extensions state to the
GIC state. We choose to increase the size of the CPU interfaces state to
add space for the vCPU interfaces (the GIC_NCPU_VCPU macro). This way,
we'll be able to reuse most of the CPU interface code for the vCPUs.
The only exception is the APR value, which is stored in h_apr in the
virtual interface state for vCPUs. This is due to some complications
with the GIC VMState, for which we don't want to break backward
compatibility. APRs being stored in 2D arrays, increasing the second
dimension would lead to some ugly VMState description. To avoid
that, we keep it in h_apr for vCPUs.
The vCPUs are numbered from GIC_NCPU to (GIC_NCPU * 2) - 1. The
`gic_is_vcpu` function help to determine if a given CPU id correspond to
a physical CPU or a virtual one.
For the in-kernel KVM VGIC, since the exposed VGIC does not implement
the virtualization extensions, we report an error if the corresponding
property is set to true.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 2 +-
hw/intc/arm_gic_common.c | 148 ++++++++++++++++++++++++++-----
hw/intc/arm_gic_kvm.c | 8 +-
hw/intc/gic_internal.h | 5 ++
include/hw/intc/arm_gic_common.h | 43 +++++++--
5 files changed, 173 insertions(+), 33 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 9fe70e5519..aaa34426a1 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1481,7 +1481,7 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
}
/* This creates distributor and main CPU interface (s->cpuiomem[0]) */
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops);
+ gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL);
/* Extra core-specific regions for the CPU interfaces. This is
* necessary for "franken-GIC" implementations, for example on
diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c
index 295ee9cc5e..547dc41185 100644
--- a/hw/intc/arm_gic_common.c
+++ b/hw/intc/arm_gic_common.c
@@ -46,6 +46,13 @@ static int gic_post_load(void *opaque, int version_id)
return 0;
}
+static bool gic_virt_state_needed(void *opaque)
+{
+ GICState *s = (GICState *)opaque;
+
+ return s->virt_extn;
+}
+
static const VMStateDescription vmstate_gic_irq_state = {
.name = "arm_gic_irq_state",
.version_id = 1,
@@ -62,6 +69,30 @@ static const VMStateDescription vmstate_gic_irq_state = {
}
};
+static const VMStateDescription vmstate_gic_virt_state = {
+ .name = "arm_gic_virt_state",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = gic_virt_state_needed,
+ .fields = (VMStateField[]) {
+ /* Virtual interface */
+ VMSTATE_UINT32_ARRAY(h_hcr, GICState, GIC_NCPU),
+ VMSTATE_UINT32_ARRAY(h_misr, GICState, GIC_NCPU),
+ VMSTATE_UINT32_2DARRAY(h_lr, GICState, GIC_MAX_LR, GIC_NCPU),
+ VMSTATE_UINT32_ARRAY(h_apr, GICState, GIC_NCPU),
+
+ /* Virtual CPU interfaces */
+ VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, GIC_NCPU, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, GIC_NCPU, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, GIC_NCPU, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, GIC_NCPU, GIC_NCPU),
+ VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, GIC_NCPU, GIC_NCPU),
+ VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, GIC_NCPU, GIC_NCPU),
+
+ VMSTATE_END_OF_LIST()
+ }
+};
+
static const VMStateDescription vmstate_gic = {
.name = "arm_gic",
.version_id = 12,
@@ -70,26 +101,31 @@ static const VMStateDescription vmstate_gic = {
.post_load = gic_post_load,
.fields = (VMStateField[]) {
VMSTATE_UINT32(ctlr, GICState),
- VMSTATE_UINT32_ARRAY(cpu_ctlr, GICState, GIC_NCPU),
+ VMSTATE_UINT32_SUB_ARRAY(cpu_ctlr, GICState, 0, GIC_NCPU),
VMSTATE_STRUCT_ARRAY(irq_state, GICState, GIC_MAXIRQ, 1,
vmstate_gic_irq_state, gic_irq_state),
VMSTATE_UINT8_ARRAY(irq_target, GICState, GIC_MAXIRQ),
VMSTATE_UINT8_2DARRAY(priority1, GICState, GIC_INTERNAL, GIC_NCPU),
VMSTATE_UINT8_ARRAY(priority2, GICState, GIC_MAXIRQ - GIC_INTERNAL),
VMSTATE_UINT8_2DARRAY(sgi_pending, GICState, GIC_NR_SGIS, GIC_NCPU),
- VMSTATE_UINT16_ARRAY(priority_mask, GICState, GIC_NCPU),
- VMSTATE_UINT16_ARRAY(running_priority, GICState, GIC_NCPU),
- VMSTATE_UINT16_ARRAY(current_pending, GICState, GIC_NCPU),
- VMSTATE_UINT8_ARRAY(bpr, GICState, GIC_NCPU),
- VMSTATE_UINT8_ARRAY(abpr, GICState, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(priority_mask, GICState, 0, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(running_priority, GICState, 0, GIC_NCPU),
+ VMSTATE_UINT16_SUB_ARRAY(current_pending, GICState, 0, GIC_NCPU),
+ VMSTATE_UINT8_SUB_ARRAY(bpr, GICState, 0, GIC_NCPU),
+ VMSTATE_UINT8_SUB_ARRAY(abpr, GICState, 0, GIC_NCPU),
VMSTATE_UINT32_2DARRAY(apr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_UINT32_2DARRAY(nsapr, GICState, GIC_NR_APRS, GIC_NCPU),
VMSTATE_END_OF_LIST()
+ },
+ .subsections = (const VMStateDescription * []) {
+ &vmstate_gic_virt_state,
+ NULL
}
};
void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
- const MemoryRegionOps *ops)
+ const MemoryRegionOps *ops,
+ const MemoryRegionOps *virt_ops)
{
SysBusDevice *sbd = SYS_BUS_DEVICE(s);
int i = s->num_irq - GIC_INTERNAL;
@@ -116,6 +152,11 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
for (i = 0; i < s->num_cpu; i++) {
sysbus_init_irq(sbd, &s->parent_vfiq[i]);
}
+ if (s->virt_extn) {
+ for (i = 0; i < s->num_cpu; i++) {
+ sysbus_init_irq(sbd, &s->maintenance_irq[i]);
+ }
+ }
/* Distributor */
memory_region_init_io(&s->iomem, OBJECT(s), ops, s, "gic_dist", 0x1000);
@@ -127,6 +168,17 @@ void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
memory_region_init_io(&s->cpuiomem[0], OBJECT(s), ops ? &ops[1] : NULL,
s, "gic_cpu", s->revision == 2 ? 0x2000 : 0x100);
sysbus_init_mmio(sbd, &s->cpuiomem[0]);
+
+ if (s->virt_extn) {
+ memory_region_init_io(&s->vifaceiomem[0], OBJECT(s), virt_ops,
+ s, "gic_viface", 0x1000);
+ sysbus_init_mmio(sbd, &s->vifaceiomem[0]);
+
+ memory_region_init_io(&s->vcpuiomem, OBJECT(s),
+ virt_ops ? &virt_ops[1] : NULL,
+ s, "gic_vcpu", 0x2000);
+ sysbus_init_mmio(sbd, &s->vcpuiomem);
+ }
}
static void arm_gic_common_realize(DeviceState *dev, Error **errp)
@@ -163,6 +215,48 @@ static void arm_gic_common_realize(DeviceState *dev, Error **errp)
"the security extensions");
return;
}
+
+ if (s->virt_extn) {
+ if (s->revision != 2) {
+ error_setg(errp, "GIC virtualization extensions are only "
+ "supported by revision 2");
+ return;
+ }
+
+ /* For now, set the number of implemented LRs to 4, as found in most
+ * real GICv2. This could be promoted as a QOM property if we need to
+ * emulate a variant with another num_lrs.
+ */
+ s->num_lrs = 4;
+ }
+}
+
+static inline void arm_gic_common_reset_irq_state(GICState *s, int first_cpu,
+ int resetprio)
+{
+ int i, j;
+
+ for (i = first_cpu; i < first_cpu + s->num_cpu; i++) {
+ if (s->revision == REV_11MPCORE) {
+ s->priority_mask[i] = 0xf0;
+ } else {
+ s->priority_mask[i] = resetprio;
+ }
+ s->current_pending[i] = 1023;
+ s->running_priority[i] = 0x100;
+ s->cpu_ctlr[i] = 0;
+ s->bpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
+ s->abpr[i] = gic_is_vcpu(i) ? GIC_VIRT_MIN_ABPR : GIC_MIN_ABPR;
+
+ if (!gic_is_vcpu(i)) {
+ for (j = 0; j < GIC_INTERNAL; j++) {
+ s->priority1[j][i] = resetprio;
+ }
+ for (j = 0; j < GIC_NR_SGIS; j++) {
+ s->sgi_pending[j][i] = 0;
+ }
+ }
+ }
}
static void arm_gic_common_reset(DeviceState *dev)
@@ -185,24 +279,15 @@ static void arm_gic_common_reset(DeviceState *dev)
}
memset(s->irq_state, 0, GIC_MAXIRQ * sizeof(gic_irq_state));
- for (i = 0 ; i < s->num_cpu; i++) {
- if (s->revision == REV_11MPCORE) {
- s->priority_mask[i] = 0xf0;
- } else {
- s->priority_mask[i] = resetprio;
- }
- s->current_pending[i] = 1023;
- s->running_priority[i] = 0x100;
- s->cpu_ctlr[i] = 0;
- s->bpr[i] = GIC_MIN_BPR;
- s->abpr[i] = GIC_MIN_ABPR;
- for (j = 0; j < GIC_INTERNAL; j++) {
- s->priority1[j][i] = resetprio;
- }
- for (j = 0; j < GIC_NR_SGIS; j++) {
- s->sgi_pending[j][i] = 0;
- }
+ arm_gic_common_reset_irq_state(s, 0, resetprio);
+
+ if (s->virt_extn) {
+ /* vCPU states are stored at indexes GIC_NCPU .. GIC_NCPU+num_cpu.
+ * The exposed vCPU interface does not have security extensions.
+ */
+ arm_gic_common_reset_irq_state(s, GIC_NCPU, 0);
}
+
for (i = 0; i < GIC_NR_SGIS; i++) {
GIC_DIST_SET_ENABLED(i, ALL_CPU_MASK);
GIC_DIST_SET_EDGE_TRIGGER(i);
@@ -226,6 +311,19 @@ static void arm_gic_common_reset(DeviceState *dev)
}
}
+ if (s->virt_extn) {
+ for (i = 0; i < s->num_lrs; i++) {
+ for (j = 0; j < s->num_cpu; j++) {
+ s->h_lr[i][j] = 0;
+ }
+ }
+
+ for (i = 0; i < s->num_cpu; i++) {
+ s->h_hcr[i] = 0;
+ s->h_misr[i] = 0;
+ }
+ }
+
s->ctlr = 0;
}
@@ -255,6 +353,8 @@ static Property arm_gic_common_properties[] = {
DEFINE_PROP_UINT32("revision", GICState, revision, 1),
/* True if the GIC should implement the security extensions */
DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0),
+ /* True if the GIC should implement the virtualization extensions */
+ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0),
DEFINE_PROP_END_OF_LIST(),
};
diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c
index 4b611c8d6d..a611e8ee12 100644
--- a/hw/intc/arm_gic_kvm.c
+++ b/hw/intc/arm_gic_kvm.c
@@ -511,6 +511,12 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
+ if (s->virt_extn) {
+ error_setg(errp, "the in-kernel VGIC does not implement the "
+ "virtualization extensions");
+ return;
+ }
+
if (!kvm_arm_gic_can_save_restore(s)) {
error_setg(&s->migration_blocker, "This operating system kernel does "
"not support vGICv2 migration");
@@ -522,7 +528,7 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp)
}
}
- gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL);
+ gic_init_irqs_and_mmio(s, kvm_arm_gicv2_set_irq, NULL, NULL);
for (i = 0; i < s->num_irq - GIC_INTERNAL; i++) {
qemu_irq irq = qdev_get_gpio_in(dev, i);
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index a2075a94db..c85427c8e3 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -94,4 +94,9 @@ static inline bool gic_test_pending(GICState *s, int irq, int cm)
}
}
+static inline bool gic_is_vcpu(int cpu)
+{
+ return cpu >= GIC_NCPU;
+}
+
#endif /* QEMU_ARM_GIC_INTERNAL_H */
diff --git a/include/hw/intc/arm_gic_common.h b/include/hw/intc/arm_gic_common.h
index af3ca18e2f..b5585fec45 100644
--- a/include/hw/intc/arm_gic_common.h
+++ b/include/hw/intc/arm_gic_common.h
@@ -30,6 +30,8 @@
#define GIC_NR_SGIS 16
/* Maximum number of possible CPU interfaces, determined by GIC architecture */
#define GIC_NCPU 8
+/* Maximum number of possible CPU interfaces with their respective vCPU */
+#define GIC_NCPU_VCPU (GIC_NCPU * 2)
#define MAX_NR_GROUP_PRIO 128
#define GIC_NR_APRS (MAX_NR_GROUP_PRIO / 32)
@@ -37,6 +39,17 @@
#define GIC_MIN_BPR 0
#define GIC_MIN_ABPR (GIC_MIN_BPR + 1)
+/* Architectural maximum number of list registers in the virtual interface */
+#define GIC_MAX_LR 64
+
+/* Only 32 priority levels and 32 preemption levels in the vCPU interfaces */
+#define GIC_VIRT_MAX_GROUP_PRIO_BITS 5
+#define GIC_VIRT_MAX_NR_GROUP_PRIO (1 << GIC_VIRT_MAX_GROUP_PRIO_BITS)
+#define GIC_VIRT_NR_APRS (GIC_VIRT_MAX_NR_GROUP_PRIO / 32)
+
+#define GIC_VIRT_MIN_BPR 2
+#define GIC_VIRT_MIN_ABPR (GIC_VIRT_MIN_BPR + 1)
+
typedef struct gic_irq_state {
/* The enable bits are only banked for per-cpu interrupts. */
uint8_t enabled;
@@ -57,6 +70,8 @@ typedef struct GICState {
qemu_irq parent_fiq[GIC_NCPU];
qemu_irq parent_virq[GIC_NCPU];
qemu_irq parent_vfiq[GIC_NCPU];
+ qemu_irq maintenance_irq[GIC_NCPU];
+
/* GICD_CTLR; for a GIC with the security extensions the NS banked version
* of this register is just an alias of bit 1 of the S banked version.
*/
@@ -64,7 +79,7 @@ typedef struct GICState {
/* GICC_CTLR; again, the NS banked version is just aliases of bits of
* the S banked register, so our state only needs to store the S version.
*/
- uint32_t cpu_ctlr[GIC_NCPU];
+ uint32_t cpu_ctlr[GIC_NCPU_VCPU];
gic_irq_state irq_state[GIC_MAXIRQ];
uint8_t irq_target[GIC_MAXIRQ];
@@ -78,9 +93,9 @@ typedef struct GICState {
*/
uint8_t sgi_pending[GIC_NR_SGIS][GIC_NCPU];
- uint16_t priority_mask[GIC_NCPU];
- uint16_t running_priority[GIC_NCPU];
- uint16_t current_pending[GIC_NCPU];
+ uint16_t priority_mask[GIC_NCPU_VCPU];
+ uint16_t running_priority[GIC_NCPU_VCPU];
+ uint16_t current_pending[GIC_NCPU_VCPU];
/* If we present the GICv2 without security extensions to a guest,
* the guest can configure the GICC_CTLR to configure group 1 binary point
@@ -88,8 +103,8 @@ typedef struct GICState {
* For a GIC with Security Extensions we use use bpr for the
* secure copy and abpr as storage for the non-secure copy of the register.
*/
- uint8_t bpr[GIC_NCPU];
- uint8_t abpr[GIC_NCPU];
+ uint8_t bpr[GIC_NCPU_VCPU];
+ uint8_t abpr[GIC_NCPU_VCPU];
/* The APR is implementation defined, so we choose a layout identical to
* the KVM ABI layout for QEMU's implementation of the gic:
@@ -100,6 +115,15 @@ typedef struct GICState {
uint32_t apr[GIC_NR_APRS][GIC_NCPU];
uint32_t nsapr[GIC_NR_APRS][GIC_NCPU];
+ /* Virtual interface control registers */
+ uint32_t h_hcr[GIC_NCPU];
+ uint32_t h_misr[GIC_NCPU];
+ uint32_t h_lr[GIC_MAX_LR][GIC_NCPU];
+ uint32_t h_apr[GIC_NCPU];
+
+ /* Number of LRs implemented in this GIC instance */
+ uint32_t num_lrs;
+
uint32_t num_cpu;
MemoryRegion iomem; /* Distributor */
@@ -108,9 +132,13 @@ typedef struct GICState {
*/
struct GICState *backref[GIC_NCPU];
MemoryRegion cpuiomem[GIC_NCPU + 1]; /* CPU interfaces */
+ MemoryRegion vifaceiomem[GIC_NCPU + 1]; /* Virtual interfaces */
+ MemoryRegion vcpuiomem; /* vCPU interface */
+
uint32_t num_irq;
uint32_t revision;
bool security_extn;
+ bool virt_extn;
bool irq_reset_nonsecure; /* configure IRQs as group 1 (NS) on reset? */
int dev_fd; /* kvm device fd if backed by kvm vgic support */
Error *migration_blocker;
@@ -134,6 +162,7 @@ typedef struct ARMGICCommonClass {
} ARMGICCommonClass;
void gic_init_irqs_and_mmio(GICState *s, qemu_irq_handler handler,
- const MemoryRegionOps *ops);
+ const MemoryRegionOps *ops,
+ const MemoryRegionOps *virt_ops);
#endif
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 06/20] intc/arm_gic: Add virtual interface register definitions
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (4 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions Luc Michel
` (14 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add the register definitions for the virtual interface of the GICv2.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/gic_internal.h | 65 ++++++++++++++++++++++++++++++++++++++++++
1 file changed, 65 insertions(+)
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index c85427c8e3..1aa888a576 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -21,6 +21,7 @@
#ifndef QEMU_ARM_GIC_INTERNAL_H
#define QEMU_ARM_GIC_INTERNAL_H
+#include "hw/registerfields.h"
#include "hw/intc/arm_gic.h"
#define ALL_CPU_MASK ((unsigned)(((1 << GIC_NCPU) - 1)))
@@ -64,6 +65,70 @@
#define GICC_CTLR_EOIMODE (1U << 9)
#define GICC_CTLR_EOIMODE_NS (1U << 10)
+REG32(GICH_HCR, 0x0)
+ FIELD(GICH_HCR, EN, 0, 1)
+ FIELD(GICH_HCR, UIE, 1, 1)
+ FIELD(GICH_HCR, LRENPIE, 2, 1)
+ FIELD(GICH_HCR, NPIE, 3, 1)
+ FIELD(GICH_HCR, VGRP0EIE, 4, 1)
+ FIELD(GICH_HCR, VGRP0DIE, 5, 1)
+ FIELD(GICH_HCR, VGRP1EIE, 6, 1)
+ FIELD(GICH_HCR, VGRP1DIE, 7, 1)
+ FIELD(GICH_HCR, EOICount, 27, 5)
+
+#define GICH_HCR_MASK \
+ (R_GICH_HCR_EN_MASK | R_GICH_HCR_UIE_MASK | \
+ R_GICH_HCR_LRENPIE_MASK | R_GICH_HCR_NPIE_MASK | \
+ R_GICH_HCR_VGRP0EIE_MASK | R_GICH_HCR_VGRP0DIE_MASK | \
+ R_GICH_HCR_VGRP1EIE_MASK | R_GICH_HCR_VGRP1DIE_MASK | \
+ R_GICH_HCR_EOICount_MASK)
+
+REG32(GICH_VTR, 0x4)
+ FIELD(GICH_VTR, ListRegs, 0, 6)
+ FIELD(GICH_VTR, PREbits, 26, 3)
+ FIELD(GICH_VTR, PRIbits, 29, 3)
+
+REG32(GICH_VMCR, 0x8)
+ FIELD(GICH_VMCR, VMCCtlr, 0, 10)
+ FIELD(GICH_VMCR, VMABP, 18, 3)
+ FIELD(GICH_VMCR, VMBP, 21, 3)
+ FIELD(GICH_VMCR, VMPriMask, 27, 5)
+
+REG32(GICH_MISR, 0x10)
+ FIELD(GICH_MISR, EOI, 0, 1)
+ FIELD(GICH_MISR, U, 1, 1)
+ FIELD(GICH_MISR, LRENP, 2, 1)
+ FIELD(GICH_MISR, NP, 3, 1)
+ FIELD(GICH_MISR, VGrp0E, 4, 1)
+ FIELD(GICH_MISR, VGrp0D, 5, 1)
+ FIELD(GICH_MISR, VGrp1E, 6, 1)
+ FIELD(GICH_MISR, VGrp1D, 7, 1)
+
+REG32(GICH_EISR0, 0x20)
+REG32(GICH_EISR1, 0x24)
+REG32(GICH_ELRSR0, 0x30)
+REG32(GICH_ELRSR1, 0x34)
+REG32(GICH_APR, 0xf0)
+
+REG32(GICH_LR0, 0x100)
+ FIELD(GICH_LR0, VirtualID, 0, 10)
+ FIELD(GICH_LR0, PhysicalID, 10, 10)
+ FIELD(GICH_LR0, CPUID, 10, 3)
+ FIELD(GICH_LR0, EOI, 19, 1)
+ FIELD(GICH_LR0, Priority, 23, 5)
+ FIELD(GICH_LR0, State, 28, 2)
+ FIELD(GICH_LR0, Grp1, 30, 1)
+ FIELD(GICH_LR0, HW, 31, 1)
+
+/* Last LR register */
+REG32(GICH_LR63, 0x1fc)
+
+#define GICH_LR_MASK \
+ (R_GICH_LR0_VirtualID_MASK | R_GICH_LR0_PhysicalID_MASK | \
+ R_GICH_LR0_CPUID_MASK | R_GICH_LR0_EOI_MASK | \
+ R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \
+ R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK)
+
/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
* GICv2 and GICv2 with security extensions:
*/
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (5 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 06/20] intc/arm_gic: Add virtual interface register definitions Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:17 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface Luc Michel
` (13 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add some helper macros and functions related to the virtualization
extensions to gic_internal.h.
The GICH_LR_* macros help extracting specific fields of a list register
value. The only tricky one is the priority field as only the MSB are
stored. The value must be shifted accordingly to obtain the correct
priority value.
gic_is_vcpu() and gic_get_vcpu_real_id() help with (v)CPU id manipulation
to abstract the fact that vCPU id are in the range
[ GIC_NCPU; (GIC_NCPU + num_cpu) [.
gic_lr_* and gic_virq_is_valid() help with the list registers.
gic_get_lr_entry() returns the LR entry for a given (vCPU, irq) pair. It
is meant to be used in contexts where we know for sure that the entry
exists, so we assert that entry is actually found, and the caller can
avoid the NULL check on the returned pointer.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 5 +++
hw/intc/gic_internal.h | 75 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 80 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index aaa34426a1..1ac0fe740c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -61,6 +61,11 @@ static inline int gic_get_current_cpu(GICState *s)
return 0;
}
+static inline int gic_get_current_vcpu(GICState *s)
+{
+ return gic_get_current_cpu(s) + GIC_NCPU;
+}
+
/* Return true if this GIC config has interrupt groups, which is
* true if we're a GICv2, or a GICv1 with the security extensions.
*/
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 1aa888a576..56e203aeb9 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -129,6 +129,20 @@ REG32(GICH_LR63, 0x1fc)
R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \
R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK)
+#define GICH_LR_STATE_INVALID 0
+#define GICH_LR_STATE_PENDING 1
+#define GICH_LR_STATE_ACTIVE 2
+#define GICH_LR_STATE_ACTIVE_PENDING 3
+
+#define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID))
+#define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID))
+#define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID))
+#define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI))
+#define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << 3)
+#define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State))
+#define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1))
+#define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
+
/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
* GICv2 and GICv2 with security extensions:
*/
@@ -164,4 +178,65 @@ static inline bool gic_is_vcpu(int cpu)
return cpu >= GIC_NCPU;
}
+static inline int gic_get_vcpu_real_id(int cpu)
+{
+ return (cpu >= GIC_NCPU) ? (cpu - GIC_NCPU) : cpu;
+}
+
+/* Return true if the given vIRQ state exists in a LR and is either active or
+ * pending and active.
+ *
+ * This function is used to check that a guest's `end of interrupt' or
+ * `interrupts deactivation' request is valid, and matches with a LR of an
+ * already acknowledged vIRQ (i.e. has the active bit set in its state).
+ */
+static inline bool gic_virq_is_valid(GICState *s, int irq, int vcpu)
+{
+ int cpu = gic_get_vcpu_real_id(vcpu);
+ int lr_idx;
+
+ for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t *entry = &s->h_lr[lr_idx][cpu];
+
+ if ((GICH_LR_VIRT_ID(*entry) == irq) &&
+ (GICH_LR_STATE(*entry) & GICH_LR_STATE_ACTIVE)) {
+ return true;
+ }
+ }
+
+ return false;
+}
+
+/* Return a pointer on the LR entry matching the given vIRQ.
+ *
+ * This function is used to retrieve an LR for which we know for sure that the
+ * corresponding vIRQ exists in the current context (i.e. its current state is
+ * not `invalid'):
+ * - Either the corresponding vIRQ has been validated with gic_virq_is_valid()
+ * so it is `active' or `active and pending',
+ * - Or it was pending and has been selected by gic_get_best_virq(). It is now
+ * `pending', `active' or `active and pending', depending on what the guest
+ * already did with this vIRQ.
+ *
+ * Having multiple LRs with the same VirtualID leads to UNPREDICTABLE
+ * behaviour in the GIC. We choose to return the first one that matches.
+ */
+static inline uint32_t *gic_get_lr_entry(GICState *s, int irq, int vcpu)
+{
+ int cpu = gic_get_vcpu_real_id(vcpu);
+ int lr_idx;
+
+ for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t *entry = &s->h_lr[lr_idx][cpu];
+
+ if ((GICH_LR_VIRT_ID(*entry) == irq) &&
+ (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID)) {
+ return entry;
+ }
+ }
+
+ g_assert_not_reached();
+ return NULL;
+}
+
#endif /* QEMU_ARM_GIC_INTERNAL_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (6 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions Luc Michel
` (12 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
An access to the CPU interface is non-secure if the current GIC instance
implements the security extensions, and the memory access is actually
non-secure. Until then, it was checked with tests such as
if (s->security_extn && !attrs.secure) { ... }
in various places of the CPU interface code.
With the implementation of the virtualization extensions, those tests
must be updated to take into account whether we are in a vCPU interface
or not. This is because the exposed vCPU interface does not implement
security extensions.
This commits replaces all those tests with a call to the
gic_cpu_ns_access() function to check if the current access to the CPU
interface is non-secure. This function takes into account whether the
current CPU is a vCPU or not.
Note that this function is used only in the (v)CPU interface code path.
The distributor code path is left unchanged, as the distributor is not
exposed to vCPUs at all.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 39 ++++++++++++++++++++++-----------------
1 file changed, 22 insertions(+), 17 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 1ac0fe740c..53cc257ed8 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -74,6 +74,11 @@ static inline bool gic_has_groups(GICState *s)
return s->revision == 2 || s->security_extn;
}
+static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs)
+{
+ return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure;
+}
+
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
static void gic_update(GICState *s)
@@ -221,7 +226,7 @@ static uint16_t gic_get_current_pending_irq(GICState *s, int cpu,
/* On a GIC without the security extensions, reading this register
* behaves in the same way as a secure access to a GIC with them.
*/
- bool secure = !s->security_extn || attrs.secure;
+ bool secure = !gic_cpu_ns_access(s, cpu, attrs);
if (group == 0 && !secure) {
/* Group0 interrupts hidden from Non-secure access */
@@ -428,7 +433,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq,
static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask,
MemTxAttrs attrs)
{
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
if (s->priority_mask[cpu] & 0x80) {
/* Priority Mask in upper half */
pmask = 0x80 | (pmask >> 1);
@@ -444,7 +449,7 @@ static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs)
{
uint32_t pmask = s->priority_mask[cpu];
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
if (pmask & 0x80) {
/* Priority Mask in upper half, return Non-secure view */
pmask = (pmask << 1) & 0xff;
@@ -460,7 +465,7 @@ static uint32_t gic_get_cpu_control(GICState *s, int cpu, MemTxAttrs attrs)
{
uint32_t ret = s->cpu_ctlr[cpu];
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
/* Construct the NS banked view of GICC_CTLR from the correct
* bits of the S banked view. We don't need to move the bypass
* control bits because we don't implement that (IMPDEF) part
@@ -476,7 +481,7 @@ static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value,
{
uint32_t mask;
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
/* The NS view can only write certain bits in the register;
* the rest are unchanged
*/
@@ -507,7 +512,7 @@ static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs)
return 0xff;
}
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
if (s->running_priority[cpu] & 0x80) {
/* Running priority in upper half of range: return the Non-secure
* view of the priority.
@@ -531,7 +536,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
/* Before GICv2 prio-drop and deactivate are not separable */
return false;
}
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE_NS;
}
return s->cpu_ctlr[cpu] & GICC_CTLR_EOIMODE;
@@ -549,7 +554,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
return;
}
- if (s->security_extn && !attrs.secure && !group) {
+ if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
return;
}
@@ -591,7 +596,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm);
- if (s->security_extn && !attrs.secure && !group) {
+ if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
return;
}
@@ -1265,7 +1270,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
*data = gic_get_priority_mask(s, cpu, attrs);
break;
case 0x08: /* Binary Point */
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
/* NS view of BPR when CBPR is 1 */
*data = MIN(s->bpr[cpu] + 1, 7);
@@ -1292,7 +1297,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
* With security extensions, secure access: ABPR (alias of NS BPR)
* With security extensions, nonsecure access: RAZ/WI
*/
- if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
+ if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
*data = 0;
} else {
*data = s->abpr[cpu];
@@ -1304,7 +1309,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) {
*data = 0;
- } else if (s->security_extn && !attrs.secure) {
+ } else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
*data = gic_apr_ns_view(s, regno, cpu);
} else {
@@ -1317,7 +1322,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
int regno = (offset - 0xe0) / 4;
if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
- (s->security_extn && !attrs.secure)) {
+ gic_cpu_ns_access(s, cpu, attrs)) {
*data = 0;
} else {
*data = s->nsapr[regno][cpu];
@@ -1344,7 +1349,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
gic_set_priority_mask(s, cpu, value, attrs);
break;
case 0x08: /* Binary Point */
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) {
/* WI when CBPR is 1 */
return MEMTX_OK;
@@ -1359,7 +1364,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
gic_complete_irq(s, cpu, value & 0x3ff, attrs);
return MEMTX_OK;
case 0x1c: /* Aliased Binary Point */
- if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
+ if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
/* unimplemented, or NS access: RAZ/WI */
return MEMTX_OK;
} else {
@@ -1373,7 +1378,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) {
return MEMTX_OK;
}
- if (s->security_extn && !attrs.secure) {
+ if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
gic_apr_write_ns_view(s, regno, cpu, value);
} else {
@@ -1388,7 +1393,7 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) {
return MEMTX_OK;
}
- if (!gic_has_groups(s) || (s->security_extn && !attrs.secure)) {
+ if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
return MEMTX_OK;
}
s->nsapr[regno][cpu] = value;
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (7 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:20 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) Luc Michel
` (11 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add some helper functions to gic_internal.h to get or change the state
of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
the GIC distributor. Otherwise, it acts on the list register matching
the IRQ in the current CPU virtual interface.
gic_clear_active can have a side effect on the distributor, even in the
vCPU case, when the correponding LR has the HW field set.
Use those functions in the CPU interface code path to prepare for the
vCPU interface implementation.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 32 +++++++---------
hw/intc/gic_internal.h | 83 ++++++++++++++++++++++++++++++++++++++++++
2 files changed, 97 insertions(+), 18 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 53cc257ed8..ad241d12c2 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -222,7 +222,8 @@ static uint16_t gic_get_current_pending_irq(GICState *s, int cpu,
uint16_t pending_irq = s->current_pending[cpu];
if (pending_irq < GIC_MAXIRQ && gic_has_groups(s)) {
- int group = GIC_DIST_TEST_GROUP(pending_irq, (1 << cpu));
+ int group = gic_test_group(s, pending_irq, cpu);
+
/* On a GIC without the security extensions, reading this register
* behaves in the same way as a secure access to a GIC with them.
*/
@@ -253,7 +254,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
if (gic_has_groups(s) &&
!(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) &&
- GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
+ gic_test_group(s, irq, cpu)) {
bpr = s->abpr[cpu] - 1;
assert(bpr >= 0);
} else {
@@ -266,7 +267,7 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq)
*/
mask = ~0U << ((bpr & 7) + 1);
- return GIC_DIST_GET_PRIORITY(irq, cpu) & mask;
+ return gic_get_priority(s, irq, cpu) & mask;
}
static void gic_activate_irq(GICState *s, int cpu, int irq)
@@ -279,14 +280,14 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
int regno = preemption_level / 32;
int bitno = preemption_level % 32;
- if (gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, (1 << cpu))) {
+ if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
s->nsapr[regno][cpu] |= (1 << bitno);
} else {
s->apr[regno][cpu] |= (1 << bitno);
}
s->running_priority[cpu] = prio;
- GIC_DIST_SET_ACTIVE(irq, 1 << cpu);
+ gic_set_active(s, irq, cpu);
}
static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
@@ -355,7 +356,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return irq;
}
- if (GIC_DIST_GET_PRIORITY(irq, cpu) >= s->running_priority[cpu]) {
+ if (gic_get_priority(s, irq, cpu) >= s->running_priority[cpu]) {
DPRINTF("ACK, pending interrupt (%d) has insufficient priority\n", irq);
return 1023;
}
@@ -364,8 +365,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
*/
- GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
- : cm);
+ gic_clear_pending(s, irq, cpu);
ret = irq;
} else {
if (irq < GIC_NR_SGIS) {
@@ -377,9 +377,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
src = ctz32(s->sgi_pending[irq][cpu]);
s->sgi_pending[irq][cpu] &= ~(1 << src);
if (s->sgi_pending[irq][cpu] == 0) {
- GIC_DIST_CLEAR_PENDING(irq,
- GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
- : cm);
+ gic_clear_pending(s, irq, cpu);
}
ret = irq | ((src & 0x7) << 10);
} else {
@@ -387,8 +385,7 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
* interrupts. (level triggered interrupts with an active line
* remain pending, see gic_test_pending)
*/
- GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
- : cm);
+ gic_clear_pending(s, irq, cpu);
ret = irq;
}
}
@@ -544,8 +541,7 @@ static bool gic_eoi_split(GICState *s, int cpu, MemTxAttrs attrs)
static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
{
- int cm = 1 << cpu;
- int group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm);
+ int group = gic_has_groups(s) && gic_test_group(s, irq, cpu);
if (!gic_eoi_split(s, cpu, attrs)) {
/* This is UNPREDICTABLE; we choose to ignore it */
@@ -559,7 +555,7 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
return;
}
- GIC_DIST_CLEAR_ACTIVE(irq, cm);
+ gic_clear_active(s, irq, cpu);
}
static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
@@ -594,7 +590,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
}
}
- group = gic_has_groups(s) && GIC_DIST_TEST_GROUP(irq, cm);
+ group = gic_has_groups(s) && gic_test_group(s, irq, cpu);
if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
DPRINTF("Non-secure EOI for Group0 interrupt %d ignored\n", irq);
@@ -610,7 +606,7 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
/* In GICv2 the guest can choose to split priority-drop and deactivate */
if (!gic_eoi_split(s, cpu, attrs)) {
- GIC_DIST_CLEAR_ACTIVE(irq, cm);
+ gic_clear_active(s, irq, cpu);
}
gic_update(s);
}
diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
index 56e203aeb9..d772d621fd 100644
--- a/hw/intc/gic_internal.h
+++ b/hw/intc/gic_internal.h
@@ -143,6 +143,13 @@ REG32(GICH_LR63, 0x1fc)
#define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1))
#define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
+#define GICH_LR_CLEAR_PENDING(entry) \
+ ((entry) &= ~(GICH_LR_STATE_PENDING << R_GICH_LR0_State_SHIFT))
+#define GICH_LR_SET_ACTIVE(entry) \
+ ((entry) |= (GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT))
+#define GICH_LR_CLEAR_ACTIVE(entry) \
+ ((entry) &= ~(GICH_LR_STATE_ACTIVE << R_GICH_LR0_State_SHIFT))
+
/* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
* GICv2 and GICv2 with security extensions:
*/
@@ -239,4 +246,80 @@ static inline uint32_t *gic_get_lr_entry(GICState *s, int irq, int vcpu)
return NULL;
}
+static inline bool gic_test_group(GICState *s, int irq, int cpu)
+{
+ if (gic_is_vcpu(cpu)) {
+ uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
+ return GICH_LR_GROUP(*entry);
+ } else {
+ return GIC_DIST_TEST_GROUP(irq, 1 << cpu);
+ }
+}
+
+static inline void gic_clear_pending(GICState *s, int irq, int cpu)
+{
+ if (gic_is_vcpu(cpu)) {
+ uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
+ GICH_LR_CLEAR_PENDING(*entry);
+ } else {
+ /* Clear pending state for both level and edge triggered
+ * interrupts. (level triggered interrupts with an active line
+ * remain pending, see gic_test_pending)
+ */
+ GIC_DIST_CLEAR_PENDING(irq, GIC_DIST_TEST_MODEL(irq) ? ALL_CPU_MASK
+ : (1 << cpu));
+ }
+}
+
+static inline void gic_set_active(GICState *s, int irq, int cpu)
+{
+ if (gic_is_vcpu(cpu)) {
+ uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
+ GICH_LR_SET_ACTIVE(*entry);
+ } else {
+ GIC_DIST_SET_ACTIVE(irq, 1 << cpu);
+ }
+}
+
+static inline void gic_clear_active(GICState *s, int irq, int cpu)
+{
+ if (gic_is_vcpu(cpu)) {
+ uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
+ GICH_LR_CLEAR_ACTIVE(*entry);
+
+ if (GICH_LR_HW(*entry)) {
+ /* Hardware interrupt. We must forward the deactivation request to
+ * the distributor.
+ */
+ int phys_irq = GICH_LR_PHYS_ID(*entry);
+ int rcpu = gic_get_vcpu_real_id(cpu);
+
+ if (phys_irq < GIC_NR_SGIS || phys_irq >= GIC_MAXIRQ) {
+ /* UNPREDICTABLE behaviour, we choose to ignore the request */
+ return;
+ }
+
+ /* This is equivalent to a NS write to DIR on the physical CPU
+ * interface. Hence group0 interrupt deactivation is ignored if
+ * the GIC is secure.
+ */
+ if (!s->security_extn || GIC_DIST_TEST_GROUP(phys_irq, 1 << rcpu)) {
+ GIC_DIST_CLEAR_ACTIVE(phys_irq, 1 << rcpu);
+ }
+ }
+ } else {
+ GIC_DIST_CLEAR_ACTIVE(irq, 1 << cpu);
+ }
+}
+
+static inline int gic_get_priority(GICState *s, int irq, int cpu)
+{
+ if (gic_is_vcpu(cpu)) {
+ uint32_t *entry = gic_get_lr_entry(s, irq, cpu);
+ return GICH_LR_PRIORITY(*entry);
+ } else {
+ return GIC_DIST_GET_PRIORITY(irq, cpu);
+ }
+}
+
#endif /* QEMU_ARM_GIC_INTERNAL_H */
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio)
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (8 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:21 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq Luc Michel
` (10 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement virtualization extensions in gic_activate_irq() and
gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
gic_drop_prio().
When the current CPU is a vCPU:
- Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
counterparts,
- the vCPU APR is stored in the virtual interface, in h_apr.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 50 +++++++++++++++++++++++++++++++++++------------
1 file changed, 38 insertions(+), 12 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index ad241d12c2..60704cabbb 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -276,16 +276,23 @@ static void gic_activate_irq(GICState *s, int cpu, int irq)
* and update the running priority.
*/
int prio = gic_get_group_priority(s, cpu, irq);
- int preemption_level = prio >> (GIC_MIN_BPR + 1);
+ int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
+ int preemption_level = prio >> (min_bpr + 1);
int regno = preemption_level / 32;
int bitno = preemption_level % 32;
+ uint32_t *papr = NULL;
- if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
- s->nsapr[regno][cpu] |= (1 << bitno);
+ if (gic_is_vcpu(cpu)) {
+ assert(regno == 0);
+ papr = &s->h_apr[gic_get_vcpu_real_id(cpu)];
+ } else if (gic_has_groups(s) && gic_test_group(s, irq, cpu)) {
+ papr = &s->nsapr[regno][cpu];
} else {
- s->apr[regno][cpu] |= (1 << bitno);
+ papr = &s->apr[regno][cpu];
}
+ *papr |= (1 << bitno);
+
s->running_priority[cpu] = prio;
gic_set_active(s, irq, cpu);
}
@@ -296,6 +303,16 @@ static int gic_get_prio_from_apr_bits(GICState *s, int cpu)
* on the set bits in the Active Priority Registers.
*/
int i;
+
+ if (gic_is_vcpu(cpu)) {
+ uint32_t apr = s->h_apr[gic_get_vcpu_real_id(cpu)];
+ if (apr) {
+ return ctz32(apr) << (GIC_VIRT_MIN_BPR + 1);
+ } else {
+ return 0x100;
+ }
+ }
+
for (i = 0; i < GIC_NR_APRS; i++) {
uint32_t apr = s->apr[i][cpu] | s->nsapr[i][cpu];
if (!apr) {
@@ -324,16 +341,25 @@ static void gic_drop_prio(GICState *s, int cpu, int group)
* running priority will be wrong, so interrupts that should preempt
* might not do so, and interrupts that should not preempt might do so.
*/
- int i;
+ if (gic_is_vcpu(cpu)) {
+ int rcpu = gic_get_vcpu_real_id(cpu);
- for (i = 0; i < GIC_NR_APRS; i++) {
- uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
- if (!*papr) {
- continue;
+ if (s->h_apr[rcpu]) {
+ /* Clear lowest set bit */
+ s->h_apr[rcpu] &= s->h_apr[rcpu] - 1;
+ }
+ } else {
+ int i;
+
+ for (i = 0; i < GIC_NR_APRS; i++) {
+ uint32_t *papr = group ? &s->nsapr[i][cpu] : &s->apr[i][cpu];
+ if (!*papr) {
+ continue;
+ }
+ /* Clear lowest set bit */
+ *papr &= *papr - 1;
+ break;
}
- /* Clear lowest set bit */
- *papr &= *papr - 1;
- break;
}
s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (9 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Luc Michel
` (9 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement virtualization extensions in the gic_acknowledge_irq()
function. This function changes the state of the highest priority IRQ
from pending to active.
When the current CPU is a vCPU, modifying the state of an IRQ modifies
the corresponding LR entry. However if we clear the pending flag before
setting the active one, we lose track of the LR entry as it becomes
invalid. The next call to gic_get_lr_entry() will fail.
To overcome this issue, we call gic_activate_irq() before
gic_clear_pending(). This does not change the general behaviour of
gic_acknowledge_irq.
We also move the SGI case in gic_clear_pending_sgi() to enhance
code readability as the virtualization extensions support adds a if-else
level.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 52 ++++++++++++++++++++++++++++++-----------------
1 file changed, 33 insertions(+), 19 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 60704cabbb..be9e2594d9 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -365,17 +365,44 @@ static void gic_drop_prio(GICState *s, int cpu, int group)
s->running_priority[cpu] = gic_get_prio_from_apr_bits(s, cpu);
}
+static inline uint32_t gic_clear_pending_sgi(GICState *s, int irq, int cpu)
+{
+ int src;
+ uint32_t ret;
+
+ if (!gic_is_vcpu(cpu)) {
+ /* Lookup the source CPU for the SGI and clear this in the
+ * sgi_pending map. Return the src and clear the overall pending
+ * state on this CPU if the SGI is not pending from any CPUs.
+ */
+ assert(s->sgi_pending[irq][cpu] != 0);
+ src = ctz32(s->sgi_pending[irq][cpu]);
+ s->sgi_pending[irq][cpu] &= ~(1 << src);
+ if (s->sgi_pending[irq][cpu] == 0) {
+ gic_clear_pending(s, irq, cpu);
+ }
+ ret = irq | ((src & 0x7) << 10);
+ } else {
+ uint32_t *lr_entry = gic_get_lr_entry(s, irq, cpu);
+ src = GICH_LR_CPUID(*lr_entry);
+
+ gic_clear_pending(s, irq, cpu);
+ ret = irq | (src << 10);
+ }
+
+ return ret;
+}
+
uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
{
- int ret, irq, src;
- int cm = 1 << cpu;
+ int ret, irq;
/* gic_get_current_pending_irq() will return 1022 or 1023 appropriately
* for the case where this GIC supports grouping and the pending interrupt
* is in the wrong group.
*/
irq = gic_get_current_pending_irq(s, cpu, attrs);
- trace_gic_acknowledge_irq(cpu, irq);
+ trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq);
if (irq >= GIC_MAXIRQ) {
DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
@@ -387,6 +414,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
return 1023;
}
+ gic_activate_irq(s, cpu, irq);
+
if (s->revision == REV_11MPCORE) {
/* Clear pending flags for both level and edge triggered interrupts.
* Level triggered IRQs will be reasserted once they become inactive.
@@ -395,28 +424,13 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
ret = irq;
} else {
if (irq < GIC_NR_SGIS) {
- /* Lookup the source CPU for the SGI and clear this in the
- * sgi_pending map. Return the src and clear the overall pending
- * state on this CPU if the SGI is not pending from any CPUs.
- */
- assert(s->sgi_pending[irq][cpu] != 0);
- src = ctz32(s->sgi_pending[irq][cpu]);
- s->sgi_pending[irq][cpu] &= ~(1 << src);
- if (s->sgi_pending[irq][cpu] == 0) {
- gic_clear_pending(s, irq, cpu);
- }
- ret = irq | ((src & 0x7) << 10);
+ ret = gic_clear_pending_sgi(s, irq, cpu);
} else {
- /* Clear pending state for both level and edge triggered
- * interrupts. (level triggered interrupts with an active line
- * remain pending, see gic_test_pending)
- */
gic_clear_pending(s, irq, cpu);
ret = irq;
}
}
- gic_activate_irq(s, cpu, irq);
gic_update(s);
DPRINTF("ACK %d\n", irq);
return ret;
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq)
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (10 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 13:32 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) Luc Michel
` (8 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement virtualization extensions in the gic_deactivate_irq() and
gic_complete_irq() functions. When a guest tries to deactivat or end an
IRQ that does not exist in the LRs, the EOICount field of the virtual
interface HCR register is incremented by one, and the request is
ignored.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index be9e2594d9..50cbbfbe24 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -590,6 +590,15 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
return;
}
+ if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
+ /* This vIRQ does not have an LR entry which is either active or
+ * pending and active. Increment EOICount and ignore the write.
+ */
+ int rcpu = gic_get_vcpu_real_id(cpu);
+ s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
+ return;
+ }
+
if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
return;
@@ -604,6 +613,15 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
int group;
DPRINTF("EOI %d\n", irq);
+ if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
+ /* This vIRQ does not have an LR entry which is either active or
+ * pending and active. Increment EOICount and ignore the write.
+ */
+ int rcpu = gic_get_vcpu_real_id(cpu);
+ s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
+ return;
+ }
+
if (irq >= s->num_irq) {
/* This handles two cases:
* 1. If software writes the ID of a spurious interrupt [ie 1023]
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write)
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (11 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface Luc Michel
` (7 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement virtualization extensions in the gic_cpu_read() and
gic_cpu_write() functions. Those are the last bits missing to fully
support virtualization extensions in the CPU interface path.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 20 +++++++++++++++-----
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 50cbbfbe24..28ecf0c1fc 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1360,9 +1360,12 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{
int regno = (offset - 0xd0) / 4;
+ int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
- if (regno >= GIC_NR_APRS || s->revision != 2) {
+ if (regno >= nr_aprs || s->revision != 2) {
*data = 0;
+ } else if (gic_is_vcpu(cpu)) {
+ *data = s->h_apr[gic_get_vcpu_real_id(cpu)];
} else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
*data = gic_apr_ns_view(s, regno, cpu);
@@ -1376,7 +1379,7 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
int regno = (offset - 0xe0) / 4;
if (regno >= GIC_NR_APRS || s->revision != 2 || !gic_has_groups(s) ||
- gic_cpu_ns_access(s, cpu, attrs)) {
+ gic_cpu_ns_access(s, cpu, attrs) || gic_is_vcpu(cpu)) {
*data = 0;
} else {
*data = s->nsapr[regno][cpu];
@@ -1411,7 +1414,8 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR);
}
} else {
- s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR);
+ int min_bpr = gic_is_vcpu(cpu) ? GIC_VIRT_MIN_BPR : GIC_MIN_BPR;
+ s->bpr[cpu] = MAX(value & 0x7, min_bpr);
}
break;
case 0x10: /* End Of Interrupt */
@@ -1428,11 +1432,14 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
case 0xd0: case 0xd4: case 0xd8: case 0xdc:
{
int regno = (offset - 0xd0) / 4;
+ int nr_aprs = gic_is_vcpu(cpu) ? GIC_VIRT_NR_APRS : GIC_NR_APRS;
- if (regno >= GIC_NR_APRS || s->revision != 2) {
+ if (regno >= nr_aprs || s->revision != 2) {
return MEMTX_OK;
}
- if (gic_cpu_ns_access(s, cpu, attrs)) {
+ if (gic_is_vcpu(cpu)) {
+ s->h_apr[gic_get_vcpu_real_id(cpu)] = value;
+ } else if (gic_cpu_ns_access(s, cpu, attrs)) {
/* NS view of GICC_APR<n> is the top half of GIC_NSAPR<n> */
gic_apr_write_ns_view(s, regno, cpu, value);
} else {
@@ -1447,6 +1454,9 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
if (regno >= GIC_NR_APRS || s->revision != 2) {
return MEMTX_OK;
}
+ if (gic_is_vcpu(cpu)) {
+ return MEMTX_OK;
+ }
if (!gic_has_groups(s) || (gic_cpu_ns_access(s, cpu, attrs))) {
return MEMTX_OK;
}
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (12 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:26 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 15/20] intc/arm_gic: Implement the virtual interface registers Luc Michel
` (6 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
As for the CPU interface, we create a base region for the vCPU interface
that fetches the current vCPU id using the current_cpu global variable, and
one mirror region per vCPU which maps to that specific vCPU id. This is
required by the GIC architecture specification.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 37 +++++++++++++++++++++++++++++++++++--
1 file changed, 35 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 28ecf0c1fc..be44015c39 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1514,6 +1514,23 @@ static MemTxResult gic_do_cpu_write(void *opaque, hwaddr addr,
return gic_cpu_write(s, id, addr, value, attrs);
}
+static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs);
+}
+
+static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs);
+}
+
static const MemoryRegionOps gic_ops[2] = {
{
.read_with_attrs = gic_dist_read,
@@ -1533,6 +1550,19 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static const MemoryRegionOps gic_virt_ops[2] = {
+ {
+ .read_with_attrs = NULL,
+ .write_with_attrs = NULL,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ },
+ {
+ .read_with_attrs = gic_thisvcpu_read,
+ .write_with_attrs = gic_thisvcpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ }
+};
+
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
@@ -1554,8 +1584,11 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
return;
}
- /* This creates distributor and main CPU interface (s->cpuiomem[0]) */
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL);
+ /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if
+ * enabled, virtualization extensions related interfaces (main virtual
+ * interface (s->vifaceiomem[0]) and virtual CPU interface).
+ */
+ gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops);
/* Extra core-specific regions for the CPU interfaces. This is
* necessary for "franken-GIC" implementations, for example on
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 15/20] intc/arm_gic: Implement the virtual interface registers
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (13 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function Luc Michel
` (5 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement the read and write functions for the virtual interface of the
virtualization extensions in the GICv2.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 235 +++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 233 insertions(+), 2 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index be44015c39..d8e9cf0a3a 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -147,6 +147,24 @@ static void gic_update(GICState *s)
}
}
+/* Return true if this LR is empty, i.e. the corresponding bit
+ * in ELRSR is set.
+ */
+static inline bool gic_lr_entry_is_free(uint32_t entry)
+{
+ return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID)
+ && (GICH_LR_HW(entry) || !GICH_LR_EOI(entry));
+}
+
+/* Return true if this LR should trigger an EOI maintenance interrupt, i.e. the
+ * corrsponding bit in EISR is set.
+ */
+static inline bool gic_lr_entry_is_eoi(uint32_t entry)
+{
+ return (GICH_LR_STATE(entry) == GICH_LR_STATE_INVALID)
+ && !GICH_LR_HW(entry) && GICH_LR_EOI(entry);
+}
+
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
@@ -1531,6 +1549,200 @@ static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr,
return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs);
}
+static uint32_t gic_compute_eisr(GICState *s, int cpu, int lr_start)
+{
+ int lr_idx;
+ uint32_t ret = 0;
+
+ for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t *entry = &s->h_lr[lr_idx][cpu];
+ ret = deposit32(ret, lr_idx - lr_start, 1,
+ gic_lr_entry_is_eoi(*entry));
+ }
+
+ return ret;
+}
+
+static uint32_t gic_compute_elrsr(GICState *s, int cpu, int lr_start)
+{
+ int lr_idx;
+ uint32_t ret = 0;
+
+ for (lr_idx = lr_start; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t *entry = &s->h_lr[lr_idx][cpu];
+ ret = deposit32(ret, lr_idx - lr_start, 1,
+ gic_lr_entry_is_free(*entry));
+ }
+
+ return ret;
+}
+
+static void gic_vmcr_write(GICState *s, uint32_t value, MemTxAttrs attrs)
+{
+ int vcpu = gic_get_current_vcpu(s);
+ uint32_t ctlr;
+ uint32_t abpr;
+ uint32_t bpr;
+ uint32_t prio_mask;
+
+ ctlr = FIELD_EX32(value, GICH_VMCR, VMCCtlr);
+ abpr = FIELD_EX32(value, GICH_VMCR, VMABP);
+ bpr = FIELD_EX32(value, GICH_VMCR, VMBP);
+ prio_mask = FIELD_EX32(value, GICH_VMCR, VMPriMask) << 3;
+
+ gic_set_cpu_control(s, vcpu, ctlr, attrs);
+ s->abpr[vcpu] = MAX(abpr, GIC_VIRT_MIN_ABPR);
+ s->bpr[vcpu] = MAX(bpr, GIC_VIRT_MIN_BPR);
+ gic_set_priority_mask(s, vcpu, prio_mask, attrs);
+}
+
+static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr,
+ uint64_t *data, MemTxAttrs attrs)
+{
+ GICState *s = ARM_GIC(opaque);
+ int vcpu = cpu + GIC_NCPU;
+
+ switch (addr) {
+ case A_GICH_HCR: /* Hypervisor Control */
+ *data = s->h_hcr[cpu];
+ break;
+
+ case A_GICH_VTR: /* VGIC Type */
+ *data = FIELD_DP32(0, GICH_VTR, ListRegs, s->num_lrs - 1);
+ *data = FIELD_DP32(*data, GICH_VTR, PREbits,
+ GIC_VIRT_MAX_GROUP_PRIO_BITS - 1);
+ *data = FIELD_DP32(*data, GICH_VTR, PRIbits,
+ (7 - GIC_VIRT_MIN_BPR) - 1);
+ break;
+
+ case A_GICH_VMCR: /* Virtual Machine Control */
+ *data = FIELD_DP32(0, GICH_VMCR, VMCCtlr,
+ extract32(s->cpu_ctlr[vcpu], 0, 10));
+ *data = FIELD_DP32(*data, GICH_VMCR, VMABP, s->abpr[vcpu]);
+ *data = FIELD_DP32(*data, GICH_VMCR, VMBP, s->bpr[vcpu]);
+ *data = FIELD_DP32(*data, GICH_VMCR, VMPriMask,
+ extract32(s->priority_mask[vcpu], 3, 5));
+ break;
+
+ case A_GICH_MISR: /* Maintenance Interrupt Status */
+ *data = s->h_misr[cpu];
+ break;
+
+ case A_GICH_EISR0: /* End of Interrupt Status 0 and 1 */
+ case A_GICH_EISR1:
+ *data = gic_compute_eisr(s, cpu, (addr - A_GICH_EISR0) * 8);
+ break;
+
+ case A_GICH_ELRSR0: /* Empty List Status 0 and 1 */
+ case A_GICH_ELRSR1:
+ *data = gic_compute_elrsr(s, cpu, (addr - A_GICH_ELRSR0) * 8);
+ break;
+
+ case A_GICH_APR: /* Active Priorities */
+ *data = s->h_apr[cpu];
+ break;
+
+ case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */
+ {
+ int lr_idx = (addr - A_GICH_LR0) / 4;
+
+ if (lr_idx > s->num_lrs) {
+ *data = 0;
+ } else {
+ *data = s->h_lr[lr_idx][cpu];
+ }
+ break;
+ }
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "gic_hyp_read: Bad offset %" HWADDR_PRIx "\n", addr);
+ return MEMTX_OK;
+ }
+
+ return MEMTX_OK;
+}
+
+static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr,
+ uint64_t value, MemTxAttrs attrs)
+{
+ GICState *s = ARM_GIC(opaque);
+ int vcpu = cpu + GIC_NCPU;
+
+ switch (addr) {
+ case A_GICH_HCR: /* Hypervisor Control */
+ s->h_hcr[cpu] = value & GICH_HCR_MASK;
+ break;
+
+ case A_GICH_VMCR: /* Virtual Machine Control */
+ gic_vmcr_write(s, value, attrs);
+ break;
+
+ case A_GICH_APR: /* Active Priorities */
+ s->h_apr[cpu] = value;
+ s->running_priority[vcpu] = gic_get_prio_from_apr_bits(s, vcpu);
+ break;
+
+ case A_GICH_LR0 ... A_GICH_LR63: /* List Registers */
+ {
+ int lr_idx = (addr - A_GICH_LR0) / 4;
+
+ if (lr_idx > s->num_lrs) {
+ return MEMTX_OK;
+ }
+
+ s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK;
+ break;
+ }
+
+ default:
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "gic_hyp_write: Bad offset %" HWADDR_PRIx "\n", addr);
+ return MEMTX_OK;
+ }
+
+ return MEMTX_OK;
+}
+
+static MemTxResult gic_thiscpu_hyp_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_hyp_read(s, gic_get_current_cpu(s), addr, data, attrs);
+}
+
+static MemTxResult gic_thiscpu_hyp_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_hyp_write(s, gic_get_current_cpu(s), addr, value, attrs);
+}
+
+static MemTxResult gic_do_hyp_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICState **backref = (GICState **)opaque;
+ GICState *s = *backref;
+ int id = (backref - s->backref);
+
+ return gic_hyp_read(s, id, addr, data, attrs);
+}
+
+static MemTxResult gic_do_hyp_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ GICState **backref = (GICState **)opaque;
+ GICState *s = *backref;
+ int id = (backref - s->backref);
+
+ return gic_hyp_write(s, id + GIC_NCPU, addr, value, attrs);
+
+}
+
static const MemoryRegionOps gic_ops[2] = {
{
.read_with_attrs = gic_dist_read,
@@ -1552,8 +1764,8 @@ static const MemoryRegionOps gic_cpu_ops = {
static const MemoryRegionOps gic_virt_ops[2] = {
{
- .read_with_attrs = NULL,
- .write_with_attrs = NULL,
+ .read_with_attrs = gic_thiscpu_hyp_read,
+ .write_with_attrs = gic_thiscpu_hyp_write,
.endianness = DEVICE_NATIVE_ENDIAN,
},
{
@@ -1563,6 +1775,12 @@ static const MemoryRegionOps gic_virt_ops[2] = {
}
};
+static const MemoryRegionOps gic_viface_ops = {
+ .read_with_attrs = gic_do_hyp_read,
+ .write_with_attrs = gic_do_hyp_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
@@ -1604,6 +1822,19 @@ static void arm_gic_realize(DeviceState *dev, Error **errp)
&s->backref[i], "gic_cpu", 0x100);
sysbus_init_mmio(sbd, &s->cpuiomem[i+1]);
}
+
+ /* Extra core-specific regions for virtual interfaces. This is required by
+ * the GICv2 specification.
+ */
+ if (s->virt_extn) {
+ for (i = 0; i < s->num_cpu; i++) {
+ memory_region_init_io(&s->vifaceiomem[i + 1], OBJECT(s),
+ &gic_viface_ops, &s->backref[i],
+ "gic_viface", 0x1000);
+ sysbus_init_mmio(sbd, &s->vifaceiomem[i + 1]);
+ }
+ }
+
}
static void arm_gic_class_init(ObjectClass *klass, void *data)
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (14 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 15/20] intc/arm_gic: Implement the virtual interface registers Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-17 14:27 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 17/20] intc/arm_gic: Implement maintenance interrupt generation Luc Michel
` (4 subsequent siblings)
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add the gic_update_virt() function to update the vCPU interface states
and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
gic_update_internal() and generalizes it to handle both cases, with a
`virt' parameter to track whether we are updating the CPU or vCPU
interfaces.
The main difference between CPU and vCPU is the way we select the best
IRQ. This part has been split into the gic_get_best_(v)irq functions.
For the virt case, the LRs are iterated to find the best candidate.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/intc/arm_gic.c | 186 ++++++++++++++++++++++++++++++++++++----------
1 file changed, 146 insertions(+), 40 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index d8e9cf0a3a..85f1a03147 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -79,74 +79,149 @@ static inline bool gic_cpu_ns_access(GICState *s, int cpu, MemTxAttrs attrs)
return !gic_is_vcpu(cpu) && s->security_extn && !attrs.secure;
}
+static inline void gic_get_best_irq(GICState *s, int cpu,
+ int *best_irq, int *best_prio, int *group)
+{
+ int irq;
+ int cm = 1 << cpu;
+
+ *best_irq = 1023;
+ *best_prio = 0x100;
+
+ for (irq = 0; irq < s->num_irq; irq++) {
+ if (GIC_DIST_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) &&
+ (!GIC_DIST_TEST_ACTIVE(irq, cm)) &&
+ (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) {
+ if (GIC_DIST_GET_PRIORITY(irq, cpu) < *best_prio) {
+ *best_prio = GIC_DIST_GET_PRIORITY(irq, cpu);
+ *best_irq = irq;
+ }
+ }
+ }
+
+ if (*best_irq < 1023) {
+ *group = GIC_DIST_TEST_GROUP(*best_irq, cm);
+ }
+}
+
+static inline void gic_get_best_virq(GICState *s, int cpu,
+ int *best_irq, int *best_prio, int *group)
+{
+ int lr_idx = 0;
+
+ *best_irq = 1023;
+ *best_prio = 0x100;
+
+ for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t lr_entry = s->h_lr[lr_idx][cpu];
+ int state = GICH_LR_STATE(lr_entry);
+
+ if (state == GICH_LR_STATE_PENDING) {
+ int prio = GICH_LR_PRIORITY(lr_entry);
+
+ if (prio < *best_prio) {
+ *best_prio = prio;
+ *best_irq = GICH_LR_VIRT_ID(lr_entry);
+ *group = GICH_LR_GROUP(lr_entry);
+ }
+ }
+ }
+}
+
+/* Return true if IRQ signaling is enabled for the given cpu and at least one
+ * of the given groups:
+ * - in the non-virt case, the distributor must be enabled for one of the
+ * given groups
+ * - in the virt case, the virtual interface must be enabled.
+ * - in all cases, the (v)CPU interface must be enabled for one of the given
+ * groups.
+ */
+static inline bool gic_irq_signaling_enabled(GICState *s, int cpu, bool virt,
+ int group_mask)
+{
+ if (!virt && !(s->ctlr & group_mask)) {
+ return false;
+ }
+
+ if (virt && !(s->h_hcr[cpu] & R_GICH_HCR_EN_MASK)) {
+ return false;
+ }
+
+ if (!(s->cpu_ctlr[cpu] & group_mask)) {
+ return false;
+ }
+
+ return true;
+}
+
/* TODO: Many places that call this routine could be optimized. */
/* Update interrupt status after enabled or pending bits have been changed. */
-static void gic_update(GICState *s)
+static inline void gic_update_internal(GICState *s, bool virt)
{
int best_irq;
int best_prio;
- int irq;
int irq_level, fiq_level;
- int cpu;
- int cm;
+ int cpu, cpu_iface;
+ int group = 0;
+ qemu_irq *irq_lines = virt ? s->parent_virq : s->parent_irq;
+ qemu_irq *fiq_lines = virt ? s->parent_vfiq : s->parent_fiq;
for (cpu = 0; cpu < s->num_cpu; cpu++) {
- cm = 1 << cpu;
- s->current_pending[cpu] = 1023;
- if (!(s->ctlr & (GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1))
- || !(s->cpu_ctlr[cpu] & (GICC_CTLR_EN_GRP0 | GICC_CTLR_EN_GRP1))) {
- qemu_irq_lower(s->parent_irq[cpu]);
- qemu_irq_lower(s->parent_fiq[cpu]);
+ cpu_iface = virt ? (cpu + GIC_NCPU) : cpu;
+
+ s->current_pending[cpu_iface] = 1023;
+ if (!gic_irq_signaling_enabled(s, cpu, virt,
+ GICD_CTLR_EN_GRP0 | GICD_CTLR_EN_GRP1)) {
+ qemu_irq_lower(irq_lines[cpu]);
+ qemu_irq_lower(fiq_lines[cpu]);
continue;
}
- best_prio = 0x100;
- best_irq = 1023;
- for (irq = 0; irq < s->num_irq; irq++) {
- if (GIC_DIST_TEST_ENABLED(irq, cm) &&
- gic_test_pending(s, irq, cm) &&
- (!GIC_DIST_TEST_ACTIVE(irq, cm)) &&
- (irq < GIC_INTERNAL || GIC_DIST_TARGET(irq) & cm)) {
- if (GIC_DIST_GET_PRIORITY(irq, cpu) < best_prio) {
- best_prio = GIC_DIST_GET_PRIORITY(irq, cpu);
- best_irq = irq;
- }
- }
+
+ if (virt) {
+ gic_get_best_virq(s, cpu, &best_irq, &best_prio, &group);
+ } else {
+ gic_get_best_irq(s, cpu, &best_irq, &best_prio, &group);
}
if (best_irq != 1023) {
trace_gic_update_bestirq(cpu, best_irq, best_prio,
- s->priority_mask[cpu], s->running_priority[cpu]);
+ s->priority_mask[cpu_iface], s->running_priority[cpu_iface]);
}
irq_level = fiq_level = 0;
- if (best_prio < s->priority_mask[cpu]) {
- s->current_pending[cpu] = best_irq;
- if (best_prio < s->running_priority[cpu]) {
- int group = GIC_DIST_TEST_GROUP(best_irq, cm);
-
- if (extract32(s->ctlr, group, 1) &&
- extract32(s->cpu_ctlr[cpu], group, 1)) {
- if (group == 0 && s->cpu_ctlr[cpu] & GICC_CTLR_FIQ_EN) {
+ if (best_prio < s->priority_mask[cpu_iface]) {
+ s->current_pending[cpu_iface] = best_irq;
+ if (best_prio < s->running_priority[cpu_iface]) {
+ if (gic_irq_signaling_enabled(s, cpu, virt, 1 << group)) {
+ if (group == 0 &&
+ s->cpu_ctlr[cpu_iface] & GICC_CTLR_FIQ_EN) {
DPRINTF("Raised pending FIQ %d (cpu %d)\n",
- best_irq, cpu);
+ best_irq, cpu_iface);
fiq_level = 1;
- trace_gic_update_set_irq(cpu, "fiq", fiq_level);
+ trace_gic_update_set_irq(cpu, virt ? "vfiq" : "fiq",
+ fiq_level);
} else {
DPRINTF("Raised pending IRQ %d (cpu %d)\n",
- best_irq, cpu);
+ best_irq, cpu_iface);
irq_level = 1;
- trace_gic_update_set_irq(cpu, "irq", irq_level);
+ trace_gic_update_set_irq(cpu, virt ? "virq" : "irq",
+ irq_level);
}
}
}
}
- qemu_set_irq(s->parent_irq[cpu], irq_level);
- qemu_set_irq(s->parent_fiq[cpu], fiq_level);
+ qemu_set_irq(irq_lines[cpu], irq_level);
+ qemu_set_irq(fiq_lines[cpu], fiq_level);
}
}
+static void gic_update(GICState *s)
+{
+ gic_update_internal(s, false);
+}
+
/* Return true if this LR is empty, i.e. the corresponding bit
* in ELRSR is set.
*/
@@ -165,6 +240,11 @@ static inline bool gic_lr_entry_is_eoi(uint32_t entry)
&& !GICH_LR_HW(entry) && GICH_LR_EOI(entry);
}
+static void gic_update_virt(GICState *s)
+{
+ gic_update_internal(s, true);
+}
+
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
int cm, int target)
{
@@ -449,7 +529,11 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
}
}
- gic_update(s);
+ if (gic_is_vcpu(cpu)) {
+ gic_update_virt(s);
+ } else {
+ gic_update(s);
+ }
DPRINTF("ACK %d\n", irq);
return ret;
}
@@ -614,6 +698,11 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
*/
int rcpu = gic_get_vcpu_real_id(cpu);
s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
+
+ /* Update the virtual interface in case a maintenance interrupt should
+ * be raised.
+ */
+ gic_update_virt(s);
return;
}
@@ -637,6 +726,11 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
*/
int rcpu = gic_get_vcpu_real_id(cpu);
s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
+
+ /* Update the virtual interface in case a maintenance interrupt should
+ * be raised.
+ */
+ gic_update_virt(s);
return;
}
@@ -684,7 +778,12 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
if (!gic_eoi_split(s, cpu, attrs)) {
gic_clear_active(s, irq, cpu);
}
- gic_update(s);
+
+ if (gic_is_vcpu(cpu)) {
+ gic_update_virt(s);
+ } else {
+ gic_update(s);
+ }
}
static uint32_t gic_dist_readb(void *opaque, hwaddr offset, MemTxAttrs attrs)
@@ -1490,7 +1589,13 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
"gic_cpu_write: Bad offset %x\n", (int)offset);
return MEMTX_OK;
}
- gic_update(s);
+
+ if (gic_is_vcpu(cpu)) {
+ gic_update_virt(s);
+ } else {
+ gic_update(s);
+ }
+
return MEMTX_OK;
}
@@ -1701,6 +1806,7 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr,
return MEMTX_OK;
}
+ gic_update_virt(s);
return MEMTX_OK;
}
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 17/20] intc/arm_gic: Implement maintenance interrupt generation
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (15 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 18/20] intc/arm_gic: Improve traces Luc Michel
` (3 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Implement the maintenance interrupt generation that is part of the GICv2
virtualization extensions.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 97 +++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 97 insertions(+)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 85f1a03147..4155fbe667 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -240,9 +240,106 @@ static inline bool gic_lr_entry_is_eoi(uint32_t entry)
&& !GICH_LR_HW(entry) && GICH_LR_EOI(entry);
}
+static inline void gic_extract_lr_info(GICState *s, int cpu,
+ int *num_eoi, int *num_valid, int *num_pending)
+{
+ int lr_idx;
+
+ *num_eoi = 0;
+ *num_valid = 0;
+ *num_pending = 0;
+
+ for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
+ uint32_t *entry = &s->h_lr[lr_idx][cpu];
+
+ if (gic_lr_entry_is_eoi(*entry)) {
+ (*num_eoi)++;
+ }
+
+ if (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID) {
+ (*num_valid)++;
+ }
+
+ if (GICH_LR_STATE(*entry) == GICH_LR_STATE_PENDING) {
+ (*num_pending)++;
+ }
+ }
+}
+
+static void gic_compute_misr(GICState *s, int cpu)
+{
+ uint32_t value = 0;
+ int vcpu = cpu + GIC_NCPU;
+
+ int num_eoi, num_valid, num_pending;
+
+ gic_extract_lr_info(s, cpu, &num_eoi, &num_valid, &num_pending);
+
+ /* EOI */
+ if (num_eoi) {
+ value |= R_GICH_MISR_EOI_MASK;
+ }
+
+ /* U: true if only 0 or 1 LR entry is valid */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_UIE_MASK) && (num_valid < 2)) {
+ value |= R_GICH_MISR_U_MASK;
+ }
+
+ /* LRENP: EOICount is not 0 */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_LRENPIE_MASK) &&
+ ((s->h_hcr[cpu] & R_GICH_HCR_EOICount_MASK) != 0)) {
+ value |= R_GICH_MISR_LRENP_MASK;
+ }
+
+ /* NP: no pending interrupts */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_NPIE_MASK) && (num_pending == 0)) {
+ value |= R_GICH_MISR_NP_MASK;
+ }
+
+ /* VGrp0E: group0 virq signaling enabled */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0EIE_MASK) &&
+ (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) {
+ value |= R_GICH_MISR_VGrp0E_MASK;
+ }
+
+ /* VGrp0D: group0 virq signaling disabled */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP0DIE_MASK) &&
+ !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP0)) {
+ value |= R_GICH_MISR_VGrp0D_MASK;
+ }
+
+ /* VGrp1E: group1 virq signaling enabled */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1EIE_MASK) &&
+ (s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) {
+ value |= R_GICH_MISR_VGrp1E_MASK;
+ }
+
+ /* VGrp1D: group1 virq signaling disabled */
+ if ((s->h_hcr[cpu] & R_GICH_HCR_VGRP1DIE_MASK) &&
+ !(s->cpu_ctlr[vcpu] & GICC_CTLR_EN_GRP1)) {
+ value |= R_GICH_MISR_VGrp1D_MASK;
+ }
+
+ s->h_misr[cpu] = value;
+}
+
+static void gic_update_maintenance(GICState *s)
+{
+ int cpu = 0;
+ int maint_level;
+
+ for (cpu = 0; cpu < s->num_cpu; cpu++) {
+ gic_compute_misr(s, cpu);
+ maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu];
+
+ qemu_set_irq(s->maintenance_irq[cpu], maint_level);
+ }
+}
+
static void gic_update_virt(GICState *s)
{
gic_update_internal(s, true);
+ gic_update_maintenance(s);
}
static void gic_set_irq_11mpcore(GICState *s, int irq, int level,
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 18/20] intc/arm_gic: Improve traces
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (16 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 17/20] intc/arm_gic: Implement maintenance interrupt generation Luc Michel
@ 2018-07-14 17:15 ` Luc Michel
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Luc Michel
` (2 subsequent siblings)
20 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:15 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add some traces to the ARM GIC to catch register accesses (distributor,
(v)cpu interface and virtual interface), and to take into account
virtualization extensions (print `vcpu` instead of `cpu` when needed).
Also add some virtualization extensions specific traces: LR updating
and maintenance IRQ generation.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gic.c | 31 +++++++++++++++++++++++++------
hw/intc/trace-events | 12 ++++++++++--
2 files changed, 35 insertions(+), 8 deletions(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 4155fbe667..bb06c90cfc 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -184,8 +184,10 @@ static inline void gic_update_internal(GICState *s, bool virt)
}
if (best_irq != 1023) {
- trace_gic_update_bestirq(cpu, best_irq, best_prio,
- s->priority_mask[cpu_iface], s->running_priority[cpu_iface]);
+ trace_gic_update_bestirq(virt ? "vcpu" : "cpu", cpu,
+ best_irq, best_prio,
+ s->priority_mask[cpu_iface],
+ s->running_priority[cpu_iface]);
}
irq_level = fiq_level = 0;
@@ -332,6 +334,7 @@ static void gic_update_maintenance(GICState *s)
gic_compute_misr(s, cpu);
maint_level = (s->h_hcr[cpu] & R_GICH_HCR_EN_MASK) && s->h_misr[cpu];
+ trace_gic_update_maintenance_irq(cpu, maint_level);
qemu_set_irq(s->maintenance_irq[cpu], maint_level);
}
}
@@ -597,7 +600,8 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs)
* is in the wrong group.
*/
irq = gic_get_current_pending_irq(s, cpu, attrs);
- trace_gic_acknowledge_irq(gic_get_vcpu_real_id(cpu), irq);
+ trace_gic_acknowledge_irq(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
+ gic_get_vcpu_real_id(cpu), irq);
if (irq >= GIC_MAXIRQ) {
DPRINTF("ACK, no pending interrupt or it is hidden: %d\n", irq);
@@ -1098,20 +1102,23 @@ static MemTxResult gic_dist_read(void *opaque, hwaddr offset, uint64_t *data,
switch (size) {
case 1:
*data = gic_dist_readb(opaque, offset, attrs);
- return MEMTX_OK;
+ break;
case 2:
*data = gic_dist_readb(opaque, offset, attrs);
*data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
- return MEMTX_OK;
+ break;
case 4:
*data = gic_dist_readb(opaque, offset, attrs);
*data |= gic_dist_readb(opaque, offset + 1, attrs) << 8;
*data |= gic_dist_readb(opaque, offset + 2, attrs) << 16;
*data |= gic_dist_readb(opaque, offset + 3, attrs) << 24;
- return MEMTX_OK;
+ break;
default:
return MEMTX_ERROR;
}
+
+ trace_gic_dist_read(offset, size, *data);
+ return MEMTX_OK;
}
static void gic_dist_writeb(void *opaque, hwaddr offset,
@@ -1450,6 +1457,8 @@ static void gic_dist_writel(void *opaque, hwaddr offset,
static MemTxResult gic_dist_write(void *opaque, hwaddr offset, uint64_t data,
unsigned size, MemTxAttrs attrs)
{
+ trace_gic_dist_write(offset, size, data);
+
switch (size) {
case 1:
gic_dist_writeb(opaque, offset, data, attrs);
@@ -1606,12 +1615,18 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset,
*data = 0;
break;
}
+
+ trace_gic_cpu_read(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
+ gic_get_vcpu_real_id(cpu), offset, *data);
return MEMTX_OK;
}
static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset,
uint32_t value, MemTxAttrs attrs)
{
+ trace_gic_cpu_write(gic_is_vcpu(cpu) ? "vcpu" : "cpu",
+ gic_get_vcpu_real_id(cpu), offset, value);
+
switch (offset) {
case 0x00: /* Control */
gic_set_cpu_control(s, cpu, value, attrs);
@@ -1862,6 +1877,7 @@ static MemTxResult gic_hyp_read(void *opaque, int cpu, hwaddr addr,
return MEMTX_OK;
}
+ trace_gic_hyp_read(addr, *data);
return MEMTX_OK;
}
@@ -1871,6 +1887,8 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr,
GICState *s = ARM_GIC(opaque);
int vcpu = cpu + GIC_NCPU;
+ trace_gic_hyp_write(addr, value);
+
switch (addr) {
case A_GICH_HCR: /* Hypervisor Control */
s->h_hcr[cpu] = value & GICH_HCR_MASK;
@@ -1894,6 +1912,7 @@ static MemTxResult gic_hyp_write(void *opaque, int cpu, hwaddr addr,
}
s->h_lr[lr_idx][cpu] = value & GICH_LR_MASK;
+ trace_gic_lr_entry(cpu, lr_idx, s->h_lr[lr_idx][cpu]);
break;
}
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 55e8c2570c..47fa4ad5c1 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -92,9 +92,17 @@ aspeed_vic_write(uint64_t offset, unsigned size, uint32_t data) "To 0x%" PRIx64
gic_enable_irq(int irq) "irq %d enabled"
gic_disable_irq(int irq) "irq %d disabled"
gic_set_irq(int irq, int level, int cpumask, int target) "irq %d level %d cpumask 0x%x target 0x%x"
-gic_update_bestirq(int cpu, int irq, int prio, int priority_mask, int running_priority) "cpu %d irq %d priority %d cpu priority mask %d cpu running priority %d"
+gic_update_bestirq(const char *s, int cpu, int irq, int prio, int priority_mask, int running_priority) "%s %d irq %d priority %d cpu priority mask %d cpu running priority %d"
gic_update_set_irq(int cpu, const char *name, int level) "cpu[%d]: %s = %d"
-gic_acknowledge_irq(int cpu, int irq) "cpu %d acknowledged irq %d"
+gic_acknowledge_irq(const char *s, int cpu, int irq) "%s %d acknowledged irq %d"
+gic_cpu_write(const char *s, int cpu, int addr, uint32_t val) "%s %d iface write at 0x%08x 0x%08" PRIx32
+gic_cpu_read(const char *s, int cpu, int addr, uint32_t val) "%s %d iface read at 0x%08x: 0x%08" PRIx32
+gic_hyp_read(int addr, uint32_t val) "hyp read at 0x%08x: 0x%08" PRIx32
+gic_hyp_write(int addr, uint32_t val) "hyp write at 0x%08x: 0x%08" PRIx32
+gic_dist_read(int addr, unsigned int size, uint32_t val) "dist read at 0x%08x size %u: 0x%08" PRIx32
+gic_dist_write(int addr, unsigned int size, uint32_t val) "dist write at 0x%08x size %u: 0x%08" PRIx32
+gic_lr_entry(int cpu, int entry, uint32_t val) "cpu %d: new lr entry %d: 0x%08" PRIx32
+gic_update_maintenance_irq(int cpu, int val) "cpu %d: maintenance = %d"
# hw/intc/arm_gicv3_cpuif.c
gicv3_icc_pmr_read(uint32_t cpu, uint64_t val) "GICv3 ICC_PMR read cpu 0x%x value 0x%" PRIx64
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (17 preceding siblings ...)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 18/20] intc/arm_gic: Improve traces Luc Michel
@ 2018-07-14 17:16 ` Luc Michel
2018-07-14 17:42 ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions Luc Michel
2018-07-17 14:33 ` [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Peter Maydell
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:16 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
This commit improve the way the GIC is realized and connected in the
ZynqMP SoC. The security extensions are enabled only if requested in the
machine state. The same goes for the virtualization extensions.
All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also
added (HYP and SEC timers).
The GIC maintenance IRQs are back-wired to the correct GIC PPIs.
Finally, the MMIO mappings are reworked to take into account the ZynqMP
specifics. The GIC (v)CPU interface is aliased 16 times:
* for the first 0x1000 bytes from 0xf9010000 to 0xf901f000
* for the second 0x1000 bytes from 0xf9020000 to 0xf902f000
Mappings of the virtual interface and virtual CPU interface are mapped
only when virtualization extensions are requested. The
XlnxZynqMPGICRegion struct has been enhanced to be able to catch all
this information.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/arm/xlnx-zynqmp.c | 92 ++++++++++++++++++++++++++++++++----
include/hw/arm/xlnx-zynqmp.h | 4 +-
2 files changed, 86 insertions(+), 10 deletions(-)
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 29df35fb75..42c29b8d06 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -29,12 +29,17 @@
#define ARM_PHYS_TIMER_PPI 30
#define ARM_VIRT_TIMER_PPI 27
+#define ARM_HYP_TIMER_PPI 26
+#define ARM_SEC_TIMER_PPI 29
+#define GIC_MAINTENANCE_PPI 25
#define GEM_REVISION 0x40070106
#define GIC_BASE_ADDR 0xf9000000
#define GIC_DIST_ADDR 0xf9010000
#define GIC_CPU_ADDR 0xf9020000
+#define GIC_VIFACE_ADDR 0xf9040000
+#define GIC_VCPU_ADDR 0xf9060000
#define SATA_INTR 133
#define SATA_ADDR 0xFD0C0000
@@ -111,11 +116,54 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
typedef struct XlnxZynqMPGICRegion {
int region_index;
uint32_t address;
+ uint32_t offset;
+ bool virt;
} XlnxZynqMPGICRegion;
static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
- { .region_index = 0, .address = GIC_DIST_ADDR, },
- { .region_index = 1, .address = GIC_CPU_ADDR, },
+ /* Distributor */
+ {
+ .region_index = 0,
+ .address = GIC_DIST_ADDR,
+ .offset = 0,
+ .virt = false
+ },
+
+ /* CPU interface */
+ {
+ .region_index = 1,
+ .address = GIC_CPU_ADDR,
+ .offset = 0,
+ .virt = false
+ },
+ {
+ .region_index = 1,
+ .address = GIC_CPU_ADDR + 0x10000,
+ .offset = 0x1000,
+ .virt = false
+ },
+
+ /* Virtual interface */
+ {
+ .region_index = 2,
+ .address = GIC_VIFACE_ADDR,
+ .offset = 0,
+ .virt = true
+ },
+
+ /* Virtual CPU interface */
+ {
+ .region_index = 3,
+ .address = GIC_VCPU_ADDR,
+ .offset = 0,
+ .virt = true
+ },
+ {
+ .region_index = 3,
+ .address = GIC_VCPU_ADDR + 0x10000,
+ .offset = 0x1000,
+ .virt = true
+ },
};
static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
@@ -286,6 +334,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
+ qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
+ qdev_prop_set_bit(DEVICE(&s->gic),
+ "has-virtualization-extensions", s->virt);
/* Realize APUs before realizing the GIC. KVM requires this. */
for (i = 0; i < num_apus; i++) {
@@ -330,19 +381,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
- MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
+ MemoryRegion *mr;
uint32_t addr = r->address;
int j;
- sysbus_mmio_map(gic, r->region_index, addr);
+ if (r->virt && !s->virt) {
+ continue;
+ }
+ mr = sysbus_mmio_get_region(gic, r->region_index);
for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
MemoryRegion *alias = &s->gic_mr[i][j];
- addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
- 0, XLNX_ZYNQMP_GIC_REGION_SIZE);
+ r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
memory_region_add_subregion(system_memory, addr, alias);
+
+ addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
}
}
@@ -352,12 +407,33 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
ARM_CPU_IRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
+ qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
+ ARM_CPU_FIQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
+ qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
+ ARM_CPU_VIRQ));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
+ qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
+ ARM_CPU_VFIQ));
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
irq = qdev_get_gpio_in(DEVICE(&s->gic),
arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
- qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
+ qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
+
+ if (s->virt) {
+ irq = qdev_get_gpio_in(DEVICE(&s->gic),
+ arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
+ }
}
if (s->has_rpu) {
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 82b6ec2486..98f925ab84 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -53,7 +53,7 @@
#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
#define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
-#define XLNX_ZYNQMP_GIC_REGIONS 2
+#define XLNX_ZYNQMP_GIC_REGIONS 6
/* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
* and under-decodes the 64k region. This mirrors the 4k regions to every 4k
@@ -62,7 +62,7 @@
*/
#define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
-#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
+#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
#define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (18 preceding siblings ...)
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Luc Michel
@ 2018-07-14 17:16 ` Luc Michel
2018-07-17 14:29 ` Peter Maydell
2018-07-17 14:33 ` [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Peter Maydell
20 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-14 17:16 UTC (permalink / raw)
To: qemu-devel
Cc: Luc Michel, qemu-arm, Peter Maydell, saipava, edgari,
mark.burton, Jan Kiszka
Add support for GICv2 virtualization extensions by mapping the necessary
I/O regions and connecting the maintenance IRQ lines.
Declare those additions in the device tree and in the ACPI tables.
Signed-off-by: Luc Michel <luc.michel@greensocs.com>
---
hw/arm/virt-acpi-build.c | 6 +++--
hw/arm/virt.c | 52 +++++++++++++++++++++++++++++++++-------
include/hw/arm/virt.h | 4 +++-
3 files changed, 50 insertions(+), 12 deletions(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 6ea47e2588..ce31abd62c 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -659,6 +659,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
gicc->length = sizeof(*gicc);
if (vms->gic_version == 2) {
gicc->base_address = cpu_to_le64(memmap[VIRT_GIC_CPU].base);
+ gicc->gich_base_address = cpu_to_le64(memmap[VIRT_GIC_HYP].base);
+ gicc->gicv_base_address = cpu_to_le64(memmap[VIRT_GIC_VCPU].base);
}
gicc->cpu_interface_number = cpu_to_le32(i);
gicc->arm_mpidr = cpu_to_le64(armcpu->mp_affinity);
@@ -668,8 +670,8 @@ build_madt(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms)
if (arm_feature(&armcpu->env, ARM_FEATURE_PMU)) {
gicc->performance_interrupt = cpu_to_le32(PPI(VIRTUAL_PMU_IRQ));
}
- if (vms->virt && vms->gic_version == 3) {
- gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GICV3_MAINT_IRQ));
+ if (vms->virt) {
+ gicc->vgic_interrupt = cpu_to_le32(PPI(ARCH_GIC_MAINT_IRQ));
}
}
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index 281ddcdf6e..0807be985c 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -131,6 +131,8 @@ static const MemMapEntry a15memmap[] = {
[VIRT_GIC_DIST] = { 0x08000000, 0x00010000 },
[VIRT_GIC_CPU] = { 0x08010000, 0x00010000 },
[VIRT_GIC_V2M] = { 0x08020000, 0x00001000 },
+ [VIRT_GIC_HYP] = { 0x08030000, 0x00010000 },
+ [VIRT_GIC_VCPU] = { 0x08040000, 0x00010000 },
/* The space in between here is reserved for GICv3 CPU/vCPU/HYP */
[VIRT_GIC_ITS] = { 0x08080000, 0x00020000 },
/* This redistributor space allows up to 2*64kB*123 CPUs */
@@ -440,18 +442,33 @@ static void fdt_add_gic_node(VirtMachineState *vms)
if (vms->virt) {
qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, ARCH_GICV3_MAINT_IRQ,
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
} else {
/* 'cortex-a15-gic' means 'GIC v2' */
qemu_fdt_setprop_string(vms->fdt, nodename, "compatible",
"arm,cortex-a15-gic");
- qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
- 2, vms->memmap[VIRT_GIC_DIST].base,
- 2, vms->memmap[VIRT_GIC_DIST].size,
- 2, vms->memmap[VIRT_GIC_CPU].base,
- 2, vms->memmap[VIRT_GIC_CPU].size);
+ if (!vms->virt) {
+ qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
+ 2, vms->memmap[VIRT_GIC_DIST].base,
+ 2, vms->memmap[VIRT_GIC_DIST].size,
+ 2, vms->memmap[VIRT_GIC_CPU].base,
+ 2, vms->memmap[VIRT_GIC_CPU].size);
+ } else {
+ qemu_fdt_setprop_sized_cells(vms->fdt, nodename, "reg",
+ 2, vms->memmap[VIRT_GIC_DIST].base,
+ 2, vms->memmap[VIRT_GIC_DIST].size,
+ 2, vms->memmap[VIRT_GIC_CPU].base,
+ 2, vms->memmap[VIRT_GIC_CPU].size,
+ 2, vms->memmap[VIRT_GIC_HYP].base,
+ 2, vms->memmap[VIRT_GIC_HYP].size,
+ 2, vms->memmap[VIRT_GIC_VCPU].base,
+ 2, vms->memmap[VIRT_GIC_VCPU].size);
+ qemu_fdt_setprop_cells(vms->fdt, nodename, "interrupts",
+ GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
+ GIC_FDT_IRQ_FLAGS_LEVEL_HI);
+ }
}
qemu_fdt_setprop_cell(vms->fdt, nodename, "phandle", vms->gic_phandle);
@@ -573,6 +590,11 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
qdev_prop_set_uint32(gicdev, "redist-region-count[1]",
MIN(smp_cpus - redist0_count, redist1_capacity));
}
+ } else {
+ if (!kvm_irqchip_in_kernel()) {
+ qdev_prop_set_bit(gicdev, "has-virtualization-extensions",
+ vms->virt);
+ }
}
qdev_init_nofail(gicdev);
gicbusdev = SYS_BUS_DEVICE(gicdev);
@@ -584,6 +606,10 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
}
} else {
sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_CPU].base);
+ if (vms->virt) {
+ sysbus_mmio_map(gicbusdev, 2, vms->memmap[VIRT_GIC_HYP].base);
+ sysbus_mmio_map(gicbusdev, 3, vms->memmap[VIRT_GIC_VCPU].base);
+ }
}
/* Wire the outputs from each CPU's generic timer and the GICv3
@@ -610,9 +636,17 @@ static void create_gic(VirtMachineState *vms, qemu_irq *pic)
ppibase + timer_irq[irq]));
}
- qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt", 0,
- qdev_get_gpio_in(gicdev, ppibase
- + ARCH_GICV3_MAINT_IRQ));
+ if (type == 3) {
+ qemu_irq irq = qdev_get_gpio_in(gicdev,
+ ppibase + ARCH_GIC_MAINT_IRQ);
+ qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interrupt",
+ 0, irq);
+ } else if (vms->virt) {
+ qemu_irq irq = qdev_get_gpio_in(gicdev,
+ ppibase + ARCH_GIC_MAINT_IRQ);
+ sysbus_connect_irq(gicbusdev, i + 4 * smp_cpus, irq);
+ }
+
qdev_connect_gpio_out_named(cpudev, "pmu-interrupt", 0,
qdev_get_gpio_in(gicdev, ppibase
+ VIRTUAL_PMU_IRQ));
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
index 9a870ccb6a..4cc57a7ef6 100644
--- a/include/hw/arm/virt.h
+++ b/include/hw/arm/virt.h
@@ -42,7 +42,7 @@
#define NUM_VIRTIO_TRANSPORTS 32
#define NUM_SMMU_IRQS 4
-#define ARCH_GICV3_MAINT_IRQ 9
+#define ARCH_GIC_MAINT_IRQ 9
#define ARCH_TIMER_VIRT_IRQ 11
#define ARCH_TIMER_S_EL1_IRQ 13
@@ -60,6 +60,8 @@ enum {
VIRT_GIC_DIST,
VIRT_GIC_CPU,
VIRT_GIC_V2M,
+ VIRT_GIC_HYP,
+ VIRT_GIC_VCPU,
VIRT_GIC_ITS,
VIRT_GIC_REDIST,
VIRT_GIC_REDIST2,
--
2.18.0
^ permalink raw reply related [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [Qemu-arm] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Luc Michel
@ 2018-07-14 17:42 ` Edgar E. Iglesias
0 siblings, 0 replies; 34+ messages in thread
From: Edgar E. Iglesias @ 2018-07-14 17:42 UTC (permalink / raw)
To: Luc Michel
Cc: qemu-devel, Peter Maydell, mark.burton, saipava, edgari,
qemu-arm, Jan Kiszka
On Sat, Jul 14, 2018 at 07:16:00PM +0200, Luc Michel wrote:
> This commit improve the way the GIC is realized and connected in the
> ZynqMP SoC. The security extensions are enabled only if requested in the
> machine state. The same goes for the virtualization extensions.
>
> All the GIC to APU CPU(s) IRQ lines are now connected, including FIQ,
> vIRQ and vFIQ. The missing CPU to GIC timers IRQ connections are also
> added (HYP and SEC timers).
>
> The GIC maintenance IRQs are back-wired to the correct GIC PPIs.
>
> Finally, the MMIO mappings are reworked to take into account the ZynqMP
> specifics. The GIC (v)CPU interface is aliased 16 times:
> * for the first 0x1000 bytes from 0xf9010000 to 0xf901f000
> * for the second 0x1000 bytes from 0xf9020000 to 0xf902f000
> Mappings of the virtual interface and virtual CPU interface are mapped
> only when virtualization extensions are requested. The
> XlnxZynqMPGICRegion struct has been enhanced to be able to catch all
> this information.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Looks good to me!
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
> ---
> hw/arm/xlnx-zynqmp.c | 92 ++++++++++++++++++++++++++++++++----
> include/hw/arm/xlnx-zynqmp.h | 4 +-
> 2 files changed, 86 insertions(+), 10 deletions(-)
>
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 29df35fb75..42c29b8d06 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -29,12 +29,17 @@
>
> #define ARM_PHYS_TIMER_PPI 30
> #define ARM_VIRT_TIMER_PPI 27
> +#define ARM_HYP_TIMER_PPI 26
> +#define ARM_SEC_TIMER_PPI 29
> +#define GIC_MAINTENANCE_PPI 25
>
> #define GEM_REVISION 0x40070106
>
> #define GIC_BASE_ADDR 0xf9000000
> #define GIC_DIST_ADDR 0xf9010000
> #define GIC_CPU_ADDR 0xf9020000
> +#define GIC_VIFACE_ADDR 0xf9040000
> +#define GIC_VCPU_ADDR 0xf9060000
>
> #define SATA_INTR 133
> #define SATA_ADDR 0xFD0C0000
> @@ -111,11 +116,54 @@ static const int adma_ch_intr[XLNX_ZYNQMP_NUM_ADMA_CH] = {
> typedef struct XlnxZynqMPGICRegion {
> int region_index;
> uint32_t address;
> + uint32_t offset;
> + bool virt;
> } XlnxZynqMPGICRegion;
>
> static const XlnxZynqMPGICRegion xlnx_zynqmp_gic_regions[] = {
> - { .region_index = 0, .address = GIC_DIST_ADDR, },
> - { .region_index = 1, .address = GIC_CPU_ADDR, },
> + /* Distributor */
> + {
> + .region_index = 0,
> + .address = GIC_DIST_ADDR,
> + .offset = 0,
> + .virt = false
> + },
> +
> + /* CPU interface */
> + {
> + .region_index = 1,
> + .address = GIC_CPU_ADDR,
> + .offset = 0,
> + .virt = false
> + },
> + {
> + .region_index = 1,
> + .address = GIC_CPU_ADDR + 0x10000,
> + .offset = 0x1000,
> + .virt = false
> + },
> +
> + /* Virtual interface */
> + {
> + .region_index = 2,
> + .address = GIC_VIFACE_ADDR,
> + .offset = 0,
> + .virt = true
> + },
> +
> + /* Virtual CPU interface */
> + {
> + .region_index = 3,
> + .address = GIC_VCPU_ADDR,
> + .offset = 0,
> + .virt = true
> + },
> + {
> + .region_index = 3,
> + .address = GIC_VCPU_ADDR + 0x10000,
> + .offset = 0x1000,
> + .virt = true
> + },
> };
>
> static inline int arm_gic_ppi_index(int cpu_nr, int ppi_index)
> @@ -286,6 +334,9 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> qdev_prop_set_uint32(DEVICE(&s->gic), "num-irq", GIC_NUM_SPI_INTR + 32);
> qdev_prop_set_uint32(DEVICE(&s->gic), "revision", 2);
> qdev_prop_set_uint32(DEVICE(&s->gic), "num-cpu", num_apus);
> + qdev_prop_set_bit(DEVICE(&s->gic), "has-security-extensions", s->secure);
> + qdev_prop_set_bit(DEVICE(&s->gic),
> + "has-virtualization-extensions", s->virt);
>
> /* Realize APUs before realizing the GIC. KVM requires this. */
> for (i = 0; i < num_apus; i++) {
> @@ -330,19 +381,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> for (i = 0; i < XLNX_ZYNQMP_GIC_REGIONS; i++) {
> SysBusDevice *gic = SYS_BUS_DEVICE(&s->gic);
> const XlnxZynqMPGICRegion *r = &xlnx_zynqmp_gic_regions[i];
> - MemoryRegion *mr = sysbus_mmio_get_region(gic, r->region_index);
> + MemoryRegion *mr;
> uint32_t addr = r->address;
> int j;
>
> - sysbus_mmio_map(gic, r->region_index, addr);
> + if (r->virt && !s->virt) {
> + continue;
> + }
>
> + mr = sysbus_mmio_get_region(gic, r->region_index);
> for (j = 0; j < XLNX_ZYNQMP_GIC_ALIASES; j++) {
> MemoryRegion *alias = &s->gic_mr[i][j];
>
> - addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
> memory_region_init_alias(alias, OBJECT(s), "zynqmp-gic-alias", mr,
> - 0, XLNX_ZYNQMP_GIC_REGION_SIZE);
> + r->offset, XLNX_ZYNQMP_GIC_REGION_SIZE);
> memory_region_add_subregion(system_memory, addr, alias);
> +
> + addr += XLNX_ZYNQMP_GIC_REGION_SIZE;
> }
> }
>
> @@ -352,12 +407,33 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i,
> qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
> ARM_CPU_IRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus,
> + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
> + ARM_CPU_FIQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 2,
> + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
> + ARM_CPU_VIRQ));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 3,
> + qdev_get_gpio_in(DEVICE(&s->apu_cpu[i]),
> + ARM_CPU_VFIQ));
> irq = qdev_get_gpio_in(DEVICE(&s->gic),
> arm_gic_ppi_index(i, ARM_PHYS_TIMER_PPI));
> - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 0, irq);
> + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_PHYS, irq);
> irq = qdev_get_gpio_in(DEVICE(&s->gic),
> arm_gic_ppi_index(i, ARM_VIRT_TIMER_PPI));
> - qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), 1, irq);
> + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_VIRT, irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_HYP_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_HYP, irq);
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, ARM_SEC_TIMER_PPI));
> + qdev_connect_gpio_out(DEVICE(&s->apu_cpu[i]), GTIMER_SEC, irq);
> +
> + if (s->virt) {
> + irq = qdev_get_gpio_in(DEVICE(&s->gic),
> + arm_gic_ppi_index(i, GIC_MAINTENANCE_PPI));
> + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gic), i + num_apus * 4, irq);
> + }
> }
>
> if (s->has_rpu) {
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 82b6ec2486..98f925ab84 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -53,7 +53,7 @@
> #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
> #define XLNX_ZYNQMP_OCM_RAM_SIZE 0x10000
>
> -#define XLNX_ZYNQMP_GIC_REGIONS 2
> +#define XLNX_ZYNQMP_GIC_REGIONS 6
>
> /* ZynqMP maps the ARM GIC regions (GICC, GICD ...) at consecutive 64k offsets
> * and under-decodes the 64k region. This mirrors the 4k regions to every 4k
> @@ -62,7 +62,7 @@
> */
>
> #define XLNX_ZYNQMP_GIC_REGION_SIZE 0x1000
> -#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE - 1)
> +#define XLNX_ZYNQMP_GIC_ALIASES (0x10000 / XLNX_ZYNQMP_GIC_REGION_SIZE)
>
> #define XLNX_ZYNQMP_MAX_LOW_RAM_SIZE 0x80000000ull
>
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Luc Michel
@ 2018-07-17 13:32 ` Peter Maydell
2018-07-18 13:22 ` Luc Michel
0 siblings, 1 reply; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 13:32 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Implement virtualization extensions in the gic_deactivate_irq() and
> gic_complete_irq() functions. When a guest tries to deactivat or end an
"deactivate"
> IRQ that does not exist in the LRs, the EOICount field of the virtual
> interface HCR register is incremented by one, and the request is
> ignored.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
> ---
> hw/intc/arm_gic.c | 18 ++++++++++++++++++
> 1 file changed, 18 insertions(+)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index be9e2594d9..50cbbfbe24 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -590,6 +590,15 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
> return;
> }
>
> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
> + /* This vIRQ does not have an LR entry which is either active or
> + * pending and active. Increment EOICount and ignore the write.
> + */
> + int rcpu = gic_get_vcpu_real_id(cpu);
> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
> + return;
> + }
It's a bit hard to tell from the amount of context in the diff,
but I think this check is being done too late in this function.
It needs to happen before we do any operations on the irq we're
passed (eg checking which group it is).
> +
> if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
> DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
> return;
> @@ -604,6 +613,15 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
> int group;
>
> DPRINTF("EOI %d\n", irq);
> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
> + /* This vIRQ does not have an LR entry which is either active or
> + * pending and active. Increment EOICount and ignore the write.
> + */
> + int rcpu = gic_get_vcpu_real_id(cpu);
> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
> + return;
> + }
This isn't consistent with the deactivate code about whether we
do this check before the "irq >= s->num_irq" check or after.
I think the correct answer is "before", because the number of
physical interrupts in the GIC shouldn't affect the valid
range of virtual interrupts.
There is also an edge case here: if the VIRQ written to the
EOI or DIR registers is a special interrupt number (1020..1023),
then should we increment the EOI count or not? The GICv2 spec
is not entirely clear on this point, but it does say in the
GICH_HCR.EOICount docs that "EOIs that do not clear a bit in
the Active Priorities register GICH_APR do not cause an increment",
and the GICv3 spec is clear so my recommendation is that for
1020..1023 we should ignore the write and not increment EOICount.
That bit about "EOIs that do not clear a bit in GICH_APR do
not increment EOICount" also suggests that our logic for DIR
and EOI needs to be something like:
if (vcpu) {
if (irq > 1020) {
return;
}
clear GICH_HCR bit;
if (no bit cleared) {
return;
}
if (!gic_virq_is_valid()) {
increment EOICount;
return;
}
clear active bit in LR;
}
?
> +
> if (irq >= s->num_irq) {
> /* This handles two cases:
> * 1. If software writes the ID of a spurious interrupt [ie 1023]
> --
> 2.18.0
>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Luc Michel
@ 2018-07-17 14:15 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:15 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers in the GICv2.
> Those registers allow to set or clear the active state of an IRQ in the
> distributor.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
> ---
> hw/intc/arm_gic.c | 61 +++++++++++++++++++++++++++++++++++++++++++----
> 1 file changed, 57 insertions(+), 4 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions Luc Michel
@ 2018-07-17 14:17 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:17 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Add some helper macros and functions related to the virtualization
> extensions to gic_internal.h.
>
> The GICH_LR_* macros help extracting specific fields of a list register
> value. The only tricky one is the priority field as only the MSB are
> stored. The value must be shifted accordingly to obtain the correct
> priority value.
>
> gic_is_vcpu() and gic_get_vcpu_real_id() help with (v)CPU id manipulation
> to abstract the fact that vCPU id are in the range
> [ GIC_NCPU; (GIC_NCPU + num_cpu) [.
>
> gic_lr_* and gic_virq_is_valid() help with the list registers.
> gic_get_lr_entry() returns the LR entry for a given (vCPU, irq) pair. It
> is meant to be used in contexts where we know for sure that the entry
> exists, so we assert that entry is actually found, and the caller can
> avoid the NULL check on the returned pointer.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
> ---
> hw/intc/arm_gic.c | 5 +++
> hw/intc/gic_internal.h | 75 ++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 80 insertions(+)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index aaa34426a1..1ac0fe740c 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -61,6 +61,11 @@ static inline int gic_get_current_cpu(GICState *s)
> return 0;
> }
>
> +static inline int gic_get_current_vcpu(GICState *s)
> +{
> + return gic_get_current_cpu(s) + GIC_NCPU;
> +}
> +
> /* Return true if this GIC config has interrupt groups, which is
> * true if we're a GICv2, or a GICv1 with the security extensions.
> */
> diff --git a/hw/intc/gic_internal.h b/hw/intc/gic_internal.h
> index 1aa888a576..56e203aeb9 100644
> --- a/hw/intc/gic_internal.h
> +++ b/hw/intc/gic_internal.h
> @@ -129,6 +129,20 @@ REG32(GICH_LR63, 0x1fc)
> R_GICH_LR0_Priority_MASK | R_GICH_LR0_State_MASK | \
> R_GICH_LR0_Grp1_MASK | R_GICH_LR0_HW_MASK)
>
> +#define GICH_LR_STATE_INVALID 0
> +#define GICH_LR_STATE_PENDING 1
> +#define GICH_LR_STATE_ACTIVE 2
> +#define GICH_LR_STATE_ACTIVE_PENDING 3
> +
> +#define GICH_LR_VIRT_ID(entry) (FIELD_EX32(entry, GICH_LR0, VirtualID))
> +#define GICH_LR_PHYS_ID(entry) (FIELD_EX32(entry, GICH_LR0, PhysicalID))
> +#define GICH_LR_CPUID(entry) (FIELD_EX32(entry, GICH_LR0, CPUID))
> +#define GICH_LR_EOI(entry) (FIELD_EX32(entry, GICH_LR0, EOI))
> +#define GICH_LR_PRIORITY(entry) (FIELD_EX32(entry, GICH_LR0, Priority) << 3)
> +#define GICH_LR_STATE(entry) (FIELD_EX32(entry, GICH_LR0, State))
> +#define GICH_LR_GROUP(entry) (FIELD_EX32(entry, GICH_LR0, Grp1))
> +#define GICH_LR_HW(entry) (FIELD_EX32(entry, GICH_LR0, HW))
> +
> /* Valid bits for GICC_CTLR for GICv1, v1 with security extensions,
> * GICv2 and GICv2 with security extensions:
> */
> @@ -164,4 +178,65 @@ static inline bool gic_is_vcpu(int cpu)
> return cpu >= GIC_NCPU;
> }
>
> +static inline int gic_get_vcpu_real_id(int cpu)
> +{
> + return (cpu >= GIC_NCPU) ? (cpu - GIC_NCPU) : cpu;
> +}
> +
> +/* Return true if the given vIRQ state exists in a LR and is either active or
> + * pending and active.
> + *
> + * This function is used to check that a guest's `end of interrupt' or
> + * `interrupts deactivation' request is valid, and matches with a LR of an
> + * already acknowledged vIRQ (i.e. has the active bit set in its state).
> + */
> +static inline bool gic_virq_is_valid(GICState *s, int irq, int vcpu)
> +{
> + int cpu = gic_get_vcpu_real_id(vcpu);
> + int lr_idx;
> +
> + for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
> + uint32_t *entry = &s->h_lr[lr_idx][cpu];
> +
> + if ((GICH_LR_VIRT_ID(*entry) == irq) &&
> + (GICH_LR_STATE(*entry) & GICH_LR_STATE_ACTIVE)) {
> + return true;
> + }
> + }
> +
> + return false;
> +}
> +
> +/* Return a pointer on the LR entry matching the given vIRQ.
> + *
> + * This function is used to retrieve an LR for which we know for sure that the
> + * corresponding vIRQ exists in the current context (i.e. its current state is
> + * not `invalid'):
> + * - Either the corresponding vIRQ has been validated with gic_virq_is_valid()
> + * so it is `active' or `active and pending',
> + * - Or it was pending and has been selected by gic_get_best_virq(). It is now
> + * `pending', `active' or `active and pending', depending on what the guest
> + * already did with this vIRQ.
> + *
> + * Having multiple LRs with the same VirtualID leads to UNPREDICTABLE
> + * behaviour in the GIC. We choose to return the first one that matches.
> + */
> +static inline uint32_t *gic_get_lr_entry(GICState *s, int irq, int vcpu)
> +{
> + int cpu = gic_get_vcpu_real_id(vcpu);
> + int lr_idx;
> +
> + for (lr_idx = 0; lr_idx < s->num_lrs; lr_idx++) {
> + uint32_t *entry = &s->h_lr[lr_idx][cpu];
> +
> + if ((GICH_LR_VIRT_ID(*entry) == irq) &&
> + (GICH_LR_STATE(*entry) != GICH_LR_STATE_INVALID)) {
> + return entry;
> + }
> + }
> +
> + g_assert_not_reached();
> + return NULL;
> +}
You can drop the 'return NULL' as that is unreachable code.
Otherwise
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions Luc Michel
@ 2018-07-17 14:20 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:20 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Add some helper functions to gic_internal.h to get or change the state
> of an IRQ. When the current CPU is not a vCPU, the call is forwarded to
> the GIC distributor. Otherwise, it acts on the list register matching
> the IRQ in the current CPU virtual interface.
>
> gic_clear_active can have a side effect on the distributor, even in the
> vCPU case, when the correponding LR has the HW field set.
>
> Use those functions in the CPU interface code path to prepare for the
> vCPU interface implementation.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio)
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) Luc Michel
@ 2018-07-17 14:21 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:21 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Implement virtualization extensions in gic_activate_irq() and
> gic_drop_prio() and in gic_get_prio_from_apr_bits() called by
> gic_drop_prio().
>
> When the current CPU is a vCPU:
> - Use GIC_VIRT_MIN_BPR and GIC_VIRT_NR_APRS instead of their non-virt
> counterparts,
> - the vCPU APR is stored in the virtual interface, in h_apr.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface Luc Michel
@ 2018-07-17 14:26 ` Peter Maydell
2018-07-18 13:24 ` Luc Michel
0 siblings, 1 reply; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:26 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Add the read/write functions to handle accesses to the vCPU interface.
> Those accesses are forwarded to the real CPU interface, with the CPU id
> being converted to the corresponding vCPU id (vCPU id = CPU id +
> GIC_NCPU).
>
> As for the CPU interface, we create a base region for the vCPU interface
> that fetches the current vCPU id using the current_cpu global variable, and
> one mirror region per vCPU which maps to that specific vCPU id. This is
> required by the GIC architecture specification.
Is it? The spec says the GICH registers need to be accessible
like this, but not the vCPU (GICV) registers...
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function Luc Michel
@ 2018-07-17 14:27 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:27 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> Add the gic_update_virt() function to update the vCPU interface states
> and raise vIRQ and vFIQ as needed. This commit renames gic_update() to
> gic_update_internal() and generalizes it to handle both cases, with a
> `virt' parameter to track whether we are updating the CPU or vCPU
> interfaces.
>
> The main difference between CPU and vCPU is the way we select the best
> IRQ. This part has been split into the gic_get_best_(v)irq functions.
> For the virt case, the LRs are iterated to find the best candidate.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
> ---
> hw/intc/arm_gic.c | 186 ++++++++++++++++++++++++++++++++++++----------
> 1 file changed, 146 insertions(+), 40 deletions(-)
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions Luc Michel
@ 2018-07-17 14:29 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:29 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:16, Luc Michel <luc.michel@greensocs.com> wrote:
> Add support for GICv2 virtualization extensions by mapping the necessary
> I/O regions and connecting the maintenance IRQ lines.
>
> Declare those additions in the device tree and in the ACPI tables.
>
> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
` (19 preceding siblings ...)
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions Luc Michel
@ 2018-07-17 14:33 ` Peter Maydell
20 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-17 14:33 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
> v4:
I've now reviewed or commented on all the patches I think
except the xilinx board one.
You'll want to rebase on top of current master -- this version
doesn't apply (probably as a result of the for-3.0 bugfix
patches that are now in master).
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq)
2018-07-17 13:32 ` Peter Maydell
@ 2018-07-18 13:22 ` Luc Michel
2018-07-20 14:21 ` Peter Maydell
0 siblings, 1 reply; 34+ messages in thread
From: Luc Michel @ 2018-07-18 13:22 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
[-- Attachment #1: Type: text/plain, Size: 5048 bytes --]
On 07/17/2018 03:32 PM, Peter Maydell wrote:
> On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
>> Implement virtualization extensions in the gic_deactivate_irq() and
>> gic_complete_irq() functions. When a guest tries to deactivat or end an
>
> "deactivate"
>
>> IRQ that does not exist in the LRs, the EOICount field of the virtual
>> interface HCR register is incremented by one, and the request is
>> ignored.
>>
>> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
>> ---
>> hw/intc/arm_gic.c | 18 ++++++++++++++++++
>> 1 file changed, 18 insertions(+)
>>
>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
>> index be9e2594d9..50cbbfbe24 100644
>> --- a/hw/intc/arm_gic.c
>> +++ b/hw/intc/arm_gic.c
>> @@ -590,6 +590,15 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
>> return;
>> }
>>
>> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
>> + /* This vIRQ does not have an LR entry which is either active or
>> + * pending and active. Increment EOICount and ignore the write.
>> + */
>> + int rcpu = gic_get_vcpu_real_id(cpu);
>> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
>> + return;
>> + }
>
> It's a bit hard to tell from the amount of context in the diff,
> but I think this check is being done too late in this function.
> It needs to happen before we do any operations on the irq we're
> passed (eg checking which group it is).For operations on the IRQ, yes. But there is also the test on the
EOIMode bit in C_CTLR before that. Writing to C_DIR when EOIMode is 0 is
unpredictable. I was thinking of keeping the same behaviour we had until
then, which is to completely ignore the write.
>
>> +
>> if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
>> DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
>> return;
>> @@ -604,6 +613,15 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
>> int group;
>>
>> DPRINTF("EOI %d\n", irq);
>> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
>> + /* This vIRQ does not have an LR entry which is either active or
>> + * pending and active. Increment EOICount and ignore the write.
>> + */
>> + int rcpu = gic_get_vcpu_real_id(cpu);
>> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
>> + return;
>> + }
>
> This isn't consistent with the deactivate code about whether we
> do this check before the "irq >= s->num_irq" check or after.
>
> I think the correct answer is "before", because the number of
> physical interrupts in the GIC shouldn't affect the valid
> range of virtual interrupts.
>
> There is also an edge case here: if the VIRQ written to the
> EOI or DIR registers is a special interrupt number (1020..1023),
> then should we increment the EOI count or not? The GICv2 spec
> is not entirely clear on this point, but it does say in the
> GICH_HCR.EOICount docs that "EOIs that do not clear a bit in
> the Active Priorities register GICH_APR do not cause an increment",
> and the GICv3 spec is clear so my recommendation is that for
> 1020..1023 we should ignore the write and not increment EOICount.
>
> That bit about "EOIs that do not clear a bit in GICH_APR do
> not increment EOICount" also suggests that our logic for DIR
> and EOI needs to be something like:
>
> if (vcpu) {
> if (irq > 1020) {
> return;
> }
> clear GICH_HCR bit;
> if (no bit cleared) {
> return;
> }
> if (!gic_virq_is_valid()) {
> increment EOICount;
> return;
> }
> clear active bit in LR;
> }
>
> ?
I agree for EOIR, but for DIR, it seems weird. A write to DIR never
causes a bit to be cleared in GICH_APR. It can only change the state of
the LR corresponding to the given vIRQ. So if we read the specification
this way, a write to DIR should never cause a EOICount increment.
However the part you quoted:
"EOIs that do not clear a bit in the Active Priorities register GICH_APR
do not cause an increment"
seems to apply to EOIs only, not to interrupt deactivations.
And in the DIR specification:
"If the specified Interrupt does not exist in the List registers, the
GICH_HCR.EOIcount field is incremented"
So I would suggest that we apply your reasoning for EOIR. For DIR, I
think something like this is sufficient:
if (vcpu) {
if (irq > 1020) {
return;
}
if (!gic_virq_is_valid()) {
increment EOICount;
return;
}
clear active bit in LR;
}
What do you think?
Thanks
Luc
>
>> +
>> if (irq >= s->num_irq) {
>> /* This handles two cases:
>> * 1. If software writes the ID of a spurious interrupt [ie 1023]
>> --
>> 2.18.0
>>
>
> thanks
> -- PMM
>
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface
2018-07-17 14:26 ` Peter Maydell
@ 2018-07-18 13:24 ` Luc Michel
0 siblings, 0 replies; 34+ messages in thread
From: Luc Michel @ 2018-07-18 13:24 UTC (permalink / raw)
To: Peter Maydell
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
[-- Attachment #1: Type: text/plain, Size: 896 bytes --]
On 07/17/2018 04:26 PM, Peter Maydell wrote:
> On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
>> Add the read/write functions to handle accesses to the vCPU interface.
>> Those accesses are forwarded to the real CPU interface, with the CPU id
>> being converted to the corresponding vCPU id (vCPU id = CPU id +
>> GIC_NCPU).
>>
>> As for the CPU interface, we create a base region for the vCPU interface
>> that fetches the current vCPU id using the current_cpu global variable, and
>> one mirror region per vCPU which maps to that specific vCPU id. This is
>> required by the GIC architecture specification.
>
> Is it? The spec says the GICH registers need to be accessible
> like this, but not the vCPU (GICV) registers...
Sorry, I changed that in the patch but forgot to update the commit
message. I'll fix that.
Luc
>
> thanks
> -- PMM
>
[-- Attachment #2: OpenPGP digital signature --]
[-- Type: application/pgp-signature, Size: 833 bytes --]
^ permalink raw reply [flat|nested] 34+ messages in thread
* Re: [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq)
2018-07-18 13:22 ` Luc Michel
@ 2018-07-20 14:21 ` Peter Maydell
0 siblings, 0 replies; 34+ messages in thread
From: Peter Maydell @ 2018-07-20 14:21 UTC (permalink / raw)
To: Luc Michel
Cc: QEMU Developers, qemu-arm, Sai Pavan Boddu, Edgar Iglesias,
Mark Burton, Jan Kiszka
On 18 July 2018 at 14:22, Luc Michel <luc.michel@greensocs.com> wrote:
>
>
> On 07/17/2018 03:32 PM, Peter Maydell wrote:
>> On 14 July 2018 at 18:15, Luc Michel <luc.michel@greensocs.com> wrote:
>>> Implement virtualization extensions in the gic_deactivate_irq() and
>>> gic_complete_irq() functions. When a guest tries to deactivat or end an
>>
>> "deactivate"
>>
>>> IRQ that does not exist in the LRs, the EOICount field of the virtual
>>> interface HCR register is incremented by one, and the request is
>>> ignored.
>>>
>>> Signed-off-by: Luc Michel <luc.michel@greensocs.com>
>>> ---
>>> hw/intc/arm_gic.c | 18 ++++++++++++++++++
>>> 1 file changed, 18 insertions(+)
>>>
>>> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
>>> index be9e2594d9..50cbbfbe24 100644
>>> --- a/hw/intc/arm_gic.c
>>> +++ b/hw/intc/arm_gic.c
>>> @@ -590,6 +590,15 @@ static void gic_deactivate_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
>>> return;
>>> }
>>>
>>> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
>>> + /* This vIRQ does not have an LR entry which is either active or
>>> + * pending and active. Increment EOICount and ignore the write.
>>> + */
>>> + int rcpu = gic_get_vcpu_real_id(cpu);
>>> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
>>> + return;
>>> + }
>>
>> It's a bit hard to tell from the amount of context in the diff,
>> but I think this check is being done too late in this function.
>> It needs to happen before we do any operations on the irq we're
>> passed (eg checking which group it is).
> For operations on the IRQ, yes. But there is also the test on the
> EOIMode bit in C_CTLR before that. Writing to C_DIR when EOIMode is 0 is
> unpredictable. I was thinking of keeping the same behaviour we had until
> then, which is to completely ignore the write.
Yes, that's a reasonable choice.
>>> +
>>> if (gic_cpu_ns_access(s, cpu, attrs) && !group) {
>>> DPRINTF("Non-secure DI for Group0 interrupt %d ignored\n", irq);
>>> return;
>>> @@ -604,6 +613,15 @@ static void gic_complete_irq(GICState *s, int cpu, int irq, MemTxAttrs attrs)
>>> int group;
>>>
>>> DPRINTF("EOI %d\n", irq);
>>> + if (gic_is_vcpu(cpu) && !gic_virq_is_valid(s, irq, cpu)) {
>>> + /* This vIRQ does not have an LR entry which is either active or
>>> + * pending and active. Increment EOICount and ignore the write.
>>> + */
>>> + int rcpu = gic_get_vcpu_real_id(cpu);
>>> + s->h_hcr[rcpu] += 1 << R_GICH_HCR_EOICount_SHIFT;
>>> + return;
>>> + }
>>
>> This isn't consistent with the deactivate code about whether we
>> do this check before the "irq >= s->num_irq" check or after.
>>
>> I think the correct answer is "before", because the number of
>> physical interrupts in the GIC shouldn't affect the valid
>> range of virtual interrupts.
>>
>> There is also an edge case here: if the VIRQ written to the
>> EOI or DIR registers is a special interrupt number (1020..1023),
>> then should we increment the EOI count or not? The GICv2 spec
>> is not entirely clear on this point, but it does say in the
>> GICH_HCR.EOICount docs that "EOIs that do not clear a bit in
>> the Active Priorities register GICH_APR do not cause an increment",
>> and the GICv3 spec is clear so my recommendation is that for
>> 1020..1023 we should ignore the write and not increment EOICount.
>>
>> That bit about "EOIs that do not clear a bit in GICH_APR do
>> not increment EOICount" also suggests that our logic for DIR
>> and EOI needs to be something like:
>>
>> if (vcpu) {
>> if (irq > 1020) {
>> return;
>> }
>> clear GICH_HCR bit;
>> if (no bit cleared) {
>> return;
>> }
>> if (!gic_virq_is_valid()) {
>> increment EOICount;
>> return;
>> }
>> clear active bit in LR;
>> }
>>
>> ?
> I agree for EOIR, but for DIR, it seems weird. A write to DIR never
> causes a bit to be cleared in GICH_APR. It can only change the state of
> the LR corresponding to the given vIRQ. So if we read the specification
> this way, a write to DIR should never cause a EOICount increment.
Yes, I think you're right and I was misreading the spec here,
at least where it regards DIR.
> However the part you quoted:
>
> "EOIs that do not clear a bit in the Active Priorities register GICH_APR
> do not cause an increment"
>
> seems to apply to EOIs only, not to interrupt deactivations.
>
> And in the DIR specification:
> "If the specified Interrupt does not exist in the List registers, the
> GICH_HCR.EOIcount field is incremented"
>
> So I would suggest that we apply your reasoning for EOIR. For DIR, I
> think something like this is sufficient:
>
> if (vcpu) {
> if (irq > 1020) {
> return;
> }
> if (!gic_virq_is_valid()) {
> increment EOICount;
> return;
> }
> clear active bit in LR;
> }
>
>
> What do you think?
Yes, I think this is right.
thanks
-- PMM
^ permalink raw reply [flat|nested] 34+ messages in thread
end of thread, other threads:[~2018-07-20 14:21 UTC | newest]
Thread overview: 34+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-14 17:15 [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 01/20] intc/arm_gic: Refactor operations on the distributor Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 02/20] intc/arm_gic: Implement GICD_ISACTIVERn and GICD_ICACTIVERn registers Luc Michel
2018-07-17 14:15 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 03/20] intc/arm_gic: Remove some dead code and put some functions static Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 06/20] intc/arm_gic: Add virtual interface register definitions Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 07/20] intc/arm_gic: Add virtualization extensions helper macros and functions Luc Michel
2018-07-17 14:17 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions Luc Michel
2018-07-17 14:20 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 10/20] intc/arm_gic: Implement virtualization extensions in gic_(activate_irq|drop_prio) Luc Michel
2018-07-17 14:21 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 12/20] intc/arm_gic: Implement virtualization extensions in gic_(deactivate|complete_irq) Luc Michel
2018-07-17 13:32 ` Peter Maydell
2018-07-18 13:22 ` Luc Michel
2018-07-20 14:21 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 13/20] intc/arm_gic: Implement virtualization extensions in gic_cpu_(read|write) Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 14/20] intc/arm_gic: Wire the vCPU interface Luc Michel
2018-07-17 14:26 ` Peter Maydell
2018-07-18 13:24 ` Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 15/20] intc/arm_gic: Implement the virtual interface registers Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 16/20] intc/arm_gic: Implement gic_update_virt() function Luc Michel
2018-07-17 14:27 ` Peter Maydell
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 17/20] intc/arm_gic: Implement maintenance interrupt generation Luc Michel
2018-07-14 17:15 ` [Qemu-devel] [PATCH v4 18/20] intc/arm_gic: Improve traces Luc Michel
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping Luc Michel
2018-07-14 17:42 ` [Qemu-devel] [Qemu-arm] " Edgar E. Iglesias
2018-07-14 17:16 ` [Qemu-devel] [PATCH v4 20/20] arm/virt: Add support for GICv2 virtualization extensions Luc Michel
2018-07-17 14:29 ` Peter Maydell
2018-07-17 14:33 ` [Qemu-devel] [PATCH v4 00/20] arm_gic: add virtualization extensions support Peter Maydell
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.