[U-Boot] [PATCH 06/25] dm: mmc: sunxi: Add ahb reset0 register write

[Maxime Ripard <maxime.ripard@bootlin.com>]

On Mon, Jul 16, 2018 at 03:25:08PM +0530, Jagan Teki wrote:
> On Mon, Jul 16, 2018 at 3:09 PM, Maxime Ripard
> <maxime.ripard@bootlin.com> wrote:
> > On Mon, Jul 16, 2018 at 01:49:37PM +0530, Jagan Teki wrote:
> >> AHB reset0 is needed for Allwinner start from sun6i, so
> >> add driver data configuration for ahb reset0 and update
> >> the register bits during probe.
> >>
> >> Cc: Jaehoon Chung <jh80.chung@samsung.com>
> >> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
> >> ---
> >>  drivers/mmc/sunxi_mmc.c | 36 +++++++++++++++++++++++++++++++++---
> >>  1 file changed, 33 insertions(+), 3 deletions(-)
> >>
> >> diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c
> >> index 38171b81f3..beeded50af 100644
> >> --- a/drivers/mmc/sunxi_mmc.c
> >> +++ b/drivers/mmc/sunxi_mmc.c
> >> @@ -30,6 +30,7 @@ struct sunxi_mmc_priv {
> >>       unsigned fatal_err;
> >>       struct gpio_desc cd_gpio;       /* Change Detect GPIO */
> >>       int cd_inverted;                /* Inverted Card Detect */
> >> +     u32 *reg_reset0;
> >>       struct sunxi_mmc *reg;
> >>       struct mmc_config cfg;
> >>  };
> >> @@ -528,6 +529,14 @@ struct mmc *sunxi_mmc_init(int sdc_no)
> >>  }
> >>  #else
> >>
> >> +#define OFF_SUN6I_AHB_RESET0 0x2c0
> >> +
> >> +struct sunxi_mmc_config {
> >> +     bool has_reset0;
> >> +     u8 pos_reset0;
> >> +     u32 off_reset0;
> >> +};
> >> +
> >>  static int sunxi_mmc_set_ios(struct udevice *dev)
> >>  {
> >>       struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >> @@ -569,6 +578,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >>       struct sunxi_mmc_plat *plat = dev_get_platdata(dev);
> >>       struct sunxi_mmc_priv *priv = dev_get_priv(dev);
> >>       struct mmc_config *cfg = &plat->cfg;
> >> +     const struct sunxi_mmc_config *data;
> >>       struct sunxi_ccm_reg *ccm;
> >>       struct ofnode_phandle_args args;
> >>       int bus_width, ret;
> >> @@ -588,6 +598,7 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >>       cfg->f_min = 400000;
> >>       cfg->f_max = 52000000;
> >>
> >> +     data = (struct sunxi_mmc_config *)dev_get_driver_data(dev);
> >>       priv->reg = (void *)dev_read_addr(dev);
> >>       priv->mmc_no = (((uintptr_t)priv->reg / 0x1000) - 0x1C0F);
> >>
> >> @@ -600,9 +611,15 @@ static int sunxi_mmc_probe(struct udevice *dev)
> >>       if (IS_ERR(ccm))
> >>               return PTR_ERR(ccm);
> >>
> >> +     priv->reg_reset0 = (void *)ccm + data->off_reset0;
> >> +
> >>       /* enable ahb gate */
> >>       setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_MMC(priv->mmc_no)));
> >>
> >> +     /* unassert reset */
> >> +     if (data->has_reset0)
> >> +             setbits_le32(priv->reg_reset0, BIT(data->pos_reset0 + priv->mmc_no));
> >> +
> >>       /* find clock reg */
> >>       switch (priv->mmc_no) {
> >>       case 0:
> >> @@ -653,10 +670,23 @@ static int sunxi_mmc_bind(struct udevice *dev)
> >>       return mmc_bind(dev, &plat->mmc, &plat->cfg);
> >>  }
> >>
> >> +static const struct sunxi_mmc_config sun4i_a10_cfg = {
> >> +     .has_reset0 = false,
> >> +};
> >> +
> >> +static const struct sunxi_mmc_config sun7i_a20_cfg = {
> >> +     .has_reset0 = true,
> >> +     .pos_reset0 = 8,
> >> +     .off_reset0 = OFF_SUN6I_AHB_RESET0,
> >> +};
> >
> > Nope. The A20 doesn't have any reset line.
> 
> Yes, I know. but sun6i-a31 has it and share same compatible
> allwinner,sun7i-a20-mmc ie reason I've attached driver data.

That doesn't make it more correct. The A20 doesn't have a reset line,
I don't see any good reason to imply this.

Maxime

-- 
Maxime Ripard, Bootlin (formerly Free Electrons)
Embedded Linux and Kernel engineering
https://bootlin.com
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