From: Patchwork <patchwork@emeril.freedesktop.org>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
Date: Tue, 17 Jul 2018 21:33:03 -0000 [thread overview]
Message-ID: <20180717213303.8215.75932@emeril.freedesktop.org> (raw)
In-Reply-To: <1531861861-10950-1-git-send-email-anusha.srivatsa@intel.com>
== Series Details ==
Series: series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters
URL : https://patchwork.freedesktop.org/series/46742/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0ccb8db4366a drm/i915/icl: Add VIDEO_DIP regsiters
-:66: WARNING:LONG_LINE: line over 100 characters
#66: FILE: drivers/gpu/drm/i915/i915_reg.h:7873:
+#define ICL_VIDEO_DIP_PPS_DATA(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_DATA_A + (i) * 4)
-:67: WARNING:LONG_LINE: line over 100 characters
#67: FILE: drivers/gpu/drm/i915/i915_reg.h:7874:
+#define ICL_VIDEO_DIP_PPS_ECC(trans, i) _MMIO_TRANS2(trans, _ICL_VIDEO_DIP_PPS_ECC_A + (i) * 4)
total: 0 errors, 2 warnings, 0 checks, 41 lines checked
f7a62fccc3eb i915/dp/dsc: Add DSC PPS register definitions
f6a9fee4d495 i915/dp/dsc: Add Rate Control Buffer Threshold Registers
-:82: CHECK:LINE_SPACING: Please don't use multiple blank lines
#82: FILE: drivers/gpu/drm/i915/i915_reg.h:10553:
+
+
total: 0 errors, 0 warnings, 1 checks, 56 lines checked
7ba6acbd53cb i915/dp/dsc: Add Rate Control Range Parameter Registers
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next prev parent reply other threads:[~2018-07-17 21:33 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
2018-07-18 18:55 ` Manasi Navare
2018-07-20 1:30 ` Manasi Navare
2018-07-17 21:11 ` [PATCH 3/4] i915/dp/dsc: Add Rate Control Buffer Threshold Registers Anusha Srivatsa
2018-07-17 21:11 ` [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers Anusha Srivatsa
2018-07-18 18:57 ` Manasi Navare
2018-07-17 21:33 ` Patchwork [this message]
2018-07-17 21:59 ` ✓ Fi.CI.BAT: success for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters Patchwork
2018-07-18 5:14 ` ✓ Fi.CI.IGT: " Patchwork
2018-07-18 18:53 ` [PATCH 1/4] " Manasi Navare
2018-07-18 20:54 ` Rodrigo Vivi
2018-07-18 22:06 ` Srivatsa, Anusha
2018-07-18 22:34 ` Rodrigo Vivi
2018-07-19 0:51 ` Rodrigo Vivi
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