From: Manasi Navare <manasi.d.navare@intel.com>
To: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: intel-gfx@lists.freedesktop.org,
Lucas De Marchi <lucas.demarchi@intel.com>
Subject: Re: [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions
Date: Wed, 18 Jul 2018 11:55:57 -0700 [thread overview]
Message-ID: <20180718185557.GC26467@intel.com> (raw)
In-Reply-To: <1531861861-10950-2-git-send-email-anusha.srivatsa@intel.com>
On Tue, Jul 17, 2018 at 02:10:59PM -0700, Anusha Srivatsa wrote:
> From: "Srivatsa, Anusha" <anusha.srivatsa@intel.com>
>
> Display Stream Compression(DSC) has a set of Picture
> Parameter Set(PPS) components that the encoder must
> communicate to the decoder.
>
> This patch adds register definitions to
> the PPS parameters for eDP/MIPI case and Display Port.
>
> v2:
> - Use _MMIO_PIPE instead of _MMIO(_PICK()). (Manasi)
> - Use DSC constants as arguments. (Manasi)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Ville Syrjala <ville.syrjala@linux.intel.com>
> Cc: Manasi Navare <manasi.d.navare@intel.com>
> Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Looks good to me, checked against the spec.
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 255 ++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 255 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 23e70a4..e8687b0 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10244,4 +10244,259 @@ enum skl_power_gate {
> _ICL_PHY_MISC_B)
> #define ICL_PHY_MISC_DE_IO_COMP_PWR_DOWN (1 << 23)
>
> +/* Icelake Display Stream Compression Registers */
> +#define DSCA_PICTURE_PARAMETER_SET_0 0x6B200
> +#define DSCC_PICTURE_PARAMETER_SET_0 0x6BA00
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB 0x78270
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB 0x78370
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC 0x78470
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC 0x78570
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_0_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_0_PC)
> +#define DSC_VBR_ENABLE (1 << 19)
> +#define DSC_422_ENABLE (1 << 18)
> +#define DSC_COLOR_SPACE_CONVERSION (1 << 17)
> +#define DSC_BLOCK_PREDICTION (1 << 16)
> +#define DSC_LINE_BUF_DEPTH_SHIFT 12
> +#define DSC_BPC_SHIFT 8
> +#define DSC_VER_MIN_SHIFT 4
> +#define DSC_VER_MAJ (0x1 << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_1 0x6B204
> +#define DSCC_PICTURE_PARAMETER_SET_1 0x6BA04
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB 0x78274
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB 0x78374
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC 0x78474
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC 0x78574
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_1_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_1(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_1_PC)
> +#define DSC_BPP(bpp) ((bpp) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_2 0x6B208
> +#define DSCC_PICTURE_PARAMETER_SET_2 0x6BA08
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB 0x78278
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB 0x78378
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC 0x78478
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC 0x78578
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_2_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_2(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_2_PC)
> +#define DSC_PIC_WIDTH(pic_width) ((pic_width) << 16)
> +#define DSC_PIC_HEIGHT(pic_height) ((pic_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_3 0x6B20C
> +#define DSCC_PICTURE_PARAMETER_SET_3 0x6BA0C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB 0x7827C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB 0x7837C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC 0x7847C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC 0x7857C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_3_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_3(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_3_PC)
> +#define DSC_SLICE_WIDTH(slice_width) ((slice_width) << 16)
> +#define DSC_SLICE_HEIGHT(slice_height) ((slice_height) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_4 0x6B210
> +#define DSCC_PICTURE_PARAMETER_SET_4 0x6BA10
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB 0x78280
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB 0x78380
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC 0x78480
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC 0x78580
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> +#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> +#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_5 0x6B214
> +#define DSCC_PICTURE_PARAMETER_SET_5 0x6BA14
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB 0x78284
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB 0x78384
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC 0x78484
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC 0x78584
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> +#define DSC_SCALE_DEC_INTINT(scale_dec) ((scale_dec) << 16)
> +#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_6 0x6B218
> +#define DSCC_PICTURE_PARAMETER_SET_6 0x6BA18
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB 0x78288
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB 0x78388
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC 0x78488
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC 0x78588
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_6_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_6(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_6_PC)
> +#define DSC_FLATNESS_MAX_QP(max_qp) (qp << 24)
> +#define DSC_FLATNESS_MIN_QP(min_qp) (qp << 16)
> +#define DSC_FIRST_LINE_BPG_OFFSET(offset) ((offset) << 8)
> +#define DSC_INITIAL_SCALE_VALUE(value) ((value) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_7 0x6B21C
> +#define DSCC_PICTURE_PARAMETER_SET_7 0x6BA1C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB 0x7828C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB 0x7838C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC 0x7848C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC 0x7858C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_7_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_7(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_7_PC)
> +#define DSC_NFL_BPG_OFFSET(bpg_offset) ((bpg_offset) << 16)
> +#define DSC_SLICE_BPG_OFFSET(bpg_offset) ((bpg_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_8 0x6B220
> +#define DSCC_PICTURE_PARAMETER_SET_8 0x6BA20
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB 0x78290
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB 0x78390
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC 0x78490
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC 0x78590
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_8_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_8(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_8_PC)
> +#define DSC_INITIAL_OFFSET(initial_offset) ((initial_offset) << 16)
> +#define DSC_FINAL_OFFSET(final_offset) ((final_offset) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_9 0x6B224
> +#define DSCC_PICTURE_PARAMETER_SET_9 0x6BA24
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB 0x78294
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB 0x78394
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC 0x78494
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC 0x78594
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_9_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_9(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_9_PC)
> +#define DSC_RC_EDGE_FACTOR(rc_edge_fact) ((rc_edge_fact) << 16)
> +#define DSC_RC_MODEL_SIZE(rc_model_size) ((rc_model_size) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_10 0x6B228
> +#define DSCC_PICTURE_PARAMETER_SET_10 0x6BA28
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB 0x78298
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB 0x78398
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC 0x78498
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC 0x78598
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_10_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_10(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_10_PC)
> +#define DSC_RC_TARGET_OFF_LOW(rc_tgt_off_low) ((rc_tgt_off_low) << 20)
> +#define DSC_RC_TARGET_OFF_HIGH(rc_tgt_off_high) ((rc_tgt_off_high) << 16)
> +#define DSC_RC_QUANT_INC_LIMIT1(lim) ((lim) << 8)
> +#define DSC_RC_QUANT_INC_LIMIT0(lim) ((lim) << 0)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_11 0x6B22C
> +#define DSCC_PICTURE_PARAMETER_SET_11 0x6BA2C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB 0x7829C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB 0x7839C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC 0x7849C
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC 0x7859C
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_11_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_11(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_11_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_12 0x6B260
> +#define DSCC_PICTURE_PARAMETER_SET_12 0x6BA60
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB 0x782A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB 0x783A0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC 0x784A0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC 0x785A0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_12_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_12(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_12_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_13 0x6B264
> +#define DSCC_PICTURE_PARAMETER_SET_13 0x6BA64
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB 0x782A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB 0x783A4
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC 0x784A4
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC 0x785A4
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_13_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_13(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_13_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_14 0x6B268
> +#define DSCC_PICTURE_PARAMETER_SET_14 0x6BA68
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB 0x782A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB 0x783A8
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC 0x784A8
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC 0x785A8
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_14_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_14(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_14_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_15 0x6B26C
> +#define DSCC_PICTURE_PARAMETER_SET_15 0x6BA6C
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB 0x782AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB 0x783AC
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC 0x784AC
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC 0x785AC
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_15_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_15(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_15_PC)
> +
> +#define DSCA_PICTURE_PARAMETER_SET_16 0x6B270
> +#define DSCC_PICTURE_PARAMETER_SET_16 0x6BA70
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB 0x782B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB 0x783B0
> +#define _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC 0x784B0
> +#define _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC 0x785B0
> +#define ICL_DSC0_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC0_PICTURE_PARAMETER_SET_16_PC)
> +#define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC)
> +#define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16)
> +#define DSC_SLICE_CHUNK_SIZE(slice_chunk_aize) (slice_chunk_size << 0)
> +
> #endif /* _I915_REG_H_ */
> --
> 2.7.4
>
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next prev parent reply other threads:[~2018-07-18 18:53 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-17 21:10 [PATCH 1/4] drm/i915/icl: Add VIDEO_DIP regsiters Anusha Srivatsa
2018-07-17 21:10 ` [PATCH 2/4] i915/dp/dsc: Add DSC PPS register definitions Anusha Srivatsa
2018-07-18 18:55 ` Manasi Navare [this message]
2018-07-20 1:30 ` Manasi Navare
2018-07-17 21:11 ` [PATCH 3/4] i915/dp/dsc: Add Rate Control Buffer Threshold Registers Anusha Srivatsa
2018-07-17 21:11 ` [PATCH 4/4] i915/dp/dsc: Add Rate Control Range Parameter Registers Anusha Srivatsa
2018-07-18 18:57 ` Manasi Navare
2018-07-17 21:33 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/4] drm/i915/icl: Add VIDEO_DIP regsiters Patchwork
2018-07-17 21:59 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-18 5:14 ` ✓ Fi.CI.IGT: " Patchwork
2018-07-18 18:53 ` [PATCH 1/4] " Manasi Navare
2018-07-18 20:54 ` Rodrigo Vivi
2018-07-18 22:06 ` Srivatsa, Anusha
2018-07-18 22:34 ` Rodrigo Vivi
2018-07-19 0:51 ` Rodrigo Vivi
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