[PATCH 1/2] drm/dp: add extended receiver capability field present bit

[PATCH 1/2] drm/dp: add extended receiver capability field present bit

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

This bit was added to DP Training Aux RD interval sometime between DP
1.2 and DP 1.3. Via description of the spec this field indicates the
panels true capabilities are described in DPCD address space 02200h
through 022FFh.

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 include/drm/drm_dp_helper.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c01564991a9f..757bd5913f3d 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -123,8 +123,9 @@
 # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 
-#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
-# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
+#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK                0x7F    /* XXX 1.2? */
+# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* XXX 1.2? */
 
 #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
 # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
-- 
2.17.1

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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..364cf41a8b89 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+		    &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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✗ Fi.CI.CHECKPATCH: warning for series starting with [1/2] drm/dp: add extended receiver capability field present bit

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: add extended receiver capability field present bit
URL   : https://patchwork.freedesktop.org/series/46743/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
042a66fcd5c9 drm/dp: add extended receiver capability field present bit
6351900d2b26 drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
-:46: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#46: FILE: drivers/gpu/drm/i915/intel_dp.c:3711:
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+		    &dpcd_ext, sizeof(dpcd_ext)) < 0)

total: 0 errors, 0 warnings, 1 checks, 43 lines checked

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✓ Fi.CI.BAT: success for series starting with [1/2] drm/dp: add extended receiver capability field present bit

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: add extended receiver capability field present bit
URL   : https://patchwork.freedesktop.org/series/46743/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4503 -> Patchwork_9700 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/46743/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_9700 that come from known issues:

  === IGT changes ===

    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      fi-skl-guc:         DMESG-FAIL (fdo#107174) -> PASS
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#106560) -> PASS

    igt@kms_chamelium@dp-crc-fast:
      fi-kbl-7500u:       FAIL (fdo#103841) -> PASS +1

    igt@kms_flip@basic-flip-vs-dpms:
      fi-skl-6700hq:      DMESG-WARN (fdo#105998) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#103841 https://bugs.freedesktop.org/show_bug.cgi?id=103841
  fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174


== Participating hosts (46 -> 41) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4503 -> Patchwork_9700

  CI_DRM_4503: 4aa6797dfafaf527949bf55d3c8513c6902dfec2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4562: 8781fd89a63eabed9359d02b50583cca67ff3673 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9700: 6351900d2b26ce7eea809c251ac5334162954d8d @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6351900d2b26 drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT
042a66fcd5c9 drm/dp: add extended receiver capability field present bit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9700/issues.html
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Dhinakaran Pandiyan]

On Tue, 2018-07-17 at 14:49 -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive
> operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected,

I still see 6 bytes read and 3 copied.

>  remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 37
> +++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c
> b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..364cf41a8b89 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux,
> DP_DP13_DPCD_REV,
> +		    &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) 

Why use memcmp and memcmpy if it's just one byte? You could just use
"=="

> {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8)))
> {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max
> Link Rate previous value %2x new value %2x\n",
> +				      intel_dp-
> >dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE],
> sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp-
> >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp-
> >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRE
> SENT]);
> +			memcpy(&intel_dp-
> >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd),
> intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Tue, Jul 17, 2018 at 03:34:35PM -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-07-17 at 14:49 -0700, matthew.s.atwood@intel.com wrote:
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> > 
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability. These
> > values will match 00000h through 0000Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > 
> > Read from DPCD once for all 3 values as this is an expensive
> > operation.
> > Spec mentions that all of address space 02200h through 0220Fh should
> > contain the right information however currently only 3 values can
> > differ.
> > 
> > There is no address space in the intel_dp->dpcd struct for addresses
> > 02200h through 0220Fh, and since so much of the data is a identical,
> > simply overwrite the values stored in 00000h through 0000Fh with the
> > values that can be overwritten from addresses 02200h through 0220Fh.
> > 
> > This patch helps with backward compatibility for devices pre DP1.3.
> > 
> > v2: read only dpcd values which can be affected,
> 
> I still see 6 bytes read and 3 copied.

+1

> 
> >  remove incorrect check,
> > split into drm include changes into separate patch, commit message,
> > verbose debugging statements during overwrite.
> > 
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 37
> > +++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..364cf41a8b89 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
> >  			     sizeof(intel_dp->dpcd)) < 0)
> >  		return false; /* aux transfer failed */
> >  
> > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > +		uint8_t dpcd_ext[6];
> > +
> > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > Field Present, accessing 02200h through 022FFh\n");
> > +
> > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > DP_DP13_DPCD_REV,
> > +		    &dpcd_ext, sizeof(dpcd_ext)) < 0)
> > +			return false; /* aux transfer failed */
> > +
> > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > &dpcd_ext[DP_DPCD_REV],
> > +			   sizeof(u8))) 
> 
> Why use memcmp and memcmpy if it's just one byte? You could just use
> "=="

I think == should work here, but why not memcmp anyways?!

> 
> > {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Revision previous value %2x new value %2x\n",
> > +				      intel_dp->dpcd[DP_DPCD_REV],
> > +				      dpcd_ext[DP_DPCD_REV]);
> > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > +			       &dpcd_ext[DP_DPCD_REV],
> > +			       sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8)))
> > {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max
> > Link Rate previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_MAX_LINK_RATE],
> > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Downstream Port Present  previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +				      dpcd_ext[DP_DOWNSTREAMPORT_PRE
> > SENT]);
> > +			memcpy(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > +			       sizeof(u8));
> > +		}
> > +	}
> >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd),
> > intel_dp->dpcd);
> >  
> >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
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Re: [Intel-gfx] [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Dhinakaran Pandiyan]

On Tue, 2018-07-17 at 15:34 -0700, Dhinakaran Pandiyan wrote:
> On Tue, 2018-07-17 at 14:49 -0700, matthew.s.atwood@intel.com wrote:
> > 
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> > 
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability.
> > These
> > values will match 00000h through 0000Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > 
> > Read from DPCD once for all 3 values as this is an expensive
> > operation.
> > Spec mentions that all of address space 02200h through 0220Fh
> > should
> > contain the right information however currently only 3 values can
> > differ.
> > 
> > There is no address space in the intel_dp->dpcd struct for
> > addresses
> > 02200h through 0220Fh, and since so much of the data is a
> > identical,
> > simply overwrite the values stored in 00000h through 0000Fh with
> > the
> > values that can be overwritten from addresses 02200h through
> > 0220Fh.
> > 
> > This patch helps with backward compatibility for devices pre DP1.3.
> > 
> > v2: read only dpcd values which can be affected,
> I still see 6 bytes read and 3 copied.
Ignore this, the original patch was reading 16B. Thanks for clarifying
Matt.

> 
> > 
> >  remove incorrect check,
> > split into drm include changes into separate patch, commit message,
> > verbose debugging statements during overwrite.
> > 
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 37
> > +++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..364cf41a8b89 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp
> > *intel_dp)
> >  			     sizeof(intel_dp->dpcd)) < 0)
> >  		return false; /* aux transfer failed */
> >  
> > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > +		uint8_t dpcd_ext[6];
> > +
> > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > Field Present, accessing 02200h through 022FFh\n");
> > +
> > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > DP_DP13_DPCD_REV,
> > +		    &dpcd_ext, sizeof(dpcd_ext)) < 0)
> > +			return false; /* aux transfer failed */
> > +
> > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > &dpcd_ext[DP_DPCD_REV],
> > +			   sizeof(u8))) 
> Why use memcmp and memcmpy if it's just one byte? You could just use
> "=="
> 

I believe this is what Jani suggested.
if (memcmp(old_dpcd, new_dpcd, sizeof(new_dpcd)) {
	DRM_DEBUG_KMS();
	memcpy(old_dpcd, new_dpcd, sizeof(new_dpcd);	
}

We lose the information about which specific fields in the 6 bytes
changed, but that's okay IMO.

> > 
> > {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Revision previous value %2x new value %2x\n",
> > +				      intel_dp->dpcd[DP_DPCD_REV],
> > +				      dpcd_ext[DP_DPCD_REV]);
> > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > +			       &dpcd_ext[DP_DPCD_REV],
> > +			       sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			   &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8)))
> > {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Max
> > Link Rate previous value %2x new value %2x\n",
> > +				      intel_dp-
> > > 
> > > dpcd[DP_MAX_LINK_RATE],
> > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp-
> > > 
> > > dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Downstream Port Present  previous value %2x new value %2x\n",
> > +				      intel_dp-
> > > 
> > > dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +				      dpcd_ext[DP_DOWNSTREAMPORT_P
> > RE
> > SENT]);
> > +			memcpy(&intel_dp-
> > > 
> > > dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT
> > ],
> > +			       sizeof(u8));
> > +		}
> > +	}
> >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > >dpcd),
> > intel_dp->dpcd);
> >  
> >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
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✓ Fi.CI.IGT: success for series starting with [1/2] drm/dp: add extended receiver capability field present bit

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: add extended receiver capability field present bit
URL   : https://patchwork.freedesktop.org/series/46743/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4503_full -> Patchwork_9700_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_9700_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_9700_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_9700_full:

  === IGT changes ===

    ==== Warnings ====

    igt@gem_exec_schedule@deep-bsd1:
      shard-kbl:          PASS -> SKIP

    igt@gem_exec_schedule@deep-bsd2:
      shard-kbl:          SKIP -> PASS +3

    igt@kms_cursor_crc@cursor-64x64-offscreen:
      shard-snb:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_9700_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_cursor_legacy@cursor-vs-flip-atomic-transitions:
      shard-hsw:          PASS -> FAIL (fdo#103355)

    igt@kms_flip@2x-plain-flip-ts-check:
      shard-glk:          PASS -> FAIL (fdo#103928)

    igt@kms_frontbuffer_tracking@fbc-suspend:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#105959)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@perf@blocking:
      shard-hsw:          PASS -> FAIL (fdo#102252)

    
    ==== Possible fixes ====

    igt@gem_exec_big:
      shard-hsw:          INCOMPLETE (fdo#103540) -> PASS
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@gem_exec_suspend@basic-s3:
      shard-apl:          FAIL (fdo#103375) -> PASS

    igt@kms_flip@flip-vs-expired-vblank-interruptible:
      shard-apl:          FAIL (fdo#102887, fdo#105363) -> PASS

    igt@kms_flip@plain-flip-ts-check-interruptible:
      shard-glk:          FAIL (fdo#100368) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
  fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252
  fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103375 https://bugs.freedesktop.org/show_bug.cgi?id=103375
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103928 https://bugs.freedesktop.org/show_bug.cgi?id=103928
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4503 -> Patchwork_9700

  CI_DRM_4503: 4aa6797dfafaf527949bf55d3c8513c6902dfec2 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4562: 8781fd89a63eabed9359d02b50583cca67ff3673 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_9700: 6351900d2b26ce7eea809c251ac5334162954d8d @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9700/shards.html
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Re: [PATCH 1/2] drm/dp: add extended receiver capability field present bit

[Rodrigo Vivi]

On Tue, Jul 17, 2018 at 02:49:38PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> This bit was added to DP Training Aux RD interval sometime between DP
> 1.2 and DP 1.3. Via description of the spec this field indicates the
> panels true capabilities are described in DPCD address space 02200h
> through 022FFh.
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c01564991a9f..757bd5913f3d 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -123,8 +123,9 @@
>  # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
>  
> -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* XXX 1.2? */
> +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* XXX 1.2? */

I couldn't find this on 1.2 version. So 1.3?!

>  
>  #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
>  # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
> -- 
> 2.17.1
> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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[PATCH 1/2] drm/dp: add extended receiver capability field present bit

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

This bit was added to DP Training Aux RD interval sometime between DP
1.2 and DP 1.3. Via description of the spec this field indicates the
panels true capabilities are described in DPCD address space 02200h
through 022FFh.

v2: version comment update

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 include/drm/drm_dp_helper.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
index c01564991a9f..28061c69136b 100644
--- a/include/drm/drm_dp_helper.h
+++ b/include/drm/drm_dp_helper.h
@@ -123,8 +123,9 @@
 # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
 # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
 
-#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
-# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
+#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
+# define DP_TRAINING_AUX_RD_MASK                0x7F    /* XXX 1.3? */
+# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* XXX 1.3? */
 
 #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
 # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
-- 
2.17.1

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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.

v3: white space fixes

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
 1 file changed, 37 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..a31fbbbd7954 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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Re: [PATCH 1/2] drm/dp: add extended receiver capability field present bit

[Rodrigo Vivi]

On Thu, Jul 19, 2018 at 01:35:48PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> This bit was added to DP Training Aux RD interval sometime between DP
> 1.2 and DP 1.3.

I understand that some 1.2 version that I had here that caused
all the trouble around XXX 1.2, but since one of the requests
from Jani was to clarify and remove the 1.2 I went there to check
again and that version that I had here doesn't work anymore.

So I went to VESA site and checked and it is not there on latest
official 1.2a.
It is there on 1.3.

This message should be updated now.

> Via description of the spec this field indicates the
> panels true capabilities are described in DPCD address space 02200h
> through 022FFh.
> 
> v2: version comment update
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  include/drm/drm_dp_helper.h | 5 +++--
>  1 file changed, 3 insertions(+), 2 deletions(-)
> 
> diff --git a/include/drm/drm_dp_helper.h b/include/drm/drm_dp_helper.h
> index c01564991a9f..28061c69136b 100644
> --- a/include/drm/drm_dp_helper.h
> +++ b/include/drm/drm_dp_helper.h
> @@ -123,8 +123,9 @@
>  # define DP_FRAMING_CHANGE_CAP		    (1 << 1)
>  # define DP_DPCD_DISPLAY_CONTROL_CAPABLE     (1 << 3) /* edp v1.2 or higher */
>  
> -#define DP_TRAINING_AUX_RD_INTERVAL         0x00e   /* XXX 1.2? */
> -# define DP_TRAINING_AUX_RD_MASK            0x7F    /* XXX 1.2? */
> +#define DP_TRAINING_AUX_RD_INTERVAL             0x00e   /* XXX 1.2? */
> +# define DP_TRAINING_AUX_RD_MASK                0x7F    /* XXX 1.3? */
> +# define DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT (1 << 7)/* XXX 1.3? */

Since that is the official and clear thing we should now remove XXX
and add /* DP 1.3 */

I believe that during 1.2 times we might had seen a lot of those
bizare cases when one version has it and another doesn't, and probably
that was the cause of many /* XXX 1.2? */ we have on the driver.

But please note that there is no XXX for 1.3 and 1.4, since things
are very clear and organized.

>  
>  #define DP_ADAPTER_CAP			    0x00f   /* 1.2 */
>  # define DP_FORCE_LOAD_SENSE_CAP	    (1 << 0)
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> 
> v3: white space fixes
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 37 +++++++++++++++++++++++++++++++++
>  1 file changed, 37 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..a31fbbbd7954 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  

We never know what vendors can do with reserved bits. We should never assume
they are zero. So we shouldn't do any of below unless it is newer than DP 1.3.

> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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✗ Fi.CI.BAT: failure for series starting with [1/2] drm/dp: add extended receiver capability field present bit (rev3)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/dp: add extended receiver capability field present bit (rev3)
URL   : https://patchwork.freedesktop.org/series/46743/
State : failure

== Summary ==

Applying: drm/dp: add extended receiver capability field present bit
Applying: drm/dp: add extended receiver capability field present bit
Using index info to reconstruct a base tree...
M	include/drm/drm_dp_helper.h
Falling back to patching base and 3-way merge...
Auto-merging include/drm/drm_dp_helper.h
CONFLICT (content): Merge conflict in include/drm/drm_dp_helper.h
error: Failed to merge in the changes.
Patch failed at 0002 drm/dp: add extended receiver capability field present bit
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".

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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Atwood, Matthew S]

On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com
> wrote:
> > From: Matt Atwood <matthew.s.atwood@intel.com>
> > 
> > According to DP spec (2.9.3.1 of DP 1.4) if
> > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > DPCD
> > 02200h through 0220Fh shall contain the DPRX's true capability.
> > These
> > values will match 00000h through 0000Fh, except for DPCD_REV,
> > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > 
> > Read from DPCD once for all 3 values as this is an expensive
> > operation.
> > Spec mentions that all of address space 02200h through 0220Fh
> > should
> > contain the right information however currently only 3 values can
> > differ.
> > 
> > There is no address space in the intel_dp->dpcd struct for
> > addresses
> > 02200h through 0220Fh, and since so much of the data is a
> > identical,
> > simply overwrite the values stored in 00000h through 0000Fh with
> > the
> > values that can be overwritten from addresses 02200h through
> > 0220Fh.
> > 
> > This patch helps with backward compatibility for devices pre DP1.3.
> > 
> > v2: read only dpcd values which can be affected, remove incorrect
> > check,
> > split into drm include changes into separate patch, commit message,
> > verbose debugging statements during overwrite.
> > 
> > v3: white space fixes
> > 
> > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_dp.c | 37
> > +++++++++++++++++++++++++++++++++
> >  1 file changed, 37 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > b/drivers/gpu/drm/i915/intel_dp.c
> > index dde92e4af5d3..a31fbbbd7954 100644
> > --- a/drivers/gpu/drm/i915/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp
> > *intel_dp)
> >  			     sizeof(intel_dp->dpcd)) < 0)
> >  		return false; /* aux transfer failed */
> >  
> 
> We never know what vendors can do with reserved bits. We should never
> assume
> they are zero. So we shouldn't do any of below unless it is newer
> than DP 1.3.
I think you mean newer than DP1.2?
> 
> > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > +		uint8_t dpcd_ext[6];
> > +
> > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > Field Present, accessing 02200h through 022FFh\n");
> > +
> > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > DP_DP13_DPCD_REV,
> > +				     &dpcd_ext, sizeof(dpcd_ext))
> > < 0)
> > +			return false; /* aux transfer failed */
> > +
> > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > &dpcd_ext[DP_DPCD_REV],
> > +			   sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Revision previous value %2x new value %2x\n",
> > +				      intel_dp->dpcd[DP_DPCD_REV],
> > +				      dpcd_ext[DP_DPCD_REV]);
> > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > +			       &dpcd_ext[DP_DPCD_REV],
> > +			       sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			   &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Max Link Rate previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_MAX_LINK_RATE],
> > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > sizeof(u8));
> > +		}
> > +		if (memcmp(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > sizeof(u8))) {
> > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > Downstream Port Present  previous value %2x new value %2x\n",
> > +				      intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +				      dpcd_ext[DP_DOWNSTREAMPORT_P
> > RESENT]);
> > +			memcpy(&intel_dp-
> > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT
> > ],
> > +			       sizeof(u8));
> > +		}
> > +	}
> >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > >dpcd), intel_dp->dpcd);
> >  
> >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > -- 
> > 2.17.1
> > 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Thu, Jul 19, 2018 at 02:47:59PM -0700, Atwood, Matthew S wrote:
> On Thu, 2018-07-19 at 14:07 -0700, Rodrigo Vivi wrote:
> > On Thu, Jul 19, 2018 at 01:35:49PM -0700, matthew.s.atwood@intel.com
> > wrote:
> > > From: Matt Atwood <matthew.s.atwood@intel.com>
> > > 
> > > According to DP spec (2.9.3.1 of DP 1.4) if
> > > EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in
> > > DPCD
> > > 02200h through 0220Fh shall contain the DPRX's true capability.
> > > These
> > > values will match 00000h through 0000Fh, except for DPCD_REV,
> > > MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> > > 
> > > Read from DPCD once for all 3 values as this is an expensive
> > > operation.
> > > Spec mentions that all of address space 02200h through 0220Fh
> > > should
> > > contain the right information however currently only 3 values can
> > > differ.
> > > 
> > > There is no address space in the intel_dp->dpcd struct for
> > > addresses
> > > 02200h through 0220Fh, and since so much of the data is a
> > > identical,
> > > simply overwrite the values stored in 00000h through 0000Fh with
> > > the
> > > values that can be overwritten from addresses 02200h through
> > > 0220Fh.
> > > 
> > > This patch helps with backward compatibility for devices pre DP1.3.
> > > 
> > > v2: read only dpcd values which can be affected, remove incorrect
> > > check,
> > > split into drm include changes into separate patch, commit message,
> > > verbose debugging statements during overwrite.
> > > 
> > > v3: white space fixes
> > > 
> > > Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_dp.c | 37
> > > +++++++++++++++++++++++++++++++++
> > >  1 file changed, 37 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_dp.c
> > > b/drivers/gpu/drm/i915/intel_dp.c
> > > index dde92e4af5d3..a31fbbbd7954 100644
> > > --- a/drivers/gpu/drm/i915/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/intel_dp.c
> > > @@ -3738,6 +3738,43 @@ intel_dp_read_dpcd(struct intel_dp
> > > *intel_dp)
> > >  			     sizeof(intel_dp->dpcd)) < 0)
> > >  		return false; /* aux transfer failed */
> > >  
> > 
> > We never know what vendors can do with reserved bits. We should never
> > assume
> > they are zero. So we shouldn't do any of below unless it is newer
> > than DP 1.3.
> I think you mean newer than DP1.2?

yeap, sorry..

>= DP1.3

> > 
> > > +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> > > +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> > > +		uint8_t dpcd_ext[6];
> > > +
> > > +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability
> > > Field Present, accessing 02200h through 022FFh\n");
> > > +
> > > +		if (drm_dp_dpcd_read(&intel_dp->aux,
> > > DP_DP13_DPCD_REV,
> > > +				     &dpcd_ext, sizeof(dpcd_ext))
> > > < 0)
> > > +			return false; /* aux transfer failed */
> > > +
> > > +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV],
> > > &dpcd_ext[DP_DPCD_REV],
> > > +			   sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Revision previous value %2x new value %2x\n",
> > > +				      intel_dp->dpcd[DP_DPCD_REV],
> > > +				      dpcd_ext[DP_DPCD_REV]);
> > > +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> > > +			       &dpcd_ext[DP_DPCD_REV],
> > > +			       sizeof(u8));
> > > +		}
> > > +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > > +			   &dpcd_ext[DP_MAX_LINK_RATE],
> > > sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Max Link Rate previous value %2x new value %2x\n",
> > > +				      intel_dp-
> > > >dpcd[DP_MAX_LINK_RATE],
> > > +				      dpcd_ext[DP_MAX_LINK_RATE]);
> > > +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> > > +			       &dpcd_ext[DP_MAX_LINK_RATE],
> > > sizeof(u8));
> > > +		}
> > > +		if (memcmp(&intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> > > sizeof(u8))) {
> > > +			DRM_DEBUG_KMS("DPCD: new value for DPCD
> > > Downstream Port Present  previous value %2x new value %2x\n",
> > > +				      intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +				      dpcd_ext[DP_DOWNSTREAMPORT_P
> > > RESENT]);
> > > +			memcpy(&intel_dp-
> > > >dpcd[DP_DOWNSTREAMPORT_PRESENT],
> > > +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT
> > > ],
> > > +			       sizeof(u8));
> > > +		}
> > > +	}
> > >  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp-
> > > >dpcd), intel_dp->dpcd);
> > >  
> > >  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> > > -- 
> > > 2.17.1
> > > 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Mon, Jul 23, 2018 at 02:27:35PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> v5: split into function, removed DPCD rev check
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..ed16b93bfe40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void
> +intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
> +{
> +	/*
> +	 * Prior to DP1.3 the bit represented by
> +	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
> +	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
> +	 * the true capability of the panel. The only way to check is to
> +	 * then compare 0000h and 2200h.
> +	 */
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return;
> +
> +		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])
> +			return;

I'm still missing the debug messages here and above... 

> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
> +}
> +
> +
>  bool
>  intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  {
> @@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	intel_dp_extended_receiver_capabilities(intel_dp);
> +
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Mon, Jul 23, 2018 at 02:27:35PM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> v5: split into function, removed DPCD rev check
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..ed16b93bfe40 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
>  	}
>  }
>  
> +static void
> +intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
> +{
> +	/*
> +	 * Prior to DP1.3 the bit represented by
> +	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
> +	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
> +	 * the true capability of the panel. The only way to check is to
> +	 * then compare 0000h and 2200h.
> +	 */
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)

DRM_ERROR

> +			return;
> +
> +		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])

DRM_DEBUG_KMS
> +			return;

The silent skip will be hard to debug and we will never know where it went
wrong.

> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
> +}
> +
> +
>  bool
>  intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  {
> @@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	intel_dp_extended_receiver_capabilities(intel_dp);
> +
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
> _______________________________________________
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> dri-devel@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/dri-devel
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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.
v3: white space fixes
v4: make path dependent on DPCD revision > 1.2
v5: split into function, removed DPCD rev check

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 54 +++++++++++++++++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..ed16b93bfe40 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3731,6 +3731,58 @@ intel_dp_link_down(struct intel_encoder *encoder,
 	}
 }
 
+static void
+intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp)
+{
+	/*
+	 * Prior to DP1.3 the bit represented by
+	 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved.
+	 * if it is set DP_DPCD_REV at 0000h could be at a value less than
+	 * the true capability of the panel. The only way to check is to
+	 * then compare 0000h and 2200h.
+	 */
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return;
+
+		if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV])
+			return;
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
+}
+
+
 bool
 intel_dp_read_dpcd(struct intel_dp *intel_dp)
 {
@@ -3738,6 +3790,8 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	intel_dp_extended_receiver_capabilities(intel_dp);
+
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Manasi Navare]

On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..9d7e1d0b1487 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> +	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {

Like I had mentioned earlier, this check for DP_DPCD_REV is not required infact
if the extended reciever cap field is present its likely that the correct REV is present in the different offset
and the original DP_DPCD_REV indicates the legacy or older REV number. This is waht i observed when I tested this earlier
on DP 1.4 sink and had to remove this REV check since the original REV register was advertising it as DP 1.1 sink.

Manasi

> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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Re: [PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[Rodrigo Vivi]

On Fri, Jul 20, 2018 at 09:18:12AM -0700, matthew.s.atwood@intel.com wrote:
> From: Matt Atwood <matthew.s.atwood@intel.com>
> 
> According to DP spec (2.9.3.1 of DP 1.4) if
> EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
> 02200h through 0220Fh shall contain the DPRX's true capability. These
> values will match 00000h through 0000Fh, except for DPCD_REV,
> MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.
> 
> Read from DPCD once for all 3 values as this is an expensive operation.
> Spec mentions that all of address space 02200h through 0220Fh should
> contain the right information however currently only 3 values can
> differ.
> 
> There is no address space in the intel_dp->dpcd struct for addresses
> 02200h through 0220Fh, and since so much of the data is a identical,
> simply overwrite the values stored in 00000h through 0000Fh with the
> values that can be overwritten from addresses 02200h through 0220Fh.
> 
> This patch helps with backward compatibility for devices pre DP1.3.
> 
> v2: read only dpcd values which can be affected, remove incorrect check,
> split into drm include changes into separate patch, commit message,
> verbose debugging statements during overwrite.
> v3: white space fixes
> v4: make path dependent on DPCD revision > 1.2
> 
> Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
> ---
>  drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index dde92e4af5d3..9d7e1d0b1487 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
>  			     sizeof(intel_dp->dpcd)) < 0)
>  		return false; /* aux transfer failed */
>  
> +	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
> +	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
> +	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {

wrong order... you don't need to read those bits if ! rev >= 1.3

> +		uint8_t dpcd_ext[6];
> +
> +		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
> +
> +		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
> +				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
> +			return false; /* aux transfer failed */
> +
> +		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
> +			   sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DPCD_REV],
> +				      dpcd_ext[DP_DPCD_REV]);
> +			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
> +			       &dpcd_ext[DP_DPCD_REV],
> +			       sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_MAX_LINK_RATE],
> +				      dpcd_ext[DP_MAX_LINK_RATE]);
> +			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
> +			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
> +		}
> +		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
> +			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
> +				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
> +			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
> +			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
> +			       sizeof(u8));
> +		}
> +	}
>  	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
>  
>  	return intel_dp->dpcd[DP_DPCD_REV] != 0;
> -- 
> 2.17.1
> 
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[PATCH 2/2] drm/i915: implement EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT

[matthew.s.atwood]

From: Matt Atwood <matthew.s.atwood@intel.com>

According to DP spec (2.9.3.1 of DP 1.4) if
EXTENDED_RECEIVER_CAPABILITY_FIELD_PRESENT is set the addresses in DPCD
02200h through 0220Fh shall contain the DPRX's true capability. These
values will match 00000h through 0000Fh, except for DPCD_REV,
MAX_LINK_RATE, DOWN_STREAM_PORT_PRESENT.

Read from DPCD once for all 3 values as this is an expensive operation.
Spec mentions that all of address space 02200h through 0220Fh should
contain the right information however currently only 3 values can
differ.

There is no address space in the intel_dp->dpcd struct for addresses
02200h through 0220Fh, and since so much of the data is a identical,
simply overwrite the values stored in 00000h through 0000Fh with the
values that can be overwritten from addresses 02200h through 0220Fh.

This patch helps with backward compatibility for devices pre DP1.3.

v2: read only dpcd values which can be affected, remove incorrect check,
split into drm include changes into separate patch, commit message,
verbose debugging statements during overwrite.
v3: white space fixes
v4: make path dependent on DPCD revision > 1.2

Signed-off-by: Matt Atwood <matthew.s.atwood@intel.com>
---
 drivers/gpu/drm/i915/intel_dp.c | 38 +++++++++++++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index dde92e4af5d3..9d7e1d0b1487 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3738,6 +3738,44 @@ intel_dp_read_dpcd(struct intel_dp *intel_dp)
 			     sizeof(intel_dp->dpcd)) < 0)
 		return false; /* aux transfer failed */
 
+	if (intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] &
+	    DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT &&
+	    intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_13) {
+		uint8_t dpcd_ext[6];
+
+		DRM_DEBUG_KMS("DPCD: Extended Receiver Capability Field Present, accessing 02200h through 022FFh\n");
+
+		if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV,
+				     &dpcd_ext, sizeof(dpcd_ext)) < 0)
+			return false; /* aux transfer failed */
+
+		if (memcmp(&intel_dp->dpcd[DP_DPCD_REV], &dpcd_ext[DP_DPCD_REV],
+			   sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Revision previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DPCD_REV],
+				      dpcd_ext[DP_DPCD_REV]);
+			memcpy(&intel_dp->dpcd[DP_DPCD_REV],
+			       &dpcd_ext[DP_DPCD_REV],
+			       sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			   &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Max Link Rate previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_MAX_LINK_RATE],
+				      dpcd_ext[DP_MAX_LINK_RATE]);
+			memcpy(&intel_dp->dpcd[DP_MAX_LINK_RATE],
+			       &dpcd_ext[DP_MAX_LINK_RATE], sizeof(u8));
+		}
+		if (memcmp(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			   &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT], sizeof(u8))) {
+			DRM_DEBUG_KMS("DPCD: new value for DPCD Downstream Port Present  previous value %2x new value %2x\n",
+				      intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+				      dpcd_ext[DP_DOWNSTREAMPORT_PRESENT]);
+			memcpy(&intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT],
+			       &dpcd_ext[DP_DOWNSTREAMPORT_PRESENT],
+			       sizeof(u8));
+		}
+	}
 	DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
 
 	return intel_dp->dpcd[DP_DPCD_REV] != 0;
-- 
2.17.1

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