[U-Boot] [PATCH V2 25/32] clk: imx: add clk driver for i.MX8QXP

[Peng Fan <peng.fan@nxp.com>]

Add clk driver for i.MX8QXP, support clk
enable/disable/get_rate/set_rate operations.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 drivers/clk/Kconfig        |   1 +
 drivers/clk/Makefile       |   1 +
 drivers/clk/imx/Kconfig    |   6 ++
 drivers/clk/imx/Makefile   |   5 ++
 drivers/clk/imx/clk-imx8.c | 212 +++++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 225 insertions(+)
 create mode 100644 drivers/clk/imx/Kconfig
 create mode 100644 drivers/clk/imx/Makefile
 create mode 100644 drivers/clk/imx/clk-imx8.c

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 18bf8a6d28..c2f2a99b40 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -86,6 +86,7 @@ config CLK_STM32MP1
 source "drivers/clk/tegra/Kconfig"
 source "drivers/clk/uniphier/Kconfig"
 source "drivers/clk/exynos/Kconfig"
+source "drivers/clk/imx/Kconfig"
 source "drivers/clk/at91/Kconfig"
 source "drivers/clk/renesas/Kconfig"
 source "drivers/clk/mvebu/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index 146283c723..2a3c83b597 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -8,6 +8,7 @@
 obj-$(CONFIG_$(SPL_TPL_)CLK) += clk-uclass.o clk_fixed_rate.o
 
 obj-y += tegra/
+obj-y += imx/
 obj-$(CONFIG_ARCH_ASPEED) += aspeed/
 obj-$(CONFIG_ARCH_MESON) += clk_meson.o
 obj-$(CONFIG_ARCH_ROCKCHIP) += rockchip/
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
new file mode 100644
index 0000000000..a6fb58d6cf
--- /dev/null
+++ b/drivers/clk/imx/Kconfig
@@ -0,0 +1,6 @@
+config CLK_IMX8
+	bool "Clock support for i.MX8"
+	depends on ARCH_IMX8
+	select CLK
+	help
+	  This enables support clock driver for i.MX8 platforms.
diff --git a/drivers/clk/imx/Makefile b/drivers/clk/imx/Makefile
new file mode 100644
index 0000000000..5505ae52e2
--- /dev/null
+++ b/drivers/clk/imx/Makefile
@@ -0,0 +1,5 @@
+# Copyright 2018 NXP
+#
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_CLK_IMX8) += clk-imx8.o
diff --git a/drivers/clk/imx/clk-imx8.c b/drivers/clk/imx/clk-imx8.c
new file mode 100644
index 0000000000..ba87ad6964
--- /dev/null
+++ b/drivers/clk/imx/clk-imx8.c
@@ -0,0 +1,212 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright 2018 NXP
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <asm/arch/sci/sci.h>
+#include <asm/arch/clock.h>
+#include <dt-bindings/clock/imx8qxp-clock.h>
+#include <dt-bindings/soc/imx_rsrc.h>
+#include <misc.h>
+
+static ulong imx8_clk_get_rate(struct clk *clk)
+{
+	sc_pm_clk_t pm_clk;
+	ulong rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%ld)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QXP_A35_DIV:
+		resource = SC_R_A35;
+		pm_clk = SC_PM_CLK_CPU;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART0_IPG_CLK:
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		dev_err(dev, "%s(Invalid #%ld)\n", __func__, clk->id);
+		return -EINVAL;
+	};
+
+	ret = sc_pm_get_clock_rate(-1, resource, pm_clk,
+				   (sc_pm_clock_rate_t *)&rate);
+	if (ret)
+		printf("%s err %d\n", __func__, ret);
+
+	return rate;
+}
+
+static ulong imx8_clk_set_rate(struct clk *clk, unsigned long rate)
+{
+	sc_pm_clk_t pm_clk;
+	u32 new_rate = rate;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%ld), rate: %lu\n", __func__, clk->id, rate);
+
+	switch (clk->id) {
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_SEL:
+	case IMX8QXP_SDHC0_SEL:
+		return 0;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		printf("%s %ld\n", __func__, clk->id);
+		return -EINVAL;
+	};
+
+	ret = sc_pm_set_clock_rate(-1, resource, pm_clk, &new_rate);
+	if (ret)
+		printf("%s err %d\n", __func__, ret);
+
+	return new_rate;
+}
+
+static int __imx8_clk_enable(struct clk *clk, bool enable)
+{
+	sc_pm_clk_t pm_clk;
+	u16 resource;
+	int ret;
+
+	debug("%s(#%ld)\n", __func__, clk->id);
+
+	switch (clk->id) {
+	case IMX8QXP_I2C0_CLK:
+		resource = SC_R_I2C_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C1_CLK:
+		resource = SC_R_I2C_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C2_CLK:
+		resource = SC_R_I2C_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_I2C3_CLK:
+		resource = SC_R_I2C_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART0_CLK:
+		resource = SC_R_UART_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART1_CLK:
+		resource = SC_R_UART_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART2_CLK:
+		resource = SC_R_UART_2;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_UART3_CLK:
+		resource = SC_R_UART_3;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC0_IPG_CLK:
+	case IMX8QXP_SDHC0_CLK:
+	case IMX8QXP_SDHC0_DIV:
+		resource = SC_R_SDHC_0;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	case IMX8QXP_SDHC1_IPG_CLK:
+	case IMX8QXP_SDHC1_CLK:
+	case IMX8QXP_SDHC1_DIV:
+		resource = SC_R_SDHC_1;
+		pm_clk = SC_PM_CLK_PER;
+		break;
+	default:
+		printf("%s not valid resource\n", __func__);
+		return -EINVAL;
+	}
+
+	ret = sc_pm_clock_enable(-1, resource, pm_clk, enable, 0);
+	if (ret)
+		printf("%s err %d\n", __func__, ret);
+
+	return ret;
+}
+
+static int imx8_clk_disable(struct clk *clk)
+{
+	return __imx8_clk_enable(clk, 0);
+}
+
+static int imx8_clk_enable(struct clk *clk)
+{
+	return __imx8_clk_enable(clk, 1);
+}
+
+static struct clk_ops imx8_clk_ops = {
+	.set_rate = imx8_clk_set_rate,
+	.get_rate = imx8_clk_get_rate,
+	.enable = imx8_clk_enable,
+	.disable = imx8_clk_disable,
+};
+
+static int imx8_clk_probe(struct udevice *dev)
+{
+	return 0;
+}
+
+static const struct udevice_id imx8_clk_ids[] = {
+	{ .compatible = "fsl,imx8qxp-clk" },
+	{ },
+};
+
+U_BOOT_DRIVER(imx8_clk) = {
+	.name = "clk_imx8",
+	.id = UCLASS_CLK,
+	.of_match = imx8_clk_ids,
+	.ops = &imx8_clk_ops,
+	.probe = imx8_clk_probe,
+	.flags = DM_FLAG_PRE_RELOC,
+};
-- 
2.14.1