* [PATCH 00/18] drm/i915: GTT remapping for display
@ 2018-07-19 18:21 Ville Syrjala
2018-07-19 18:21 ` [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175 Ville Syrjala
` (25 more replies)
0 siblings, 26 replies; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display engine has unfortunately low stride limits when compared to
modern display resolutions. 2x4k is about as big as we can go currently.
This series aims to overcome that by shuffling the pages in the GTT to
provide the display engine with a view of memory with a smaller stride.
We pretty much had all the code already on account of rotation and
whatnot, just had to massage the surroundings a bit. Strictly speaking
I could probably drop most of the plane check() refactoring patches from
this without affecting the outcome, but things kept bugging me all the
time so naturally I had to change them.
Entire series is available here:
git://github.com/vsyrjala/linux.git fb_vma_remap_6
Ville Syrjälä (18):
drm/i915: Fix glk/cnl display w/a #1175
drm/i915: s/tile_offset/aligned_offset/
drm/i915: Add .max_stride() plane hook
drm/i915: Use pipe A primary plane .max_stride() as the global stride
limit
drm/i915: Rename the plane_state->main/aux to
plane_state->color_plane[]
drm/i915: Store the final plane stride in plane_state
drm/i915: Store ggtt_view in plane_state
drm/i915: s/int plane/int color_plane/
drm/i915: Nuke plane->can_scale/min_downscale
drm/i915: Extract per-platform plane->check() functions
drm/i915: Move skl plane fb related checks into a better place
drm/i915: Move display w/a #1175
drm/i915: Move chv rotation checks to plane->check()
drm/i915: Extract intel_cursor_check_surface()
drm/i915: Add a new "remapped" gtt_view
drm/i915: Overcome display engine stride limits via GTT remapping
drm/i915: Bump gen4+ fb stride limit to 256KiB
drm/i915: Bump gen4+ fb size limits to 32kx32k
drivers/gpu/drm/i915/i915_debugfs.c | 12 +
drivers/gpu/drm/i915/i915_gem_gtt.c | 91 +++
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +
drivers/gpu/drm/i915/i915_vma.c | 6 +-
drivers/gpu/drm/i915/i915_vma.h | 5 +-
drivers/gpu/drm/i915/intel_atomic_plane.c | 53 +-
drivers/gpu/drm/i915/intel_display.c | 969 +++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 51 +-
drivers/gpu/drm/i915/intel_fbc.c | 4 +-
drivers/gpu/drm/i915/intel_fbdev.c | 6 +-
drivers/gpu/drm/i915/intel_sprite.c | 495 ++++++++++-----
11 files changed, 1138 insertions(+), 570 deletions(-)
--
2.16.4
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
@ 2018-07-19 18:21 ` Ville Syrjala
2018-07-20 10:55 ` Imre Deak
2018-07-19 18:21 ` [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/ Ville Syrjala
` (24 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The workaround was supposed to look at the plane destination
coordinates. Currently it's looking at some mixture of src
and dst coordinates that doesn't make sense. Fix it up.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 7 ++++---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 87e4cfbfd096..8efff0c56920 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2988,6 +2988,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
int w = drm_rect_width(&plane_state->base.src) >> 16;
int h = drm_rect_height(&plane_state->base.src) >> 16;
int dst_x = plane_state->base.dst.x1;
+ int dst_w = drm_rect_width(&plane_state->base.dst);
int pipe_src_w = crtc_state->pipe_src_w;
int max_width = skl_max_plane_width(fb, 0, rotation);
int max_height = 4096;
@@ -3009,10 +3010,10 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
* screen may cause FIFO underflow and display corruption.
*/
if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
+ (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
- dst_x + w < 4 ? "end" : "start",
- dst_x + w < 4 ? dst_x + w : dst_x,
+ dst_x + dst_w < 4 ? "end" : "start",
+ dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
4, pipe_src_w - 4);
return -ERANGE;
}
--
2.16.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
2018-07-19 18:21 ` [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175 Ville Syrjala
@ 2018-07-19 18:21 ` Ville Syrjala
2018-08-22 21:55 ` Souza, Jose
2018-07-19 18:21 ` [PATCH 03/18] drm/i915: Add .max_stride() plane hook Ville Syrjala
` (23 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Rename some of the tile_offset() functions to aligned_offset() since
they operate on both linear and tiled functions. And we'll include
_plane_ in the name of all the variants that take a plane state.
Should make it more clear which function to use where.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 123 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_drv.h | 2 -
2 files changed, 63 insertions(+), 62 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8efff0c56920..5f8304a11482 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2229,13 +2229,13 @@ void intel_add_fb_offsets(int *x, int *y,
}
}
-static u32 __intel_adjust_tile_offset(int *x, int *y,
- unsigned int tile_width,
- unsigned int tile_height,
- unsigned int tile_size,
- unsigned int pitch_tiles,
- u32 old_offset,
- u32 new_offset)
+static u32 intel_adjust_tile_offset(int *x, int *y,
+ unsigned int tile_width,
+ unsigned int tile_height,
+ unsigned int tile_size,
+ unsigned int pitch_tiles,
+ u32 old_offset,
+ u32 new_offset)
{
unsigned int pitch_pixels = pitch_tiles * tile_width;
unsigned int tiles;
@@ -2256,12 +2256,12 @@ static u32 __intel_adjust_tile_offset(int *x, int *y,
return new_offset;
}
-static u32 _intel_adjust_tile_offset(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int rotation,
- u32 old_offset, u32 new_offset)
+static u32 intel_adjust_aligned_offset(int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int rotation,
+ u32 old_offset, u32 new_offset)
{
- const struct drm_i915_private *dev_priv = to_i915(fb->dev);
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int cpp = fb->format->cpp[plane];
unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
@@ -2281,9 +2281,9 @@ static u32 _intel_adjust_tile_offset(int *x, int *y,
pitch_tiles = pitch / (tile_width * cpp);
}
- __intel_adjust_tile_offset(x, y, tile_width, tile_height,
- tile_size, pitch_tiles,
- old_offset, new_offset);
+ intel_adjust_tile_offset(x, y, tile_width, tile_height,
+ tile_size, pitch_tiles,
+ old_offset, new_offset);
} else {
old_offset += *y * pitch + *x * cpp;
@@ -2298,17 +2298,18 @@ static u32 _intel_adjust_tile_offset(int *x, int *y,
* Adjust the tile offset by moving the difference into
* the x/y offsets.
*/
-static u32 intel_adjust_tile_offset(int *x, int *y,
- const struct intel_plane_state *state, int plane,
- u32 old_offset, u32 new_offset)
+static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
+ const struct intel_plane_state *state,
+ int plane,
+ u32 old_offset, u32 new_offset)
{
- return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
- state->base.rotation,
- old_offset, new_offset);
+ return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
+ state->base.rotation,
+ old_offset, new_offset);
}
/*
- * Computes the linear offset to the base tile and adjusts
+ * Computes the aligned offset to the base tile and adjusts
* x, y. bytes per pixel is assumed to be a power-of-two.
*
* In the 90/270 rotated case, x and y are assumed
@@ -2321,12 +2322,12 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
* used. This is why the user has to pass in the pitch since it
* is specified in the rotated orientation.
*/
-static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
- int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
- unsigned int pitch,
- unsigned int rotation,
- u32 alignment)
+static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
+ int *x, int *y,
+ const struct drm_framebuffer *fb, int plane,
+ unsigned int pitch,
+ unsigned int rotation,
+ u32 alignment)
{
uint64_t fb_modifier = fb->modifier;
unsigned int cpp = fb->format->cpp[plane];
@@ -2358,9 +2359,9 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
offset = (tile_rows * pitch_tiles + tiles) * tile_size;
offset_aligned = offset & ~alignment;
- __intel_adjust_tile_offset(x, y, tile_width, tile_height,
- tile_size, pitch_tiles,
- offset, offset_aligned);
+ intel_adjust_tile_offset(x, y, tile_width, tile_height,
+ tile_size, pitch_tiles,
+ offset, offset_aligned);
} else {
offset = *y * pitch + *x * cpp;
offset_aligned = offset & ~alignment;
@@ -2372,9 +2373,9 @@ static u32 _intel_compute_tile_offset(const struct drm_i915_private *dev_priv,
return offset_aligned;
}
-u32 intel_compute_tile_offset(int *x, int *y,
- const struct intel_plane_state *state,
- int plane)
+static u32 intel_plane_compute_aligned_offset(int *x, int *y,
+ const struct intel_plane_state *state,
+ int plane)
{
struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
@@ -2388,8 +2389,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
else
alignment = intel_surf_alignment(fb, plane);
- return _intel_compute_tile_offset(dev_priv, x, y, fb, plane, pitch,
- rotation, alignment);
+ return intel_compute_aligned_offset(dev_priv, x, y, fb, plane,
+ pitch, rotation, alignment);
}
/* Convert the fb->offset[] into x/y offsets */
@@ -2405,9 +2406,9 @@ static int intel_fb_offset_to_xy(int *x, int *y,
*x = 0;
*y = 0;
- _intel_adjust_tile_offset(x, y,
- fb, plane, DRM_MODE_ROTATE_0,
- fb->offsets[plane], 0);
+ intel_adjust_aligned_offset(x, y,
+ fb, plane, DRM_MODE_ROTATE_0,
+ fb->offsets[plane], 0);
return 0;
}
@@ -2559,9 +2560,10 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
intel_fb->normal[i].x = x;
intel_fb->normal[i].y = y;
- offset = _intel_compute_tile_offset(dev_priv, &x, &y,
- fb, i, fb->pitches[i],
- DRM_MODE_ROTATE_0, tile_size);
+ offset = intel_compute_aligned_offset(dev_priv, &x, &y, fb, i,
+ fb->pitches[i],
+ DRM_MODE_ROTATE_0,
+ tile_size);
offset /= tile_size;
if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -2608,10 +2610,10 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
* We only keep the x/y offsets, so push all of the
* gtt offset into the x/y offsets.
*/
- __intel_adjust_tile_offset(&x, &y,
- tile_width, tile_height,
- tile_size, pitch_tiles,
- gtt_offset_rotated * tile_size, 0);
+ intel_adjust_tile_offset(&x, &y,
+ tile_width, tile_height,
+ tile_size, pitch_tiles,
+ gtt_offset_rotated * tile_size, 0);
gtt_offset_rotated += rot_info->plane[i].width * rot_info->plane[i].height;
@@ -2960,8 +2962,8 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
x = aux_x / hsub;
y = aux_y / vsub;
- aux_offset = intel_adjust_tile_offset(&x, &y, plane_state, 1,
- aux_offset, aux_offset - alignment);
+ aux_offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 1,
+ aux_offset, aux_offset - alignment);
aux_x = x * hsub + aux_x % hsub;
aux_y = y * vsub + aux_y % vsub;
}
@@ -3019,7 +3021,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
}
intel_add_fb_offsets(&x, &y, plane_state, 0);
- offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
alignment = intel_surf_alignment(fb, 0);
/*
@@ -3028,8 +3030,8 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
* sure that is what we will get.
*/
if (offset > aux_offset)
- offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
- offset, aux_offset & ~(alignment - 1));
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
+ offset, aux_offset & ~(alignment - 1));
/*
* When using an X-tiled surface, the plane blows up
@@ -3046,8 +3048,8 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
- offset, offset - alignment);
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
+ offset, offset - alignment);
}
}
@@ -3061,8 +3063,8 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
if (offset == 0)
break;
- offset = intel_adjust_tile_offset(&x, &y, plane_state, 0,
- offset, offset - alignment);
+ offset = intel_plane_adjust_aligned_offset(&x, &y, plane_state, 0,
+ offset, offset - alignment);
}
if (x != plane_state->aux.x || y != plane_state->aux.y) {
@@ -3114,7 +3116,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
u32 offset;
intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
/* FIXME not quite sure how/if these apply to the chroma plane */
if (w > max_width || h > max_height) {
@@ -3148,7 +3150,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
}
intel_add_fb_offsets(&x, &y, plane_state, 1);
- offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
+ offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
plane_state->aux.offset = offset;
plane_state->aux.x = x * hsub + src_x % hsub;
@@ -3281,8 +3283,8 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
- offset = intel_compute_tile_offset(&src_x, &src_y,
- plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
+ plane_state, 0);
else
offset = 0;
@@ -9657,7 +9659,8 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
src_y = plane_state->base.src_y >> 16;
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
- offset = intel_compute_tile_offset(&src_x, &src_y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
+ plane_state, 0);
if (src_x != 0 || src_y != 0) {
DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c275f91244a6..b9f6de3a8f53 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1604,8 +1604,6 @@ void assert_fdi_rx_pll(struct drm_i915_private *dev_priv,
void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, bool state);
#define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
#define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
-u32 intel_compute_tile_offset(int *x, int *y,
- const struct intel_plane_state *state, int plane);
void intel_prepare_reset(struct drm_i915_private *dev_priv);
void intel_finish_reset(struct drm_i915_private *dev_priv);
void hsw_enable_pc8(struct drm_i915_private *dev_priv);
--
2.16.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 03/18] drm/i915: Add .max_stride() plane hook
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
2018-07-19 18:21 ` [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175 Ville Syrjala
2018-07-19 18:21 ` [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/ Ville Syrjala
@ 2018-07-19 18:21 ` Ville Syrjala
2018-08-22 22:03 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit Ville Syrjala
` (22 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:21 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Each plane may have different stride limitations. Let's add a new
plane function to retutn the maximum stride for each plane. There's
going to be some use for this outside the .atomic_check() stuff hence
the separate hook.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 46 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_drv.h | 10 ++++++++
drivers/gpu/drm/i915/intel_sprite.c | 34 ++++++++++++++++++++++++--
3 files changed, 88 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5f8304a11482..a09e11e0596f 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3210,6 +3210,31 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
return 0;
}
+unsigned int
+i9xx_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+
+ if (INTEL_GEN(dev_priv) >= 4) {
+ if (modifier == I915_FORMAT_MOD_X_TILED)
+ return 16*1024;
+ else
+ return 32*1024;
+ } else if (INTEL_GEN(dev_priv) >= 3) {
+ if (modifier == I915_FORMAT_MOD_X_TILED)
+ return 8*1024;
+ else
+ return 16*1024;
+ } else {
+ if (plane->i9xx_plane == PLANE_C)
+ return 4*1024;
+ else
+ return 8*1024;
+ }
+}
+
static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -9672,6 +9697,14 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return 0;
}
+static unsigned int
+i845_cursor_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ return 2048;
+}
+
static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -9805,6 +9838,14 @@ static bool i845_cursor_get_hw_state(struct intel_plane *plane,
return ret;
}
+static unsigned int
+i9xx_cursor_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ return plane->base.dev->mode_config.cursor_width * 4;
+}
+
static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -13699,6 +13740,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
else
modifiers = skl_format_modifiers_noccs;
+ primary->max_stride = skl_plane_max_stride;
primary->update_plane = skl_update_plane;
primary->disable_plane = skl_disable_plane;
primary->get_hw_state = skl_plane_get_hw_state;
@@ -13709,6 +13751,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
num_formats = ARRAY_SIZE(i965_primary_formats);
modifiers = i9xx_format_modifiers;
+ primary->max_stride = i9xx_plane_max_stride;
primary->update_plane = i9xx_update_plane;
primary->disable_plane = i9xx_disable_plane;
primary->get_hw_state = i9xx_plane_get_hw_state;
@@ -13719,6 +13762,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
num_formats = ARRAY_SIZE(i8xx_primary_formats);
modifiers = i9xx_format_modifiers;
+ primary->max_stride = i9xx_plane_max_stride;
primary->update_plane = i9xx_update_plane;
primary->disable_plane = i9xx_disable_plane;
primary->get_hw_state = i9xx_plane_get_hw_state;
@@ -13826,11 +13870,13 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
+ cursor->max_stride = i845_cursor_max_stride;
cursor->update_plane = i845_update_cursor;
cursor->disable_plane = i845_disable_cursor;
cursor->get_hw_state = i845_cursor_get_hw_state;
cursor->check_plane = i845_check_cursor;
} else {
+ cursor->max_stride = i9xx_cursor_max_stride;
cursor->update_plane = i9xx_update_cursor;
cursor->disable_plane = i9xx_disable_cursor;
cursor->get_hw_state = i9xx_cursor_get_hw_state;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b9f6de3a8f53..ad2bd62ee553 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -963,6 +963,9 @@ struct intel_plane {
* the intel_plane_state structure and accessed via plane_state.
*/
+ unsigned int (*max_stride)(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation);
void (*update_plane)(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
@@ -1652,6 +1655,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
+unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation);
/* intel_csr.c */
void intel_csr_ucode_init(struct drm_i915_private *);
@@ -2102,6 +2108,10 @@ bool skl_plane_has_ccs(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
enum pipe pipe, enum plane_id plane_id);
+unsigned int skl_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation);
+
/* intel_tv.c */
void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f7026e887fa9..e35760814f25 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -228,6 +228,23 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
#endif
}
+unsigned int
+skl_plane_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ int cpp = drm_format_plane_cpp(pixel_format, 0);
+
+ /*
+ * "The stride in bytes must not exceed the
+ * of the size of 8K pixels and 32K bytes."
+ */
+ if (drm_rotation_90_or_270(rotation))
+ return min(8192, 32768 / cpp);
+ else
+ return min(8192 * cpp, 32768);
+}
+
void
skl_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
@@ -798,6 +815,14 @@ ivb_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
+static unsigned int
+g4x_sprite_max_stride(struct intel_plane *plane,
+ u32 pixel_format, u64 modifier,
+ unsigned int rotation)
+{
+ return 16384;
+}
+
static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
@@ -964,7 +989,6 @@ intel_check_sprite_plane(struct intel_plane *plane,
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = state->base.fb;
- int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
int max_scale, min_scale;
bool can_scale;
int ret;
@@ -982,7 +1006,9 @@ intel_check_sprite_plane(struct intel_plane *plane,
}
/* FIXME check all gen limits */
- if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > max_stride) {
+ if (fb->width < 3 || fb->height < 3 ||
+ fb->pitches[0] > plane->max_stride(plane, fb->format->format,
+ fb->modifier, DRM_MODE_ROTATE_0)) {
DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
return -EINVAL;
}
@@ -1528,6 +1554,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_SPRITE0 + plane);
+ intel_plane->max_stride = skl_plane_max_stride;
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
@@ -1551,6 +1578,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->can_scale = false;
intel_plane->max_downscale = 1;
+ intel_plane->max_stride = i9xx_plane_max_stride;
intel_plane->update_plane = vlv_update_plane;
intel_plane->disable_plane = vlv_disable_plane;
intel_plane->get_hw_state = vlv_plane_get_hw_state;
@@ -1569,6 +1597,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->max_downscale = 1;
}
+ intel_plane->max_stride = g4x_sprite_max_stride;
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
intel_plane->get_hw_state = ivb_plane_get_hw_state;
@@ -1582,6 +1611,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->can_scale = true;
intel_plane->max_downscale = 16;
+ intel_plane->max_stride = g4x_sprite_max_stride;
intel_plane->update_plane = g4x_update_plane;
intel_plane->disable_plane = g4x_disable_plane;
intel_plane->get_hw_state = g4x_plane_get_hw_state;
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (2 preceding siblings ...)
2018-07-19 18:21 ` [PATCH 03/18] drm/i915: Add .max_stride() plane hook Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-22 22:22 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] Ville Syrjala
` (21 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's assume that the primary plane for pipe A has the highest max
stride of all planes, and we'll use that as the global limit when
creating a new framebuffer.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 33 ++++++++++-----------------------
1 file changed, 10 insertions(+), 23 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a09e11e0596f..994685230b97 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -14399,31 +14399,18 @@ static
u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
uint64_t fb_modifier, uint32_t pixel_format)
{
- u32 gen = INTEL_GEN(dev_priv);
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
- if (gen >= 9) {
- int cpp = drm_format_plane_cpp(pixel_format, 0);
+ /*
+ * We assume the primary plane for pipe A has
+ * the highest stride limits of them all.
+ */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
- /* "The stride in bytes must not exceed the of the size of 8K
- * pixels and 32K bytes."
- */
- return min(8192 * cpp, 32768);
- } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
- return 32*1024;
- } else if (gen >= 4) {
- if (fb_modifier == I915_FORMAT_MOD_X_TILED)
- return 16*1024;
- else
- return 32*1024;
- } else if (gen >= 3) {
- if (fb_modifier == I915_FORMAT_MOD_X_TILED)
- return 8*1024;
- else
- return 16*1024;
- } else {
- /* XXX DSPC is limited to 4k tiled */
- return 8*1024;
- }
+ return plane->max_stride(plane, pixel_format, fb_modifier,
+ DRM_MODE_ROTATE_0);
}
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (3 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-22 23:02 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 06/18] drm/i915: Store the final plane stride in plane_state Ville Syrjala
` (20 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Make the main/aux surface stuff a bit more generic by using an array
of structures. This will allow us to deal with both the main and aux
surfaces with common code.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++------------------
drivers/gpu/drm/i915/intel_drv.h | 6 +---
drivers/gpu/drm/i915/intel_fbc.c | 4 +--
drivers/gpu/drm/i915/intel_sprite.c | 29 ++++++++++---------
4 files changed, 46 insertions(+), 49 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 994685230b97..3aec789657b1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2946,9 +2946,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
const struct drm_framebuffer *fb = plane_state->base.fb;
int hsub = fb->format->hsub;
int vsub = fb->format->vsub;
- int aux_x = plane_state->aux.x;
- int aux_y = plane_state->aux.y;
- u32 aux_offset = plane_state->aux.offset;
+ int aux_x = plane_state->color_plane[1].x;
+ int aux_y = plane_state->color_plane[1].y;
+ u32 aux_offset = plane_state->color_plane[1].offset;
u32 alignment = intel_surf_alignment(fb, 1);
while (aux_offset >= main_offset && aux_y <= main_y) {
@@ -2971,9 +2971,9 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
if (aux_x != main_x || aux_y != main_y)
return false;
- plane_state->aux.offset = aux_offset;
- plane_state->aux.x = aux_x;
- plane_state->aux.y = aux_y;
+ plane_state->color_plane[1].offset = aux_offset;
+ plane_state->color_plane[1].x = aux_x;
+ plane_state->color_plane[1].y = aux_y;
return true;
}
@@ -2994,7 +2994,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
int pipe_src_w = crtc_state->pipe_src_w;
int max_width = skl_max_plane_width(fb, 0, rotation);
int max_height = 4096;
- u32 alignment, offset, aux_offset = plane_state->aux.offset;
+ u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
if (w > max_width || h > max_height) {
DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too big (limit %dx%d)\n",
@@ -3067,15 +3067,15 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
offset, offset - alignment);
}
- if (x != plane_state->aux.x || y != plane_state->aux.y) {
+ if (x != plane_state->color_plane[1].x || y != plane_state->color_plane[1].y) {
DRM_DEBUG_KMS("Unable to find suitable display surface offset due to CCS\n");
return -EINVAL;
}
}
- plane_state->main.offset = offset;
- plane_state->main.x = x;
- plane_state->main.y = y;
+ plane_state->color_plane[0].offset = offset;
+ plane_state->color_plane[0].x = x;
+ plane_state->color_plane[0].y = y;
return 0;
}
@@ -3125,9 +3125,9 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
return -EINVAL;
}
- plane_state->aux.offset = offset;
- plane_state->aux.x = x;
- plane_state->aux.y = y;
+ plane_state->color_plane[1].offset = offset;
+ plane_state->color_plane[1].x = x;
+ plane_state->color_plane[1].y = y;
return 0;
}
@@ -3152,9 +3152,9 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
intel_add_fb_offsets(&x, &y, plane_state, 1);
offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
- plane_state->aux.offset = offset;
- plane_state->aux.x = x * hsub + src_x % hsub;
- plane_state->aux.y = y * vsub + src_y % vsub;
+ plane_state->color_plane[1].offset = offset;
+ plane_state->color_plane[1].x = x * hsub + src_x % hsub;
+ plane_state->color_plane[1].y = y * vsub + src_y % vsub;
return 0;
}
@@ -3198,9 +3198,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
if (ret)
return ret;
} else {
- plane_state->aux.offset = ~0xfff;
- plane_state->aux.x = 0;
- plane_state->aux.y = 0;
+ plane_state->color_plane[1].offset = ~0xfff;
+ plane_state->color_plane[1].x = 0;
+ plane_state->color_plane[1].y = 0;
}
ret = skl_check_main_surface(crtc_state, plane_state);
@@ -3327,9 +3327,9 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
}
}
- plane_state->main.offset = offset;
- plane_state->main.x = src_x;
- plane_state->main.y = src_y;
+ plane_state->color_plane[0].offset = offset;
+ plane_state->color_plane[0].x = src_x;
+ plane_state->color_plane[0].y = src_y;
return 0;
}
@@ -3344,15 +3344,15 @@ static void i9xx_update_plane(struct intel_plane *plane,
u32 linear_offset;
u32 dspcntr = plane_state->ctl;
i915_reg_t reg = DSPCNTR(i9xx_plane);
- int x = plane_state->main.x;
- int y = plane_state->main.y;
+ int x = plane_state->color_plane[0].x;
+ int y = plane_state->color_plane[0].y;
unsigned long irqflags;
u32 dspaddr_offset;
linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
- dspaddr_offset = plane_state->main.offset;
+ dspaddr_offset = plane_state->color_plane[0].offset;
else
dspaddr_offset = linear_offset;
@@ -9613,7 +9613,7 @@ static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
else
base = intel_plane_ggtt_offset(plane_state);
- base += plane_state->main.offset;
+ base += plane_state->color_plane[0].offset;
/* ILK+ do this automagically */
if (HAS_GMCH_DISPLAY(dev_priv) &&
@@ -9692,7 +9692,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- plane_state->main.offset = offset;
+ plane_state->color_plane[0].offset = offset;
return 0;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index ad2bd62ee553..24282b855e81 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -501,11 +501,7 @@ struct intel_plane_state {
struct {
u32 offset;
int x, y;
- } main;
- struct {
- u32 offset;
- int x, y;
- } aux;
+ } color_plane[2];
/* plane control register */
u32 ctl;
diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 01d1d2088f04..74d425c700ef 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -670,8 +670,8 @@ static void intel_fbc_update_state_cache(struct intel_crtc *crtc,
cache->plane.src_w = drm_rect_width(&plane_state->base.src) >> 16;
cache->plane.src_h = drm_rect_height(&plane_state->base.src) >> 16;
cache->plane.visible = plane_state->base.visible;
- cache->plane.adjusted_x = plane_state->main.x;
- cache->plane.adjusted_y = plane_state->main.y;
+ cache->plane.adjusted_x = plane_state->color_plane[0].x;
+ cache->plane.adjusted_y = plane_state->color_plane[0].y;
cache->plane.y = plane_state->base.src.y1 >> 16;
if (!cache->plane.visible)
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index e35760814f25..d4b3d32d5e4a 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -256,7 +256,7 @@ skl_update_plane(struct intel_plane *plane,
enum pipe pipe = plane->pipe;
u32 plane_ctl = plane_state->ctl;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
- u32 surf_addr = plane_state->main.offset;
+ u32 surf_addr = plane_state->color_plane[0].offset;
unsigned int rotation = plane_state->base.rotation;
u32 stride = skl_plane_stride(fb, 0, rotation);
u32 aux_stride = skl_plane_stride(fb, 1, rotation);
@@ -264,8 +264,8 @@ skl_update_plane(struct intel_plane *plane,
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->main.x;
- uint32_t y = plane_state->main.y;
+ uint32_t x = plane_state->color_plane[0].x;
+ uint32_t y = plane_state->color_plane[0].y;
uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
unsigned long irqflags;
@@ -292,9 +292,10 @@ skl_update_plane(struct intel_plane *plane,
I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
- (plane_state->aux.offset - surf_addr) | aux_stride);
+ (plane_state->color_plane[1].offset - surf_addr) | aux_stride);
I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
- (plane_state->aux.y << 16) | plane_state->aux.x);
+ (plane_state->color_plane[1].y << 16) |
+ plane_state->color_plane[1].x);
/* program plane scaler */
if (plane_state->scaler_id >= 0) {
@@ -560,15 +561,15 @@ vlv_update_plane(struct intel_plane *plane,
enum pipe pipe = plane->pipe;
enum plane_id plane_id = plane->id;
u32 sprctl = plane_state->ctl;
- u32 sprsurf_offset = plane_state->main.offset;
+ u32 sprsurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->main.x;
- uint32_t y = plane_state->main.y;
+ uint32_t x = plane_state->color_plane[0].x;
+ uint32_t y = plane_state->color_plane[0].y;
unsigned long irqflags;
/* Sizes are 0 based */
@@ -719,15 +720,15 @@ ivb_update_plane(struct intel_plane *plane,
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
u32 sprctl = plane_state->ctl, sprscale = 0;
- u32 sprsurf_offset = plane_state->main.offset;
+ u32 sprsurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->main.x;
- uint32_t y = plane_state->main.y;
+ uint32_t x = plane_state->color_plane[0].x;
+ uint32_t y = plane_state->color_plane[0].y;
uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
unsigned long irqflags;
@@ -891,15 +892,15 @@ g4x_update_plane(struct intel_plane *plane,
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
u32 dvscntr = plane_state->ctl, dvsscale = 0;
- u32 dvssurf_offset = plane_state->main.offset;
+ u32 dvssurf_offset = plane_state->color_plane[0].offset;
u32 linear_offset;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
- uint32_t x = plane_state->main.x;
- uint32_t y = plane_state->main.y;
+ uint32_t x = plane_state->color_plane[0].x;
+ uint32_t y = plane_state->color_plane[0].y;
uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
unsigned long irqflags;
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 06/18] drm/i915: Store the final plane stride in plane_state
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (4 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-07-20 11:06 ` [PATCH v2 " Ville Syrjala
2018-07-19 18:22 ` [PATCH 07/18] drm/i915: Store ggtt_view " Ville Syrjala
` (19 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's store the final plane stride in the plane state. This avoids
having to pick betwen the normal vs. rotated stride during hardware
programming. And once we get GTT remapping the plane stride will
no longer match the fb stride so we'll need a place to store it
anyway.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 49 +++++++++++++++++++++++-------------
drivers/gpu/drm/i915/intel_drv.h | 10 ++++++--
drivers/gpu/drm/i915/intel_sprite.c | 12 ++++-----
3 files changed, 45 insertions(+), 26 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3aec789657b1..eadb8b20d504 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2202,7 +2202,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
{
const struct drm_framebuffer *fb = state->base.fb;
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = fb->pitches[plane];
+ unsigned int pitch = state->color_plane[plane].stride;
return y * pitch + x * cpp;
}
@@ -2259,11 +2259,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static u32 intel_adjust_aligned_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
unsigned int rotation,
+ unsigned int pitch,
u32 old_offset, u32 new_offset)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
WARN_ON(new_offset > old_offset);
@@ -2305,6 +2305,7 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
{
return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
state->base.rotation,
+ state->color_plane[plane].stride,
old_offset, new_offset);
}
@@ -2381,7 +2382,7 @@ static u32 intel_plane_compute_aligned_offset(int *x, int *y,
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
const struct drm_framebuffer *fb = state->base.fb;
unsigned int rotation = state->base.rotation;
- int pitch = intel_fb_pitch(fb, plane, rotation);
+ int pitch = state->color_plane[plane].stride;
u32 alignment;
if (intel_plane->id == PLANE_CURSOR)
@@ -2408,6 +2409,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
intel_adjust_aligned_offset(x, y,
fb, plane, DRM_MODE_ROTATE_0,
+ fb->pitches[0],
fb->offsets[plane], 0);
return 0;
@@ -2849,6 +2851,9 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
return;
valid_fb:
+ intel_state->color_plane[0].stride =
+ intel_fb_pitch(fb, 0, intel_state->base.rotation);
+
mutex_lock(&dev->struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb,
@@ -3166,6 +3171,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
unsigned int rotation = plane_state->base.rotation;
int ret;
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+ plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
+
if (rotation & DRM_MODE_REFLECT_X &&
fb->modifier == DRM_FORMAT_MOD_LINEAR) {
DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
@@ -3301,10 +3309,14 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
int src_x = plane_state->base.src.x1 >> 16;
int src_y = plane_state->base.src.y1 >> 16;
u32 offset;
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -3315,7 +3327,6 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
- unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3339,7 +3350,6 @@ static void i9xx_update_plane(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 linear_offset;
u32 dspcntr = plane_state->ctl;
@@ -3376,7 +3386,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
I915_WRITE_FW(reg, dspcntr);
- I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
+ I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
@@ -3486,16 +3496,16 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
}
}
-u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
- unsigned int rotation)
+u32 skl_plane_stride(const struct intel_plane_state *plane_state,
+ int plane)
{
- u32 stride;
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride = plane_state->color_plane[plane].stride;
if (plane >= fb->format->num_planes)
return 0;
- stride = intel_fb_pitch(fb, plane, rotation);
-
/*
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
@@ -9660,6 +9670,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
int ret;
@@ -9680,6 +9691,8 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+
src_x = plane_state->base.src_x >> 16;
src_y = plane_state->base.src_y >> 16;
@@ -9708,12 +9721,10 @@ i845_cursor_max_stride(struct intel_plane *plane,
static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
-
return CURSOR_ENABLE |
CURSOR_GAMMA_ENABLE |
CURSOR_FORMAT_ARGB |
- CURSOR_STRIDE(fb->pitches[0]);
+ CURSOR_STRIDE(plane_state->color_plane[0].stride);
}
static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
@@ -9750,7 +9761,7 @@ static int i845_check_cursor(struct intel_plane *plane,
return -EINVAL;
}
- switch (fb->pitches[0]) {
+ switch (plane_state->color_plane[0].stride) {
case 256:
case 512:
case 1024:
@@ -9758,7 +9769,7 @@ static int i845_check_cursor(struct intel_plane *plane,
break;
default:
DRM_DEBUG_KMS("Invalid cursor stride (%u)\n",
- fb->pitches[0]);
+ plane_state->color_plane[0].stride);
return -EINVAL;
}
@@ -9951,9 +9962,11 @@ static int i9xx_check_cursor(struct intel_plane *plane,
return -EINVAL;
}
- if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
+ if (plane_state->color_plane[0].stride !=
+ plane_state->base.crtc_w * fb->format->cpp[0]) {
DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
- fb->pitches[0], plane_state->base.crtc_w);
+ plane_state->color_plane[0].stride,
+ plane_state->base.crtc_w);
return -EINVAL;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24282b855e81..f647f9e1f671 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -500,6 +500,12 @@ struct intel_plane_state {
struct {
u32 offset;
+ /*
+ * Plane stride in:
+ * bytes for 0/180 degree rotation
+ * pixels for 90/270 degree rotation
+ */
+ u32 stride;
int x, y;
} color_plane[2];
@@ -1645,8 +1651,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
u32 glk_color_ctl(const struct intel_plane_state *plane_state);
-u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
- unsigned int rotation);
+u32 skl_plane_stride(const struct intel_plane_state *plane_state,
+ int plane);
int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d4b3d32d5e4a..a07d951afbf9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -257,9 +257,8 @@ skl_update_plane(struct intel_plane *plane,
u32 plane_ctl = plane_state->ctl;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[0].offset;
- unsigned int rotation = plane_state->base.rotation;
- u32 stride = skl_plane_stride(fb, 0, rotation);
- u32 aux_stride = skl_plane_stride(fb, 1, rotation);
+ u32 stride = skl_plane_stride(plane_state, 0);
+ u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
@@ -590,7 +589,8 @@ vlv_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
}
- I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
+ I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
+ plane_state->color_plane[0].stride);
I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -752,7 +752,7 @@ ivb_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
}
- I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
+ I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
@@ -924,7 +924,7 @@ g4x_update_plane(struct intel_plane *plane,
I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
}
- I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
+ I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 07/18] drm/i915: Store ggtt_view in plane_state
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (5 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 06/18] drm/i915: Store the final plane stride in plane_state Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 20:13 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 08/18] drm/i915: s/int plane/int color_plane/ Ville Syrjala
` (18 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Stash the gtt_view structure into the plane state. This will become
useful when we do GTT remapping as the gtt_view will not come directly
from the fb anymore.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 16 +++++++++-------
drivers/gpu/drm/i915/intel_drv.h | 3 ++-
drivers/gpu/drm/i915/intel_fbdev.c | 6 ++++--
3 files changed, 15 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index eadb8b20d504..e6cb8238f257 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2079,14 +2079,13 @@ static bool intel_plane_uses_fence(const struct intel_plane_state *plane_state)
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- unsigned int rotation,
+ const struct i915_ggtt_view *view,
bool uses_fence,
unsigned long *out_flags)
{
struct drm_device *dev = fb->dev;
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_i915_gem_object *obj = intel_fb_obj(fb);
- struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned int pinctl;
u32 alignment;
@@ -2095,8 +2094,6 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
alignment = intel_surf_alignment(fb, 0);
- intel_fill_fb_ggtt_view(&view, fb, rotation);
-
/* Note that the w/a also requires 64 PTE of padding following the
* bo. We currently fill all unused PTE with the shadow page and so
* we should always have valid PTE following the scanout preventing
@@ -2129,7 +2126,7 @@ intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
pinctl |= PIN_MAPPABLE;
vma = i915_gem_object_pin_to_display_plane(obj,
- alignment, &view, pinctl);
+ alignment, view, pinctl);
if (IS_ERR(vma))
goto err;
@@ -2851,13 +2848,15 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
return;
valid_fb:
+ intel_fill_fb_ggtt_view(&intel_state->view, fb,
+ intel_state->base.rotation);
intel_state->color_plane[0].stride =
intel_fb_pitch(fb, 0, intel_state->base.rotation);
mutex_lock(&dev->struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb,
- primary->state->rotation,
+ &intel_state->view,
intel_plane_uses_fence(intel_state),
&intel_state->flags);
mutex_unlock(&dev->struct_mutex);
@@ -3171,6 +3170,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
unsigned int rotation = plane_state->base.rotation;
int ret;
+ intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
@@ -3315,6 +3315,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
int src_y = plane_state->base.src.y1 >> 16;
u32 offset;
+ intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
@@ -9691,6 +9692,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
+ intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
src_x = plane_state->base.src_x >> 16;
@@ -13029,7 +13031,7 @@ static int intel_plane_pin_fb(struct intel_plane_state *plane_state)
}
vma = intel_pin_and_fence_fb_obj(fb,
- plane_state->base.rotation,
+ &plane_state->view,
intel_plane_uses_fence(plane_state),
&plane_state->flags);
if (IS_ERR(vma))
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index f647f9e1f671..d70276ff3d0e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -494,6 +494,7 @@ struct intel_atomic_state {
struct intel_plane_state {
struct drm_plane_state base;
+ struct i915_ggtt_view view;
struct i915_vma *vma;
unsigned long flags;
#define PLANE_HAS_FENCE BIT(0)
@@ -1560,7 +1561,7 @@ void intel_release_load_detect_pipe(struct drm_connector *connector,
struct drm_modeset_acquire_ctx *ctx);
struct i915_vma *
intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
- unsigned int rotation,
+ const struct i915_ggtt_view *view,
bool uses_fence,
unsigned long *out_flags);
void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
diff --git a/drivers/gpu/drm/i915/intel_fbdev.c b/drivers/gpu/drm/i915/intel_fbdev.c
index fb2f9fce34cd..f99332972b7a 100644
--- a/drivers/gpu/drm/i915/intel_fbdev.c
+++ b/drivers/gpu/drm/i915/intel_fbdev.c
@@ -175,6 +175,9 @@ static int intelfb_create(struct drm_fb_helper *helper,
struct drm_i915_private *dev_priv = to_i915(dev);
struct pci_dev *pdev = dev_priv->drm.pdev;
struct i915_ggtt *ggtt = &dev_priv->ggtt;
+ const struct i915_ggtt_view view = {
+ .type = I915_GGTT_VIEW_NORMAL,
+ };
struct fb_info *info;
struct drm_framebuffer *fb;
struct i915_vma *vma;
@@ -214,8 +217,7 @@ static int intelfb_create(struct drm_fb_helper *helper,
* BIOS is suitable for own access.
*/
vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base,
- DRM_MODE_ROTATE_0,
- false, &flags);
+ &view, false, &flags);
if (IS_ERR(vma)) {
ret = PTR_ERR(vma);
goto out_unlock;
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 08/18] drm/i915: s/int plane/int color_plane/
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (6 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 07/18] drm/i915: Store ggtt_view " Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-23 1:14 ` Rodrigo Vivi
2018-07-19 18:22 ` [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale Ville Syrjala
` (17 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To reduce the confusion between a drm plane and the planes of
framebuffers let's desiginate the latter as "color plane".
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 106 ++++++++++++++++++-----------------
drivers/gpu/drm/i915/intel_drv.h | 2 +-
2 files changed, 56 insertions(+), 52 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e6cb8238f257..bc2a712311ba 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1916,10 +1916,10 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
}
static unsigned int
-intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
+intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
- unsigned int cpp = fb->format->cpp[plane];
+ unsigned int cpp = fb->format->cpp[color_plane];
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
@@ -1930,7 +1930,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
else
return 512;
case I915_FORMAT_MOD_Y_TILED_CCS:
- if (plane == 1)
+ if (color_plane == 1)
return 128;
/* fall through */
case I915_FORMAT_MOD_Y_TILED:
@@ -1939,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
else
return 512;
case I915_FORMAT_MOD_Yf_TILED_CCS:
- if (plane == 1)
+ if (color_plane == 1)
return 128;
/* fall through */
case I915_FORMAT_MOD_Yf_TILED:
@@ -1964,22 +1964,22 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
}
static unsigned int
-intel_tile_height(const struct drm_framebuffer *fb, int plane)
+intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 1;
else
return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, plane);
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
-static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
+static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
unsigned int *tile_width,
unsigned int *tile_height)
{
- unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
- unsigned int cpp = fb->format->cpp[plane];
+ unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
+ unsigned int cpp = fb->format->cpp[color_plane];
*tile_width = tile_width_bytes / cpp;
*tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
@@ -1987,9 +1987,9 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
unsigned int
intel_fb_align_height(const struct drm_framebuffer *fb,
- int plane, unsigned int height)
+ int color_plane, unsigned int height)
{
- unsigned int tile_height = intel_tile_height(fb, plane);
+ unsigned int tile_height = intel_tile_height(fb, color_plane);
return ALIGN(height, tile_height);
}
@@ -2043,12 +2043,12 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
}
static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
- int plane)
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
/* AUX_DIST needs only 4K alignment */
- if (plane == 1)
+ if (color_plane == 1)
return 4096;
switch (fb->modifier) {
@@ -2178,13 +2178,13 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
i915_vma_put(vma);
}
-static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
+static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
unsigned int rotation)
{
if (drm_rotation_90_or_270(rotation))
- return to_intel_framebuffer(fb)->rotated[plane].pitch;
+ return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
else
- return fb->pitches[plane];
+ return fb->pitches[color_plane];
}
/*
@@ -2195,11 +2195,11 @@ static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
*/
u32 intel_fb_xy_to_linear(int x, int y,
const struct intel_plane_state *state,
- int plane)
+ int color_plane)
{
const struct drm_framebuffer *fb = state->base.fb;
- unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = state->color_plane[plane].stride;
+ unsigned int cpp = fb->format->cpp[color_plane];
+ unsigned int pitch = state->color_plane[color_plane].stride;
return y * pitch + x * cpp;
}
@@ -2211,18 +2211,18 @@ u32 intel_fb_xy_to_linear(int x, int y,
*/
void intel_add_fb_offsets(int *x, int *y,
const struct intel_plane_state *state,
- int plane)
+ int color_plane)
{
const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
unsigned int rotation = state->base.rotation;
if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[plane].x;
- *y += intel_fb->rotated[plane].y;
+ *x += intel_fb->rotated[color_plane].x;
+ *y += intel_fb->rotated[color_plane].y;
} else {
- *x += intel_fb->normal[plane].x;
- *y += intel_fb->normal[plane].y;
+ *x += intel_fb->normal[color_plane].x;
+ *y += intel_fb->normal[color_plane].y;
}
}
@@ -2254,13 +2254,14 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
}
static u32 intel_adjust_aligned_offset(int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
+ const struct drm_framebuffer *fb,
+ int color_plane,
unsigned int rotation,
unsigned int pitch,
u32 old_offset, u32 new_offset)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
- unsigned int cpp = fb->format->cpp[plane];
+ unsigned int cpp = fb->format->cpp[color_plane];
WARN_ON(new_offset > old_offset);
@@ -2269,7 +2270,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
unsigned int pitch_tiles;
tile_size = intel_tile_size(dev_priv);
- intel_tile_dims(fb, plane, &tile_width, &tile_height);
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
if (drm_rotation_90_or_270(rotation)) {
pitch_tiles = pitch / tile_height;
@@ -2297,12 +2298,12 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
*/
static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
- int plane,
+ int color_plane,
u32 old_offset, u32 new_offset)
{
- return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
+ return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
state->base.rotation,
- state->color_plane[plane].stride,
+ state->color_plane[color_plane].stride,
old_offset, new_offset);
}
@@ -2322,13 +2323,14 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
*/
static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
int *x, int *y,
- const struct drm_framebuffer *fb, int plane,
+ const struct drm_framebuffer *fb,
+ int color_plane,
unsigned int pitch,
unsigned int rotation,
u32 alignment)
{
uint64_t fb_modifier = fb->modifier;
- unsigned int cpp = fb->format->cpp[plane];
+ unsigned int cpp = fb->format->cpp[color_plane];
u32 offset, offset_aligned;
if (alignment)
@@ -2339,7 +2341,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
unsigned int tile_rows, tiles, pitch_tiles;
tile_size = intel_tile_size(dev_priv);
- intel_tile_dims(fb, plane, &tile_width, &tile_height);
+ intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
if (drm_rotation_90_or_270(rotation)) {
pitch_tiles = pitch / tile_height;
@@ -2373,41 +2375,42 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
static u32 intel_plane_compute_aligned_offset(int *x, int *y,
const struct intel_plane_state *state,
- int plane)
+ int color_plane)
{
struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
const struct drm_framebuffer *fb = state->base.fb;
unsigned int rotation = state->base.rotation;
- int pitch = state->color_plane[plane].stride;
+ int pitch = state->color_plane[color_plane].stride;
u32 alignment;
if (intel_plane->id == PLANE_CURSOR)
alignment = intel_cursor_alignment(dev_priv);
else
- alignment = intel_surf_alignment(fb, plane);
+ alignment = intel_surf_alignment(fb, color_plane);
- return intel_compute_aligned_offset(dev_priv, x, y, fb, plane,
+ return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
pitch, rotation, alignment);
}
/* Convert the fb->offset[] into x/y offsets */
static int intel_fb_offset_to_xy(int *x, int *y,
- const struct drm_framebuffer *fb, int plane)
+ const struct drm_framebuffer *fb,
+ int color_plane)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
- fb->offsets[plane] % intel_tile_size(dev_priv))
+ fb->offsets[color_plane] % intel_tile_size(dev_priv))
return -EINVAL;
*x = 0;
*y = 0;
intel_adjust_aligned_offset(x, y,
- fb, plane, DRM_MODE_ROTATE_0,
- fb->pitches[0],
- fb->offsets[plane], 0);
+ fb, color_plane, DRM_MODE_ROTATE_0,
+ fb->pitches[color_plane],
+ fb->offsets[color_plane], 0);
return 0;
}
@@ -2899,10 +2902,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
&obj->frontbuffer_bits);
}
-static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
+static int skl_max_plane_width(const struct drm_framebuffer *fb,
+ int color_plane,
unsigned int rotation)
{
- int cpp = fb->format->cpp[plane];
+ int cpp = fb->format->cpp[color_plane];
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
@@ -3462,12 +3466,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
}
static u32
-intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
{
if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
return 64;
else
- return intel_tile_width_bytes(fb, plane);
+ return intel_tile_width_bytes(fb, color_plane);
}
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
@@ -3498,13 +3502,13 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
}
u32 skl_plane_stride(const struct intel_plane_state *plane_state,
- int plane)
+ int color_plane)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
- u32 stride = plane_state->color_plane[plane].stride;
+ u32 stride = plane_state->color_plane[color_plane].stride;
- if (plane >= fb->format->num_planes)
+ if (color_plane >= fb->format->num_planes)
return 0;
/*
@@ -3512,9 +3516,9 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state,
* linear buffers or in number of tiles for tiled buffers.
*/
if (drm_rotation_90_or_270(rotation))
- stride /= intel_tile_height(fb, plane);
+ stride /= intel_tile_height(fb, color_plane);
else
- stride /= intel_fb_stride_alignment(fb, plane);
+ stride /= intel_fb_stride_alignment(fb, color_plane);
return stride;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index d70276ff3d0e..cc381f680338 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1438,7 +1438,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
struct drm_atomic_state *old_state);
unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
- int plane, unsigned int height);
+ int color_plane, unsigned int height);
/* intel_audio.c */
void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (7 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 08/18] drm/i915: s/int plane/int color_plane/ Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 0:32 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions Ville Syrjala
` (16 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We can easily calculate the plane can_scale/min_downscale on demand.
And later on we'll probably want to start calculating these dynamically
based on the cdclk just as skl already does.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 +-------
drivers/gpu/drm/i915/intel_drv.h | 2 --
drivers/gpu/drm/i915/intel_sprite.c | 38 ++++++++++++------------------------
3 files changed, 13 insertions(+), 35 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index bc2a712311ba..fdc5bedc5135 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13708,12 +13708,8 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->base.state = &state->base;
- primary->can_scale = false;
- primary->max_downscale = 1;
- if (INTEL_GEN(dev_priv) >= 9) {
- primary->can_scale = true;
+ if (INTEL_GEN(dev_priv) >= 9)
state->scaler_id = -1;
- }
primary->pipe = pipe;
/*
* On gen2/3 only plane A can do FBC, but the panel fitter and LVDS
@@ -13881,8 +13877,6 @@ intel_cursor_plane_create(struct drm_i915_private *dev_priv,
cursor->base.state = &state->base;
- cursor->can_scale = false;
- cursor->max_downscale = 1;
cursor->pipe = pipe;
cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
cursor->id = PLANE_CURSOR;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index cc381f680338..c6c782e14897 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -950,10 +950,8 @@ struct intel_plane {
enum i9xx_plane_id i9xx_plane;
enum plane_id id;
enum pipe pipe;
- bool can_scale;
bool has_fbc;
bool has_ccs;
- int max_downscale;
uint32_t frontbuffer_bit;
struct {
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index a07d951afbf9..0d3931b8a981 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -765,7 +765,7 @@ ivb_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
- if (plane->can_scale)
+ if (IS_IVYBRIDGE(dev_priv))
I915_WRITE_FW(SPRSCALE(pipe), sprscale);
I915_WRITE_FW(SPRCTL(pipe), sprctl);
I915_WRITE_FW(SPRSURF(pipe),
@@ -786,7 +786,7 @@ ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
I915_WRITE_FW(SPRCTL(pipe), 0);
/* Can't leave the scaler enabled... */
- if (plane->can_scale)
+ if (IS_IVYBRIDGE(dev_priv))
I915_WRITE_FW(SPRSCALE(pipe), 0);
I915_WRITE_FW(SPRSURF(pipe), 0);
@@ -991,7 +991,6 @@ intel_check_sprite_plane(struct intel_plane *plane,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
struct drm_framebuffer *fb = state->base.fb;
int max_scale, min_scale;
- bool can_scale;
int ret;
uint32_t pixel_format = 0;
@@ -1014,25 +1013,29 @@ intel_check_sprite_plane(struct intel_plane *plane,
return -EINVAL;
}
- /* setup can_scale, min_scale, max_scale */
if (INTEL_GEN(dev_priv) >= 9) {
if (state->base.fb)
pixel_format = state->base.fb->format->format;
/* use scaler when colorkey is not required */
if (!state->ckey.flags) {
- can_scale = 1;
min_scale = 1;
max_scale =
skl_max_scale(crtc, crtc_state, pixel_format);
} else {
- can_scale = 0;
min_scale = DRM_PLANE_HELPER_NO_SCALING;
max_scale = DRM_PLANE_HELPER_NO_SCALING;
}
} else {
- can_scale = plane->can_scale;
- max_scale = plane->max_downscale << 16;
- min_scale = plane->can_scale ? 1 : (1 << 16);
+ if (INTEL_GEN(dev_priv) < 7) {
+ min_scale = 1;
+ max_scale = 16 << 16;
+ } else if (IS_IVYBRIDGE(dev_priv)) {
+ min_scale = 1;
+ max_scale = 2 << 16;
+ } else {
+ min_scale = DRM_PLANE_HELPER_NO_SCALING;
+ max_scale = DRM_PLANE_HELPER_NO_SCALING;
+ }
}
ret = drm_atomic_helper_check_plane_state(&state->base,
@@ -1078,8 +1081,6 @@ intel_check_sprite_plane(struct intel_plane *plane,
unsigned int width_bytes;
int cpp = fb->format->cpp[0];
- WARN_ON(!can_scale);
-
width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
/* FIXME interlacing min height is 6 */
@@ -1549,7 +1550,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->base.state = &state->base;
if (INTEL_GEN(dev_priv) >= 9) {
- intel_plane->can_scale = true;
state->scaler_id = -1;
intel_plane->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
@@ -1576,9 +1576,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &skl_plane_funcs;
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- intel_plane->can_scale = false;
- intel_plane->max_downscale = 1;
-
intel_plane->max_stride = i9xx_plane_max_stride;
intel_plane->update_plane = vlv_update_plane;
intel_plane->disable_plane = vlv_disable_plane;
@@ -1590,14 +1587,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &vlv_sprite_funcs;
} else if (INTEL_GEN(dev_priv) >= 7) {
- if (IS_IVYBRIDGE(dev_priv)) {
- intel_plane->can_scale = true;
- intel_plane->max_downscale = 2;
- } else {
- intel_plane->can_scale = false;
- intel_plane->max_downscale = 1;
- }
-
intel_plane->max_stride = g4x_sprite_max_stride;
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
@@ -1609,9 +1598,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
plane_funcs = &snb_sprite_funcs;
} else {
- intel_plane->can_scale = true;
- intel_plane->max_downscale = 16;
-
intel_plane->max_stride = g4x_sprite_max_stride;
intel_plane->update_plane = g4x_update_plane;
intel_plane->disable_plane = g4x_disable_plane;
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (8 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 1:01 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place Ville Syrjala
` (15 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Split up intel_check_primary_plane() and intel_check_sprite_plane()
into per-platform variants. This way we can get a unified behaviour
between the SKL universal planes, and we stop checking for non-SKL
specific scaling limits for the "sprite" planes. And we now get
a natural place where to add more plarform specific checks.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 123 +++++-------
drivers/gpu/drm/i915/intel_drv.h | 13 +-
drivers/gpu/drm/i915/intel_sprite.c | 303 +++++++++++++++++++-----------
4 files changed, 249 insertions(+), 192 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index dcba645cabb8..eddcdd6e4b3b 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -159,7 +159,7 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
}
intel_state->base.visible = false;
- ret = intel_plane->check_plane(intel_plane, crtc_state, intel_state);
+ ret = intel_plane->check_plane(crtc_state, intel_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fdc5bedc5135..9b9eaeda15dd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3350,6 +3350,36 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
return 0;
}
+static int
+i9xx_plane_check(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ int ret;
+
+ ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ &crtc_state->base,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ false, true);
+ if (ret)
+ return ret;
+
+ if (!plane_state->base.visible)
+ return 0;
+
+ ret = intel_plane_check_src_coordinates(plane_state);
+ if (ret)
+ return ret;
+
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
+ plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
+
+ return 0;
+}
+
static void i9xx_update_plane(struct intel_plane *plane,
const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
@@ -9680,6 +9710,11 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
u32 offset;
int ret;
+ if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
+ DRM_DEBUG_KMS("cursor cannot be tiled\n");
+ return -EINVAL;
+ }
+
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
&crtc_state->base,
DRM_PLANE_HELPER_NO_SCALING,
@@ -9688,13 +9723,12 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- if (!fb)
+ if (!plane_state->base.visible)
return 0;
- if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
- DRM_DEBUG_KMS("cursor cannot be tiled\n");
- return -EINVAL;
- }
+ ret = intel_plane_check_src_coordinates(plane_state);
+ if (ret)
+ return ret;
intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
@@ -9744,8 +9778,7 @@ static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
}
-static int i845_check_cursor(struct intel_plane *plane,
- struct intel_crtc_state *crtc_state,
+static int i845_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
@@ -9943,10 +9976,10 @@ static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
return true;
}
-static int i9xx_check_cursor(struct intel_plane *plane,
- struct intel_crtc_state *crtc_state,
+static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
enum pipe pipe = plane->pipe;
@@ -13193,19 +13226,17 @@ intel_cleanup_plane_fb(struct drm_plane *plane,
}
int
-skl_max_scale(struct intel_crtc *intel_crtc,
- struct intel_crtc_state *crtc_state,
- uint32_t pixel_format)
+skl_max_scale(const struct intel_crtc_state *crtc_state,
+ u32 pixel_format)
{
- struct drm_i915_private *dev_priv;
+ struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
+ struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
int max_scale, mult;
int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
- if (!intel_crtc || !crtc_state->base.enable)
+ if (!crtc_state->base.enable)
return DRM_PLANE_HELPER_NO_SCALING;
- dev_priv = to_i915(intel_crtc->base.dev);
-
crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
max_dotclk = to_intel_atomic_state(crtc_state->base.state)->cdclk.logical.cdclk;
@@ -13229,61 +13260,6 @@ skl_max_scale(struct intel_crtc *intel_crtc,
return max_scale;
}
-static int
-intel_check_primary_plane(struct intel_plane *plane,
- struct intel_crtc_state *crtc_state,
- struct intel_plane_state *state)
-{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct drm_crtc *crtc = state->base.crtc;
- int min_scale = DRM_PLANE_HELPER_NO_SCALING;
- int max_scale = DRM_PLANE_HELPER_NO_SCALING;
- bool can_position = false;
- int ret;
- uint32_t pixel_format = 0;
-
- if (INTEL_GEN(dev_priv) >= 9) {
- /* use scaler when colorkey is not required */
- if (!state->ckey.flags) {
- min_scale = 1;
- if (state->base.fb)
- pixel_format = state->base.fb->format->format;
- max_scale = skl_max_scale(to_intel_crtc(crtc),
- crtc_state, pixel_format);
- }
- can_position = true;
- }
-
- ret = drm_atomic_helper_check_plane_state(&state->base,
- &crtc_state->base,
- min_scale, max_scale,
- can_position, true);
- if (ret)
- return ret;
-
- if (!state->base.fb)
- return 0;
-
- if (INTEL_GEN(dev_priv) >= 9) {
- ret = skl_check_plane_surface(crtc_state, state);
- if (ret)
- return ret;
-
- state->ctl = skl_plane_ctl(crtc_state, state);
- } else {
- ret = i9xx_check_plane_surface(state);
- if (ret)
- return ret;
-
- state->ctl = i9xx_plane_ctl(crtc_state, state);
- }
-
- if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
- state->color_ctl = glk_plane_color_ctl(crtc_state, state);
-
- return 0;
-}
-
static void intel_begin_crtc_commit(struct drm_crtc *crtc,
struct drm_crtc_state *old_crtc_state)
{
@@ -13736,8 +13712,6 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
fbc->possible_framebuffer_bits |= primary->frontbuffer_bit;
}
- primary->check_plane = intel_check_primary_plane;
-
if (INTEL_GEN(dev_priv) >= 9) {
primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
PLANE_PRIMARY);
@@ -13759,6 +13733,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->update_plane = skl_update_plane;
primary->disable_plane = skl_disable_plane;
primary->get_hw_state = skl_plane_get_hw_state;
+ primary->check_plane = skl_plane_check;
plane_funcs = &skl_plane_funcs;
} else if (INTEL_GEN(dev_priv) >= 4) {
@@ -13770,6 +13745,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->update_plane = i9xx_update_plane;
primary->disable_plane = i9xx_disable_plane;
primary->get_hw_state = i9xx_plane_get_hw_state;
+ primary->check_plane = i9xx_plane_check;
plane_funcs = &i965_plane_funcs;
} else {
@@ -13781,6 +13757,7 @@ intel_primary_plane_create(struct drm_i915_private *dev_priv, enum pipe pipe)
primary->update_plane = i9xx_update_plane;
primary->disable_plane = i9xx_disable_plane;
primary->get_hw_state = i9xx_plane_get_hw_state;
+ primary->check_plane = i9xx_plane_check;
plane_funcs = &i8xx_plane_funcs;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c6c782e14897..6d57c6a508d4 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -973,9 +973,8 @@ struct intel_plane {
void (*disable_plane)(struct intel_plane *plane,
struct intel_crtc *crtc);
bool (*get_hw_state)(struct intel_plane *plane, enum pipe *pipe);
- int (*check_plane)(struct intel_plane *plane,
- struct intel_crtc_state *crtc_state,
- struct intel_plane_state *state);
+ int (*check_plane)(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state);
};
struct intel_watermark_params {
@@ -1637,8 +1636,8 @@ void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
u16 skl_scaler_calc_phase(int sub, bool chroma_center);
int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
-int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state *crtc_state,
- uint32_t pixel_format);
+int skl_max_scale(const struct intel_crtc_state *crtc_state,
+ u32 pixel_format);
static inline u32 intel_plane_ggtt_offset(const struct intel_plane_state *state)
{
@@ -2112,7 +2111,9 @@ bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
unsigned int skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
unsigned int rotation);
-
+int skl_plane_check(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state);
+int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
/* intel_tv.c */
void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 0d3931b8a981..36e150885897 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -228,6 +228,39 @@ void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
#endif
}
+int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ struct drm_rect *src = &plane_state->base.src;
+ u32 src_x, src_y, src_w, src_h;
+
+ /*
+ * Hardware doesn't handle subpixel coordinates.
+ * Adjust to (macro)pixel boundary, but be careful not to
+ * increase the source viewport size, because that could
+ * push the downscaling factor out of bounds.
+ */
+ src_x = src->x1 >> 16;
+ src_w = drm_rect_width(src) >> 16;
+ src_y = src->y1 >> 16;
+ src_h = drm_rect_height(src) >> 16;
+
+ src->x1 = src_x << 16;
+ src->x2 = (src_x + src_w) << 16;
+ src->y1 = src_y << 16;
+ src->y2 = (src_y + src_h) << 16;
+
+ if (fb->format->is_yuv &&
+ fb->format->format != DRM_FORMAT_NV12 &&
+ (src_x & 1 || src_w & 1)) {
+ DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
+ src_x, src_w);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
unsigned int
skl_plane_max_stride(struct intel_plane *plane,
u32 pixel_format, u64 modifier,
@@ -983,146 +1016,189 @@ g4x_plane_get_hw_state(struct intel_plane *plane,
}
static int
-intel_check_sprite_plane(struct intel_plane *plane,
- struct intel_crtc_state *crtc_state,
- struct intel_plane_state *state)
+g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
- struct drm_framebuffer *fb = state->base.fb;
- int max_scale, min_scale;
- int ret;
- uint32_t pixel_format = 0;
-
- if (!fb) {
- state->base.visible = false;
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ const struct drm_rect *src = &plane_state->base.src;
+ const struct drm_rect *dst = &plane_state->base.dst;
+ int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->base.adjusted_mode;
+ unsigned int cpp = fb->format->cpp[0];
+ unsigned int width_bytes;
+ int min_width, min_height;
+
+ crtc_w = drm_rect_width(dst);
+ crtc_h = drm_rect_height(dst);
+
+ src_x = src->x1 >> 16;
+ src_y = src->y1 >> 16;
+ src_w = drm_rect_width(src) >> 16;
+ src_h = drm_rect_height(src) >> 16;
+
+ if (src_w == crtc_w && src_h == crtc_h)
return 0;
+
+ min_width = 3;
+
+ if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
+ if (src_h & 1) {
+ DRM_DEBUG_KMS("Source height must be even with interlaced modes\n");
+ return -EINVAL;
+ }
+ min_height = 6;
+ } else {
+ min_height = 3;
}
- /* Don't modify another pipe's plane */
- if (plane->pipe != crtc->pipe) {
- DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
+ width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
+
+ if (src_w < min_width || src_h < min_height ||
+ src_w > 2048 || src_h > 2048) {
+ DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed hardware limits (%dx%d - %dx%d)\n",
+ src_w, src_h, min_width, min_height, 2048, 2048);
return -EINVAL;
}
- /* FIXME check all gen limits */
- if (fb->width < 3 || fb->height < 3 ||
- fb->pitches[0] > plane->max_stride(plane, fb->format->format,
- fb->modifier, DRM_MODE_ROTATE_0)) {
- DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
+ if (width_bytes > 4096) {
+ DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max with scaling (%u)\n",
+ width_bytes, 4096);
return -EINVAL;
}
- if (INTEL_GEN(dev_priv) >= 9) {
- if (state->base.fb)
- pixel_format = state->base.fb->format->format;
- /* use scaler when colorkey is not required */
- if (!state->ckey.flags) {
- min_scale = 1;
- max_scale =
- skl_max_scale(crtc, crtc_state, pixel_format);
- } else {
- min_scale = DRM_PLANE_HELPER_NO_SCALING;
- max_scale = DRM_PLANE_HELPER_NO_SCALING;
- }
+ if (width_bytes > 4096 || fb->pitches[0] > 4096) {
+ DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with scaling (%u)\n",
+ fb->pitches[0], 4096);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static int
+g4x_sprite_check(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ int max_scale, min_scale;
+ int ret;
+
+ if (INTEL_GEN(dev_priv) < 7) {
+ min_scale = 1;
+ max_scale = 16 << 16;
+ } else if (IS_IVYBRIDGE(dev_priv)) {
+ min_scale = 1;
+ max_scale = 2 << 16;
} else {
- if (INTEL_GEN(dev_priv) < 7) {
- min_scale = 1;
- max_scale = 16 << 16;
- } else if (IS_IVYBRIDGE(dev_priv)) {
- min_scale = 1;
- max_scale = 2 << 16;
- } else {
- min_scale = DRM_PLANE_HELPER_NO_SCALING;
- max_scale = DRM_PLANE_HELPER_NO_SCALING;
- }
+ min_scale = DRM_PLANE_HELPER_NO_SCALING;
+ max_scale = DRM_PLANE_HELPER_NO_SCALING;
}
- ret = drm_atomic_helper_check_plane_state(&state->base,
+ ret = drm_atomic_helper_check_plane_state(&plane_state->base,
&crtc_state->base,
min_scale, max_scale,
true, true);
if (ret)
return ret;
- if (state->base.visible) {
- struct drm_rect *src = &state->base.src;
- struct drm_rect *dst = &state->base.dst;
- unsigned int crtc_w = drm_rect_width(dst);
- unsigned int crtc_h = drm_rect_height(dst);
- uint32_t src_x, src_y, src_w, src_h;
+ if (!plane_state->base.visible)
+ return 0;
- /*
- * Hardware doesn't handle subpixel coordinates.
- * Adjust to (macro)pixel boundary, but be careful not to
- * increase the source viewport size, because that could
- * push the downscaling factor out of bounds.
- */
- src_x = src->x1 >> 16;
- src_w = drm_rect_width(src) >> 16;
- src_y = src->y1 >> 16;
- src_h = drm_rect_height(src) >> 16;
-
- src->x1 = src_x << 16;
- src->x2 = (src_x + src_w) << 16;
- src->y1 = src_y << 16;
- src->y2 = (src_y + src_h) << 16;
-
- if (fb->format->is_yuv &&
- fb->format->format != DRM_FORMAT_NV12 &&
- (src_x % 2 || src_w % 2)) {
- DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2 for YUV planes\n",
- src_x, src_w);
- return -EINVAL;
- }
+ ret = intel_plane_check_src_coordinates(plane_state);
+ if (ret)
+ return ret;
- /* Check size restrictions when scaling */
- if (src_w != crtc_w || src_h != crtc_h) {
- unsigned int width_bytes;
- int cpp = fb->format->cpp[0];
-
- width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
-
- /* FIXME interlacing min height is 6 */
- if (INTEL_GEN(dev_priv) < 9 && (
- src_w < 3 || src_h < 3 ||
- src_w > 2048 || src_h > 2048 ||
- crtc_w < 3 || crtc_h < 3 ||
- width_bytes > 4096 || fb->pitches[0] > 4096)) {
- DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
- return -EINVAL;
- }
- }
- }
+ ret = g4x_sprite_check_scaling(crtc_state, plane_state);
+ if (ret)
+ return ret;
- if (INTEL_GEN(dev_priv) >= 9) {
- ret = skl_check_plane_surface(crtc_state, state);
- if (ret)
- return ret;
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
- state->ctl = skl_plane_ctl(crtc_state, state);
- } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- ret = i9xx_check_plane_surface(state);
- if (ret)
- return ret;
+ if (INTEL_GEN(dev_priv) >= 7)
+ plane_state->ctl = ivb_sprite_ctl(crtc_state, plane_state);
+ else
+ plane_state->ctl = g4x_sprite_ctl(crtc_state, plane_state);
- state->ctl = vlv_sprite_ctl(crtc_state, state);
- } else if (INTEL_GEN(dev_priv) >= 7) {
- ret = i9xx_check_plane_surface(state);
- if (ret)
- return ret;
+ return 0;
+}
- state->ctl = ivb_sprite_ctl(crtc_state, state);
- } else {
- ret = i9xx_check_plane_surface(state);
- if (ret)
- return ret;
+static int
+vlv_sprite_check(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ int ret;
+
+ ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ &crtc_state->base,
+ DRM_PLANE_HELPER_NO_SCALING,
+ DRM_PLANE_HELPER_NO_SCALING,
+ true, true);
+ if (ret)
+ return ret;
+
+ if (!plane_state->base.visible)
+ return 0;
+
+ ret = intel_plane_check_src_coordinates(plane_state);
+ if (ret)
+ return ret;
+
+ ret = i9xx_check_plane_surface(plane_state);
+ if (ret)
+ return ret;
+
+ plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
- state->ctl = g4x_sprite_ctl(crtc_state, state);
+ return 0;
+}
+
+int skl_plane_check(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ int max_scale, min_scale;
+ int ret;
+
+ /* use scaler when colorkey is not required */
+ if (!plane_state->ckey.flags) {
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+
+ min_scale = 1;
+ max_scale = skl_max_scale(crtc_state,
+ fb ? fb->format->format : 0);
+ } else {
+ min_scale = DRM_PLANE_HELPER_NO_SCALING;
+ max_scale = DRM_PLANE_HELPER_NO_SCALING;
}
+ ret = drm_atomic_helper_check_plane_state(&plane_state->base,
+ &crtc_state->base,
+ min_scale, max_scale,
+ true, true);
+ if (ret)
+ return ret;
+
+ if (!plane_state->base.visible)
+ return 0;
+
+ ret = intel_plane_check_src_coordinates(plane_state);
+ if (ret)
+ return ret;
+
+ ret = skl_check_plane_surface(crtc_state, plane_state);
+ if (ret)
+ return ret;
+
+ plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
+
if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
- state->color_ctl = glk_plane_color_ctl(crtc_state, state);
+ plane_state->color_ctl = glk_plane_color_ctl(crtc_state,
+ plane_state);
return 0;
}
@@ -1559,6 +1635,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->update_plane = skl_update_plane;
intel_plane->disable_plane = skl_disable_plane;
intel_plane->get_hw_state = skl_plane_get_hw_state;
+ intel_plane->check_plane = skl_plane_check;
if (skl_plane_has_planar(dev_priv, pipe,
PLANE_SPRITE0 + plane)) {
@@ -1580,6 +1657,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->update_plane = vlv_update_plane;
intel_plane->disable_plane = vlv_disable_plane;
intel_plane->get_hw_state = vlv_plane_get_hw_state;
+ intel_plane->check_plane = vlv_sprite_check;
plane_formats = vlv_plane_formats;
num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
@@ -1591,6 +1669,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->update_plane = ivb_update_plane;
intel_plane->disable_plane = ivb_disable_plane;
intel_plane->get_hw_state = ivb_plane_get_hw_state;
+ intel_plane->check_plane = g4x_sprite_check;
plane_formats = snb_plane_formats;
num_plane_formats = ARRAY_SIZE(snb_plane_formats);
@@ -1602,6 +1681,7 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->update_plane = g4x_update_plane;
intel_plane->disable_plane = g4x_disable_plane;
intel_plane->get_hw_state = g4x_plane_get_hw_state;
+ intel_plane->check_plane = g4x_sprite_check;
modifiers = i9xx_plane_format_modifiers;
if (IS_GEN6(dev_priv)) {
@@ -1634,7 +1714,6 @@ intel_sprite_plane_create(struct drm_i915_private *dev_priv,
intel_plane->i9xx_plane = plane;
intel_plane->id = PLANE_SPRITE0 + plane;
intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, intel_plane->id);
- intel_plane->check_plane = intel_check_sprite_plane;
possible_crtcs = (1 << pipe);
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (9 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 19:56 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 12/18] drm/i915: Move display w/a #1175 Ville Syrjala
` (14 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the skl+ specific framebuffer related checks from
intel_plane_atomic_check_with_state() into a new function
(skl_plane_check_fb()) which we'll simply call from the skl
plane->check() hook.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 42 --------------------
drivers/gpu/drm/i915/intel_display.c | 12 ------
drivers/gpu/drm/i915/intel_sprite.c | 66 +++++++++++++++++++++++++++++++
3 files changed, 66 insertions(+), 54 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index eddcdd6e4b3b..7c0873060934 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -116,40 +116,11 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
struct drm_i915_private *dev_priv = to_i915(plane->dev);
struct drm_plane_state *state = &intel_state->base;
struct intel_plane *intel_plane = to_intel_plane(plane);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->base.adjusted_mode;
int ret;
if (!intel_state->base.crtc && !old_plane_state->base.crtc)
return 0;
- if (state->fb && drm_rotation_90_or_270(state->rotation)) {
- struct drm_format_name_buf format_name;
-
- if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
- state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
- DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
- return -EINVAL;
- }
-
- /*
- * 90/270 is not allowed with RGB64 16:16:16:16,
- * RGB 16-bit 5:6:5, and Indexed 8-bit.
- * TBD: Add RGB64 case once its added in supported format list.
- */
- switch (state->fb->format->format) {
- case DRM_FORMAT_C8:
- case DRM_FORMAT_RGB565:
- DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
- drm_get_format_name(state->fb->format->format,
- &format_name));
- return -EINVAL;
-
- default:
- break;
- }
- }
-
/* CHV ignores the mirror bit when the rotate bit is set :( */
if (IS_CHERRYVIEW(dev_priv) &&
state->rotation & DRM_MODE_ROTATE_180 &&
@@ -163,19 +134,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
if (ret)
return ret;
- /*
- * Y-tiling is not supported in IF-ID Interlace mode in
- * GEN9 and above.
- */
- if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state->base.enable &&
- adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
- if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
- state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
- DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
- return -EINVAL;
- }
- }
-
/* FIXME pre-g4x don't work like this */
if (state->visible)
crtc_state->active_planes |= BIT(intel_plane->id);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9b9eaeda15dd..2381b762d109 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3151,12 +3151,6 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int y = src_y / vsub;
u32 offset;
- if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180)) {
- DRM_DEBUG_KMS("RC support only with 0/180 degree rotation %x\n",
- plane_state->base.rotation);
- return -EINVAL;
- }
-
intel_add_fb_offsets(&x, &y, plane_state, 1);
offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 1);
@@ -3178,12 +3172,6 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
- if (rotation & DRM_MODE_REFLECT_X &&
- fb->modifier == DRM_FORMAT_MOD_LINEAR) {
- DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
- return -EINVAL;
- }
-
if (!plane_state->base.visible)
return 0;
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 36e150885897..041b8921f4fe 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1156,6 +1156,68 @@ vlv_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ struct drm_format_name_buf format_name;
+
+ if (!fb)
+ return 0;
+
+ if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
+ (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS &&
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ DRM_DEBUG_KMS("RC support only with 0/180 degree rotation (%x)\n",
+ rotation);
+ return -EINVAL;
+ }
+
+ if (rotation & DRM_MODE_REFLECT_X &&
+ fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
+ return -EINVAL;
+ }
+
+ if (drm_rotation_90_or_270(rotation)) {
+ if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
+ fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
+ DRM_DEBUG_KMS("Y/Yf tiling required for 90/270!\n");
+ return -EINVAL;
+ }
+
+ /*
+ * 90/270 is not allowed with RGB64 16:16:16:16,
+ * RGB 16-bit 5:6:5, and Indexed 8-bit.
+ * TBD: Add RGB64 case once its added in supported format list.
+ */
+ switch (fb->format->format) {
+ case DRM_FORMAT_C8:
+ case DRM_FORMAT_RGB565:
+ DRM_DEBUG_KMS("Unsupported pixel format %s for 90/270!\n",
+ drm_get_format_name(fb->format->format,
+ &format_name));
+ return -EINVAL;
+ default:
+ break;
+ }
+ }
+
+ /* Y-tiling is not supported in IF-ID Interlace mode */
+ if (crtc_state->base.enable &&
+ crtc_state->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE &&
+ (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
+ fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
+ DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID mode\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
@@ -1164,6 +1226,10 @@ int skl_plane_check(struct intel_crtc_state *crtc_state,
int max_scale, min_scale;
int ret;
+ ret = skl_plane_check_fb(crtc_state, plane_state);
+ if (ret)
+ return ret;
+
/* use scaler when colorkey is not required */
if (!plane_state->ckey.flags) {
const struct drm_framebuffer *fb = plane_state->base.fb;
--
2.16.4
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 12/18] drm/i915: Move display w/a #1175
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (10 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-23 1:09 ` Rodrigo Vivi
2018-07-19 18:22 ` [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check() Ville Syrjala
` (13 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the display w/a #1175 to a better place. That place
being the new skl+ specific plane->check() hook. This leaves
the skl_check_plane_surface() stuff to deal with the gtt offset
and src coordinate stuff as originally envisioned.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 36 +++++-------------------------------
drivers/gpu/drm/i915/intel_drv.h | 3 +--
drivers/gpu/drm/i915/intel_sprite.c | 36 +++++++++++++++++++++++++++++++++++-
3 files changed, 41 insertions(+), 34 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 2381b762d109..dbcc9a23eefa 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2986,20 +2986,14 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
return true;
}
-static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state)
+static int skl_check_main_surface(struct intel_plane_state *plane_state)
{
- struct drm_i915_private *dev_priv =
- to_i915(plane_state->base.plane->dev);
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
int x = plane_state->base.src.x1 >> 16;
int y = plane_state->base.src.y1 >> 16;
int w = drm_rect_width(&plane_state->base.src) >> 16;
int h = drm_rect_height(&plane_state->base.src) >> 16;
- int dst_x = plane_state->base.dst.x1;
- int dst_w = drm_rect_width(&plane_state->base.dst);
- int pipe_src_w = crtc_state->pipe_src_w;
int max_width = skl_max_plane_width(fb, 0, rotation);
int max_height = 4096;
u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
@@ -3010,24 +3004,6 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
return -EINVAL;
}
- /*
- * Display WA #1175: cnl,glk
- * Planes other than the cursor may cause FIFO underflow and display
- * corruption if starting less than 4 pixels from the right edge of
- * the screen.
- * Besides the above WA fix the similar problem, where planes other
- * than the cursor ending less than 4 pixels from the left edge of the
- * screen may cause FIFO underflow and display corruption.
- */
- if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
- (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
- DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
- dst_x + dst_w < 4 ? "end" : "start",
- dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
- 4, pipe_src_w - 4);
- return -ERANGE;
- }
-
intel_add_fb_offsets(&x, &y, plane_state, 0);
offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
alignment = intel_surf_alignment(fb, 0);
@@ -3089,8 +3065,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
}
static int
-skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state)
+skl_check_nv12_surface(struct intel_plane_state *plane_state)
{
/* Display WA #1106 */
if (plane_state->base.rotation !=
@@ -3161,8 +3136,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
return 0;
}
-int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state)
+int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
@@ -3186,7 +3160,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
* the main surface setup depends on it.
*/
if (fb->format->format == DRM_FORMAT_NV12) {
- ret = skl_check_nv12_surface(crtc_state, plane_state);
+ ret = skl_check_nv12_surface(plane_state);
if (ret)
return ret;
ret = skl_check_nv12_aux_surface(plane_state);
@@ -3203,7 +3177,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
plane_state->color_plane[1].y = 0;
}
- ret = skl_check_main_surface(crtc_state, plane_state);
+ ret = skl_check_main_surface(plane_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 6d57c6a508d4..55f3537ba8f8 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1651,8 +1651,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
u32 glk_color_ctl(const struct intel_plane_state *plane_state);
u32 skl_plane_stride(const struct intel_plane_state *plane_state,
int plane);
-int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state);
+int skl_check_plane_surface(struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index 041b8921f4fe..f43884f76212 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1218,6 +1218,36 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
return 0;
}
+static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
+ const struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ int crtc_x = plane_state->base.dst.x1;
+ int crtc_w = drm_rect_width(&plane_state->base.dst);
+ int pipe_src_w = crtc_state->pipe_src_w;
+
+ /*
+ * Display WA #1175: cnl,glk
+ * Planes other than the cursor may cause FIFO underflow and display
+ * corruption if starting less than 4 pixels from the right edge of
+ * the screen.
+ * Besides the above WA fix the similar problem, where planes other
+ * than the cursor ending less than 4 pixels from the left edge of the
+ * screen may cause FIFO underflow and display corruption.
+ */
+ if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
+ (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
+ DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
+ crtc_x + crtc_w < 4 ? "end" : "start",
+ crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
+ 4, pipe_src_w - 4);
+ return -ERANGE;
+ }
+
+ return 0;
+}
+
int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
@@ -1252,11 +1282,15 @@ int skl_plane_check(struct intel_crtc_state *crtc_state,
if (!plane_state->base.visible)
return 0;
+ ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
+ if (ret)
+ return ret;
+
ret = intel_plane_check_src_coordinates(plane_state);
if (ret)
return ret;
- ret = skl_check_plane_surface(crtc_state, plane_state);
+ ret = skl_check_plane_surface(plane_state);
if (ret)
return ret;
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check()
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (11 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 12/18] drm/i915: Move display w/a #1175 Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 20:04 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface() Ville Syrjala
` (12 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Move the chv rotation vs. reflections checks to the plane->check() hook,
away from the (now) platform agnostic
intel_plane_atomic_check_with_state().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_atomic_plane.c | 9 ---------
drivers/gpu/drm/i915/intel_display.c | 4 ++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
drivers/gpu/drm/i915/intel_sprite.c | 21 +++++++++++++++++++++
4 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c b/drivers/gpu/drm/i915/intel_atomic_plane.c
index 7c0873060934..aabebe0d2e9b 100644
--- a/drivers/gpu/drm/i915/intel_atomic_plane.c
+++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
@@ -113,7 +113,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
struct intel_plane_state *intel_state)
{
struct drm_plane *plane = intel_state->base.plane;
- struct drm_i915_private *dev_priv = to_i915(plane->dev);
struct drm_plane_state *state = &intel_state->base;
struct intel_plane *intel_plane = to_intel_plane(plane);
int ret;
@@ -121,14 +120,6 @@ int intel_plane_atomic_check_with_state(const struct intel_crtc_state *old_crtc_
if (!intel_state->base.crtc && !old_plane_state->base.crtc)
return 0;
- /* CHV ignores the mirror bit when the rotate bit is set :( */
- if (IS_CHERRYVIEW(dev_priv) &&
- state->rotation & DRM_MODE_ROTATE_180 &&
- state->rotation & DRM_MODE_REFLECT_X) {
- DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
- return -EINVAL;
- }
-
intel_state->base.visible = false;
ret = intel_plane->check_plane(crtc_state, intel_state);
if (ret)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index dbcc9a23eefa..b0e39dcf2fb8 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -3318,6 +3318,10 @@ i9xx_plane_check(struct intel_crtc_state *crtc_state,
{
int ret;
+ ret = chv_plane_check_rotation(plane_state);
+ if (ret)
+ return ret;
+
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
&crtc_state->base,
DRM_PLANE_HELPER_NO_SCALING,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 55f3537ba8f8..91b7fb6a07e1 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -2113,6 +2113,7 @@ unsigned int skl_plane_max_stride(struct intel_plane *plane,
int skl_plane_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int intel_plane_check_src_coordinates(struct intel_plane_state *plane_state);
+int chv_plane_check_rotation(const struct intel_plane_state *plane_state);
/* intel_tv.c */
void intel_tv_init(struct drm_i915_private *dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index f43884f76212..93aa355f00e3 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -1126,12 +1126,33 @@ g4x_sprite_check(struct intel_crtc_state *crtc_state,
return 0;
}
+int chv_plane_check_rotation(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ unsigned int rotation = plane_state->base.rotation;
+
+ /* CHV ignores the mirror bit when the rotate bit is set :( */
+ if (IS_CHERRYVIEW(dev_priv) &&
+ rotation & DRM_MODE_ROTATE_180 &&
+ rotation & DRM_MODE_REFLECT_X) {
+ DRM_DEBUG_KMS("Cannot rotate and reflect at the same time\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
static int
vlv_sprite_check(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
int ret;
+ ret = chv_plane_check_rotation(plane_state);
+ if (ret)
+ return ret;
+
ret = drm_atomic_helper_check_plane_state(&plane_state->base,
&crtc_state->base,
DRM_PLANE_HELPER_NO_SCALING,
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface()
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (12 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check() Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 20:08 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
` (11 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Extract intel_cursor_check_surface() to better match the code layout
of the other plane types.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++--------------
1 file changed, 29 insertions(+), 18 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b0e39dcf2fb8..b39c941b4791 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -9667,13 +9667,37 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
height > 0 && height <= config->cursor_height;
}
-static int intel_check_cursor(struct intel_crtc_state *crtc_state,
- struct intel_plane_state *plane_state)
+static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
+
+ intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+
+ src_x = plane_state->base.src_x >> 16;
+ src_y = plane_state->base.src_y >> 16;
+
+ intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
+ offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
+ plane_state, 0);
+
+ if (src_x != 0 || src_y != 0) {
+ DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
+ return -EINVAL;
+ }
+
+ plane_state->color_plane[0].offset = offset;
+
+ return 0;
+}
+
+static int intel_check_cursor(struct intel_crtc_state *crtc_state,
+ struct intel_plane_state *plane_state)
+{
+ const struct drm_framebuffer *fb = plane_state->base.fb;
int ret;
if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
@@ -9696,22 +9720,9 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
if (ret)
return ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
-
- src_x = plane_state->base.src_x >> 16;
- src_y = plane_state->base.src_y >> 16;
-
- intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
- offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
- plane_state, 0);
-
- if (src_x != 0 || src_y != 0) {
- DRM_DEBUG_KMS("Arbitrary cursor panning not supported\n");
- return -EINVAL;
- }
-
- plane_state->color_plane[0].offset = offset;
+ ret = intel_cursor_check_surface(plane_state);
+ if (ret)
+ return ret;
return 0;
}
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (13 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface() Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-07-19 18:59 ` Chris Wilson
2018-07-19 18:22 ` [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
` (10 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
To overcome display engine stride limits we'll want to remap the
pages in the GTT. To that end we need a new gtt_view type which
is just like the "rotated" type except not rotated.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 12 +++++
drivers/gpu/drm/i915/i915_gem_gtt.c | 91 ++++++++++++++++++++++++++++++++++++
drivers/gpu/drm/i915/i915_gem_gtt.h | 16 +++++++
drivers/gpu/drm/i915/i915_vma.c | 6 ++-
drivers/gpu/drm/i915/i915_vma.h | 5 +-
drivers/gpu/drm/i915/intel_display.c | 11 +++++
drivers/gpu/drm/i915/intel_drv.h | 1 +
7 files changed, 140 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index b3aefd623557..82b2984eabee 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -196,6 +196,18 @@ describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj)
vma->ggtt_view.rotated.plane[1].offset);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ seq_printf(m, ", remapped [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]",
+ vma->ggtt_view.remapped.plane[0].width,
+ vma->ggtt_view.remapped.plane[0].height,
+ vma->ggtt_view.remapped.plane[0].stride,
+ vma->ggtt_view.remapped.plane[0].offset,
+ vma->ggtt_view.remapped.plane[1].width,
+ vma->ggtt_view.remapped.plane[1].height,
+ vma->ggtt_view.remapped.plane[1].stride,
+ vma->ggtt_view.remapped.plane[1].offset);
+ break;
+
default:
MISSING_CASE(vma->ggtt_view.type);
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c
index f00c7fbef79e..29b16f564225 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.c
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.c
@@ -3800,6 +3800,92 @@ intel_rotate_pages(struct intel_rotation_info *rot_info,
return ERR_PTR(ret);
}
+static struct scatterlist *
+remap_pages(const dma_addr_t *in, unsigned int offset,
+ unsigned int width, unsigned int height,
+ unsigned int stride,
+ struct sg_table *st, struct scatterlist *sg)
+{
+ unsigned int column, row;
+
+ for (row = 0; row < height; row++) {
+ for (column = 0; column < width; column++) {
+ st->nents++;
+ /* We don't need the pages, but need to initialize
+ * the entries so the sg list can be happily traversed.
+ * The only thing we need are DMA addresses.
+ */
+ sg_set_page(sg, NULL, PAGE_SIZE, 0);
+ sg_dma_address(sg) = in[offset + column];
+ sg_dma_len(sg) = PAGE_SIZE;
+ sg = sg_next(sg);
+ }
+ offset += stride;
+ }
+
+ return sg;
+}
+
+static noinline struct sg_table *
+intel_remap_pages(struct intel_remapped_info *rem_info,
+ struct drm_i915_gem_object *obj)
+{
+ const unsigned long n_pages = obj->base.size / PAGE_SIZE;
+ unsigned int size = intel_remapped_info_size(rem_info);
+ struct sgt_iter sgt_iter;
+ dma_addr_t dma_addr;
+ unsigned long i;
+ dma_addr_t *page_addr_list;
+ struct sg_table *st;
+ struct scatterlist *sg;
+ int ret = -ENOMEM;
+
+ /* Allocate a temporary list of source pages for random access. */
+ page_addr_list = kvmalloc_array(n_pages,
+ sizeof(dma_addr_t),
+ GFP_KERNEL);
+ if (!page_addr_list)
+ return ERR_PTR(ret);
+
+ /* Allocate target SG list. */
+ st = kmalloc(sizeof(*st), GFP_KERNEL);
+ if (!st)
+ goto err_st_alloc;
+
+ ret = sg_alloc_table(st, size, GFP_KERNEL);
+ if (ret)
+ goto err_sg_alloc;
+
+ /* Populate source page list from the object. */
+ i = 0;
+ for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
+ page_addr_list[i++] = dma_addr;
+
+ GEM_BUG_ON(i != n_pages);
+ st->nents = 0;
+ sg = st->sgl;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
+ sg = remap_pages(page_addr_list, rem_info->plane[i].offset,
+ rem_info->plane[i].width, rem_info->plane[i].height,
+ rem_info->plane[i].stride, st, sg);
+ }
+
+ kvfree(page_addr_list);
+
+ return st;
+
+err_sg_alloc:
+ kfree(st);
+err_st_alloc:
+ kvfree(page_addr_list);
+
+ DRM_DEBUG_DRIVER("Failed to create remapped mapping for object size %zu! (%ux%u tiles, %u pages)\n",
+ obj->base.size, rem_info->plane[0].width, rem_info->plane[0].height, size);
+
+ return ERR_PTR(ret);
+}
+
static noinline struct sg_table *
intel_partial_pages(const struct i915_ggtt_view *view,
struct drm_i915_gem_object *obj)
@@ -3876,6 +3962,11 @@ i915_get_ggtt_vma_pages(struct i915_vma *vma)
intel_rotate_pages(&vma->ggtt_view.rotated, vma->obj);
break;
+ case I915_GGTT_VIEW_REMAPPED:
+ vma->pages =
+ intel_remap_pages(&vma->ggtt_view.remapped, vma->obj);
+ break;
+
case I915_GGTT_VIEW_PARTIAL:
vma->pages = intel_partial_pages(&vma->ggtt_view, vma->obj);
break;
diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
index 2a116a91420b..e15ac9f64c36 100644
--- a/drivers/gpu/drm/i915/i915_gem_gtt.h
+++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
@@ -160,6 +160,19 @@ typedef u64 gen8_ppgtt_pml4e_t;
struct sg_table;
+struct intel_remapped_info {
+ struct intel_remapped_plane_info {
+ /* tiles */
+ unsigned int width, height, stride, offset;
+ } plane[2];
+ unsigned int unused;
+} __packed;
+
+static inline void assert_intel_remapped_info_is_packed(void)
+{
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
+}
+
struct intel_rotation_info {
struct intel_rotation_plane_info {
/* tiles */
@@ -186,6 +199,7 @@ enum i915_ggtt_view_type {
I915_GGTT_VIEW_NORMAL = 0,
I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
+ I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
};
static inline void assert_i915_ggtt_view_type_is_unique(void)
@@ -197,6 +211,7 @@ static inline void assert_i915_ggtt_view_type_is_unique(void)
case I915_GGTT_VIEW_NORMAL:
case I915_GGTT_VIEW_PARTIAL:
case I915_GGTT_VIEW_ROTATED:
+ case I915_GGTT_VIEW_REMAPPED:
/* gcc complains if these are identical cases */
break;
}
@@ -208,6 +223,7 @@ struct i915_ggtt_view {
/* Members need to contain no holes/padding */
struct intel_partial_info partial;
struct intel_rotation_info rotated;
+ struct intel_remapped_info remapped;
};
};
diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
index 11d834f94220..eb54755ec25b 100644
--- a/drivers/gpu/drm/i915/i915_vma.c
+++ b/drivers/gpu/drm/i915/i915_vma.c
@@ -164,6 +164,9 @@ vma_create(struct drm_i915_gem_object *obj,
} else if (view->type == I915_GGTT_VIEW_ROTATED) {
vma->size = intel_rotation_info_size(&view->rotated);
vma->size <<= PAGE_SHIFT;
+ } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
+ vma->size = intel_remapped_info_size(&view->remapped);
+ vma->size <<= PAGE_SHIFT;
}
}
@@ -462,7 +465,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
* Explicitly disable for rotated VMA since the display does not
* need the fence and the VMA is not accessible to other users.
*/
- if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
+ if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
+ vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
return;
fenceable = (vma->node.size >= vma->fence_size &&
diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
index f06d66377107..19bb3115226c 100644
--- a/drivers/gpu/drm/i915/i915_vma.h
+++ b/drivers/gpu/drm/i915/i915_vma.h
@@ -257,8 +257,11 @@ i915_vma_compare(struct i915_vma *vma,
*/
BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
+ BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
- offsetof(typeof(*view), partial));
+ offsetof(typeof(*view), partial) ||
+ offsetof(typeof(*view), rotated) !=
+ offsetof(typeof(*view), remapped));
return memcmp(&vma->ggtt_view.partial, &view->partial, view->type);
}
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index b39c941b4791..e6f48fab65de 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2005,6 +2005,17 @@ unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info
return size;
}
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info)
+{
+ unsigned int size = 0;
+ int i;
+
+ for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++)
+ size += rem_info->plane[i].width * rem_info->plane[i].height;
+
+ return size;
+}
+
static void
intel_fill_fb_ggtt_view(struct i915_ggtt_view *view,
const struct drm_framebuffer *fb,
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 91b7fb6a07e1..2be5821fc24f 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1492,6 +1492,7 @@ unsigned int intel_fb_xy_to_linear(int x, int y,
void intel_add_fb_offsets(int *x, int *y,
const struct intel_plane_state *state, int plane);
unsigned int intel_rotation_info_size(const struct intel_rotation_info *rot_info);
+unsigned int intel_remapped_info_size(const struct intel_remapped_info *rem_info);
bool intel_has_pending_fb_unpin(struct drm_i915_private *dev_priv);
void intel_mark_busy(struct drm_i915_private *dev_priv);
void intel_mark_idle(struct drm_i915_private *dev_priv);
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (14 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-07-19 19:01 ` Chris Wilson
2018-07-19 18:22 ` [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
` (9 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The display engine stride limits are getting in our way. On SKL+
we are limited to 8k pixels, which is easily exceeded with three
4k displays. To overcome this limitation we can remap the pages
in the GTT to provide the display engine with a view of memory
with a smaller stride.
The code is mostly already there as We already play tricks with
the plane surface address and x/y offsets.
A few caveats apply:
* linear buffers need the fb stride to be page aligned, as
otherwise the remapped lines wouldn't start at the same
spot
* compressed buffers can't be remapped due to the new
ccs hash mode causing the virtual address of the pages
to affect the interpretation of the compressed data. IIRC
the old hash was limited to the low 12 bits so if we were
using that mode we could remap. As it stands we just refuse
to remapp with compressed fbs.
* no remapping gen2/3 as we'd need a fence for the remapped
vma, which we currently don't have
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 387 ++++++++++++++++++++++++++++-------
1 file changed, 311 insertions(+), 76 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index e6f48fab65de..8fb78214b4be 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1923,7 +1923,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
switch (fb->modifier) {
case DRM_FORMAT_MOD_LINEAR:
- return cpp;
+ return intel_tile_size(dev_priv);
case I915_FORMAT_MOD_X_TILED:
if (IS_GEN2(dev_priv))
return 128;
@@ -1966,11 +1966,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
static unsigned int
intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 1;
- else
- return intel_tile_size(to_i915(fb->dev)) /
- intel_tile_width_bytes(fb, color_plane);
+ return intel_tile_size(to_i915(fb->dev)) /
+ intel_tile_width_bytes(fb, color_plane);
}
/* Return the tile dimensions in pixel units */
@@ -2225,16 +2222,8 @@ void intel_add_fb_offsets(int *x, int *y,
int color_plane)
{
- const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
- unsigned int rotation = state->base.rotation;
-
- if (drm_rotation_90_or_270(rotation)) {
- *x += intel_fb->rotated[color_plane].x;
- *y += intel_fb->rotated[color_plane].y;
- } else {
- *x += intel_fb->normal[color_plane].x;
- *y += intel_fb->normal[color_plane].y;
- }
+ *x += state->color_plane[color_plane].x;
+ *y += state->color_plane[color_plane].y;
}
static u32 intel_adjust_tile_offset(int *x, int *y,
@@ -2488,6 +2477,111 @@ intel_get_format_info(const struct drm_mode_fb_cmd2 *cmd)
}
}
+static bool intel_modifier_has_ccs(u64 modifier)
+{
+ return modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
+ modifier == I915_FORMAT_MOD_Yf_TILED_CCS;
+}
+
+static
+u32 intel_plane_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ struct intel_crtc *crtc;
+ struct intel_plane *plane;
+
+ /*
+ * We assume the primary plane for pipe A has
+ * the highest stride limits of them all.
+ */
+ crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
+ plane = to_intel_plane(crtc->base.primary);
+
+ return plane->max_stride(plane, pixel_format, modifier,
+ DRM_MODE_ROTATE_0);
+}
+
+static
+u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
+ u32 pixel_format, u64 modifier)
+{
+ return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
+}
+
+static u32
+intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
+{
+ struct drm_i915_private *dev_priv = to_i915(fb->dev);
+
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR) {
+ u32 max_stride = intel_plane_fb_max_stride(dev_priv,
+ fb->format->format,
+ fb->modifier);
+
+ /*
+ * To make remapping with linear generally feasible
+ * we need the stride to be page aligned.
+ */
+ if (fb->pitches[color_plane] > max_stride)
+ return intel_tile_size(dev_priv);
+ else
+ return 64;
+ } else {
+ return intel_tile_width_bytes(fb, color_plane);
+ }
+}
+
+static int
+intel_plane_check_stride(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride, max_stride;
+
+ /* FIXME other color planes? */
+ stride = plane_state->color_plane[0].stride;
+ max_stride = plane->max_stride(plane, fb->format->format,
+ fb->modifier, rotation);
+
+ if (stride > max_stride) {
+ DRM_DEBUG_KMS("[FB:%d] stride (%d) exceeds [PLANE:%d:%s] max stride (%d)\n",
+ fb->base.id, stride,
+ plane->base.base.id, plane->base.name, max_stride);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+static bool intel_plane_needs_remap(const struct intel_plane_state *plane_state)
+{
+ struct intel_plane *plane = to_intel_plane(plane_state->base.plane);
+ struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride, max_stride;
+
+ /* We don't want to deal with remapping with cursors */
+ if (plane->id == PLANE_CURSOR)
+ return false;
+
+ /* No fence for the remapped vma */
+ if (INTEL_GEN(dev_priv) < 4)
+ return false;
+
+ /* New CCS hash mode makes remapping impossible */
+ if (intel_modifier_has_ccs(fb->modifier))
+ return false;
+
+ /* FIXME other color planes? */
+ stride = intel_fb_pitch(fb, 0, rotation);
+ max_stride = plane->max_stride(plane, fb->format->format,
+ fb->modifier, rotation);
+
+ return stride > max_stride;
+}
+
static int
intel_fill_fb_info(struct drm_i915_private *dev_priv,
struct drm_framebuffer *fb)
@@ -2654,6 +2748,181 @@ intel_fill_fb_info(struct drm_i915_private *dev_priv,
return 0;
}
+static void
+intel_plane_remap_gtt(struct intel_plane_state *plane_state)
+{
+ struct drm_i915_private *dev_priv =
+ to_i915(plane_state->base.plane->dev);
+ struct drm_framebuffer *fb = plane_state->base.fb;
+ struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
+ struct intel_rotation_info *info = &plane_state->view.rotated;
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->format->num_planes;
+ unsigned int tile_size = intel_tile_size(dev_priv);
+ unsigned int tile_width, tile_height;
+ unsigned int aligned_x, aligned_y;
+ unsigned int aligned_w, aligned_h;
+ unsigned int src_x, src_y;
+ unsigned int src_w, src_h;
+ unsigned int x, y;
+ u32 gtt_offset = 0;
+
+ plane_state->view.type = drm_rotation_90_or_270(rotation) ?
+ I915_GGTT_VIEW_ROTATED : I915_GGTT_VIEW_REMAPPED;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
+ src_w = drm_rect_width(&plane_state->base.src) >> 16;
+ src_h = drm_rect_height(&plane_state->base.src) >> 16;
+
+ WARN_ON(intel_modifier_has_ccs(fb->modifier));
+
+ /* Align our viewport start to tile boundary */
+ intel_tile_dims(fb, 0, &tile_width, &tile_height);
+
+ x = src_x & (tile_width - 1);
+ y = src_y & (tile_height - 1);
+
+ aligned_x = src_x - x;
+ aligned_y = src_y - y;
+
+ aligned_w = x + src_w;
+ aligned_h = y + src_h;
+
+ /* Make src coordinates relative to the aligned viewport */
+ drm_rect_translate(&plane_state->base.src,
+ -(aligned_x << 16), -(aligned_y << 16));
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ aligned_w << 16, aligned_h << 16,
+ DRM_MODE_ROTATE_270);
+
+ for (i = 0; i < num_planes; i++) {
+ unsigned int hsub = i ? fb->format->hsub : 1;
+ unsigned int vsub = i ? fb->format->vsub : 1;
+ unsigned int cpp = fb->format->cpp[i];
+ unsigned int width, height;
+ unsigned int pitch_tiles;
+ unsigned int x, y;
+ u32 offset;
+
+ intel_tile_dims(fb, i, &tile_width, &tile_height);
+
+ x = aligned_x / hsub;
+ y = aligned_y / vsub;
+ width = aligned_w / hsub;
+ height = aligned_h / vsub;
+
+ /*
+ * First pixel of the aligned src viewport
+ * from the start of the normal gtt mapping.
+ */
+ x += intel_fb->normal[i].x;
+ y += intel_fb->normal[i].y;
+
+ offset = intel_compute_aligned_offset(dev_priv, &x, &y,
+ fb, i, fb->pitches[i],
+ DRM_MODE_ROTATE_0, tile_size);
+ offset /= tile_size;
+
+ info->plane[i].offset = offset;
+ info->plane[i].stride = DIV_ROUND_UP(fb->pitches[i],
+ tile_width * cpp);
+ info->plane[i].width = DIV_ROUND_UP(x + width, tile_width);
+ info->plane[i].height = DIV_ROUND_UP(y + height, tile_height);
+
+ if (drm_rotation_90_or_270(rotation)) {
+ struct drm_rect r;
+
+ /* rotate the x/y offsets to match the GTT view */
+ r.x1 = x;
+ r.y1 = y;
+ r.x2 = x + width;
+ r.y2 = y + height;
+ drm_rect_rotate(&r,
+ info->plane[i].width * tile_width,
+ info->plane[i].height * tile_height,
+ DRM_MODE_ROTATE_270);
+ x = r.x1;
+ y = r.y1;
+
+ pitch_tiles = info->plane[i].height;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_height;
+
+ /* rotate the tile dimensions to match the GTT view */
+ swap(tile_width, tile_height);
+ } else {
+ pitch_tiles = info->plane[i].width;
+ plane_state->color_plane[i].stride = pitch_tiles * tile_width * cpp;
+ }
+
+ /*
+ * We only keep the x/y offsets, so push all of the
+ * gtt offset into the x/y offsets.
+ */
+ intel_adjust_tile_offset(&x, &y,
+ tile_width, tile_height,
+ tile_size, pitch_tiles,
+ gtt_offset * tile_size, 0);
+
+ gtt_offset += info->plane[i].width * info->plane[i].height;
+
+ plane_state->color_plane[i].offset = 0;
+ plane_state->color_plane[i].x = x;
+ plane_state->color_plane[i].y = y;
+ }
+}
+
+static int
+intel_plane_compute_gtt(struct intel_plane_state *plane_state)
+{
+ const struct intel_framebuffer *fb =
+ to_intel_framebuffer(plane_state->base.fb);
+ unsigned int rotation = plane_state->base.rotation;
+ int i, num_planes = fb->base.format->num_planes;
+ int ret;
+
+ if (intel_plane_needs_remap(plane_state)) {
+ intel_plane_remap_gtt(plane_state);
+
+ /* Remapping should take care of this always */
+ ret = intel_plane_check_stride(plane_state);
+ if (WARN_ON(ret))
+ return ret;
+
+ return 0;
+ }
+
+ intel_fill_fb_ggtt_view(&plane_state->view, &fb->base, rotation);
+
+ for (i = 0; i < num_planes; i++) {
+ plane_state->color_plane[i].stride = intel_fb_pitch(&fb->base, i, rotation);
+ plane_state->color_plane[i].offset = 0;
+
+ if (drm_rotation_90_or_270(rotation)) {
+ plane_state->color_plane[i].x = fb->rotated[i].x;
+ plane_state->color_plane[i].y = fb->rotated[i].y;
+ } else {
+ plane_state->color_plane[i].x = fb->normal[i].x;
+ plane_state->color_plane[i].y = fb->normal[i].y;
+ }
+ }
+
+ /* Rotate src coordinates to match rotated GTT view */
+ if (drm_rotation_90_or_270(rotation))
+ drm_rect_rotate(&plane_state->base.src,
+ fb->base.width << 16, fb->base.height << 16,
+ DRM_MODE_ROTATE_270);
+
+ ret = intel_plane_check_stride(plane_state);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
static int i9xx_format_to_fourcc(int format)
{
switch (format) {
@@ -3150,21 +3419,11 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
int skl_check_plane_surface(struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
- plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
-
- if (!plane_state->base.visible)
- return 0;
-
- /* Rotate src coordinates to match rotated GTT view */
- if (drm_rotation_90_or_270(rotation))
- drm_rect_rotate(&plane_state->base.src,
- fb->width << 16, fb->height << 16,
- DRM_MODE_ROTATE_270);
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
/*
* Handle the AUX surface first since
@@ -3286,14 +3545,16 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
- int src_x = plane_state->base.src.x1 >> 16;
- int src_y = plane_state->base.src.y1 >> 16;
+ int src_x, src_y;
u32 offset;
+ int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
+
+ src_x = plane_state->base.src.x1 >> 16;
+ src_y = plane_state->base.src.y1 >> 16;
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
@@ -3305,6 +3566,7 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
+ unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3472,15 +3734,6 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
return ret;
}
-static u32
-intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
-{
- if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
- return 64;
- else
- return intel_tile_width_bytes(fb, color_plane);
-}
-
static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
{
struct drm_device *dev = intel_crtc->base.dev;
@@ -3522,12 +3775,12 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state,
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
*/
- if (drm_rotation_90_or_270(rotation))
- stride /= intel_tile_height(fb, color_plane);
+ if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
+ return stride / 64;
+ else if (drm_rotation_90_or_270(rotation))
+ return stride / intel_tile_height(fb, color_plane);
else
- stride /= intel_fb_stride_alignment(fb, color_plane);
-
- return stride;
+ return stride / intel_tile_width_bytes(fb, color_plane);
}
static u32 skl_plane_ctl_format(uint32_t pixel_format)
@@ -9680,13 +9933,13 @@ static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
- unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
+ int ret;
- intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
- plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+ ret = intel_plane_compute_gtt(plane_state);
+ if (ret)
+ return ret;
src_x = plane_state->base.src_x >> 16;
src_y = plane_state->base.src_y >> 16;
@@ -14373,24 +14626,6 @@ static const struct drm_framebuffer_funcs intel_fb_funcs = {
.dirty = intel_user_framebuffer_dirty,
};
-static
-u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
- uint64_t fb_modifier, uint32_t pixel_format)
-{
- struct intel_crtc *crtc;
- struct intel_plane *plane;
-
- /*
- * We assume the primary plane for pipe A has
- * the highest stride limits of them all.
- */
- crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
- plane = to_intel_plane(crtc->base.primary);
-
- return plane->max_stride(plane, pixel_format, fb_modifier,
- DRM_MODE_ROTATE_0);
-}
-
static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_gem_object *obj,
struct drm_mode_fb_cmd2 *mode_cmd)
@@ -14398,7 +14633,7 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
struct drm_framebuffer *fb = &intel_fb->base;
struct drm_format_name_buf format_name;
- u32 pitch_limit;
+ u32 max_stride;
unsigned int tiling, stride;
int ret = -EINVAL;
int i;
@@ -14469,13 +14704,13 @@ static int intel_framebuffer_init(struct intel_framebuffer *intel_fb,
goto err;
}
- pitch_limit = intel_fb_pitch_limit(dev_priv, mode_cmd->modifier[0],
- mode_cmd->pixel_format);
- if (mode_cmd->pitches[0] > pitch_limit) {
+ max_stride = intel_fb_max_stride(dev_priv, mode_cmd->modifier[0],
+ mode_cmd->pixel_format);
+ if (mode_cmd->pitches[0] > max_stride) {
DRM_DEBUG_KMS("%s pitch (%u) must be at most %d\n",
mode_cmd->modifier[0] != DRM_FORMAT_MOD_LINEAR ?
"tiled" : "linear",
- mode_cmd->pitches[0], pitch_limit);
+ mode_cmd->pitches[0], max_stride);
goto err;
}
--
2.16.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (15 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 20:49 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k Ville Syrjala
` (8 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping plugged in we can simply raise the stride
limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
No remapping CCS because the virtual address of each page actually
matters due to the new hash mode
(WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no remapping
on gen2/3 due to lack of fence on the remapped vma.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8fb78214b4be..fa199f469e81 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2505,6 +2505,19 @@ static
u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
u32 pixel_format, u64 modifier)
{
+ /*
+ * Arbitrary limit for gen4+. We can deal with any page
+ * aligned stride via GTT remapping. Gen2/3 need a fence
+ * for tiled scanout which the remapped vma won't have,
+ * so we don't allow remapping on those platforms.
+ *
+ * Also the new hash mode we use for CCS isn't compatible
+ * with remapping as the virtual address of the pages
+ * affects the compressed data.
+ */
+ if (INTEL_GEN(dev_priv) >= 4 && !intel_modifier_has_ccs(modifier))
+ return 256*1024;
+
return intel_plane_fb_max_stride(dev_priv, pixel_format, modifier);
}
--
2.16.4
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (16 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
@ 2018-07-19 18:22 ` Ville Syrjala
2018-08-24 20:49 ` Souza, Jose
2018-07-19 18:52 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
` (7 subsequent siblings)
25 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-19 18:22 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
With gtt remapping in place we can use arbitraily large framebuffers.
Let's bump the limits as high as we can (32k-1). Going beyond that
would require switching out s16.16 src coordinate representation to
something with more spare bits.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index fa199f469e81..8aa2a61d2943 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15429,8 +15429,8 @@ int intel_modeset_init(struct drm_device *dev)
dev->mode_config.max_width = 4096;
dev->mode_config.max_height = 4096;
} else {
- dev->mode_config.max_width = 8192;
- dev->mode_config.max_height = 8192;
+ dev->mode_config.max_width = 32767;
+ dev->mode_config.max_height = 32767;
}
if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
--
2.16.4
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^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (17 preceding siblings ...)
2018-07-19 18:22 ` [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k Ville Syrjala
@ 2018-07-19 18:52 ` Patchwork
2018-07-19 19:00 ` ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-19 18:52 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
0655c1625b0a drm/i915: Fix glk/cnl display w/a #1175
c95e166cfd63 drm/i915: s/tile_offset/aligned_offset/
020d82fa9ed9 drm/i915: Add .max_stride() plane hook
-:33: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#33: FILE: drivers/gpu/drm/i915/intel_display.c:3222:
+ return 16*1024;
^
-:35: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/intel_display.c:3224:
+ return 32*1024;
^
-:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:3227:
+ return 8*1024;
^
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:3229:
+ return 16*1024;
^
-:43: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/intel_display.c:3232:
+ return 4*1024;
^
-:45: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/intel_display.c:3234:
+ return 8*1024;
^
total: 0 errors, 0 warnings, 6 checks, 203 lines checked
1081f1cd3907 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
466e9b94ef6b drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
22a29833142d drm/i915: Store the final plane stride in plane_state
2f03e86953a0 drm/i915: Store ggtt_view in plane_state
efc25030f9e0 drm/i915: s/int plane/int color_plane/
05b220464c98 drm/i915: Nuke plane->can_scale/min_downscale
416335e1c500 drm/i915: Extract per-platform plane->check() functions
eea47ec1a126 drm/i915: Move skl plane fb related checks into a better place
05adce059f5c drm/i915: Move display w/a #1175
6d2816cc9e13 drm/i915: Move chv rotation checks to plane->check()
ad9b29709a6c drm/i915: Extract intel_cursor_check_surface()
f0c079c521ab drm/i915: Add a new "remapped" gtt_view
-:165: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#165: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:173:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 1 checks, 215 lines checked
9ff0fb075794 drm/i915: Overcome display engine stride limits via GTT remapping
57b7b6f7429b drm/i915: Bump gen4+ fb stride limit to 256KiB
-:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:2519:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
b6b0962ca481 drm/i915: Bump gen4+ fb size limits to 32kx32k
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 18:22 ` [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
@ 2018-07-19 18:59 ` Chris Wilson
2018-07-19 19:33 ` Ville Syrjälä
0 siblings, 1 reply; 59+ messages in thread
From: Chris Wilson @ 2018-07-19 18:59 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2018-07-19 19:22:11)
> +static struct scatterlist *
> +remap_pages(const dma_addr_t *in, unsigned int offset,
> + unsigned int width, unsigned int height,
> + unsigned int stride,
> + struct sg_table *st, struct scatterlist *sg)
> +{
> + unsigned int column, row;
> +
> + for (row = 0; row < height; row++) {
> + for (column = 0; column < width; column++) {
> + st->nents++;
> + /* We don't need the pages, but need to initialize
> + * the entries so the sg list can be happily traversed.
> + * The only thing we need are DMA addresses.
> + */
> + sg_set_page(sg, NULL, PAGE_SIZE, 0);
> + sg_dma_address(sg) = in[offset + column];
> + sg_dma_len(sg) = PAGE_SIZE;
> + sg = sg_next(sg);
Ok. But should be I915_GTT_PAGE_SIZE?
And yes, following that argument looks like rotation should be converted.
> + }
> + offset += stride;
> + }
> +
> + return sg;
> +}
> +
> +static noinline struct sg_table *
> +intel_remap_pages(struct intel_remapped_info *rem_info,
> + struct drm_i915_gem_object *obj)
> +{
> + const unsigned long n_pages = obj->base.size / PAGE_SIZE;
> + unsigned int size = intel_remapped_info_size(rem_info);
> + struct sgt_iter sgt_iter;
> + dma_addr_t dma_addr;
> + unsigned long i;
> + dma_addr_t *page_addr_list;
> + struct sg_table *st;
> + struct scatterlist *sg;
> + int ret = -ENOMEM;
> +
> + /* Allocate a temporary list of source pages for random access. */
> + page_addr_list = kvmalloc_array(n_pages,
> + sizeof(dma_addr_t),
> + GFP_KERNEL);
> + if (!page_addr_list)
> + return ERR_PTR(ret);
> +
> + /* Allocate target SG list. */
> + st = kmalloc(sizeof(*st), GFP_KERNEL);
> + if (!st)
> + goto err_st_alloc;
> +
> + ret = sg_alloc_table(st, size, GFP_KERNEL);
> + if (ret)
> + goto err_sg_alloc;
> +
> + /* Populate source page list from the object. */
> + i = 0;
> + for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
> + page_addr_list[i++] = dma_addr;
You could use the i915_gem_object_get_dma_address() for this. We
definitely will reuse the index (as the one object will likely be
remapped into each CRTC). (Avoids having a temporary vmalloc here.)
> +
> + GEM_BUG_ON(i != n_pages);
> + st->nents = 0;
> + sg = st->sgl;
> +
> + for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
> + sg = remap_pages(page_addr_list, rem_info->plane[i].offset,
> + rem_info->plane[i].width, rem_info->plane[i].height,
> + rem_info->plane[i].stride, st, sg);
> + }
> diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> index 2a116a91420b..e15ac9f64c36 100644
> --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> @@ -160,6 +160,19 @@ typedef u64 gen8_ppgtt_pml4e_t;
>
> struct sg_table;
>
> +struct intel_remapped_info {
> + struct intel_remapped_plane_info {
> + /* tiles */
> + unsigned int width, height, stride, offset;
> + } plane[2];
> + unsigned int unused;
Tag it as mbz, since we do use it inside the compare. Hmm, I wonder if
it actually is better if it doesn't exist if it isn't used, then it
should be zero.. Hmm, not sure if that's defined at all, might have to
say memset and don't rely on {} zeroing?
Should work fine as a memcmp key for the rbtree.
> +} __packed;
> +
> +static inline void assert_intel_remapped_info_is_packed(void)
> +{
> + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
> +}
> +
> struct intel_rotation_info {
> struct intel_rotation_plane_info {
> /* tiles */
> @@ -186,6 +199,7 @@ enum i915_ggtt_view_type {
> I915_GGTT_VIEW_NORMAL = 0,
> I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
> I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
> + I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
> };
>
> static inline void assert_i915_ggtt_view_type_is_unique(void)
> @@ -197,6 +211,7 @@ static inline void assert_i915_ggtt_view_type_is_unique(void)
> case I915_GGTT_VIEW_NORMAL:
> case I915_GGTT_VIEW_PARTIAL:
> case I915_GGTT_VIEW_ROTATED:
> + case I915_GGTT_VIEW_REMAPPED:
> /* gcc complains if these are identical cases */
> break;
> }
> @@ -208,6 +223,7 @@ struct i915_ggtt_view {
> /* Members need to contain no holes/padding */
> struct intel_partial_info partial;
> struct intel_rotation_info rotated;
> + struct intel_remapped_info remapped;
> };
> };
>
> diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> index 11d834f94220..eb54755ec25b 100644
> --- a/drivers/gpu/drm/i915/i915_vma.c
> +++ b/drivers/gpu/drm/i915/i915_vma.c
> @@ -164,6 +164,9 @@ vma_create(struct drm_i915_gem_object *obj,
> } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> vma->size = intel_rotation_info_size(&view->rotated);
> vma->size <<= PAGE_SHIFT;
> + } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
> + vma->size = intel_remapped_info_size(&view->remapped);
> + vma->size <<= PAGE_SHIFT;
> }
> }
>
> @@ -462,7 +465,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> * Explicitly disable for rotated VMA since the display does not
> * need the fence and the VMA is not accessible to other users.
> */
> - if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
> + if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
> + vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
> return;
Not fenceable? I suppose, you only want the fence tracking from GGTT
mmaps. Do we need to make sure FBC finally works on unfenced vma? I
guess we do.
> fenceable = (vma->node.size >= vma->fence_size &&
> diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> index f06d66377107..19bb3115226c 100644
> --- a/drivers/gpu/drm/i915/i915_vma.h
> +++ b/drivers/gpu/drm/i915/i915_vma.h
> @@ -257,8 +257,11 @@ i915_vma_compare(struct i915_vma *vma,
> */
> BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
> BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
> + BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
> BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
> - offsetof(typeof(*view), partial));
> + offsetof(typeof(*view), partial) ||
> + offsetof(typeof(*view), rotated) !=
> + offsetof(typeof(*view), remapped));
Two separate BUILD_BUG_ON() I think, one pair of offsetof() will be
harder to interpret should if fail; two pairs never!
-Chris
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^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (18 preceding siblings ...)
2018-07-19 18:52 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
@ 2018-07-19 19:00 ` Patchwork
2018-07-19 19:15 ` ✓ Fi.CI.BAT: success " Patchwork
` (5 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-19 19:00 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Fix glk/cnl display w/a #1175
Okay!
Commit: drm/i915: s/tile_offset/aligned_offset/
Okay!
Commit: drm/i915: Add .max_stride() plane hook
+drivers/gpu/drm/i915/intel_sprite.c:243:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_sprite.c:245:24: warning: expression using sizeof(void)
Commit: drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
-O:drivers/gpu/drm/i915/intel_display.c:14410:24: warning: expression using sizeof(void)
Commit: drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
Okay!
Commit: drm/i915: Store the final plane stride in plane_state
Okay!
Commit: drm/i915: Store ggtt_view in plane_state
Okay!
Commit: drm/i915: s/int plane/int color_plane/
Okay!
Commit: drm/i915: Nuke plane->can_scale/min_downscale
Okay!
Commit: drm/i915: Extract per-platform plane->check() functions
Okay!
Commit: drm/i915: Move skl plane fb related checks into a better place
Okay!
Commit: drm/i915: Move display w/a #1175
Okay!
Commit: drm/i915: Move chv rotation checks to plane->check()
Okay!
Commit: drm/i915: Extract intel_cursor_check_surface()
Okay!
Commit: drm/i915: Add a new "remapped" gtt_view
+./include/linux/mm.h:572:13: error: not a function <noident>
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB
Okay!
Commit: drm/i915: Bump gen4+ fb size limits to 32kx32k
Okay!
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping
2018-07-19 18:22 ` [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
@ 2018-07-19 19:01 ` Chris Wilson
2018-07-19 19:20 ` Ville Syrjälä
0 siblings, 1 reply; 59+ messages in thread
From: Chris Wilson @ 2018-07-19 19:01 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2018-07-19 19:22:12)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The display engine stride limits are getting in our way. On SKL+
> we are limited to 8k pixels, which is easily exceeded with three
> 4k displays. To overcome this limitation we can remap the pages
> in the GTT to provide the display engine with a view of memory
> with a smaller stride.
>
> The code is mostly already there as We already play tricks with
> the plane surface address and x/y offsets.
>
> A few caveats apply:
> * linear buffers need the fb stride to be page aligned, as
> otherwise the remapped lines wouldn't start at the same
> spot
> * compressed buffers can't be remapped due to the new
> ccs hash mode causing the virtual address of the pages
> to affect the interpretation of the compressed data. IIRC
> the old hash was limited to the low 12 bits so if we were
> using that mode we could remap. As it stands we just refuse
> to remapp with compressed fbs.
> * no remapping gen2/3 as we'd need a fence for the remapped
> vma, which we currently don't have
But... you just forbade us getting a fence, there's nothing that
actually would stop the fence register assignment from working?
-Chris
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (19 preceding siblings ...)
2018-07-19 19:00 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-07-19 19:15 ` Patchwork
2018-07-20 0:02 ` ✗ Fi.CI.IGT: failure " Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-19 19:15 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4515 -> Patchwork_9720 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46886/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9720:
=== IGT changes ===
==== Warnings ====
igt@drv_selftest@live_execlists:
{fi-cfl-8109u}: SKIP -> PASS +1
== Known issues ==
Here are the changes found in Patchwork_9720 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_hangcheck:
fi-kbl-7560u: PASS -> DMESG-FAIL (fdo#106560, fdo#106947)
fi-skl-6600u: PASS -> DMESG-FAIL (fdo#106560, fdo#107174)
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: PASS -> DMESG-FAIL (fdo#107292)
igt@gem_ringfill@basic-default:
{fi-kbl-8809g}: PASS -> DMESG-WARN (fdo#107221)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
{fi-cfl-8109u}: DMESG-FAIL -> PASS
igt@gem_exec_suspend@basic-s4-devices:
fi-kbl-7500u: DMESG-WARN (fdo#107139, fdo#105128) -> PASS
igt@gem_render_tiled_blits@basic:
{fi-kbl-8809g}: DMESG-WARN (fdo#107221) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#105128 https://bugs.freedesktop.org/show_bug.cgi?id=105128
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107139 https://bugs.freedesktop.org/show_bug.cgi?id=107139
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107221 https://bugs.freedesktop.org/show_bug.cgi?id=107221
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (47 -> 42) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4515 -> Patchwork_9720
CI_DRM_4515: 7d965fa499d11f7547066a827b3ae420f9e26f39 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4568: 86f7b724ef18986bc58d35558d22e1ed3f8df4f9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9720: b6b0962ca4811bf575148132f299fd0b14bbf8f4 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
b6b0962ca481 drm/i915: Bump gen4+ fb size limits to 32kx32k
57b7b6f7429b drm/i915: Bump gen4+ fb stride limit to 256KiB
9ff0fb075794 drm/i915: Overcome display engine stride limits via GTT remapping
f0c079c521ab drm/i915: Add a new "remapped" gtt_view
ad9b29709a6c drm/i915: Extract intel_cursor_check_surface()
6d2816cc9e13 drm/i915: Move chv rotation checks to plane->check()
05adce059f5c drm/i915: Move display w/a #1175
eea47ec1a126 drm/i915: Move skl plane fb related checks into a better place
416335e1c500 drm/i915: Extract per-platform plane->check() functions
05b220464c98 drm/i915: Nuke plane->can_scale/min_downscale
efc25030f9e0 drm/i915: s/int plane/int color_plane/
2f03e86953a0 drm/i915: Store ggtt_view in plane_state
22a29833142d drm/i915: Store the final plane stride in plane_state
466e9b94ef6b drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
1081f1cd3907 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
020d82fa9ed9 drm/i915: Add .max_stride() plane hook
c95e166cfd63 drm/i915: s/tile_offset/aligned_offset/
0655c1625b0a drm/i915: Fix glk/cnl display w/a #1175
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9720/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping
2018-07-19 19:01 ` Chris Wilson
@ 2018-07-19 19:20 ` Ville Syrjälä
0 siblings, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-07-19 19:20 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 08:01:12PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-07-19 19:22:12)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > The display engine stride limits are getting in our way. On SKL+
> > we are limited to 8k pixels, which is easily exceeded with three
> > 4k displays. To overcome this limitation we can remap the pages
> > in the GTT to provide the display engine with a view of memory
> > with a smaller stride.
> >
> > The code is mostly already there as We already play tricks with
> > the plane surface address and x/y offsets.
> >
> > A few caveats apply:
> > * linear buffers need the fb stride to be page aligned, as
> > otherwise the remapped lines wouldn't start at the same
> > spot
> > * compressed buffers can't be remapped due to the new
> > ccs hash mode causing the virtual address of the pages
> > to affect the interpretation of the compressed data. IIRC
> > the old hash was limited to the low 12 bits so if we were
> > using that mode we could remap. As it stands we just refuse
> > to remapp with compressed fbs.
> > * no remapping gen2/3 as we'd need a fence for the remapped
> > vma, which we currently don't have
>
> But... you just forbade us getting a fence, there's nothing that
> actually would stop the fence register assignment from working?
Hmm. I thought we still had some kind of fence==object relationship.
Or maybe I'm just thinking about the uapi. I should probably read the
actual code instead of relying on ancient/invalid knowledge :)
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 18:59 ` Chris Wilson
@ 2018-07-19 19:33 ` Ville Syrjälä
2018-07-19 19:46 ` Chris Wilson
0 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjälä @ 2018-07-19 19:33 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2018-07-19 19:22:11)
> > +static struct scatterlist *
> > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > + unsigned int width, unsigned int height,
> > + unsigned int stride,
> > + struct sg_table *st, struct scatterlist *sg)
> > +{
> > + unsigned int column, row;
> > +
> > + for (row = 0; row < height; row++) {
> > + for (column = 0; column < width; column++) {
> > + st->nents++;
> > + /* We don't need the pages, but need to initialize
> > + * the entries so the sg list can be happily traversed.
> > + * The only thing we need are DMA addresses.
> > + */
> > + sg_set_page(sg, NULL, PAGE_SIZE, 0);
> > + sg_dma_address(sg) = in[offset + column];
> > + sg_dma_len(sg) = PAGE_SIZE;
> > + sg = sg_next(sg);
>
> Ok. But should be I915_GTT_PAGE_SIZE?
I suppose. And now I wonder what would happen on gen2 with its
2KiB gtt pages. Probably nothing good.
>
> And yes, following that argument looks like rotation should be converted.
>
> > + }
> > + offset += stride;
> > + }
> > +
> > + return sg;
> > +}
> > +
> > +static noinline struct sg_table *
> > +intel_remap_pages(struct intel_remapped_info *rem_info,
> > + struct drm_i915_gem_object *obj)
> > +{
> > + const unsigned long n_pages = obj->base.size / PAGE_SIZE;
> > + unsigned int size = intel_remapped_info_size(rem_info);
> > + struct sgt_iter sgt_iter;
> > + dma_addr_t dma_addr;
> > + unsigned long i;
> > + dma_addr_t *page_addr_list;
> > + struct sg_table *st;
> > + struct scatterlist *sg;
> > + int ret = -ENOMEM;
> > +
> > + /* Allocate a temporary list of source pages for random access. */
> > + page_addr_list = kvmalloc_array(n_pages,
> > + sizeof(dma_addr_t),
> > + GFP_KERNEL);
> > + if (!page_addr_list)
> > + return ERR_PTR(ret);
> > +
> > + /* Allocate target SG list. */
> > + st = kmalloc(sizeof(*st), GFP_KERNEL);
> > + if (!st)
> > + goto err_st_alloc;
> > +
> > + ret = sg_alloc_table(st, size, GFP_KERNEL);
> > + if (ret)
> > + goto err_sg_alloc;
> > +
> > + /* Populate source page list from the object. */
> > + i = 0;
> > + for_each_sgt_dma(dma_addr, sgt_iter, obj->mm.pages)
> > + page_addr_list[i++] = dma_addr;
>
> You could use the i915_gem_object_get_dma_address() for this. We
> definitely will reuse the index (as the one object will likely be
> remapped into each CRTC). (Avoids having a temporary vmalloc here.)
>
> > +
> > + GEM_BUG_ON(i != n_pages);
> > + st->nents = 0;
> > + sg = st->sgl;
> > +
> > + for (i = 0 ; i < ARRAY_SIZE(rem_info->plane); i++) {
> > + sg = remap_pages(page_addr_list, rem_info->plane[i].offset,
> > + rem_info->plane[i].width, rem_info->plane[i].height,
> > + rem_info->plane[i].stride, st, sg);
> > + }
>
> > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.h b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > index 2a116a91420b..e15ac9f64c36 100644
> > --- a/drivers/gpu/drm/i915/i915_gem_gtt.h
> > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.h
> > @@ -160,6 +160,19 @@ typedef u64 gen8_ppgtt_pml4e_t;
> >
> > struct sg_table;
> >
> > +struct intel_remapped_info {
> > + struct intel_remapped_plane_info {
> > + /* tiles */
> > + unsigned int width, height, stride, offset;
> > + } plane[2];
> > + unsigned int unused;
>
> Tag it as mbz, since we do use it inside the compare. Hmm, I wonder if
> it actually is better if it doesn't exist if it isn't used, then it
> should be zero.. Hmm, not sure if that's defined at all, might have to
> say memset and don't rely on {} zeroing?
>
> Should work fine as a memcmp key for the rbtree.
This whole thing is a bit questionale the way I did it. When populating
the gtt_view I just poke at view->rotated and rely on matching layout
for view->remapped. To make it less magic maybe I should embed one
inside the other?
>
> > +} __packed;
> > +
> > +static inline void assert_intel_remapped_info_is_packed(void)
> > +{
> > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
> > +}
> > +
> > struct intel_rotation_info {
> > struct intel_rotation_plane_info {
> > /* tiles */
> > @@ -186,6 +199,7 @@ enum i915_ggtt_view_type {
> > I915_GGTT_VIEW_NORMAL = 0,
> > I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
> > I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
> > + I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
> > };
> >
> > static inline void assert_i915_ggtt_view_type_is_unique(void)
> > @@ -197,6 +211,7 @@ static inline void assert_i915_ggtt_view_type_is_unique(void)
> > case I915_GGTT_VIEW_NORMAL:
> > case I915_GGTT_VIEW_PARTIAL:
> > case I915_GGTT_VIEW_ROTATED:
> > + case I915_GGTT_VIEW_REMAPPED:
> > /* gcc complains if these are identical cases */
> > break;
> > }
> > @@ -208,6 +223,7 @@ struct i915_ggtt_view {
> > /* Members need to contain no holes/padding */
> > struct intel_partial_info partial;
> > struct intel_rotation_info rotated;
> > + struct intel_remapped_info remapped;
> > };
> > };
> >
> > diff --git a/drivers/gpu/drm/i915/i915_vma.c b/drivers/gpu/drm/i915/i915_vma.c
> > index 11d834f94220..eb54755ec25b 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.c
> > +++ b/drivers/gpu/drm/i915/i915_vma.c
> > @@ -164,6 +164,9 @@ vma_create(struct drm_i915_gem_object *obj,
> > } else if (view->type == I915_GGTT_VIEW_ROTATED) {
> > vma->size = intel_rotation_info_size(&view->rotated);
> > vma->size <<= PAGE_SHIFT;
> > + } else if (view->type == I915_GGTT_VIEW_REMAPPED) {
> > + vma->size = intel_remapped_info_size(&view->remapped);
> > + vma->size <<= PAGE_SHIFT;
> > }
> > }
> >
> > @@ -462,7 +465,8 @@ void __i915_vma_set_map_and_fenceable(struct i915_vma *vma)
> > * Explicitly disable for rotated VMA since the display does not
> > * need the fence and the VMA is not accessible to other users.
> > */
> > - if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED)
> > + if (vma->ggtt_view.type == I915_GGTT_VIEW_ROTATED ||
> > + vma->ggtt_view.type == I915_GGTT_VIEW_REMAPPED)
> > return;
>
> Not fenceable? I suppose, you only want the fence tracking from GGTT
> mmaps. Do we need to make sure FBC finally works on unfenced vma? I
> guess we do.
Might be a nice bonus. I keep putting off touching FBC in a significant
way though because I know it won't stop with the first patch.
>
> > fenceable = (vma->node.size >= vma->fence_size &&
> > diff --git a/drivers/gpu/drm/i915/i915_vma.h b/drivers/gpu/drm/i915/i915_vma.h
> > index f06d66377107..19bb3115226c 100644
> > --- a/drivers/gpu/drm/i915/i915_vma.h
> > +++ b/drivers/gpu/drm/i915/i915_vma.h
> > @@ -257,8 +257,11 @@ i915_vma_compare(struct i915_vma *vma,
> > */
> > BUILD_BUG_ON(I915_GGTT_VIEW_NORMAL >= I915_GGTT_VIEW_PARTIAL);
> > BUILD_BUG_ON(I915_GGTT_VIEW_PARTIAL >= I915_GGTT_VIEW_ROTATED);
> > + BUILD_BUG_ON(I915_GGTT_VIEW_ROTATED >= I915_GGTT_VIEW_REMAPPED);
> > BUILD_BUG_ON(offsetof(typeof(*view), rotated) !=
> > - offsetof(typeof(*view), partial));
> > + offsetof(typeof(*view), partial) ||
> > + offsetof(typeof(*view), rotated) !=
> > + offsetof(typeof(*view), remapped));
>
> Two separate BUILD_BUG_ON() I think, one pair of offsetof() will be
> harder to interpret should if fail; two pairs never!
ack
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 19:33 ` Ville Syrjälä
@ 2018-07-19 19:46 ` Chris Wilson
2018-07-19 19:55 ` Ville Syrjälä
2018-07-19 20:16 ` Ville Syrjälä
0 siblings, 2 replies; 59+ messages in thread
From: Chris Wilson @ 2018-07-19 19:46 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2018-07-19 20:33:57)
> On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > +static struct scatterlist *
> > > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > > + unsigned int width, unsigned int height,
> > > + unsigned int stride,
> > > + struct sg_table *st, struct scatterlist *sg)
> > > +{
> > > + unsigned int column, row;
> > > +
> > > + for (row = 0; row < height; row++) {
> > > + for (column = 0; column < width; column++) {
> > > + st->nents++;
> > > + /* We don't need the pages, but need to initialize
> > > + * the entries so the sg list can be happily traversed.
> > > + * The only thing we need are DMA addresses.
> > > + */
> > > + sg_set_page(sg, NULL, PAGE_SIZE, 0);
> > > + sg_dma_address(sg) = in[offset + column];
> > > + sg_dma_len(sg) = PAGE_SIZE;
> > > + sg = sg_next(sg);
> >
> > Ok. But should be I915_GTT_PAGE_SIZE?
>
> I suppose. And now I wonder what would happen on gen2 with its
> 2KiB gtt pages. Probably nothing good.
Pffifle. We call it 4KiB. It's just about the semantics, and here we
should be splitting the dma addresses by GTT_PAGE_SIZE rather than
system page size.
> > > +struct intel_remapped_info {
> > > + struct intel_remapped_plane_info {
> > > + /* tiles */
> > > + unsigned int width, height, stride, offset;
> > > + } plane[2];
> > > + unsigned int unused;
> >
> > Tag it as mbz, since we do use it inside the compare. Hmm, I wonder if
> > it actually is better if it doesn't exist if it isn't used, then it
> > should be zero.. Hmm, not sure if that's defined at all, might have to
> > say memset and don't rely on {} zeroing?
> >
> > Should work fine as a memcmp key for the rbtree.
>
> This whole thing is a bit questionale the way I did it. When populating
> the gtt_view I just poke at view->rotated and rely on matching layout
> for view->remapped. To make it less magic maybe I should embed one
> inside the other?
Hmm. If it's intentionally the same layout, then we should just use the
same struct for both. remapped/remap_info is generic enough to cover
rotation as well.
> > > +} __packed;
> > > +
> > > +static inline void assert_intel_remapped_info_is_packed(void)
> > > +{
> > > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
> > > +}
> > > +
> > > struct intel_rotation_info {
> > > struct intel_rotation_plane_info {
> > > /* tiles */
> > > @@ -186,6 +199,7 @@ enum i915_ggtt_view_type {
> > > I915_GGTT_VIEW_NORMAL = 0,
> > > I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
> > > I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
> > > + I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
Oh, forgot about that trick. Yeah, they do need to differ in structs.
Hmm, so I think keep the remap_plane_info and reuse that?
struct intel_remapped_info {
struct intel_remapped_plane_info {
/* tiles */
unsigned int width, height, stride, offset;
} plane[2];
int unused_mbz;
};
struct intel_rotation_info {
struct intel_remmaped_plane_info plane[2];
};
static inline void assert_intel_rotation_matches_remapped_info(void)
{
/* Check that rotation/remapped shares offsets for simplicity */
BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
offsetof(struct intel_rotation_info, plane[0]));
BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
offsetofend(struct intel_rotation_info, plane[1]));
}
-Chris
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 19:46 ` Chris Wilson
@ 2018-07-19 19:55 ` Ville Syrjälä
2018-07-19 20:16 ` Ville Syrjälä
1 sibling, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-07-19 19:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 08:46:54PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-07-19 20:33:57)
> > On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > > +static struct scatterlist *
> > > > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > > > + unsigned int width, unsigned int height,
> > > > + unsigned int stride,
> > > > + struct sg_table *st, struct scatterlist *sg)
> > > > +{
> > > > + unsigned int column, row;
> > > > +
> > > > + for (row = 0; row < height; row++) {
> > > > + for (column = 0; column < width; column++) {
> > > > + st->nents++;
> > > > + /* We don't need the pages, but need to initialize
> > > > + * the entries so the sg list can be happily traversed.
> > > > + * The only thing we need are DMA addresses.
> > > > + */
> > > > + sg_set_page(sg, NULL, PAGE_SIZE, 0);
> > > > + sg_dma_address(sg) = in[offset + column];
> > > > + sg_dma_len(sg) = PAGE_SIZE;
> > > > + sg = sg_next(sg);
> > >
> > > Ok. But should be I915_GTT_PAGE_SIZE?
> >
> > I suppose. And now I wonder what would happen on gen2 with its
> > 2KiB gtt pages. Probably nothing good.
>
> Pffifle. We call it 4KiB. It's just about the semantics, and here we
> should be splitting the dma addresses by GTT_PAGE_SIZE rather than
> system page size.
>
> > > > +struct intel_remapped_info {
> > > > + struct intel_remapped_plane_info {
> > > > + /* tiles */
> > > > + unsigned int width, height, stride, offset;
> > > > + } plane[2];
> > > > + unsigned int unused;
> > >
> > > Tag it as mbz, since we do use it inside the compare. Hmm, I wonder if
> > > it actually is better if it doesn't exist if it isn't used, then it
> > > should be zero.. Hmm, not sure if that's defined at all, might have to
> > > say memset and don't rely on {} zeroing?
> > >
> > > Should work fine as a memcmp key for the rbtree.
> >
> > This whole thing is a bit questionale the way I did it. When populating
> > the gtt_view I just poke at view->rotated and rely on matching layout
> > for view->remapped. To make it less magic maybe I should embed one
> > inside the other?
>
> Hmm. If it's intentionally the same layout, then we should just use the
> same struct for both. remapped/remap_info is generic enough to cover
> rotation as well.
>
> > > > +} __packed;
> > > > +
> > > > +static inline void assert_intel_remapped_info_is_packed(void)
> > > > +{
> > > > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
> > > > +}
> > > > +
> > > > struct intel_rotation_info {
> > > > struct intel_rotation_plane_info {
> > > > /* tiles */
> > > > @@ -186,6 +199,7 @@ enum i915_ggtt_view_type {
> > > > I915_GGTT_VIEW_NORMAL = 0,
> > > > I915_GGTT_VIEW_ROTATED = sizeof(struct intel_rotation_info),
> > > > I915_GGTT_VIEW_PARTIAL = sizeof(struct intel_partial_info),
> > > > + I915_GGTT_VIEW_REMAPPED = sizeof(struct intel_remapped_info),
>
> Oh, forgot about that trick. Yeah, they do need to differ in structs.
>
> Hmm, so I think keep the remap_plane_info and reuse that?
>
> struct intel_remapped_info {
> struct intel_remapped_plane_info {
> /* tiles */
> unsigned int width, height, stride, offset;
> } plane[2];
> int unused_mbz;
> };
>
>
> struct intel_rotation_info {
> struct intel_remmaped_plane_info plane[2];
> };
>
> static inline void assert_intel_rotation_matches_remapped_info(void)
> {
> /* Check that rotation/remapped shares offsets for simplicity */
> BUILD_BUG_ON(offsetof(struct intel_remapped_info, plane[0]) !=
> offsetof(struct intel_rotation_info, plane[0]));
> BUILD_BUG_ON(offsetofend(struct intel_remapped_info, plane[1]) !=
> offsetofend(struct intel_rotation_info, plane[1]));
> }
Yeah, something like that could work.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 19:46 ` Chris Wilson
2018-07-19 19:55 ` Ville Syrjälä
@ 2018-07-19 20:16 ` Ville Syrjälä
2018-07-19 20:25 ` Chris Wilson
1 sibling, 1 reply; 59+ messages in thread
From: Ville Syrjälä @ 2018-07-19 20:16 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 08:46:54PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjälä (2018-07-19 20:33:57)
> > On Thu, Jul 19, 2018 at 07:59:33PM +0100, Chris Wilson wrote:
> > > Quoting Ville Syrjala (2018-07-19 19:22:11)
> > > > +static struct scatterlist *
> > > > +remap_pages(const dma_addr_t *in, unsigned int offset,
> > > > + unsigned int width, unsigned int height,
> > > > + unsigned int stride,
> > > > + struct sg_table *st, struct scatterlist *sg)
> > > > +{
> > > > + unsigned int column, row;
> > > > +
> > > > + for (row = 0; row < height; row++) {
> > > > + for (column = 0; column < width; column++) {
> > > > + st->nents++;
> > > > + /* We don't need the pages, but need to initialize
> > > > + * the entries so the sg list can be happily traversed.
> > > > + * The only thing we need are DMA addresses.
> > > > + */
> > > > + sg_set_page(sg, NULL, PAGE_SIZE, 0);
> > > > + sg_dma_address(sg) = in[offset + column];
> > > > + sg_dma_len(sg) = PAGE_SIZE;
> > > > + sg = sg_next(sg);
> > >
> > > Ok. But should be I915_GTT_PAGE_SIZE?
> >
> > I suppose. And now I wonder what would happen on gen2 with its
> > 2KiB gtt pages. Probably nothing good.
>
> Pffifle. We call it 4KiB. It's just about the semantics, and here we
> should be splitting the dma addresses by GTT_PAGE_SIZE rather than
> system page size.
>
> > > > +struct intel_remapped_info {
> > > > + struct intel_remapped_plane_info {
> > > > + /* tiles */
> > > > + unsigned int width, height, stride, offset;
> > > > + } plane[2];
> > > > + unsigned int unused;
> > >
> > > Tag it as mbz, since we do use it inside the compare. Hmm, I wonder if
> > > it actually is better if it doesn't exist if it isn't used, then it
> > > should be zero.. Hmm, not sure if that's defined at all, might have to
> > > say memset and don't rely on {} zeroing?
> > >
> > > Should work fine as a memcmp key for the rbtree.
> >
> > This whole thing is a bit questionale the way I did it. When populating
> > the gtt_view I just poke at view->rotated and rely on matching layout
> > for view->remapped. To make it less magic maybe I should embed one
> > inside the other?
>
> Hmm. If it's intentionally the same layout, then we should just use the
> same struct for both. remapped/remap_info is generic enough to cover
> rotation as well.
>
> > > > +} __packed;
> > > > +
> > > > +static inline void assert_intel_remapped_info_is_packed(void)
> > > > +{
> > > > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
Hmm. These assert inlines don't seem to be doing their job. Clearly
my struct size was 9 ints not 10.
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view
2018-07-19 20:16 ` Ville Syrjälä
@ 2018-07-19 20:25 ` Chris Wilson
0 siblings, 0 replies; 59+ messages in thread
From: Chris Wilson @ 2018-07-19 20:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
Quoting Ville Syrjälä (2018-07-19 21:16:20)
> > > > > +} __packed;
> > > > > +
> > > > > +static inline void assert_intel_remapped_info_is_packed(void)
> > > > > +{
> > > > > + BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
>
> Hmm. These assert inlines don't seem to be doing their job. Clearly
> my struct size was 9 ints not 10.
gcc is getting overly smart. Pull all the asserts into one
assert_i915_gem_gtt_types() and then call that from i915_vma_compare().
-Chris
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^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: GTT remapping for display
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (20 preceding siblings ...)
2018-07-19 19:15 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-07-20 0:02 ` Patchwork
2018-07-20 11:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2) Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-20 0:02 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/46886/
State : failure
== Summary ==
= CI Bug Log - changes from CI_DRM_4515_full -> Patchwork_9720_full =
== Summary - FAILURE ==
Serious unknown changes coming with Patchwork_9720_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9720_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9720_full:
=== IGT changes ===
==== Possible regressions ====
igt@kms_chv_cursor_fail@pipe-a-128x128-bottom-edge:
shard-glk: PASS -> FAIL +40
igt@kms_chv_cursor_fail@pipe-b-256x256-top-edge:
shard-hsw: PASS -> FAIL +42
igt@kms_cursor_legacy@all-pipes-forked-move:
shard-snb: PASS -> FAIL +33
igt@kms_cursor_legacy@long-nonblocking-modeset-vs-cursor-atomic:
shard-apl: PASS -> FAIL +48
igt@kms_cursor_legacy@pipe-c-single-bo:
shard-kbl: PASS -> FAIL +47
== Known issues ==
Here are the changes found in Patchwork_9720_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-glk: PASS -> INCOMPLETE (fdo#106886, fdo#103359, k.org#198133)
igt@kms_cursor_legacy@nonblocking-modeset-vs-cursor-atomic:
shard-kbl: PASS -> FAIL (fdo#106026) +1
==== Possible fixes ====
igt@drv_suspend@shrink:
shard-apl: FAIL (fdo#106886) -> PASS
igt@kms_rotation_crc@sprite-rotation-180:
shard-hsw: FAIL (fdo#103925) -> PASS
fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925
fdo#106026 https://bugs.freedesktop.org/show_bug.cgi?id=106026
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4515 -> Patchwork_9720
CI_DRM_4515: 7d965fa499d11f7547066a827b3ae420f9e26f39 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4568: 86f7b724ef18986bc58d35558d22e1ed3f8df4f9 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9720: b6b0962ca4811bf575148132f299fd0b14bbf8f4 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9720/shards.html
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175
2018-07-19 18:21 ` [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175 Ville Syrjala
@ 2018-07-20 10:55 ` Imre Deak
0 siblings, 0 replies; 59+ messages in thread
From: Imre Deak @ 2018-07-20 10:55 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 09:21:57PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> The workaround was supposed to look at the plane destination
> coordinates. Currently it's looking at some mixture of src
> and dst coordinates that doesn't make sense. Fix it up.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Fixes: 394676f05bee ("drm/i915: Add WA for planes ending close to left screen edge")
Reviewed-by: Imre Deak <imre.deak@intel.com>
Not sure why I thought it's ok to use the source width. As I understand now
it wouldn't work with scaling on.
> ---
> drivers/gpu/drm/i915/intel_display.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 87e4cfbfd096..8efff0c56920 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2988,6 +2988,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> int w = drm_rect_width(&plane_state->base.src) >> 16;
> int h = drm_rect_height(&plane_state->base.src) >> 16;
> int dst_x = plane_state->base.dst.x1;
> + int dst_w = drm_rect_width(&plane_state->base.dst);
> int pipe_src_w = crtc_state->pipe_src_w;
> int max_width = skl_max_plane_width(fb, 0, rotation);
> int max_height = 4096;
> @@ -3009,10 +3010,10 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> * screen may cause FIFO underflow and display corruption.
> */
> if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> - (dst_x + w < 4 || dst_x > pipe_src_w - 4)) {
> + (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
> DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
> - dst_x + w < 4 ? "end" : "start",
> - dst_x + w < 4 ? dst_x + w : dst_x,
> + dst_x + dst_w < 4 ? "end" : "start",
> + dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
> 4, pipe_src_w - 4);
> return -ERANGE;
> }
> --
> 2.16.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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^ permalink raw reply [flat|nested] 59+ messages in thread
* [PATCH v2 06/18] drm/i915: Store the final plane stride in plane_state
2018-07-19 18:22 ` [PATCH 06/18] drm/i915: Store the final plane stride in plane_state Ville Syrjala
@ 2018-07-20 11:06 ` Ville Syrjala
2018-08-22 23:44 ` Souza, Jose
0 siblings, 1 reply; 59+ messages in thread
From: Ville Syrjala @ 2018-07-20 11:06 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Let's store the final plane stride in the plane state. This avoids
having to pick betwen the normal vs. rotated stride during hardware
programming. And once we get GTT remapping the plane stride will
no longer match the fb stride so we'll need a place to store it
anyway.
v2: Keep checking fb->pitches[0] for cursor as later on we won't
populate plane_state->color_plane[0].stride for invisible planes
and we have been checking the cursor fb stride even for invisible
planes
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 10 ++++++--
drivers/gpu/drm/i915/intel_sprite.c | 12 +++++-----
3 files changed, 45 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3aec789657b1..6184053fd385 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -2202,7 +2202,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
{
const struct drm_framebuffer *fb = state->base.fb;
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = fb->pitches[plane];
+ unsigned int pitch = state->color_plane[plane].stride;
return y * pitch + x * cpp;
}
@@ -2259,11 +2259,11 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
static u32 intel_adjust_aligned_offset(int *x, int *y,
const struct drm_framebuffer *fb, int plane,
unsigned int rotation,
+ unsigned int pitch,
u32 old_offset, u32 new_offset)
{
struct drm_i915_private *dev_priv = to_i915(fb->dev);
unsigned int cpp = fb->format->cpp[plane];
- unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
WARN_ON(new_offset > old_offset);
@@ -2305,6 +2305,7 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
{
return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
state->base.rotation,
+ state->color_plane[plane].stride,
old_offset, new_offset);
}
@@ -2381,7 +2382,7 @@ static u32 intel_plane_compute_aligned_offset(int *x, int *y,
struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
const struct drm_framebuffer *fb = state->base.fb;
unsigned int rotation = state->base.rotation;
- int pitch = intel_fb_pitch(fb, plane, rotation);
+ int pitch = state->color_plane[plane].stride;
u32 alignment;
if (intel_plane->id == PLANE_CURSOR)
@@ -2408,6 +2409,7 @@ static int intel_fb_offset_to_xy(int *x, int *y,
intel_adjust_aligned_offset(x, y,
fb, plane, DRM_MODE_ROTATE_0,
+ fb->pitches[0],
fb->offsets[plane], 0);
return 0;
@@ -2849,6 +2851,9 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
return;
valid_fb:
+ intel_state->color_plane[0].stride =
+ intel_fb_pitch(fb, 0, intel_state->base.rotation);
+
mutex_lock(&dev->struct_mutex);
intel_state->vma =
intel_pin_and_fence_fb_obj(fb,
@@ -3166,6 +3171,9 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
unsigned int rotation = plane_state->base.rotation;
int ret;
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+ plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1, rotation);
+
if (rotation & DRM_MODE_REFLECT_X &&
fb->modifier == DRM_FORMAT_MOD_LINEAR) {
DRM_DEBUG_KMS("horizontal flip is not supported with linear surface formats\n");
@@ -3301,10 +3309,14 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv =
to_i915(plane_state->base.plane->dev);
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
int src_x = plane_state->base.src.x1 >> 16;
int src_y = plane_state->base.src.y1 >> 16;
u32 offset;
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+
intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
if (INTEL_GEN(dev_priv) >= 4)
@@ -3315,7 +3327,6 @@ int i9xx_check_plane_surface(struct intel_plane_state *plane_state)
/* HSW/BDW do this automagically in hardware */
if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
- unsigned int rotation = plane_state->base.rotation;
int src_w = drm_rect_width(&plane_state->base.src) >> 16;
int src_h = drm_rect_height(&plane_state->base.src) >> 16;
@@ -3339,7 +3350,6 @@ static void i9xx_update_plane(struct intel_plane *plane,
const struct intel_plane_state *plane_state)
{
struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
- const struct drm_framebuffer *fb = plane_state->base.fb;
enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
u32 linear_offset;
u32 dspcntr = plane_state->ctl;
@@ -3376,7 +3386,7 @@ static void i9xx_update_plane(struct intel_plane *plane,
I915_WRITE_FW(reg, dspcntr);
- I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
+ I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state->color_plane[0].stride);
if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
I915_WRITE_FW(DSPSURF(i9xx_plane),
intel_plane_ggtt_offset(plane_state) +
@@ -3486,16 +3496,16 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
}
}
-u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
- unsigned int rotation)
+u32 skl_plane_stride(const struct intel_plane_state *plane_state,
+ int plane)
{
- u32 stride;
+ const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
+ u32 stride = plane_state->color_plane[plane].stride;
if (plane >= fb->format->num_planes)
return 0;
- stride = intel_fb_pitch(fb, plane, rotation);
-
/*
* The stride is either expressed as a multiple of 64 bytes chunks for
* linear buffers or in number of tiles for tiled buffers.
@@ -9660,6 +9670,7 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state)
{
const struct drm_framebuffer *fb = plane_state->base.fb;
+ unsigned int rotation = plane_state->base.rotation;
int src_x, src_y;
u32 offset;
int ret;
@@ -9680,6 +9691,8 @@ static int intel_check_cursor(struct intel_crtc_state *crtc_state,
return -EINVAL;
}
+ plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0, rotation);
+
src_x = plane_state->base.src_x >> 16;
src_y = plane_state->base.src_y >> 16;
@@ -9708,12 +9721,10 @@ i845_cursor_max_stride(struct intel_plane *plane,
static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state)
{
- const struct drm_framebuffer *fb = plane_state->base.fb;
-
return CURSOR_ENABLE |
CURSOR_GAMMA_ENABLE |
CURSOR_FORMAT_ARGB |
- CURSOR_STRIDE(fb->pitches[0]);
+ CURSOR_STRIDE(plane_state->color_plane[0].stride);
}
static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
@@ -9750,6 +9761,9 @@ static int i845_check_cursor(struct intel_plane *plane,
return -EINVAL;
}
+ WARN_ON(plane_state->base.visible &&
+ plane_state->color_plane[0].stride != fb->pitches[0]);
+
switch (fb->pitches[0]) {
case 256:
case 512:
@@ -9951,6 +9965,9 @@ static int i9xx_check_cursor(struct intel_plane *plane,
return -EINVAL;
}
+ WARN_ON(plane_state->base.visible &&
+ plane_state->color_plane[0].stride != fb->pitches[0]);
+
if (fb->pitches[0] != plane_state->base.crtc_w * fb->format->cpp[0]) {
DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width %d)\n",
fb->pitches[0], plane_state->base.crtc_w);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 24282b855e81..f647f9e1f671 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -500,6 +500,12 @@ struct intel_plane_state {
struct {
u32 offset;
+ /*
+ * Plane stride in:
+ * bytes for 0/180 degree rotation
+ * pixels for 90/270 degree rotation
+ */
+ u32 stride;
int x, y;
} color_plane[2];
@@ -1645,8 +1651,8 @@ u32 glk_plane_color_ctl(const struct intel_crtc_state *crtc_state,
u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
const struct intel_plane_state *plane_state);
u32 glk_color_ctl(const struct intel_plane_state *plane_state);
-u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
- unsigned int rotation);
+u32 skl_plane_stride(const struct intel_plane_state *plane_state,
+ int plane);
int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
struct intel_plane_state *plane_state);
int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
index d4b3d32d5e4a..a07d951afbf9 100644
--- a/drivers/gpu/drm/i915/intel_sprite.c
+++ b/drivers/gpu/drm/i915/intel_sprite.c
@@ -257,9 +257,8 @@ skl_update_plane(struct intel_plane *plane,
u32 plane_ctl = plane_state->ctl;
const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
u32 surf_addr = plane_state->color_plane[0].offset;
- unsigned int rotation = plane_state->base.rotation;
- u32 stride = skl_plane_stride(fb, 0, rotation);
- u32 aux_stride = skl_plane_stride(fb, 1, rotation);
+ u32 stride = skl_plane_stride(plane_state, 0);
+ u32 aux_stride = skl_plane_stride(plane_state, 1);
int crtc_x = plane_state->base.dst.x1;
int crtc_y = plane_state->base.dst.y1;
uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
@@ -590,7 +589,8 @@ vlv_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
}
- I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
+ I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
+ plane_state->color_plane[0].stride);
I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
@@ -752,7 +752,7 @@ ivb_update_plane(struct intel_plane *plane,
I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
}
- I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
+ I915_WRITE_FW(SPRSTRIDE(pipe), plane_state->color_plane[0].stride);
I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
/* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
@@ -924,7 +924,7 @@ g4x_update_plane(struct intel_plane *plane,
I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
}
- I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
+ I915_WRITE_FW(DVSSTRIDE(pipe), plane_state->color_plane[0].stride);
I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
if (fb->modifier == I915_FORMAT_MOD_X_TILED)
--
2.16.4
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 59+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2)
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (21 preceding siblings ...)
2018-07-20 0:02 ` ✗ Fi.CI.IGT: failure " Patchwork
@ 2018-07-20 11:15 ` Patchwork
2018-07-20 11:23 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-20 11:15 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
e205f0cf0cc1 drm/i915: Fix glk/cnl display w/a #1175
c6a91ca3ac1f drm/i915: s/tile_offset/aligned_offset/
4ee0a1a700d7 drm/i915: Add .max_stride() plane hook
-:33: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#33: FILE: drivers/gpu/drm/i915/intel_display.c:3222:
+ return 16*1024;
^
-:35: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#35: FILE: drivers/gpu/drm/i915/intel_display.c:3224:
+ return 32*1024;
^
-:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:3227:
+ return 8*1024;
^
-:40: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#40: FILE: drivers/gpu/drm/i915/intel_display.c:3229:
+ return 16*1024;
^
-:43: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#43: FILE: drivers/gpu/drm/i915/intel_display.c:3232:
+ return 4*1024;
^
-:45: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#45: FILE: drivers/gpu/drm/i915/intel_display.c:3234:
+ return 8*1024;
^
total: 0 errors, 0 warnings, 6 checks, 203 lines checked
93251a9665a0 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
4b1480959ec6 drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
1c5d64f97780 drm/i915: Store the final plane stride in plane_state
ff0cc350264a drm/i915: Store ggtt_view in plane_state
20740285ed71 drm/i915: s/int plane/int color_plane/
7ba7bd1f398a drm/i915: Nuke plane->can_scale/min_downscale
65bc9cb0ca53 drm/i915: Extract per-platform plane->check() functions
e1e9380a3fd9 drm/i915: Move skl plane fb related checks into a better place
7da6e070d957 drm/i915: Move display w/a #1175
5825b1993f3a drm/i915: Move chv rotation checks to plane->check()
e84f5ff122b3 drm/i915: Extract intel_cursor_check_surface()
3ea198dea8eb drm/i915: Add a new "remapped" gtt_view
-:165: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#165: FILE: drivers/gpu/drm/i915/i915_gem_gtt.h:173:
+ BUILD_BUG_ON(sizeof(struct intel_remapped_info) != 10*sizeof(unsigned int));
^
total: 0 errors, 0 warnings, 1 checks, 215 lines checked
6f75836c2a10 drm/i915: Overcome display engine stride limits via GTT remapping
8d6a79c031b9 drm/i915: Bump gen4+ fb stride limit to 256KiB
-:38: CHECK:SPACING: spaces preferred around that '*' (ctx:VxV)
#38: FILE: drivers/gpu/drm/i915/intel_display.c:2519:
+ return 256*1024;
^
total: 0 errors, 0 warnings, 1 checks, 19 lines checked
f27708878ebf drm/i915: Bump gen4+ fb size limits to 32kx32k
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.SPARSE: warning for drm/i915: GTT remapping for display (rev2)
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (22 preceding siblings ...)
2018-07-20 11:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2) Patchwork
@ 2018-07-20 11:23 ` Patchwork
2018-07-20 11:37 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-21 14:16 ` ✓ Fi.CI.IGT: " Patchwork
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-20 11:23 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/46886/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: Fix glk/cnl display w/a #1175
Okay!
Commit: drm/i915: s/tile_offset/aligned_offset/
Okay!
Commit: drm/i915: Add .max_stride() plane hook
+drivers/gpu/drm/i915/intel_sprite.c:243:24: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/intel_sprite.c:245:24: warning: expression using sizeof(void)
Commit: drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
-O:drivers/gpu/drm/i915/intel_display.c:14410:24: warning: expression using sizeof(void)
Commit: drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
Okay!
Commit: drm/i915: Store the final plane stride in plane_state
Okay!
Commit: drm/i915: Store ggtt_view in plane_state
Okay!
Commit: drm/i915: s/int plane/int color_plane/
Okay!
Commit: drm/i915: Nuke plane->can_scale/min_downscale
Okay!
Commit: drm/i915: Extract per-platform plane->check() functions
Okay!
Commit: drm/i915: Move skl plane fb related checks into a better place
Okay!
Commit: drm/i915: Move display w/a #1175
Okay!
Commit: drm/i915: Move chv rotation checks to plane->check()
Okay!
Commit: drm/i915: Extract intel_cursor_check_surface()
Okay!
Commit: drm/i915: Add a new "remapped" gtt_view
+./include/linux/mm.h:572:13: error: not a function <noident>
Commit: drm/i915: Overcome display engine stride limits via GTT remapping
Okay!
Commit: drm/i915: Bump gen4+ fb stride limit to 256KiB
Okay!
Commit: drm/i915: Bump gen4+ fb size limits to 32kx32k
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: GTT remapping for display (rev2)
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (23 preceding siblings ...)
2018-07-20 11:23 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2018-07-20 11:37 ` Patchwork
2018-07-21 14:16 ` ✓ Fi.CI.IGT: " Patchwork
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-20 11:37 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/46886/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4518 -> Patchwork_9730 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46886/revisions/2/mbox/
== Known issues ==
Here are the changes found in Patchwork_9730 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_workarounds:
fi-skl-6700k2: PASS -> DMESG-FAIL (fdo#107292)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: PASS -> INCOMPLETE (fdo#103713)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
fi-skl-guc: DMESG-FAIL (fdo#107174) -> PASS
igt@drv_selftest@live_workarounds:
{fi-cfl-8109u}: DMESG-FAIL (fdo#107292) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
== Participating hosts (47 -> 42) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4518 -> Patchwork_9730
CI_DRM_4518: 85bdcb875339b30f7beecbc7cba6bc2041cdd28b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4569: bf70728a951cd3c08dd9bbc9310e16aaa252164f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9730: f27708878ebf7ec004e94aa31c2989e4b76799dd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f27708878ebf drm/i915: Bump gen4+ fb size limits to 32kx32k
8d6a79c031b9 drm/i915: Bump gen4+ fb stride limit to 256KiB
6f75836c2a10 drm/i915: Overcome display engine stride limits via GTT remapping
3ea198dea8eb drm/i915: Add a new "remapped" gtt_view
e84f5ff122b3 drm/i915: Extract intel_cursor_check_surface()
5825b1993f3a drm/i915: Move chv rotation checks to plane->check()
7da6e070d957 drm/i915: Move display w/a #1175
e1e9380a3fd9 drm/i915: Move skl plane fb related checks into a better place
65bc9cb0ca53 drm/i915: Extract per-platform plane->check() functions
7ba7bd1f398a drm/i915: Nuke plane->can_scale/min_downscale
20740285ed71 drm/i915: s/int plane/int color_plane/
ff0cc350264a drm/i915: Store ggtt_view in plane_state
1c5d64f97780 drm/i915: Store the final plane stride in plane_state
4b1480959ec6 drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
93251a9665a0 drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
4ee0a1a700d7 drm/i915: Add .max_stride() plane hook
c6a91ca3ac1f drm/i915: s/tile_offset/aligned_offset/
e205f0cf0cc1 drm/i915: Fix glk/cnl display w/a #1175
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9730/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915: GTT remapping for display (rev2)
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
` (24 preceding siblings ...)
2018-07-20 11:37 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-07-21 14:16 ` Patchwork
25 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2018-07-21 14:16 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display (rev2)
URL : https://patchwork.freedesktop.org/series/46886/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4518_full -> Patchwork_9730_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_9730_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_9730_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_9730_full:
=== IGT changes ===
==== Warnings ====
igt@gem_exec_schedule@deep-blt:
shard-kbl: SKIP -> PASS +1
igt@gem_mocs_settings@mocs-rc6-vebox:
shard-kbl: PASS -> SKIP +2
== Known issues ==
Here are the changes found in Patchwork_9730_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_cursor_legacy@pipe-c-torture-bo:
shard-apl: PASS -> DMESG-WARN (fdo#107122)
igt@kms_universal_plane@cursor-fb-leak-pipe-b:
shard-apl: PASS -> FAIL (fdo#107241)
==== Possible fixes ====
igt@drv_suspend@shrink:
shard-kbl: FAIL (fdo#106886) -> PASS
igt@kms_flip@plain-flip-fb-recreate:
shard-glk: FAIL (fdo#100368) -> PASS
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#107122 https://bugs.freedesktop.org/show_bug.cgi?id=107122
fdo#107241 https://bugs.freedesktop.org/show_bug.cgi?id=107241
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4518 -> Patchwork_9730
CI_DRM_4518: 85bdcb875339b30f7beecbc7cba6bc2041cdd28b @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4569: bf70728a951cd3c08dd9bbc9310e16aaa252164f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9730: f27708878ebf7ec004e94aa31c2989e4b76799dd @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9730/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/
2018-07-19 18:21 ` [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/ Ville Syrjala
@ 2018-08-22 21:55 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 21:55 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Rename some of the tile_offset() functions to aligned_offset() since
> they operate on both linear and tiled functions. And we'll include
> _plane_ in the name of all the variants that take a plane state.
> Should make it more clear which function to use where.
>
Maybe rename the title as it is not doing only
s/tile_offset/aligned_offset/ as described in the commit message and in
code.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 123 ++++++++++++++++++-------
> ----------
> drivers/gpu/drm/i915/intel_drv.h | 2 -
> 2 files changed, 63 insertions(+), 62 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8efff0c56920..5f8304a11482 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2229,13 +2229,13 @@ void intel_add_fb_offsets(int *x, int *y,
> }
> }
>
> -static u32 __intel_adjust_tile_offset(int *x, int *y,
> - unsigned int tile_width,
> - unsigned int tile_height,
> - unsigned int tile_size,
> - unsigned int pitch_tiles,
> - u32 old_offset,
> - u32 new_offset)
> +static u32 intel_adjust_tile_offset(int *x, int *y,
> + unsigned int tile_width,
> + unsigned int tile_height,
> + unsigned int tile_size,
> + unsigned int pitch_tiles,
> + u32 old_offset,
> + u32 new_offset)
> {
> unsigned int pitch_pixels = pitch_tiles * tile_width;
> unsigned int tiles;
> @@ -2256,12 +2256,12 @@ static u32 __intel_adjust_tile_offset(int *x,
> int *y,
> return new_offset;
> }
>
> -static u32 _intel_adjust_tile_offset(int *x, int *y,
> - const struct drm_framebuffer *fb,
> int plane,
> - unsigned int rotation,
> - u32 old_offset, u32 new_offset)
> +static u32 intel_adjust_aligned_offset(int *x, int *y,
> + const struct drm_framebuffer
> *fb, int plane,
> + unsigned int rotation,
> + u32 old_offset, u32 new_offset)
> {
> - const struct drm_i915_private *dev_priv = to_i915(fb->dev);
> + struct drm_i915_private *dev_priv = to_i915(fb->dev);
> unsigned int cpp = fb->format->cpp[plane];
> unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
>
> @@ -2281,9 +2281,9 @@ static u32 _intel_adjust_tile_offset(int *x,
> int *y,
> pitch_tiles = pitch / (tile_width * cpp);
> }
>
> - __intel_adjust_tile_offset(x, y, tile_width,
> tile_height,
> - tile_size, pitch_tiles,
> - old_offset, new_offset);
> + intel_adjust_tile_offset(x, y, tile_width, tile_height,
> + tile_size, pitch_tiles,
> + old_offset, new_offset);
> } else {
> old_offset += *y * pitch + *x * cpp;
>
> @@ -2298,17 +2298,18 @@ static u32 _intel_adjust_tile_offset(int *x,
> int *y,
> * Adjust the tile offset by moving the difference into
> * the x/y offsets.
> */
> -static u32 intel_adjust_tile_offset(int *x, int *y,
> - const struct intel_plane_state
> *state, int plane,
> - u32 old_offset, u32 new_offset)
> +static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
> + const struct
> intel_plane_state *state,
> + int plane,
> + u32 old_offset, u32
> new_offset)
> {
> - return _intel_adjust_tile_offset(x, y, state->base.fb, plane,
> - state->base.rotation,
> - old_offset, new_offset);
> + return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
> + state->base.rotation,
> + old_offset, new_offset);
> }
>
> /*
> - * Computes the linear offset to the base tile and adjusts
> + * Computes the aligned offset to the base tile and adjusts
> * x, y. bytes per pixel is assumed to be a power-of-two.
> *
> * In the 90/270 rotated case, x and y are assumed
> @@ -2321,12 +2322,12 @@ static u32 intel_adjust_tile_offset(int *x,
> int *y,
> * used. This is why the user has to pass in the pitch since it
> * is specified in the rotated orientation.
> */
> -static u32 _intel_compute_tile_offset(const struct drm_i915_private
> *dev_priv,
> - int *x, int *y,
> - const struct drm_framebuffer *fb,
> int plane,
> - unsigned int pitch,
> - unsigned int rotation,
> - u32 alignment)
> +static u32 intel_compute_aligned_offset(struct drm_i915_private
> *dev_priv,
> + int *x, int *y,
> + const struct drm_framebuffer
> *fb, int plane,
> + unsigned int pitch,
> + unsigned int rotation,
> + u32 alignment)
> {
> uint64_t fb_modifier = fb->modifier;
> unsigned int cpp = fb->format->cpp[plane];
> @@ -2358,9 +2359,9 @@ static u32 _intel_compute_tile_offset(const
> struct drm_i915_private *dev_priv,
> offset = (tile_rows * pitch_tiles + tiles) * tile_size;
> offset_aligned = offset & ~alignment;
>
> - __intel_adjust_tile_offset(x, y, tile_width,
> tile_height,
> - tile_size, pitch_tiles,
> - offset, offset_aligned);
> + intel_adjust_tile_offset(x, y, tile_width, tile_height,
> + tile_size, pitch_tiles,
> + offset, offset_aligned);
> } else {
> offset = *y * pitch + *x * cpp;
> offset_aligned = offset & ~alignment;
> @@ -2372,9 +2373,9 @@ static u32 _intel_compute_tile_offset(const
> struct drm_i915_private *dev_priv,
> return offset_aligned;
> }
>
> -u32 intel_compute_tile_offset(int *x, int *y,
> - const struct intel_plane_state *state,
> - int plane)
> +static u32 intel_plane_compute_aligned_offset(int *x, int *y,
> + const struct
> intel_plane_state *state,
> + int plane)
> {
> struct intel_plane *intel_plane = to_intel_plane(state-
> >base.plane);
> struct drm_i915_private *dev_priv = to_i915(intel_plane-
> >base.dev);
> @@ -2388,8 +2389,8 @@ u32 intel_compute_tile_offset(int *x, int *y,
> else
> alignment = intel_surf_alignment(fb, plane);
>
> - return _intel_compute_tile_offset(dev_priv, x, y, fb, plane,
> pitch,
> - rotation, alignment);
> + return intel_compute_aligned_offset(dev_priv, x, y, fb, plane,
> + pitch, rotation,
> alignment);
> }
>
> /* Convert the fb->offset[] into x/y offsets */
> @@ -2405,9 +2406,9 @@ static int intel_fb_offset_to_xy(int *x, int
> *y,
> *x = 0;
> *y = 0;
>
> - _intel_adjust_tile_offset(x, y,
> - fb, plane, DRM_MODE_ROTATE_0,
> - fb->offsets[plane], 0);
> + intel_adjust_aligned_offset(x, y,
> + fb, plane, DRM_MODE_ROTATE_0,
> + fb->offsets[plane], 0);
>
> return 0;
> }
> @@ -2559,9 +2560,10 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
> intel_fb->normal[i].x = x;
> intel_fb->normal[i].y = y;
>
> - offset = _intel_compute_tile_offset(dev_priv, &x, &y,
> - fb, i, fb-
> >pitches[i],
> - DRM_MODE_ROTATE_0,
> tile_size);
> + offset = intel_compute_aligned_offset(dev_priv, &x, &y,
> fb, i,
> + fb->pitches[i],
> + DRM_MODE_ROTATE_0
> ,
> + tile_size);
> offset /= tile_size;
>
> if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> @@ -2608,10 +2610,10 @@ intel_fill_fb_info(struct drm_i915_private
> *dev_priv,
> * We only keep the x/y offsets, so push all of
> the
> * gtt offset into the x/y offsets.
> */
> - __intel_adjust_tile_offset(&x, &y,
> - tile_width,
> tile_height,
> - tile_size,
> pitch_tiles,
> - gtt_offset_rotated *
> tile_size, 0);
> + intel_adjust_tile_offset(&x, &y,
> + tile_width,
> tile_height,
> + tile_size,
> pitch_tiles,
> + gtt_offset_rotated *
> tile_size, 0);
>
> gtt_offset_rotated += rot_info->plane[i].width
> * rot_info->plane[i].height;
>
> @@ -2960,8 +2962,8 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
>
> x = aux_x / hsub;
> y = aux_y / vsub;
> - aux_offset = intel_adjust_tile_offset(&x, &y,
> plane_state, 1,
> - aux_offset,
> aux_offset - alignment);
> + aux_offset = intel_plane_adjust_aligned_offset(&x, &y,
> plane_state, 1,
> + aux_offs
> et, aux_offset - alignment);
> aux_x = x * hsub + aux_x % hsub;
> aux_y = y * vsub + aux_y % vsub;
> }
> @@ -3019,7 +3021,7 @@ static int skl_check_main_surface(const struct
> intel_crtc_state *crtc_state,
> }
>
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> - offset = intel_compute_tile_offset(&x, &y, plane_state, 0);
> + offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 0);
> alignment = intel_surf_alignment(fb, 0);
>
> /*
> @@ -3028,8 +3030,8 @@ static int skl_check_main_surface(const struct
> intel_crtc_state *crtc_state,
> * sure that is what we will get.
> */
> if (offset > aux_offset)
> - offset = intel_adjust_tile_offset(&x, &y, plane_state,
> 0,
> - offset, aux_offset &
> ~(alignment - 1));
> + offset = intel_plane_adjust_aligned_offset(&x, &y,
> plane_state, 0,
> + offset,
> aux_offset & ~(alignment - 1));
>
> /*
> * When using an X-tiled surface, the plane blows up
> @@ -3046,8 +3048,8 @@ static int skl_check_main_surface(const struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - offset = intel_adjust_tile_offset(&x, &y,
> plane_state, 0,
> - offset,
> offset - alignment);
> + offset = intel_plane_adjust_aligned_offset(&x,
> &y, plane_state, 0,
> + offs
> et, offset - alignment);
> }
> }
>
> @@ -3061,8 +3063,8 @@ static int skl_check_main_surface(const struct
> intel_crtc_state *crtc_state,
> if (offset == 0)
> break;
>
> - offset = intel_adjust_tile_offset(&x, &y,
> plane_state, 0,
> - offset,
> offset - alignment);
> + offset = intel_plane_adjust_aligned_offset(&x,
> &y, plane_state, 0,
> + offs
> et, offset - alignment);
> }
>
> if (x != plane_state->aux.x || y != plane_state->aux.y)
> {
> @@ -3114,7 +3116,7 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
> u32 offset;
>
> intel_add_fb_offsets(&x, &y, plane_state, 1);
> - offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
> + offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>
> /* FIXME not quite sure how/if these apply to the chroma plane
> */
> if (w > max_width || h > max_height) {
> @@ -3148,7 +3150,7 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
> }
>
> intel_add_fb_offsets(&x, &y, plane_state, 1);
> - offset = intel_compute_tile_offset(&x, &y, plane_state, 1);
> + offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>
> plane_state->aux.offset = offset;
> plane_state->aux.x = x * hsub + src_x % hsub;
> @@ -3281,8 +3283,8 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>
> if (INTEL_GEN(dev_priv) >= 4)
> - offset = intel_compute_tile_offset(&src_x, &src_y,
> - plane_state, 0);
> + offset = intel_plane_compute_aligned_offset(&src_x,
> &src_y,
> + plane_state
> , 0);
> else
> offset = 0;
>
> @@ -9657,7 +9659,8 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> src_y = plane_state->base.src_y >> 16;
>
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> - offset = intel_compute_tile_offset(&src_x, &src_y, plane_state,
> 0);
> + offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> + plane_state, 0);
>
> if (src_x != 0 || src_y != 0) {
> DRM_DEBUG_KMS("Arbitrary cursor panning not
> supported\n");
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index c275f91244a6..b9f6de3a8f53 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1604,8 +1604,6 @@ void assert_fdi_rx_pll(struct drm_i915_private
> *dev_priv,
> void assert_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
> bool state);
> #define assert_pipe_enabled(d, p) assert_pipe(d, p, true)
> #define assert_pipe_disabled(d, p) assert_pipe(d, p, false)
> -u32 intel_compute_tile_offset(int *x, int *y,
> - const struct intel_plane_state *state,
> int plane);
> void intel_prepare_reset(struct drm_i915_private *dev_priv);
> void intel_finish_reset(struct drm_i915_private *dev_priv);
> void hsw_enable_pc8(struct drm_i915_private *dev_priv);
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 03/18] drm/i915: Add .max_stride() plane hook
2018-07-19 18:21 ` [PATCH 03/18] drm/i915: Add .max_stride() plane hook Ville Syrjala
@ 2018-08-22 22:03 ` Souza, Jose
2018-08-22 22:19 ` Souza, Jose
2018-08-23 14:52 ` Ville Syrjälä
0 siblings, 2 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 22:03 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:21 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Each plane may have different stride limitations. Let's add a new
> plane function to retutn the maximum stride for each plane. There's
> going to be some use for this outside the .atomic_check() stuff hence
> the separate hook.
I just not checked the the spec for the VLV and CHV other than that
LGTM but just take a look to the nitpick bellow:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 46
> ++++++++++++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_drv.h | 10 ++++++++
> drivers/gpu/drm/i915/intel_sprite.c | 34 ++++++++++++++++++++++++--
> 3 files changed, 88 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 5f8304a11482..a09e11e0596f 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3210,6 +3210,31 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> return 0;
> }
>
> +unsigned int
> +i9xx_plane_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> +
> + if (INTEL_GEN(dev_priv) >= 4) {
> + if (modifier == I915_FORMAT_MOD_X_TILED)
> + return 16*1024;
> + else
> + return 32*1024;
> + } else if (INTEL_GEN(dev_priv) >= 3) {
> + if (modifier == I915_FORMAT_MOD_X_TILED)
> + return 8*1024;
> + else
> + return 16*1024;
> + } else {
> + if (plane->i9xx_plane == PLANE_C)
> + return 4*1024;
> + else
> + return 8*1024;
> + }
> +}
> +
> static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> @@ -9672,6 +9697,14 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> return 0;
> }
>
> +static unsigned int
> +i845_cursor_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + return 2048;
> +}
> +
> static u32 i845_cursor_ctl(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> @@ -9805,6 +9838,14 @@ static bool i845_cursor_get_hw_state(struct
> intel_plane *plane,
> return ret;
> }
>
> +static unsigned int
> +i9xx_cursor_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + return plane->base.dev->mode_config.cursor_width * 4;
> +}
> +
> static u32 i9xx_cursor_ctl(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> @@ -13699,6 +13740,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> else
> modifiers = skl_format_modifiers_noccs;
>
> + primary->max_stride = skl_plane_max_stride;
> primary->update_plane = skl_update_plane;
> primary->disable_plane = skl_disable_plane;
> primary->get_hw_state = skl_plane_get_hw_state;
> @@ -13709,6 +13751,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> num_formats = ARRAY_SIZE(i965_primary_formats);
> modifiers = i9xx_format_modifiers;
>
> + primary->max_stride = i9xx_plane_max_stride;
> primary->update_plane = i9xx_update_plane;
> primary->disable_plane = i9xx_disable_plane;
> primary->get_hw_state = i9xx_plane_get_hw_state;
> @@ -13719,6 +13762,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> num_formats = ARRAY_SIZE(i8xx_primary_formats);
> modifiers = i9xx_format_modifiers;
>
> + primary->max_stride = i9xx_plane_max_stride;
> primary->update_plane = i9xx_update_plane;
> primary->disable_plane = i9xx_disable_plane;
> primary->get_hw_state = i9xx_plane_get_hw_state;
> @@ -13826,11 +13870,13 @@ intel_cursor_plane_create(struct
> drm_i915_private *dev_priv,
> cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> + cursor->max_stride = i845_cursor_max_stride;
> cursor->update_plane = i845_update_cursor;
> cursor->disable_plane = i845_disable_cursor;
> cursor->get_hw_state = i845_cursor_get_hw_state;
> cursor->check_plane = i845_check_cursor;
> } else {
> + cursor->max_stride = i9xx_cursor_max_stride;
> cursor->update_plane = i9xx_update_cursor;
> cursor->disable_plane = i9xx_disable_cursor;
> cursor->get_hw_state = i9xx_cursor_get_hw_state;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index b9f6de3a8f53..ad2bd62ee553 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -963,6 +963,9 @@ struct intel_plane {
> * the intel_plane_state structure and accessed via
> plane_state.
> */
>
> + unsigned int (*max_stride)(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation);
> void (*update_plane)(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state
> *plane_state);
> @@ -1652,6 +1655,9 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
> +unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation);
>
> /* intel_csr.c */
> void intel_csr_ucode_init(struct drm_i915_private *);
> @@ -2102,6 +2108,10 @@ bool skl_plane_has_ccs(struct drm_i915_private
> *dev_priv,
> enum pipe pipe, enum plane_id plane_id);
> bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> enum pipe pipe, enum plane_id plane_id);
> +unsigned int skl_plane_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation);
> +
>
> /* intel_tv.c */
> void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index f7026e887fa9..e35760814f25 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -228,6 +228,23 @@ void intel_pipe_update_end(struct
> intel_crtc_state *new_crtc_state)
> #endif
> }
>
> +unsigned int
> +skl_plane_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + int cpp = drm_format_plane_cpp(pixel_format, 0);
> +
> + /*
> + * "The stride in bytes must not exceed the
> + * of the size of 8K pixels and 32K bytes."
> + */
> + if (drm_rotation_90_or_270(rotation))
> + return min(8192, 32768 / cpp);
> + else
> + return min(8192 * cpp, 32768);
> +}
> +
> void
> skl_update_plane(struct intel_plane *plane,
> const struct intel_crtc_state *crtc_state,
> @@ -798,6 +815,14 @@ ivb_plane_get_hw_state(struct intel_plane
> *plane,
> return ret;
> }
>
> +static unsigned int
> +g4x_sprite_max_stride(struct intel_plane *plane,
> + u32 pixel_format, u64 modifier,
> + unsigned int rotation)
> +{
> + return 16384;
> +}
> +
> static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> @@ -964,7 +989,6 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_framebuffer *fb = state->base.fb;
> - int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
Why not keep max_stride and call plane->max_stride() here or in a line
bellow, this would make less changes a easier 'if' to read and fix the
line over 80 characters warning.
> int max_scale, min_scale;
> bool can_scale;
> int ret;
> @@ -982,7 +1006,9 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> }
>
> /* FIXME check all gen limits */
> - if (fb->width < 3 || fb->height < 3 || fb->pitches[0] >
> max_stride) {
> + if (fb->width < 3 || fb->height < 3 ||
> + fb->pitches[0] > plane->max_stride(plane, fb->format-
> >format,
> + fb->modifier,
> DRM_MODE_ROTATE_0)) {
> DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
> return -EINVAL;
> }
> @@ -1528,6 +1554,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->has_ccs = skl_plane_has_ccs(dev_priv,
> pipe,
> PLANE_SPRITE0
> + plane);
>
> + intel_plane->max_stride = skl_plane_max_stride;
> intel_plane->update_plane = skl_update_plane;
> intel_plane->disable_plane = skl_disable_plane;
> intel_plane->get_hw_state = skl_plane_get_hw_state;
> @@ -1551,6 +1578,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->can_scale = false;
> intel_plane->max_downscale = 1;
>
> + intel_plane->max_stride = i9xx_plane_max_stride;
> intel_plane->update_plane = vlv_update_plane;
> intel_plane->disable_plane = vlv_disable_plane;
> intel_plane->get_hw_state = vlv_plane_get_hw_state;
> @@ -1569,6 +1597,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->max_downscale = 1;
> }
>
> + intel_plane->max_stride = g4x_sprite_max_stride;
> intel_plane->update_plane = ivb_update_plane;
> intel_plane->disable_plane = ivb_disable_plane;
> intel_plane->get_hw_state = ivb_plane_get_hw_state;
> @@ -1582,6 +1611,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->can_scale = true;
> intel_plane->max_downscale = 16;
>
> + intel_plane->max_stride = g4x_sprite_max_stride;
> intel_plane->update_plane = g4x_update_plane;
> intel_plane->disable_plane = g4x_disable_plane;
> intel_plane->get_hw_state = g4x_plane_get_hw_state;
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 03/18] drm/i915: Add .max_stride() plane hook
2018-08-22 22:03 ` Souza, Jose
@ 2018-08-22 22:19 ` Souza, Jose
2018-08-23 14:48 ` Ville Syrjälä
2018-08-23 14:52 ` Ville Syrjälä
1 sibling, 1 reply; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 22:19 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Wed, 2018-08-22 at 22:03 +0000, Souza, Jose wrote:
> On Thu, 2018-07-19 at 21:21 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Each plane may have different stride limitations. Let's add a new
> > plane function to retutn the maximum stride for each plane. There's
> > going to be some use for this outside the .atomic_check() stuff
> > hence
> > the separate hook.
>
> I just not checked the the spec for the VLV and CHV other than that
> LGTM but just take a look to the nitpick bellow:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 46
> > ++++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 10 ++++++++
> > drivers/gpu/drm/i915/intel_sprite.c | 34
> > ++++++++++++++++++++++++--
> > 3 files changed, 88 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 5f8304a11482..a09e11e0596f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3210,6 +3210,31 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > return 0;
> > }
> >
> > +unsigned int
> > +i9xx_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
Reviwing 'drm/i915: Use pipe A primary plane .max_stride() as the
global stride limit' I notice that this case was not moved here:
} else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
return 32*1024;
}
Not relevant anymore?
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > + return 16*1024;
> > + else
> > + return 32*1024;
> > + } else if (INTEL_GEN(dev_priv) >= 3) {
> > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > + return 8*1024;
> > + else
> > + return 16*1024;
> > + } else {
> > + if (plane->i9xx_plane == PLANE_C)
> > + return 4*1024;
> > + else
> > + return 8*1024;
> > + }
> > +}
> > +
> > static u32 i9xx_plane_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -9672,6 +9697,14 @@ static int intel_check_cursor(struct
> > intel_crtc_state *crtc_state,
> > return 0;
> > }
> >
> > +static unsigned int
> > +i845_cursor_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return 2048;
> > +}
> > +
> > static u32 i845_cursor_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -9805,6 +9838,14 @@ static bool i845_cursor_get_hw_state(struct
> > intel_plane *plane,
> > return ret;
> > }
> >
> > +static unsigned int
> > +i9xx_cursor_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return plane->base.dev->mode_config.cursor_width * 4;
> > +}
> > +
> > static u32 i9xx_cursor_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -13699,6 +13740,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > else
> > modifiers = skl_format_modifiers_noccs;
> >
> > + primary->max_stride = skl_plane_max_stride;
> > primary->update_plane = skl_update_plane;
> > primary->disable_plane = skl_disable_plane;
> > primary->get_hw_state = skl_plane_get_hw_state;
> > @@ -13709,6 +13751,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > num_formats = ARRAY_SIZE(i965_primary_formats);
> > modifiers = i9xx_format_modifiers;
> >
> > + primary->max_stride = i9xx_plane_max_stride;
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > @@ -13719,6 +13762,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > num_formats = ARRAY_SIZE(i8xx_primary_formats);
> > modifiers = i9xx_format_modifiers;
> >
> > + primary->max_stride = i9xx_plane_max_stride;
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > @@ -13826,11 +13870,13 @@ intel_cursor_plane_create(struct
> > drm_i915_private *dev_priv,
> > cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
> >
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> > + cursor->max_stride = i845_cursor_max_stride;
> > cursor->update_plane = i845_update_cursor;
> > cursor->disable_plane = i845_disable_cursor;
> > cursor->get_hw_state = i845_cursor_get_hw_state;
> > cursor->check_plane = i845_check_cursor;
> > } else {
> > + cursor->max_stride = i9xx_cursor_max_stride;
> > cursor->update_plane = i9xx_update_cursor;
> > cursor->disable_plane = i9xx_disable_cursor;
> > cursor->get_hw_state = i9xx_cursor_get_hw_state;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index b9f6de3a8f53..ad2bd62ee553 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -963,6 +963,9 @@ struct intel_plane {
> > * the intel_plane_state structure and accessed via
> > plane_state.
> > */
> >
> > + unsigned int (*max_stride)(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> > void (*update_plane)(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state
> > *plane_state);
> > @@ -1652,6 +1655,9 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state);
> > int i9xx_check_plane_surface(struct intel_plane_state
> > *plane_state);
> > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
> > +unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> >
> > /* intel_csr.c */
> > void intel_csr_ucode_init(struct drm_i915_private *);
> > @@ -2102,6 +2108,10 @@ bool skl_plane_has_ccs(struct
> > drm_i915_private
> > *dev_priv,
> > enum pipe pipe, enum plane_id plane_id);
> > bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id);
> > +unsigned int skl_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> > +
> >
> > /* intel_tv.c */
> > void intel_tv_init(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index f7026e887fa9..e35760814f25 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -228,6 +228,23 @@ void intel_pipe_update_end(struct
> > intel_crtc_state *new_crtc_state)
> > #endif
> > }
> >
> > +unsigned int
> > +skl_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + int cpp = drm_format_plane_cpp(pixel_format, 0);
> > +
> > + /*
> > + * "The stride in bytes must not exceed the
> > + * of the size of 8K pixels and 32K bytes."
> > + */
> > + if (drm_rotation_90_or_270(rotation))
> > + return min(8192, 32768 / cpp);
> > + else
> > + return min(8192 * cpp, 32768);
> > +}
> > +
> > void
> > skl_update_plane(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > @@ -798,6 +815,14 @@ ivb_plane_get_hw_state(struct intel_plane
> > *plane,
> > return ret;
> > }
> >
> > +static unsigned int
> > +g4x_sprite_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return 16384;
> > +}
> > +
> > static u32 g4x_sprite_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -964,7 +989,6 @@ intel_check_sprite_plane(struct intel_plane
> > *plane,
> > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > struct drm_framebuffer *fb = state->base.fb;
> > - int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
>
> Why not keep max_stride and call plane->max_stride() here or in a
> line
> bellow, this would make less changes a easier 'if' to read and fix
> the
> line over 80 characters warning.
>
> > int max_scale, min_scale;
> > bool can_scale;
> > int ret;
> > @@ -982,7 +1006,9 @@ intel_check_sprite_plane(struct intel_plane
> > *plane,
> > }
> >
> > /* FIXME check all gen limits */
> > - if (fb->width < 3 || fb->height < 3 || fb->pitches[0] >
> > max_stride) {
> > + if (fb->width < 3 || fb->height < 3 ||
> > + fb->pitches[0] > plane->max_stride(plane, fb->format-
> > > format,
> >
> > + fb->modifier,
> > DRM_MODE_ROTATE_0)) {
> > DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
> > return -EINVAL;
> > }
> > @@ -1528,6 +1554,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->has_ccs = skl_plane_has_ccs(dev_priv,
> > pipe,
> > PLANE_SPRITE0
> > + plane);
> >
> > + intel_plane->max_stride = skl_plane_max_stride;
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > intel_plane->get_hw_state = skl_plane_get_hw_state;
> > @@ -1551,6 +1578,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->can_scale = false;
> > intel_plane->max_downscale = 1;
> >
> > + intel_plane->max_stride = i9xx_plane_max_stride;
> > intel_plane->update_plane = vlv_update_plane;
> > intel_plane->disable_plane = vlv_disable_plane;
> > intel_plane->get_hw_state = vlv_plane_get_hw_state;
> > @@ -1569,6 +1597,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->max_downscale = 1;
> > }
> >
> > + intel_plane->max_stride = g4x_sprite_max_stride;
> > intel_plane->update_plane = ivb_update_plane;
> > intel_plane->disable_plane = ivb_disable_plane;
> > intel_plane->get_hw_state = ivb_plane_get_hw_state;
> > @@ -1582,6 +1611,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->can_scale = true;
> > intel_plane->max_downscale = 16;
> >
> > + intel_plane->max_stride = g4x_sprite_max_stride;
> > intel_plane->update_plane = g4x_update_plane;
> > intel_plane->disable_plane = g4x_disable_plane;
> > intel_plane->get_hw_state = g4x_plane_get_hw_state;
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit
2018-07-19 18:22 ` [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit Ville Syrjala
@ 2018-08-22 22:22 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 22:22 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's assume that the primary plane for pipe A has the highest max
> stride of all planes, and we'll use that as the global limit when
> creating a new framebuffer.
Well it was already assuming that but using the new max_stride hook is
way better.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 33 ++++++++++--------------
> ---------
> 1 file changed, 10 insertions(+), 23 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index a09e11e0596f..994685230b97 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -14399,31 +14399,18 @@ static
> u32 intel_fb_pitch_limit(struct drm_i915_private *dev_priv,
> uint64_t fb_modifier, uint32_t pixel_format)
> {
> - u32 gen = INTEL_GEN(dev_priv);
> + struct intel_crtc *crtc;
> + struct intel_plane *plane;
>
> - if (gen >= 9) {
> - int cpp = drm_format_plane_cpp(pixel_format, 0);
> + /*
> + * We assume the primary plane for pipe A has
> + * the highest stride limits of them all.
> + */
> + crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A);
> + plane = to_intel_plane(crtc->base.primary);
>
> - /* "The stride in bytes must not exceed the of the size
> of 8K
> - * pixels and 32K bytes."
> - */
> - return min(8192 * cpp, 32768);
> - } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
> - return 32*1024;
> - } else if (gen >= 4) {
> - if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> - return 16*1024;
> - else
> - return 32*1024;
> - } else if (gen >= 3) {
> - if (fb_modifier == I915_FORMAT_MOD_X_TILED)
> - return 8*1024;
> - else
> - return 16*1024;
> - } else {
> - /* XXX DSPC is limited to 4k tiled */
> - return 8*1024;
> - }
> + return plane->max_stride(plane, pixel_format, fb_modifier,
> + DRM_MODE_ROTATE_0);
> }
>
> static int intel_framebuffer_init(struct intel_framebuffer
> *intel_fb,
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[]
2018-07-19 18:22 ` [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] Ville Syrjala
@ 2018-08-22 23:02 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 23:02 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Make the main/aux surface stuff a bit more generic by using an array
> of structures. This will allow us to deal with both the main and aux
> surfaces with common code.
Nitpick: consider having a enum { SURFACE_MAIN = 0, SURFACE_AUX } and
use it instead of the magic numbers 0 and 1.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 56 ++++++++++++++++++------
> ------------
> drivers/gpu/drm/i915/intel_drv.h | 6 +---
> drivers/gpu/drm/i915/intel_fbc.c | 4 +--
> drivers/gpu/drm/i915/intel_sprite.c | 29 ++++++++++---------
> 4 files changed, 46 insertions(+), 49 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 994685230b97..3aec789657b1 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2946,9 +2946,9 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> const struct drm_framebuffer *fb = plane_state->base.fb;
> int hsub = fb->format->hsub;
> int vsub = fb->format->vsub;
> - int aux_x = plane_state->aux.x;
> - int aux_y = plane_state->aux.y;
> - u32 aux_offset = plane_state->aux.offset;
> + int aux_x = plane_state->color_plane[1].x;
> + int aux_y = plane_state->color_plane[1].y;
> + u32 aux_offset = plane_state->color_plane[1].offset;
> u32 alignment = intel_surf_alignment(fb, 1);
>
> while (aux_offset >= main_offset && aux_y <= main_y) {
> @@ -2971,9 +2971,9 @@ static bool
> skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> if (aux_x != main_x || aux_y != main_y)
> return false;
>
> - plane_state->aux.offset = aux_offset;
> - plane_state->aux.x = aux_x;
> - plane_state->aux.y = aux_y;
> + plane_state->color_plane[1].offset = aux_offset;
> + plane_state->color_plane[1].x = aux_x;
> + plane_state->color_plane[1].y = aux_y;
>
> return true;
> }
> @@ -2994,7 +2994,7 @@ static int skl_check_main_surface(const struct
> intel_crtc_state *crtc_state,
> int pipe_src_w = crtc_state->pipe_src_w;
> int max_width = skl_max_plane_width(fb, 0, rotation);
> int max_height = 4096;
> - u32 alignment, offset, aux_offset = plane_state->aux.offset;
> + u32 alignment, offset, aux_offset = plane_state-
> >color_plane[1].offset;
>
> if (w > max_width || h > max_height) {
> DRM_DEBUG_KMS("requested Y/RGB source size %dx%d too
> big (limit %dx%d)\n",
> @@ -3067,15 +3067,15 @@ static int skl_check_main_surface(const
> struct intel_crtc_state *crtc_state,
> offs
> et, offset - alignment);
> }
>
> - if (x != plane_state->aux.x || y != plane_state->aux.y)
> {
> + if (x != plane_state->color_plane[1].x || y !=
> plane_state->color_plane[1].y) {
> DRM_DEBUG_KMS("Unable to find suitable display
> surface offset due to CCS\n");
> return -EINVAL;
> }
> }
>
> - plane_state->main.offset = offset;
> - plane_state->main.x = x;
> - plane_state->main.y = y;
> + plane_state->color_plane[0].offset = offset;
> + plane_state->color_plane[0].x = x;
> + plane_state->color_plane[0].y = y;
>
> return 0;
> }
> @@ -3125,9 +3125,9 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
> return -EINVAL;
> }
>
> - plane_state->aux.offset = offset;
> - plane_state->aux.x = x;
> - plane_state->aux.y = y;
> + plane_state->color_plane[1].offset = offset;
> + plane_state->color_plane[1].x = x;
> + plane_state->color_plane[1].y = y;
>
> return 0;
> }
> @@ -3152,9 +3152,9 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
> intel_add_fb_offsets(&x, &y, plane_state, 1);
> offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>
> - plane_state->aux.offset = offset;
> - plane_state->aux.x = x * hsub + src_x % hsub;
> - plane_state->aux.y = y * vsub + src_y % vsub;
> + plane_state->color_plane[1].offset = offset;
> + plane_state->color_plane[1].x = x * hsub + src_x % hsub;
> + plane_state->color_plane[1].y = y * vsub + src_y % vsub;
>
> return 0;
> }
> @@ -3198,9 +3198,9 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> if (ret)
> return ret;
> } else {
> - plane_state->aux.offset = ~0xfff;
> - plane_state->aux.x = 0;
> - plane_state->aux.y = 0;
> + plane_state->color_plane[1].offset = ~0xfff;
> + plane_state->color_plane[1].x = 0;
> + plane_state->color_plane[1].y = 0;
> }
>
> ret = skl_check_main_surface(crtc_state, plane_state);
> @@ -3327,9 +3327,9 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
> }
> }
>
> - plane_state->main.offset = offset;
> - plane_state->main.x = src_x;
> - plane_state->main.y = src_y;
> + plane_state->color_plane[0].offset = offset;
> + plane_state->color_plane[0].x = src_x;
> + plane_state->color_plane[0].y = src_y;
>
> return 0;
> }
> @@ -3344,15 +3344,15 @@ static void i9xx_update_plane(struct
> intel_plane *plane,
> u32 linear_offset;
> u32 dspcntr = plane_state->ctl;
> i915_reg_t reg = DSPCNTR(i9xx_plane);
> - int x = plane_state->main.x;
> - int y = plane_state->main.y;
> + int x = plane_state->color_plane[0].x;
> + int y = plane_state->color_plane[0].y;
> unsigned long irqflags;
> u32 dspaddr_offset;
>
> linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
>
> if (INTEL_GEN(dev_priv) >= 4)
> - dspaddr_offset = plane_state->main.offset;
> + dspaddr_offset = plane_state->color_plane[0].offset;
> else
> dspaddr_offset = linear_offset;
>
> @@ -9613,7 +9613,7 @@ static u32 intel_cursor_base(const struct
> intel_plane_state *plane_state)
> else
> base = intel_plane_ggtt_offset(plane_state);
>
> - base += plane_state->main.offset;
> + base += plane_state->color_plane[0].offset;
>
> /* ILK+ do this automagically */
> if (HAS_GMCH_DISPLAY(dev_priv) &&
> @@ -9692,7 +9692,7 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - plane_state->main.offset = offset;
> + plane_state->color_plane[0].offset = offset;
>
> return 0;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index ad2bd62ee553..24282b855e81 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -501,11 +501,7 @@ struct intel_plane_state {
> struct {
> u32 offset;
> int x, y;
> - } main;
> - struct {
> - u32 offset;
> - int x, y;
> - } aux;
> + } color_plane[2];
>
> /* plane control register */
> u32 ctl;
> diff --git a/drivers/gpu/drm/i915/intel_fbc.c
> b/drivers/gpu/drm/i915/intel_fbc.c
> index 01d1d2088f04..74d425c700ef 100644
> --- a/drivers/gpu/drm/i915/intel_fbc.c
> +++ b/drivers/gpu/drm/i915/intel_fbc.c
> @@ -670,8 +670,8 @@ static void intel_fbc_update_state_cache(struct
> intel_crtc *crtc,
> cache->plane.src_w = drm_rect_width(&plane_state->base.src) >>
> 16;
> cache->plane.src_h = drm_rect_height(&plane_state->base.src) >>
> 16;
> cache->plane.visible = plane_state->base.visible;
> - cache->plane.adjusted_x = plane_state->main.x;
> - cache->plane.adjusted_y = plane_state->main.y;
> + cache->plane.adjusted_x = plane_state->color_plane[0].x;
> + cache->plane.adjusted_y = plane_state->color_plane[0].y;
> cache->plane.y = plane_state->base.src.y1 >> 16;
>
> if (!cache->plane.visible)
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index e35760814f25..d4b3d32d5e4a 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -256,7 +256,7 @@ skl_update_plane(struct intel_plane *plane,
> enum pipe pipe = plane->pipe;
> u32 plane_ctl = plane_state->ctl;
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> - u32 surf_addr = plane_state->main.offset;
> + u32 surf_addr = plane_state->color_plane[0].offset;
> unsigned int rotation = plane_state->base.rotation;
> u32 stride = skl_plane_stride(fb, 0, rotation);
> u32 aux_stride = skl_plane_stride(fb, 1, rotation);
> @@ -264,8 +264,8 @@ skl_update_plane(struct intel_plane *plane,
> int crtc_y = plane_state->base.dst.y1;
> uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->main.x;
> - uint32_t y = plane_state->main.y;
> + uint32_t x = plane_state->color_plane[0].x;
> + uint32_t y = plane_state->color_plane[0].y;
> uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> unsigned long irqflags;
> @@ -292,9 +292,10 @@ skl_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
> I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) |
> src_w);
> I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
> - (plane_state->aux.offset - surf_addr) |
> aux_stride);
> + (plane_state->color_plane[1].offset - surf_addr)
> | aux_stride);
> I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
> - (plane_state->aux.y << 16) | plane_state->aux.x);
> + (plane_state->color_plane[1].y << 16) |
> + plane_state->color_plane[1].x);
>
> /* program plane scaler */
> if (plane_state->scaler_id >= 0) {
> @@ -560,15 +561,15 @@ vlv_update_plane(struct intel_plane *plane,
> enum pipe pipe = plane->pipe;
> enum plane_id plane_id = plane->id;
> u32 sprctl = plane_state->ctl;
> - u32 sprsurf_offset = plane_state->main.offset;
> + u32 sprsurf_offset = plane_state->color_plane[0].offset;
> u32 linear_offset;
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->main.x;
> - uint32_t y = plane_state->main.y;
> + uint32_t x = plane_state->color_plane[0].x;
> + uint32_t y = plane_state->color_plane[0].y;
> unsigned long irqflags;
>
> /* Sizes are 0 based */
> @@ -719,15 +720,15 @@ ivb_update_plane(struct intel_plane *plane,
> const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> u32 sprctl = plane_state->ctl, sprscale = 0;
> - u32 sprsurf_offset = plane_state->main.offset;
> + u32 sprsurf_offset = plane_state->color_plane[0].offset;
> u32 linear_offset;
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->main.x;
> - uint32_t y = plane_state->main.y;
> + uint32_t x = plane_state->color_plane[0].x;
> + uint32_t y = plane_state->color_plane[0].y;
> uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> unsigned long irqflags;
> @@ -891,15 +892,15 @@ g4x_update_plane(struct intel_plane *plane,
> const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> u32 dvscntr = plane_state->ctl, dvsscale = 0;
> - u32 dvssurf_offset = plane_state->main.offset;
> + u32 dvssurf_offset = plane_state->color_plane[0].offset;
> u32 linear_offset;
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
> - uint32_t x = plane_state->main.x;
> - uint32_t y = plane_state->main.y;
> + uint32_t x = plane_state->color_plane[0].x;
> + uint32_t y = plane_state->color_plane[0].y;
> uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
> uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
> unsigned long irqflags;
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH v2 06/18] drm/i915: Store the final plane stride in plane_state
2018-07-20 11:06 ` [PATCH v2 " Ville Syrjala
@ 2018-08-22 23:44 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-22 23:44 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Fri, 2018-07-20 at 14:06 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Let's store the final plane stride in the plane state. This avoids
> having to pick betwen the normal vs. rotated stride during hardware
s/betwen/between
> programming. And once we get GTT remapping the plane stride will
> no longer match the fb stride so we'll need a place to store it
> anyway.
>
> v2: Keep checking fb->pitches[0] for cursor as later on we won't
> populate plane_state->color_plane[0].stride for invisible planes
> and we have been checking the cursor fb stride even for invisible
> planes
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 45 +++++++++++++++++++++++++-
> ----------
> drivers/gpu/drm/i915/intel_drv.h | 10 ++++++--
> drivers/gpu/drm/i915/intel_sprite.c | 12 +++++-----
> 3 files changed, 45 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 3aec789657b1..6184053fd385 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2202,7 +2202,7 @@ u32 intel_fb_xy_to_linear(int x, int y,
> {
> const struct drm_framebuffer *fb = state->base.fb;
> unsigned int cpp = fb->format->cpp[plane];
> - unsigned int pitch = fb->pitches[plane];
> + unsigned int pitch = state->color_plane[plane].stride;
>
> return y * pitch + x * cpp;
> }
> @@ -2259,11 +2259,11 @@ static u32 intel_adjust_tile_offset(int *x,
> int *y,
> static u32 intel_adjust_aligned_offset(int *x, int *y,
> const struct drm_framebuffer
> *fb, int plane,
> unsigned int rotation,
> + unsigned int pitch,
> u32 old_offset, u32 new_offset)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> unsigned int cpp = fb->format->cpp[plane];
> - unsigned int pitch = intel_fb_pitch(fb, plane, rotation);
>
> WARN_ON(new_offset > old_offset);
>
> @@ -2305,6 +2305,7 @@ static u32
> intel_plane_adjust_aligned_offset(int *x, int *y,
> {
> return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
> state->base.rotation,
> + state-
> >color_plane[plane].stride,
> old_offset, new_offset);
> }
>
> @@ -2381,7 +2382,7 @@ static u32
> intel_plane_compute_aligned_offset(int *x, int *y,
> struct drm_i915_private *dev_priv = to_i915(intel_plane-
> >base.dev);
> const struct drm_framebuffer *fb = state->base.fb;
> unsigned int rotation = state->base.rotation;
> - int pitch = intel_fb_pitch(fb, plane, rotation);
> + int pitch = state->color_plane[plane].stride;
> u32 alignment;
>
> if (intel_plane->id == PLANE_CURSOR)
> @@ -2408,6 +2409,7 @@ static int intel_fb_offset_to_xy(int *x, int
> *y,
>
> intel_adjust_aligned_offset(x, y,
> fb, plane, DRM_MODE_ROTATE_0,
> + fb->pitches[0],
> fb->offsets[plane], 0);
>
> return 0;
> @@ -2849,6 +2851,9 @@ intel_find_initial_plane_obj(struct intel_crtc
> *intel_crtc,
> return;
>
> valid_fb:
> + intel_state->color_plane[0].stride =
> + intel_fb_pitch(fb, 0, intel_state->base.rotation);
> +
> mutex_lock(&dev->struct_mutex);
> intel_state->vma =
> intel_pin_and_fence_fb_obj(fb,
> @@ -3166,6 +3171,9 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> unsigned int rotation = plane_state->base.rotation;
> int ret;
>
> + plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> + plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> rotation);
> +
> if (rotation & DRM_MODE_REFLECT_X &&
> fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> DRM_DEBUG_KMS("horizontal flip is not supported with
> linear surface formats\n");
> @@ -3301,10 +3309,14 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
> {
> struct drm_i915_private *dev_priv =
> to_i915(plane_state->base.plane->dev);
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + unsigned int rotation = plane_state->base.rotation;
> int src_x = plane_state->base.src.x1 >> 16;
> int src_y = plane_state->base.src.y1 >> 16;
> u32 offset;
>
> + plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> +
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
>
> if (INTEL_GEN(dev_priv) >= 4)
> @@ -3315,7 +3327,6 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
>
> /* HSW/BDW do this automagically in hardware */
> if (!IS_HASWELL(dev_priv) && !IS_BROADWELL(dev_priv)) {
> - unsigned int rotation = plane_state->base.rotation;
> int src_w = drm_rect_width(&plane_state->base.src) >>
> 16;
> int src_h = drm_rect_height(&plane_state->base.src) >>
> 16;
>
> @@ -3339,7 +3350,6 @@ static void i9xx_update_plane(struct
> intel_plane *plane,
> const struct intel_plane_state
> *plane_state)
> {
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> enum i9xx_plane_id i9xx_plane = plane->i9xx_plane;
> u32 linear_offset;
> u32 dspcntr = plane_state->ctl;
> @@ -3376,7 +3386,7 @@ static void i9xx_update_plane(struct
> intel_plane *plane,
>
> I915_WRITE_FW(reg, dspcntr);
>
> - I915_WRITE_FW(DSPSTRIDE(i9xx_plane), fb->pitches[0]);
> + I915_WRITE_FW(DSPSTRIDE(i9xx_plane), plane_state-
> >color_plane[0].stride);
> if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> I915_WRITE_FW(DSPSURF(i9xx_plane),
> intel_plane_ggtt_offset(plane_state) +
> @@ -3486,16 +3496,16 @@ static void skl_detach_scalers(struct
> intel_crtc *intel_crtc)
> }
> }
>
> -u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation)
> +u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> + int plane)
> {
> - u32 stride;
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + unsigned int rotation = plane_state->base.rotation;
> + u32 stride = plane_state->color_plane[plane].stride;
>
> if (plane >= fb->format->num_planes)
> return 0;
>
> - stride = intel_fb_pitch(fb, plane, rotation);
> -
> /*
> * The stride is either expressed as a multiple of 64 bytes
> chunks for
> * linear buffers or in number of tiles for tiled buffers.
> @@ -9660,6 +9670,7 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> + unsigned int rotation = plane_state->base.rotation;
> int src_x, src_y;
> u32 offset;
> int ret;
> @@ -9680,6 +9691,8 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> + plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> +
> src_x = plane_state->base.src_x >> 16;
> src_y = plane_state->base.src_y >> 16;
>
> @@ -9708,12 +9721,10 @@ i845_cursor_max_stride(struct intel_plane
> *plane,
> static u32 i845_cursor_ctl(const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state *plane_state)
> {
> - const struct drm_framebuffer *fb = plane_state->base.fb;
> -
> return CURSOR_ENABLE |
> CURSOR_GAMMA_ENABLE |
> CURSOR_FORMAT_ARGB |
> - CURSOR_STRIDE(fb->pitches[0]);
> + CURSOR_STRIDE(plane_state->color_plane[0].stride);
> }
>
> static bool i845_cursor_size_ok(const struct intel_plane_state
> *plane_state)
> @@ -9750,6 +9761,9 @@ static int i845_check_cursor(struct intel_plane
> *plane,
> return -EINVAL;
> }
>
> + WARN_ON(plane_state->base.visible &&
> + plane_state->color_plane[0].stride != fb->pitches[0]);
> +
> switch (fb->pitches[0]) {
> case 256:
> case 512:
> @@ -9951,6 +9965,9 @@ static int i9xx_check_cursor(struct intel_plane
> *plane,
> return -EINVAL;
> }
>
> + WARN_ON(plane_state->base.visible &&
> + plane_state->color_plane[0].stride != fb->pitches[0]);
> +
> if (fb->pitches[0] != plane_state->base.crtc_w * fb->format-
> >cpp[0]) {
> DRM_DEBUG_KMS("Invalid cursor stride (%u) (cursor width
> %d)\n",
> fb->pitches[0], plane_state-
> >base.crtc_w);
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 24282b855e81..f647f9e1f671 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -500,6 +500,12 @@ struct intel_plane_state {
>
> struct {
> u32 offset;
> + /*
> + * Plane stride in:
> + * bytes for 0/180 degree rotation
> + * pixels for 90/270 degree rotation
> + */
> + u32 stride;
> int x, y;
> } color_plane[2];
>
> @@ -1645,8 +1651,8 @@ u32 glk_plane_color_ctl(const struct
> intel_crtc_state *crtc_state,
> u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> const struct intel_plane_state *plane_state);
> u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> -u32 skl_plane_stride(const struct drm_framebuffer *fb, int plane,
> - unsigned int rotation);
> +u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> + int plane);
> int skl_check_plane_surface(const struct intel_crtc_state
> *crtc_state,
> struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index d4b3d32d5e4a..a07d951afbf9 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -257,9 +257,8 @@ skl_update_plane(struct intel_plane *plane,
> u32 plane_ctl = plane_state->ctl;
> const struct drm_intel_sprite_colorkey *key = &plane_state-
> >ckey;
> u32 surf_addr = plane_state->color_plane[0].offset;
> - unsigned int rotation = plane_state->base.rotation;
> - u32 stride = skl_plane_stride(fb, 0, rotation);
> - u32 aux_stride = skl_plane_stride(fb, 1, rotation);
> + u32 stride = skl_plane_stride(plane_state, 0);
> + u32 aux_stride = skl_plane_stride(plane_state, 1);
> int crtc_x = plane_state->base.dst.x1;
> int crtc_y = plane_state->base.dst.y1;
> uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
> @@ -590,7 +589,8 @@ vlv_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key-
> >max_value);
> I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key-
> >channel_mask);
> }
> - I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
> + I915_WRITE_FW(SPSTRIDE(pipe, plane_id),
> + plane_state->color_plane[0].stride);
> I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
>
> if (fb->modifier == I915_FORMAT_MOD_X_TILED)
> @@ -752,7 +752,7 @@ ivb_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
> }
>
> - I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
> + I915_WRITE_FW(SPRSTRIDE(pipe), plane_state-
> >color_plane[0].stride);
> I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
>
> /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single
> SPROFFSET
> @@ -924,7 +924,7 @@ g4x_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
> }
>
> - I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
> + I915_WRITE_FW(DVSSTRIDE(pipe), plane_state-
> >color_plane[0].stride);
> I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
>
> if (fb->modifier == I915_FORMAT_MOD_X_TILED)
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 12/18] drm/i915: Move display w/a #1175
2018-07-19 18:22 ` [PATCH 12/18] drm/i915: Move display w/a #1175 Ville Syrjala
@ 2018-08-23 1:09 ` Rodrigo Vivi
0 siblings, 0 replies; 59+ messages in thread
From: Rodrigo Vivi @ 2018-08-23 1:09 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 09:22:08PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the display w/a #1175 to a better place. That place
> being the new skl+ specific plane->check() hook. This leaves
> the skl_check_plane_surface() stuff to deal with the gtt offset
> and src coordinate stuff as originally envisioned.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 36 +++++-------------------------------
> drivers/gpu/drm/i915/intel_drv.h | 3 +--
> drivers/gpu/drm/i915/intel_sprite.c | 36 +++++++++++++++++++++++++++++++++++-
> 3 files changed, 41 insertions(+), 34 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 2381b762d109..dbcc9a23eefa 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2986,20 +2986,14 @@ static bool skl_check_main_ccs_coordinates(struct intel_plane_state *plane_state
> return true;
> }
>
> -static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state)
> +static int skl_check_main_surface(struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv =
> - to_i915(plane_state->base.plane->dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> int x = plane_state->base.src.x1 >> 16;
> int y = plane_state->base.src.y1 >> 16;
> int w = drm_rect_width(&plane_state->base.src) >> 16;
> int h = drm_rect_height(&plane_state->base.src) >> 16;
> - int dst_x = plane_state->base.dst.x1;
> - int dst_w = drm_rect_width(&plane_state->base.dst);
> - int pipe_src_w = crtc_state->pipe_src_w;
> int max_width = skl_max_plane_width(fb, 0, rotation);
> int max_height = 4096;
> u32 alignment, offset, aux_offset = plane_state->color_plane[1].offset;
> @@ -3010,24 +3004,6 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> - /*
> - * Display WA #1175: cnl,glk
> - * Planes other than the cursor may cause FIFO underflow and display
> - * corruption if starting less than 4 pixels from the right edge of
> - * the screen.
> - * Besides the above WA fix the similar problem, where planes other
> - * than the cursor ending less than 4 pixels from the left edge of the
> - * screen may cause FIFO underflow and display corruption.
> - */
> - if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> - (dst_x + dst_w < 4 || dst_x > pipe_src_w - 4)) {
> - DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
> - dst_x + dst_w < 4 ? "end" : "start",
> - dst_x + dst_w < 4 ? dst_x + dst_w : dst_x,
> - 4, pipe_src_w - 4);
> - return -ERANGE;
> - }
> -
> intel_add_fb_offsets(&x, &y, plane_state, 0);
> offset = intel_plane_compute_aligned_offset(&x, &y, plane_state, 0);
> alignment = intel_surf_alignment(fb, 0);
> @@ -3089,8 +3065,7 @@ static int skl_check_main_surface(const struct intel_crtc_state *crtc_state,
> }
>
> static int
> -skl_check_nv12_surface(const struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state)
> +skl_check_nv12_surface(struct intel_plane_state *plane_state)
> {
> /* Display WA #1106 */
> if (plane_state->base.rotation !=
> @@ -3161,8 +3136,7 @@ static int skl_check_ccs_aux_surface(struct intel_plane_state *plane_state)
> return 0;
> }
>
> -int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state)
> +int skl_check_plane_surface(struct intel_plane_state *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> @@ -3186,7 +3160,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> * the main surface setup depends on it.
> */
> if (fb->format->format == DRM_FORMAT_NV12) {
> - ret = skl_check_nv12_surface(crtc_state, plane_state);
> + ret = skl_check_nv12_surface(plane_state);
> if (ret)
> return ret;
> ret = skl_check_nv12_aux_surface(plane_state);
> @@ -3203,7 +3177,7 @@ int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> plane_state->color_plane[1].y = 0;
> }
>
> - ret = skl_check_main_surface(crtc_state, plane_state);
> + ret = skl_check_main_surface(plane_state);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 6d57c6a508d4..55f3537ba8f8 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1651,8 +1651,7 @@ u32 skl_plane_ctl(const struct intel_crtc_state *crtc_state,
> u32 glk_color_ctl(const struct intel_plane_state *plane_state);
> u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> int plane);
> -int skl_check_plane_surface(const struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state);
> +int skl_check_plane_surface(struct intel_plane_state *plane_state);
> int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
> unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c b/drivers/gpu/drm/i915/intel_sprite.c
> index 041b8921f4fe..f43884f76212 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1218,6 +1218,36 @@ static int skl_plane_check_fb(const struct intel_crtc_state *crtc_state,
> return 0;
> }
>
> +static int skl_plane_check_dst_coordinates(const struct intel_crtc_state *crtc_state,
> + const struct intel_plane_state *plane_state)
> +{
> + struct drm_i915_private *dev_priv =
> + to_i915(plane_state->base.plane->dev);
> + int crtc_x = plane_state->base.dst.x1;
> + int crtc_w = drm_rect_width(&plane_state->base.dst);
> + int pipe_src_w = crtc_state->pipe_src_w;
> +
> + /*
> + * Display WA #1175: cnl,glk
> + * Planes other than the cursor may cause FIFO underflow and display
> + * corruption if starting less than 4 pixels from the right edge of
> + * the screen.
> + * Besides the above WA fix the similar problem, where planes other
> + * than the cursor ending less than 4 pixels from the left edge of the
> + * screen may cause FIFO underflow and display corruption.
> + */
> + if ((IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) &&
> + (crtc_x + crtc_w < 4 || crtc_x > pipe_src_w - 4)) {
> + DRM_DEBUG_KMS("requested plane X %s position %d invalid (valid range %d-%d)\n",
> + crtc_x + crtc_w < 4 ? "end" : "start",
> + crtc_x + crtc_w < 4 ? crtc_x + crtc_w : crtc_x,
> + 4, pipe_src_w - 4);
> + return -ERANGE;
> + }
> +
> + return 0;
> +}
> +
> int skl_plane_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> @@ -1252,11 +1282,15 @@ int skl_plane_check(struct intel_crtc_state *crtc_state,
> if (!plane_state->base.visible)
> return 0;
>
> + ret = skl_plane_check_dst_coordinates(crtc_state, plane_state);
> + if (ret)
> + return ret;
> +
> ret = intel_plane_check_src_coordinates(plane_state);
> if (ret)
> return ret;
>
> - ret = skl_check_plane_surface(crtc_state, plane_state);
> + ret = skl_check_plane_surface(plane_state);
> if (ret)
> return ret;
>
> --
> 2.16.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 08/18] drm/i915: s/int plane/int color_plane/
2018-07-19 18:22 ` [PATCH 08/18] drm/i915: s/int plane/int color_plane/ Ville Syrjala
@ 2018-08-23 1:14 ` Rodrigo Vivi
2018-08-24 0:05 ` Souza, Jose
0 siblings, 1 reply; 59+ messages in thread
From: Rodrigo Vivi @ 2018-08-23 1:14 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
On Thu, Jul 19, 2018 at 09:22:04PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> To reduce the confusion between a drm plane and the planes of
> framebuffers let's desiginate the latter as "color plane".
what about fb_plane instead of color?
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 106 ++++++++++++++++++-----------------
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> 2 files changed, 56 insertions(+), 52 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index e6cb8238f257..bc2a712311ba 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -1916,10 +1916,10 @@ static unsigned int intel_tile_size(const struct drm_i915_private *dev_priv)
> }
>
> static unsigned int
> -intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
> +intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> - unsigned int cpp = fb->format->cpp[plane];
> + unsigned int cpp = fb->format->cpp[color_plane];
>
> switch (fb->modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> @@ -1930,7 +1930,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
> else
> return 512;
> case I915_FORMAT_MOD_Y_TILED_CCS:
> - if (plane == 1)
> + if (color_plane == 1)
> return 128;
> /* fall through */
> case I915_FORMAT_MOD_Y_TILED:
> @@ -1939,7 +1939,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
> else
> return 512;
> case I915_FORMAT_MOD_Yf_TILED_CCS:
> - if (plane == 1)
> + if (color_plane == 1)
> return 128;
> /* fall through */
> case I915_FORMAT_MOD_Yf_TILED:
> @@ -1964,22 +1964,22 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int plane)
> }
>
> static unsigned int
> -intel_tile_height(const struct drm_framebuffer *fb, int plane)
> +intel_tile_height(const struct drm_framebuffer *fb, int color_plane)
> {
> if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> return 1;
> else
> return intel_tile_size(to_i915(fb->dev)) /
> - intel_tile_width_bytes(fb, plane);
> + intel_tile_width_bytes(fb, color_plane);
> }
>
> /* Return the tile dimensions in pixel units */
> -static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
> +static void intel_tile_dims(const struct drm_framebuffer *fb, int color_plane,
> unsigned int *tile_width,
> unsigned int *tile_height)
> {
> - unsigned int tile_width_bytes = intel_tile_width_bytes(fb, plane);
> - unsigned int cpp = fb->format->cpp[plane];
> + unsigned int tile_width_bytes = intel_tile_width_bytes(fb, color_plane);
> + unsigned int cpp = fb->format->cpp[color_plane];
>
> *tile_width = tile_width_bytes / cpp;
> *tile_height = intel_tile_size(to_i915(fb->dev)) / tile_width_bytes;
> @@ -1987,9 +1987,9 @@ static void intel_tile_dims(const struct drm_framebuffer *fb, int plane,
>
> unsigned int
> intel_fb_align_height(const struct drm_framebuffer *fb,
> - int plane, unsigned int height)
> + int color_plane, unsigned int height)
> {
> - unsigned int tile_height = intel_tile_height(fb, plane);
> + unsigned int tile_height = intel_tile_height(fb, color_plane);
>
> return ALIGN(height, tile_height);
> }
> @@ -2043,12 +2043,12 @@ static unsigned int intel_linear_alignment(const struct drm_i915_private *dev_pr
> }
>
> static unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
> - int plane)
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>
> /* AUX_DIST needs only 4K alignment */
> - if (plane == 1)
> + if (color_plane == 1)
> return 4096;
>
> switch (fb->modifier) {
> @@ -2178,13 +2178,13 @@ void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags)
> i915_vma_put(vma);
> }
>
> -static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
> +static int intel_fb_pitch(const struct drm_framebuffer *fb, int color_plane,
> unsigned int rotation)
> {
> if (drm_rotation_90_or_270(rotation))
> - return to_intel_framebuffer(fb)->rotated[plane].pitch;
> + return to_intel_framebuffer(fb)->rotated[color_plane].pitch;
> else
> - return fb->pitches[plane];
> + return fb->pitches[color_plane];
> }
>
> /*
> @@ -2195,11 +2195,11 @@ static int intel_fb_pitch(const struct drm_framebuffer *fb, int plane,
> */
> u32 intel_fb_xy_to_linear(int x, int y,
> const struct intel_plane_state *state,
> - int plane)
> + int color_plane)
> {
> const struct drm_framebuffer *fb = state->base.fb;
> - unsigned int cpp = fb->format->cpp[plane];
> - unsigned int pitch = state->color_plane[plane].stride;
> + unsigned int cpp = fb->format->cpp[color_plane];
> + unsigned int pitch = state->color_plane[color_plane].stride;
>
> return y * pitch + x * cpp;
> }
> @@ -2211,18 +2211,18 @@ u32 intel_fb_xy_to_linear(int x, int y,
> */
> void intel_add_fb_offsets(int *x, int *y,
> const struct intel_plane_state *state,
> - int plane)
> + int color_plane)
>
> {
> const struct intel_framebuffer *intel_fb = to_intel_framebuffer(state->base.fb);
> unsigned int rotation = state->base.rotation;
>
> if (drm_rotation_90_or_270(rotation)) {
> - *x += intel_fb->rotated[plane].x;
> - *y += intel_fb->rotated[plane].y;
> + *x += intel_fb->rotated[color_plane].x;
> + *y += intel_fb->rotated[color_plane].y;
> } else {
> - *x += intel_fb->normal[plane].x;
> - *y += intel_fb->normal[plane].y;
> + *x += intel_fb->normal[color_plane].x;
> + *y += intel_fb->normal[color_plane].y;
> }
> }
>
> @@ -2254,13 +2254,14 @@ static u32 intel_adjust_tile_offset(int *x, int *y,
> }
>
> static u32 intel_adjust_aligned_offset(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> + const struct drm_framebuffer *fb,
> + int color_plane,
> unsigned int rotation,
> unsigned int pitch,
> u32 old_offset, u32 new_offset)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
> - unsigned int cpp = fb->format->cpp[plane];
> + unsigned int cpp = fb->format->cpp[color_plane];
>
> WARN_ON(new_offset > old_offset);
>
> @@ -2269,7 +2270,7 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
> unsigned int pitch_tiles;
>
> tile_size = intel_tile_size(dev_priv);
> - intel_tile_dims(fb, plane, &tile_width, &tile_height);
> + intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
>
> if (drm_rotation_90_or_270(rotation)) {
> pitch_tiles = pitch / tile_height;
> @@ -2297,12 +2298,12 @@ static u32 intel_adjust_aligned_offset(int *x, int *y,
> */
> static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
> const struct intel_plane_state *state,
> - int plane,
> + int color_plane,
> u32 old_offset, u32 new_offset)
> {
> - return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
> + return intel_adjust_aligned_offset(x, y, state->base.fb, color_plane,
> state->base.rotation,
> - state->color_plane[plane].stride,
> + state->color_plane[color_plane].stride,
> old_offset, new_offset);
> }
>
> @@ -2322,13 +2323,14 @@ static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
> */
> static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> int *x, int *y,
> - const struct drm_framebuffer *fb, int plane,
> + const struct drm_framebuffer *fb,
> + int color_plane,
> unsigned int pitch,
> unsigned int rotation,
> u32 alignment)
> {
> uint64_t fb_modifier = fb->modifier;
> - unsigned int cpp = fb->format->cpp[plane];
> + unsigned int cpp = fb->format->cpp[color_plane];
> u32 offset, offset_aligned;
>
> if (alignment)
> @@ -2339,7 +2341,7 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> unsigned int tile_rows, tiles, pitch_tiles;
>
> tile_size = intel_tile_size(dev_priv);
> - intel_tile_dims(fb, plane, &tile_width, &tile_height);
> + intel_tile_dims(fb, color_plane, &tile_width, &tile_height);
>
> if (drm_rotation_90_or_270(rotation)) {
> pitch_tiles = pitch / tile_height;
> @@ -2373,41 +2375,42 @@ static u32 intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
>
> static u32 intel_plane_compute_aligned_offset(int *x, int *y,
> const struct intel_plane_state *state,
> - int plane)
> + int color_plane)
> {
> struct intel_plane *intel_plane = to_intel_plane(state->base.plane);
> struct drm_i915_private *dev_priv = to_i915(intel_plane->base.dev);
> const struct drm_framebuffer *fb = state->base.fb;
> unsigned int rotation = state->base.rotation;
> - int pitch = state->color_plane[plane].stride;
> + int pitch = state->color_plane[color_plane].stride;
> u32 alignment;
>
> if (intel_plane->id == PLANE_CURSOR)
> alignment = intel_cursor_alignment(dev_priv);
> else
> - alignment = intel_surf_alignment(fb, plane);
> + alignment = intel_surf_alignment(fb, color_plane);
>
> - return intel_compute_aligned_offset(dev_priv, x, y, fb, plane,
> + return intel_compute_aligned_offset(dev_priv, x, y, fb, color_plane,
> pitch, rotation, alignment);
> }
>
> /* Convert the fb->offset[] into x/y offsets */
> static int intel_fb_offset_to_xy(int *x, int *y,
> - const struct drm_framebuffer *fb, int plane)
> + const struct drm_framebuffer *fb,
> + int color_plane)
> {
> struct drm_i915_private *dev_priv = to_i915(fb->dev);
>
> if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
> - fb->offsets[plane] % intel_tile_size(dev_priv))
> + fb->offsets[color_plane] % intel_tile_size(dev_priv))
> return -EINVAL;
>
> *x = 0;
> *y = 0;
>
> intel_adjust_aligned_offset(x, y,
> - fb, plane, DRM_MODE_ROTATE_0,
> - fb->pitches[0],
> - fb->offsets[plane], 0);
> + fb, color_plane, DRM_MODE_ROTATE_0,
> + fb->pitches[color_plane],
> + fb->offsets[color_plane], 0);
>
> return 0;
> }
> @@ -2899,10 +2902,11 @@ intel_find_initial_plane_obj(struct intel_crtc *intel_crtc,
> &obj->frontbuffer_bits);
> }
>
> -static int skl_max_plane_width(const struct drm_framebuffer *fb, int plane,
> +static int skl_max_plane_width(const struct drm_framebuffer *fb,
> + int color_plane,
> unsigned int rotation)
> {
> - int cpp = fb->format->cpp[plane];
> + int cpp = fb->format->cpp[color_plane];
>
> switch (fb->modifier) {
> case DRM_FORMAT_MOD_LINEAR:
> @@ -3462,12 +3466,12 @@ static bool i9xx_plane_get_hw_state(struct intel_plane *plane,
> }
>
> static u32
> -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int plane)
> +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int color_plane)
> {
> if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> return 64;
> else
> - return intel_tile_width_bytes(fb, plane);
> + return intel_tile_width_bytes(fb, color_plane);
> }
>
> static void skl_detach_scaler(struct intel_crtc *intel_crtc, int id)
> @@ -3498,13 +3502,13 @@ static void skl_detach_scalers(struct intel_crtc *intel_crtc)
> }
>
> u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> - int plane)
> + int color_plane)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> - u32 stride = plane_state->color_plane[plane].stride;
> + u32 stride = plane_state->color_plane[color_plane].stride;
>
> - if (plane >= fb->format->num_planes)
> + if (color_plane >= fb->format->num_planes)
> return 0;
>
> /*
> @@ -3512,9 +3516,9 @@ u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> * linear buffers or in number of tiles for tiled buffers.
> */
> if (drm_rotation_90_or_270(rotation))
> - stride /= intel_tile_height(fb, plane);
> + stride /= intel_tile_height(fb, color_plane);
> else
> - stride /= intel_fb_stride_alignment(fb, plane);
> + stride /= intel_fb_stride_alignment(fb, color_plane);
>
> return stride;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index d70276ff3d0e..cc381f680338 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1438,7 +1438,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc *crtc,
> struct drm_atomic_state *old_state);
>
> unsigned int intel_fb_align_height(const struct drm_framebuffer *fb,
> - int plane, unsigned int height);
> + int color_plane, unsigned int height);
>
> /* intel_audio.c */
> void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
> --
> 2.16.4
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 03/18] drm/i915: Add .max_stride() plane hook
2018-08-22 22:19 ` Souza, Jose
@ 2018-08-23 14:48 ` Ville Syrjälä
0 siblings, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-08-23 14:48 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Aug 22, 2018 at 10:19:55PM +0000, Souza, Jose wrote:
> On Wed, 2018-08-22 at 22:03 +0000, Souza, Jose wrote:
> > On Thu, 2018-07-19 at 21:21 +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > >
> > > Each plane may have different stride limitations. Let's add a new
> > > plane function to retutn the maximum stride for each plane. There's
> > > going to be some use for this outside the .atomic_check() stuff
> > > hence
> > > the separate hook.
> >
> > I just not checked the the spec for the VLV and CHV other than that
> > LGTM but just take a look to the nitpick bellow:
> >
> > Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> >
> > >
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > > drivers/gpu/drm/i915/intel_display.c | 46
> > > ++++++++++++++++++++++++++++++++++++
> > > drivers/gpu/drm/i915/intel_drv.h | 10 ++++++++
> > > drivers/gpu/drm/i915/intel_sprite.c | 34
> > > ++++++++++++++++++++++++--
> > > 3 files changed, 88 insertions(+), 2 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > > b/drivers/gpu/drm/i915/intel_display.c
> > > index 5f8304a11482..a09e11e0596f 100644
> > > --- a/drivers/gpu/drm/i915/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/intel_display.c
> > > @@ -3210,6 +3210,31 @@ int skl_check_plane_surface(const struct
> > > intel_crtc_state *crtc_state,
> > > return 0;
> > > }
> > >
> > > +unsigned int
> > > +i9xx_plane_max_stride(struct intel_plane *plane,
> > > + u32 pixel_format, u64 modifier,
> > > + unsigned int rotation)
> > > +{
> > > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > > +
>
> Reviwing 'drm/i915: Use pipe A primary plane .max_stride() as the
> global stride limit' I notice that this case was not moved here:
>
> } else if (gen >= 5 && !HAS_GMCH_DISPLAY(dev_priv)) {
> return 32*1024;
> }
>
> Not relevant anymore?
No, that should not have been dropped. Good catch. I'll respin.
>
>
> > > + if (INTEL_GEN(dev_priv) >= 4) {
> > > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > > + return 16*1024;
> > > + else
> > > + return 32*1024;
> > > + } else if (INTEL_GEN(dev_priv) >= 3) {
> > > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > > + return 8*1024;
> > > + else
> > > + return 16*1024;
> > > + } else {
> > > + if (plane->i9xx_plane == PLANE_C)
> > > + return 4*1024;
> > > + else
> > > + return 8*1024;
> > > + }
> > > +}
> > > +
--
Ville Syrjälä
Intel
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 03/18] drm/i915: Add .max_stride() plane hook
2018-08-22 22:03 ` Souza, Jose
2018-08-22 22:19 ` Souza, Jose
@ 2018-08-23 14:52 ` Ville Syrjälä
1 sibling, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-08-23 14:52 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Wed, Aug 22, 2018 at 10:03:17PM +0000, Souza, Jose wrote:
> On Thu, 2018-07-19 at 21:21 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Each plane may have different stride limitations. Let's add a new
> > plane function to retutn the maximum stride for each plane. There's
> > going to be some use for this outside the .atomic_check() stuff hence
> > the separate hook.
>
> I just not checked the the spec for the VLV and CHV other than that
> LGTM but just take a look to the nitpick bellow:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 46
> > ++++++++++++++++++++++++++++++++++++
> > drivers/gpu/drm/i915/intel_drv.h | 10 ++++++++
> > drivers/gpu/drm/i915/intel_sprite.c | 34 ++++++++++++++++++++++++--
> > 3 files changed, 88 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 5f8304a11482..a09e11e0596f 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3210,6 +3210,31 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > return 0;
> > }
> >
> > +unsigned int
> > +i9xx_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > +
> > + if (INTEL_GEN(dev_priv) >= 4) {
> > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > + return 16*1024;
> > + else
> > + return 32*1024;
> > + } else if (INTEL_GEN(dev_priv) >= 3) {
> > + if (modifier == I915_FORMAT_MOD_X_TILED)
> > + return 8*1024;
> > + else
> > + return 16*1024;
> > + } else {
> > + if (plane->i9xx_plane == PLANE_C)
> > + return 4*1024;
> > + else
> > + return 8*1024;
> > + }
> > +}
> > +
> > static u32 i9xx_plane_ctl(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -9672,6 +9697,14 @@ static int intel_check_cursor(struct
> > intel_crtc_state *crtc_state,
> > return 0;
> > }
> >
> > +static unsigned int
> > +i845_cursor_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return 2048;
> > +}
> > +
> > static u32 i845_cursor_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -9805,6 +9838,14 @@ static bool i845_cursor_get_hw_state(struct
> > intel_plane *plane,
> > return ret;
> > }
> >
> > +static unsigned int
> > +i9xx_cursor_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return plane->base.dev->mode_config.cursor_width * 4;
> > +}
> > +
> > static u32 i9xx_cursor_ctl(const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -13699,6 +13740,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > else
> > modifiers = skl_format_modifiers_noccs;
> >
> > + primary->max_stride = skl_plane_max_stride;
> > primary->update_plane = skl_update_plane;
> > primary->disable_plane = skl_disable_plane;
> > primary->get_hw_state = skl_plane_get_hw_state;
> > @@ -13709,6 +13751,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > num_formats = ARRAY_SIZE(i965_primary_formats);
> > modifiers = i9xx_format_modifiers;
> >
> > + primary->max_stride = i9xx_plane_max_stride;
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > @@ -13719,6 +13762,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > num_formats = ARRAY_SIZE(i8xx_primary_formats);
> > modifiers = i9xx_format_modifiers;
> >
> > + primary->max_stride = i9xx_plane_max_stride;
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > @@ -13826,11 +13870,13 @@ intel_cursor_plane_create(struct
> > drm_i915_private *dev_priv,
> > cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
> >
> > if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
> > + cursor->max_stride = i845_cursor_max_stride;
> > cursor->update_plane = i845_update_cursor;
> > cursor->disable_plane = i845_disable_cursor;
> > cursor->get_hw_state = i845_cursor_get_hw_state;
> > cursor->check_plane = i845_check_cursor;
> > } else {
> > + cursor->max_stride = i9xx_cursor_max_stride;
> > cursor->update_plane = i9xx_update_cursor;
> > cursor->disable_plane = i9xx_disable_cursor;
> > cursor->get_hw_state = i9xx_cursor_get_hw_state;
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index b9f6de3a8f53..ad2bd62ee553 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -963,6 +963,9 @@ struct intel_plane {
> > * the intel_plane_state structure and accessed via
> > plane_state.
> > */
> >
> > + unsigned int (*max_stride)(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> > void (*update_plane)(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state
> > *plane_state);
> > @@ -1652,6 +1655,9 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state);
> > int i9xx_check_plane_surface(struct intel_plane_state *plane_state);
> > int skl_format_to_fourcc(int format, bool rgb_order, bool alpha);
> > +unsigned int i9xx_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> >
> > /* intel_csr.c */
> > void intel_csr_ucode_init(struct drm_i915_private *);
> > @@ -2102,6 +2108,10 @@ bool skl_plane_has_ccs(struct drm_i915_private
> > *dev_priv,
> > enum pipe pipe, enum plane_id plane_id);
> > bool skl_plane_has_planar(struct drm_i915_private *dev_priv,
> > enum pipe pipe, enum plane_id plane_id);
> > +unsigned int skl_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation);
> > +
> >
> > /* intel_tv.c */
> > void intel_tv_init(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index f7026e887fa9..e35760814f25 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -228,6 +228,23 @@ void intel_pipe_update_end(struct
> > intel_crtc_state *new_crtc_state)
> > #endif
> > }
> >
> > +unsigned int
> > +skl_plane_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + int cpp = drm_format_plane_cpp(pixel_format, 0);
> > +
> > + /*
> > + * "The stride in bytes must not exceed the
> > + * of the size of 8K pixels and 32K bytes."
> > + */
> > + if (drm_rotation_90_or_270(rotation))
> > + return min(8192, 32768 / cpp);
> > + else
> > + return min(8192 * cpp, 32768);
> > +}
> > +
> > void
> > skl_update_plane(struct intel_plane *plane,
> > const struct intel_crtc_state *crtc_state,
> > @@ -798,6 +815,14 @@ ivb_plane_get_hw_state(struct intel_plane
> > *plane,
> > return ret;
> > }
> >
> > +static unsigned int
> > +g4x_sprite_max_stride(struct intel_plane *plane,
> > + u32 pixel_format, u64 modifier,
> > + unsigned int rotation)
> > +{
> > + return 16384;
> > +}
> > +
> > static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
> > const struct intel_plane_state *plane_state)
> > {
> > @@ -964,7 +989,6 @@ intel_check_sprite_plane(struct intel_plane
> > *plane,
> > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > struct drm_framebuffer *fb = state->base.fb;
> > - int max_stride = INTEL_GEN(dev_priv) >= 9 ? 32768 : 16384;
>
> Why not keep max_stride and call plane->max_stride() here or in a line
> bellow, this would make less changes a easier 'if' to read and fix the
> line over 80 characters warning.
I guess we could do that. Although this code is going away later
anyway so doesn't matter too much.
>
> > int max_scale, min_scale;
> > bool can_scale;
> > int ret;
> > @@ -982,7 +1006,9 @@ intel_check_sprite_plane(struct intel_plane
> > *plane,
> > }
> >
> > /* FIXME check all gen limits */
> > - if (fb->width < 3 || fb->height < 3 || fb->pitches[0] >
> > max_stride) {
> > + if (fb->width < 3 || fb->height < 3 ||
> > + fb->pitches[0] > plane->max_stride(plane, fb->format-
> > >format,
> > + fb->modifier,
> > DRM_MODE_ROTATE_0)) {
> > DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
> > return -EINVAL;
> > }
> > @@ -1528,6 +1554,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->has_ccs = skl_plane_has_ccs(dev_priv,
> > pipe,
> > PLANE_SPRITE0
> > + plane);
> >
> > + intel_plane->max_stride = skl_plane_max_stride;
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > intel_plane->get_hw_state = skl_plane_get_hw_state;
> > @@ -1551,6 +1578,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->can_scale = false;
> > intel_plane->max_downscale = 1;
> >
> > + intel_plane->max_stride = i9xx_plane_max_stride;
> > intel_plane->update_plane = vlv_update_plane;
> > intel_plane->disable_plane = vlv_disable_plane;
> > intel_plane->get_hw_state = vlv_plane_get_hw_state;
> > @@ -1569,6 +1597,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->max_downscale = 1;
> > }
> >
> > + intel_plane->max_stride = g4x_sprite_max_stride;
> > intel_plane->update_plane = ivb_update_plane;
> > intel_plane->disable_plane = ivb_disable_plane;
> > intel_plane->get_hw_state = ivb_plane_get_hw_state;
> > @@ -1582,6 +1611,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->can_scale = true;
> > intel_plane->max_downscale = 16;
> >
> > + intel_plane->max_stride = g4x_sprite_max_stride;
> > intel_plane->update_plane = g4x_update_plane;
> > intel_plane->disable_plane = g4x_disable_plane;
> > intel_plane->get_hw_state = g4x_plane_get_hw_state;
--
Ville Syrjälä
Intel
_______________________________________________
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 08/18] drm/i915: s/int plane/int color_plane/
2018-08-23 1:14 ` Rodrigo Vivi
@ 2018-08-24 0:05 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 0:05 UTC (permalink / raw)
To: ville.syrjala, Vivi, Rodrigo; +Cc: intel-gfx
On Wed, 2018-08-22 at 18:14 -0700, Rodrigo Vivi wrote:
> On Thu, Jul 19, 2018 at 09:22:04PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > To reduce the confusion between a drm plane and the planes of
> > framebuffers let's desiginate the latter as "color plane".
>
>
> what about fb_plane instead of color?
I liked color_plane more than fb_plane.
Not taking in care the choosed name, the rename looks good to me but it
would be nice someone else also review it.
Weak-Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
>
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_display.c | 106 ++++++++++++++++++-----
> > ------------
> > drivers/gpu/drm/i915/intel_drv.h | 2 +-
> > 2 files changed, 56 insertions(+), 52 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index e6cb8238f257..bc2a712311ba 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -1916,10 +1916,10 @@ static unsigned int intel_tile_size(const
> > struct drm_i915_private *dev_priv)
> > }
> >
> > static unsigned int
> > -intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> > plane)
> > +intel_tile_width_bytes(const struct drm_framebuffer *fb, int
> > color_plane)
> > {
> > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > - unsigned int cpp = fb->format->cpp[plane];
> > + unsigned int cpp = fb->format->cpp[color_plane];
> >
> > switch (fb->modifier) {
> > case DRM_FORMAT_MOD_LINEAR:
> > @@ -1930,7 +1930,7 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Y_TILED_CCS:
> > - if (plane == 1)
> > + if (color_plane == 1)
> > return 128;
> > /* fall through */
> > case I915_FORMAT_MOD_Y_TILED:
> > @@ -1939,7 +1939,7 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int plane)
> > else
> > return 512;
> > case I915_FORMAT_MOD_Yf_TILED_CCS:
> > - if (plane == 1)
> > + if (color_plane == 1)
> > return 128;
> > /* fall through */
> > case I915_FORMAT_MOD_Yf_TILED:
> > @@ -1964,22 +1964,22 @@ intel_tile_width_bytes(const struct
> > drm_framebuffer *fb, int plane)
> > }
> >
> > static unsigned int
> > -intel_tile_height(const struct drm_framebuffer *fb, int plane)
> > +intel_tile_height(const struct drm_framebuffer *fb, int
> > color_plane)
> > {
> > if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > return 1;
> > else
> > return intel_tile_size(to_i915(fb->dev)) /
> > - intel_tile_width_bytes(fb, plane);
> > + intel_tile_width_bytes(fb, color_plane);
> > }
> >
> > /* Return the tile dimensions in pixel units */
> > -static void intel_tile_dims(const struct drm_framebuffer *fb, int
> > plane,
> > +static void intel_tile_dims(const struct drm_framebuffer *fb, int
> > color_plane,
> > unsigned int *tile_width,
> > unsigned int *tile_height)
> > {
> > - unsigned int tile_width_bytes = intel_tile_width_bytes(fb,
> > plane);
> > - unsigned int cpp = fb->format->cpp[plane];
> > + unsigned int tile_width_bytes = intel_tile_width_bytes(fb,
> > color_plane);
> > + unsigned int cpp = fb->format->cpp[color_plane];
> >
> > *tile_width = tile_width_bytes / cpp;
> > *tile_height = intel_tile_size(to_i915(fb->dev)) /
> > tile_width_bytes;
> > @@ -1987,9 +1987,9 @@ static void intel_tile_dims(const struct
> > drm_framebuffer *fb, int plane,
> >
> > unsigned int
> > intel_fb_align_height(const struct drm_framebuffer *fb,
> > - int plane, unsigned int height)
> > + int color_plane, unsigned int height)
> > {
> > - unsigned int tile_height = intel_tile_height(fb, plane);
> > + unsigned int tile_height = intel_tile_height(fb, color_plane);
> >
> > return ALIGN(height, tile_height);
> > }
> > @@ -2043,12 +2043,12 @@ static unsigned int
> > intel_linear_alignment(const struct drm_i915_private *dev_pr
> > }
> >
> > static unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> > - int plane)
> > + int color_plane)
> > {
> > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >
> > /* AUX_DIST needs only 4K alignment */
> > - if (plane == 1)
> > + if (color_plane == 1)
> > return 4096;
> >
> > switch (fb->modifier) {
> > @@ -2178,13 +2178,13 @@ void intel_unpin_fb_vma(struct i915_vma
> > *vma, unsigned long flags)
> > i915_vma_put(vma);
> > }
> >
> > -static int intel_fb_pitch(const struct drm_framebuffer *fb, int
> > plane,
> > +static int intel_fb_pitch(const struct drm_framebuffer *fb, int
> > color_plane,
> > unsigned int rotation)
> > {
> > if (drm_rotation_90_or_270(rotation))
> > - return to_intel_framebuffer(fb)->rotated[plane].pitch;
> > + return to_intel_framebuffer(fb)-
> > >rotated[color_plane].pitch;
> > else
> > - return fb->pitches[plane];
> > + return fb->pitches[color_plane];
> > }
> >
> > /*
> > @@ -2195,11 +2195,11 @@ static int intel_fb_pitch(const struct
> > drm_framebuffer *fb, int plane,
> > */
> > u32 intel_fb_xy_to_linear(int x, int y,
> > const struct intel_plane_state *state,
> > - int plane)
> > + int color_plane)
> > {
> > const struct drm_framebuffer *fb = state->base.fb;
> > - unsigned int cpp = fb->format->cpp[plane];
> > - unsigned int pitch = state->color_plane[plane].stride;
> > + unsigned int cpp = fb->format->cpp[color_plane];
> > + unsigned int pitch = state->color_plane[color_plane].stride;
> >
> > return y * pitch + x * cpp;
> > }
> > @@ -2211,18 +2211,18 @@ u32 intel_fb_xy_to_linear(int x, int y,
> > */
> > void intel_add_fb_offsets(int *x, int *y,
> > const struct intel_plane_state *state,
> > - int plane)
> > + int color_plane)
> >
> > {
> > const struct intel_framebuffer *intel_fb =
> > to_intel_framebuffer(state->base.fb);
> > unsigned int rotation = state->base.rotation;
> >
> > if (drm_rotation_90_or_270(rotation)) {
> > - *x += intel_fb->rotated[plane].x;
> > - *y += intel_fb->rotated[plane].y;
> > + *x += intel_fb->rotated[color_plane].x;
> > + *y += intel_fb->rotated[color_plane].y;
> > } else {
> > - *x += intel_fb->normal[plane].x;
> > - *y += intel_fb->normal[plane].y;
> > + *x += intel_fb->normal[color_plane].x;
> > + *y += intel_fb->normal[color_plane].y;
> > }
> > }
> >
> > @@ -2254,13 +2254,14 @@ static u32 intel_adjust_tile_offset(int *x,
> > int *y,
> > }
> >
> > static u32 intel_adjust_aligned_offset(int *x, int *y,
> > - const struct drm_framebuffer
> > *fb, int plane,
> > + const struct drm_framebuffer
> > *fb,
> > + int color_plane,
> > unsigned int rotation,
> > unsigned int pitch,
> > u32 old_offset, u32 new_offset)
> > {
> > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> > - unsigned int cpp = fb->format->cpp[plane];
> > + unsigned int cpp = fb->format->cpp[color_plane];
> >
> > WARN_ON(new_offset > old_offset);
> >
> > @@ -2269,7 +2270,7 @@ static u32 intel_adjust_aligned_offset(int
> > *x, int *y,
> > unsigned int pitch_tiles;
> >
> > tile_size = intel_tile_size(dev_priv);
> > - intel_tile_dims(fb, plane, &tile_width, &tile_height);
> > + intel_tile_dims(fb, color_plane, &tile_width,
> > &tile_height);
> >
> > if (drm_rotation_90_or_270(rotation)) {
> > pitch_tiles = pitch / tile_height;
> > @@ -2297,12 +2298,12 @@ static u32 intel_adjust_aligned_offset(int
> > *x, int *y,
> > */
> > static u32 intel_plane_adjust_aligned_offset(int *x, int *y,
> > const struct
> > intel_plane_state *state,
> > - int plane,
> > + int color_plane,
> > u32 old_offset, u32
> > new_offset)
> > {
> > - return intel_adjust_aligned_offset(x, y, state->base.fb, plane,
> > + return intel_adjust_aligned_offset(x, y, state->base.fb,
> > color_plane,
> > state->base.rotation,
> > - state-
> > >color_plane[plane].stride,
> > + state-
> > >color_plane[color_plane].stride,
> > old_offset, new_offset);
> > }
> >
> > @@ -2322,13 +2323,14 @@ static u32
> > intel_plane_adjust_aligned_offset(int *x, int *y,
> > */
> > static u32 intel_compute_aligned_offset(struct drm_i915_private
> > *dev_priv,
> > int *x, int *y,
> > - const struct drm_framebuffer
> > *fb, int plane,
> > + const struct drm_framebuffer
> > *fb,
> > + int color_plane,
> > unsigned int pitch,
> > unsigned int rotation,
> > u32 alignment)
> > {
> > uint64_t fb_modifier = fb->modifier;
> > - unsigned int cpp = fb->format->cpp[plane];
> > + unsigned int cpp = fb->format->cpp[color_plane];
> > u32 offset, offset_aligned;
> >
> > if (alignment)
> > @@ -2339,7 +2341,7 @@ static u32
> > intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> > unsigned int tile_rows, tiles, pitch_tiles;
> >
> > tile_size = intel_tile_size(dev_priv);
> > - intel_tile_dims(fb, plane, &tile_width, &tile_height);
> > + intel_tile_dims(fb, color_plane, &tile_width,
> > &tile_height);
> >
> > if (drm_rotation_90_or_270(rotation)) {
> > pitch_tiles = pitch / tile_height;
> > @@ -2373,41 +2375,42 @@ static u32
> > intel_compute_aligned_offset(struct drm_i915_private *dev_priv,
> >
> > static u32 intel_plane_compute_aligned_offset(int *x, int *y,
> > const struct
> > intel_plane_state *state,
> > - int plane)
> > + int color_plane)
> > {
> > struct intel_plane *intel_plane = to_intel_plane(state-
> > >base.plane);
> > struct drm_i915_private *dev_priv = to_i915(intel_plane-
> > >base.dev);
> > const struct drm_framebuffer *fb = state->base.fb;
> > unsigned int rotation = state->base.rotation;
> > - int pitch = state->color_plane[plane].stride;
> > + int pitch = state->color_plane[color_plane].stride;
> > u32 alignment;
> >
> > if (intel_plane->id == PLANE_CURSOR)
> > alignment = intel_cursor_alignment(dev_priv);
> > else
> > - alignment = intel_surf_alignment(fb, plane);
> > + alignment = intel_surf_alignment(fb, color_plane);
> >
> > - return intel_compute_aligned_offset(dev_priv, x, y, fb, plane,
> > + return intel_compute_aligned_offset(dev_priv, x, y, fb,
> > color_plane,
> > pitch, rotation,
> > alignment);
> > }
> >
> > /* Convert the fb->offset[] into x/y offsets */
> > static int intel_fb_offset_to_xy(int *x, int *y,
> > - const struct drm_framebuffer *fb, int
> > plane)
> > + const struct drm_framebuffer *fb,
> > + int color_plane)
> > {
> > struct drm_i915_private *dev_priv = to_i915(fb->dev);
> >
> > if (fb->modifier != DRM_FORMAT_MOD_LINEAR &&
> > - fb->offsets[plane] % intel_tile_size(dev_priv))
> > + fb->offsets[color_plane] % intel_tile_size(dev_priv))
> > return -EINVAL;
> >
> > *x = 0;
> > *y = 0;
> >
> > intel_adjust_aligned_offset(x, y,
> > - fb, plane, DRM_MODE_ROTATE_0,
> > - fb->pitches[0],
> > - fb->offsets[plane], 0);
> > + fb, color_plane, DRM_MODE_ROTATE_0,
> > + fb->pitches[color_plane],
> > + fb->offsets[color_plane], 0);
> >
> > return 0;
> > }
> > @@ -2899,10 +2902,11 @@ intel_find_initial_plane_obj(struct
> > intel_crtc *intel_crtc,
> > &obj->frontbuffer_bits);
> > }
> >
> > -static int skl_max_plane_width(const struct drm_framebuffer *fb,
> > int plane,
> > +static int skl_max_plane_width(const struct drm_framebuffer *fb,
> > + int color_plane,
> > unsigned int rotation)
> > {
> > - int cpp = fb->format->cpp[plane];
> > + int cpp = fb->format->cpp[color_plane];
> >
> > switch (fb->modifier) {
> > case DRM_FORMAT_MOD_LINEAR:
> > @@ -3462,12 +3466,12 @@ static bool i9xx_plane_get_hw_state(struct
> > intel_plane *plane,
> > }
> >
> > static u32
> > -intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > plane)
> > +intel_fb_stride_alignment(const struct drm_framebuffer *fb, int
> > color_plane)
> > {
> > if (fb->modifier == DRM_FORMAT_MOD_LINEAR)
> > return 64;
> > else
> > - return intel_tile_width_bytes(fb, plane);
> > + return intel_tile_width_bytes(fb, color_plane);
> > }
> >
> > static void skl_detach_scaler(struct intel_crtc *intel_crtc, int
> > id)
> > @@ -3498,13 +3502,13 @@ static void skl_detach_scalers(struct
> > intel_crtc *intel_crtc)
> > }
> >
> > u32 skl_plane_stride(const struct intel_plane_state *plane_state,
> > - int plane)
> > + int color_plane)
> > {
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > unsigned int rotation = plane_state->base.rotation;
> > - u32 stride = plane_state->color_plane[plane].stride;
> > + u32 stride = plane_state->color_plane[color_plane].stride;
> >
> > - if (plane >= fb->format->num_planes)
> > + if (color_plane >= fb->format->num_planes)
> > return 0;
> >
> > /*
> > @@ -3512,9 +3516,9 @@ u32 skl_plane_stride(const struct
> > intel_plane_state *plane_state,
> > * linear buffers or in number of tiles for tiled buffers.
> > */
> > if (drm_rotation_90_or_270(rotation))
> > - stride /= intel_tile_height(fb, plane);
> > + stride /= intel_tile_height(fb, color_plane);
> > else
> > - stride /= intel_fb_stride_alignment(fb, plane);
> > + stride /= intel_fb_stride_alignment(fb, color_plane);
> >
> > return stride;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index d70276ff3d0e..cc381f680338 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -1438,7 +1438,7 @@ void icl_unmap_plls_to_ports(struct drm_crtc
> > *crtc,
> > struct drm_atomic_state *old_state);
> >
> > unsigned int intel_fb_align_height(const struct drm_framebuffer
> > *fb,
> > - int plane, unsigned int height);
> > + int color_plane, unsigned int
> > height);
> >
> > /* intel_audio.c */
> > void intel_init_audio_hooks(struct drm_i915_private *dev_priv);
> > --
> > 2.16.4
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale
2018-07-19 18:22 ` [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale Ville Syrjala
@ 2018-08-24 0:32 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 0:32 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> We can easily calculate the plane can_scale/min_downscale on demand.
> And later on we'll probably want to start calculating these
> dynamically
> based on the cdclk just as skl already does.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 8 +-------
> drivers/gpu/drm/i915/intel_drv.h | 2 --
> drivers/gpu/drm/i915/intel_sprite.c | 38 ++++++++++++------------
> ------------
> 3 files changed, 13 insertions(+), 35 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index bc2a712311ba..fdc5bedc5135 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -13708,12 +13708,8 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
>
> primary->base.state = &state->base;
>
> - primary->can_scale = false;
> - primary->max_downscale = 1;
> - if (INTEL_GEN(dev_priv) >= 9) {
> - primary->can_scale = true;
> + if (INTEL_GEN(dev_priv) >= 9)
> state->scaler_id = -1;
> - }
> primary->pipe = pipe;
> /*
> * On gen2/3 only plane A can do FBC, but the panel fitter and
> LVDS
> @@ -13881,8 +13877,6 @@ intel_cursor_plane_create(struct
> drm_i915_private *dev_priv,
>
> cursor->base.state = &state->base;
>
> - cursor->can_scale = false;
> - cursor->max_downscale = 1;
> cursor->pipe = pipe;
> cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
> cursor->id = PLANE_CURSOR;
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index cc381f680338..c6c782e14897 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -950,10 +950,8 @@ struct intel_plane {
> enum i9xx_plane_id i9xx_plane;
> enum plane_id id;
> enum pipe pipe;
> - bool can_scale;
> bool has_fbc;
> bool has_ccs;
> - int max_downscale;
> uint32_t frontbuffer_bit;
>
> struct {
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index a07d951afbf9..0d3931b8a981 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -765,7 +765,7 @@ ivb_update_plane(struct intel_plane *plane,
> I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
>
> I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
> - if (plane->can_scale)
> + if (IS_IVYBRIDGE(dev_priv))
> I915_WRITE_FW(SPRSCALE(pipe), sprscale);
> I915_WRITE_FW(SPRCTL(pipe), sprctl);
> I915_WRITE_FW(SPRSURF(pipe),
> @@ -786,7 +786,7 @@ ivb_disable_plane(struct intel_plane *plane,
> struct intel_crtc *crtc)
>
> I915_WRITE_FW(SPRCTL(pipe), 0);
> /* Can't leave the scaler enabled... */
> - if (plane->can_scale)
> + if (IS_IVYBRIDGE(dev_priv))
> I915_WRITE_FW(SPRSCALE(pipe), 0);
>
> I915_WRITE_FW(SPRSURF(pipe), 0);
> @@ -991,7 +991,6 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> struct drm_framebuffer *fb = state->base.fb;
> int max_scale, min_scale;
> - bool can_scale;
> int ret;
> uint32_t pixel_format = 0;
>
> @@ -1014,25 +1013,29 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> return -EINVAL;
> }
>
> - /* setup can_scale, min_scale, max_scale */
> if (INTEL_GEN(dev_priv) >= 9) {
> if (state->base.fb)
> pixel_format = state->base.fb->format->format;
> /* use scaler when colorkey is not required */
> if (!state->ckey.flags) {
> - can_scale = 1;
> min_scale = 1;
> max_scale =
> skl_max_scale(crtc, crtc_state,
> pixel_format);
> } else {
> - can_scale = 0;
> min_scale = DRM_PLANE_HELPER_NO_SCALING;
> max_scale = DRM_PLANE_HELPER_NO_SCALING;
> }
> } else {
> - can_scale = plane->can_scale;
> - max_scale = plane->max_downscale << 16;
> - min_scale = plane->can_scale ? 1 : (1 << 16);
> + if (INTEL_GEN(dev_priv) < 7) {
> + min_scale = 1;
> + max_scale = 16 << 16;
> + } else if (IS_IVYBRIDGE(dev_priv)) {
> + min_scale = 1;
> + max_scale = 2 << 16;
> + } else {
> + min_scale = DRM_PLANE_HELPER_NO_SCALING;
> + max_scale = DRM_PLANE_HELPER_NO_SCALING;
> + }
> }
>
> ret = drm_atomic_helper_check_plane_state(&state->base,
> @@ -1078,8 +1081,6 @@ intel_check_sprite_plane(struct intel_plane
> *plane,
> unsigned int width_bytes;
> int cpp = fb->format->cpp[0];
>
> - WARN_ON(!can_scale);
> -
> width_bytes = ((src_x * cpp) & 63) + src_w *
> cpp;
>
> /* FIXME interlacing min height is 6 */
> @@ -1549,7 +1550,6 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->base.state = &state->base;
>
> if (INTEL_GEN(dev_priv) >= 9) {
> - intel_plane->can_scale = true;
> state->scaler_id = -1;
>
> intel_plane->has_ccs = skl_plane_has_ccs(dev_priv,
> pipe,
> @@ -1576,9 +1576,6 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
>
> plane_funcs = &skl_plane_funcs;
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> {
> - intel_plane->can_scale = false;
> - intel_plane->max_downscale = 1;
> -
> intel_plane->max_stride = i9xx_plane_max_stride;
> intel_plane->update_plane = vlv_update_plane;
> intel_plane->disable_plane = vlv_disable_plane;
> @@ -1590,14 +1587,6 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
>
> plane_funcs = &vlv_sprite_funcs;
> } else if (INTEL_GEN(dev_priv) >= 7) {
> - if (IS_IVYBRIDGE(dev_priv)) {
> - intel_plane->can_scale = true;
> - intel_plane->max_downscale = 2;
> - } else {
> - intel_plane->can_scale = false;
> - intel_plane->max_downscale = 1;
> - }
> -
> intel_plane->max_stride = g4x_sprite_max_stride;
> intel_plane->update_plane = ivb_update_plane;
> intel_plane->disable_plane = ivb_disable_plane;
> @@ -1609,9 +1598,6 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
>
> plane_funcs = &snb_sprite_funcs;
> } else {
> - intel_plane->can_scale = true;
> - intel_plane->max_downscale = 16;
> -
> intel_plane->max_stride = g4x_sprite_max_stride;
> intel_plane->update_plane = g4x_update_plane;
> intel_plane->disable_plane = g4x_disable_plane;
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions
2018-07-19 18:22 ` [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions Ville Syrjala
@ 2018-08-24 1:01 ` Souza, Jose
2018-08-24 12:03 ` Ville Syrjälä
0 siblings, 1 reply; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 1:01 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Split up intel_check_primary_plane() and intel_check_sprite_plane()
> into per-platform variants. This way we can get a unified behaviour
> between the SKL universal planes, and we stop checking for non-SKL
> specific scaling limits for the "sprite" planes. And we now get
> a natural place where to add more plarform specific checks.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 123 +++++-------
> drivers/gpu/drm/i915/intel_drv.h | 13 +-
> drivers/gpu/drm/i915/intel_sprite.c | 303 +++++++++++++++++++-
> ----------
> 4 files changed, 249 insertions(+), 192 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index dcba645cabb8..eddcdd6e4b3b 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -159,7 +159,7 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
> }
>
> intel_state->base.visible = false;
> - ret = intel_plane->check_plane(intel_plane, crtc_state,
> intel_state);
> + ret = intel_plane->check_plane(crtc_state, intel_state);
> if (ret)
> return ret;
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index fdc5bedc5135..9b9eaeda15dd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3350,6 +3350,36 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
> return 0;
> }
>
> +static int
> +i9xx_plane_check(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> +{
> + int ret;
> +
> + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> + &crtc_state->base,
> + DRM_PLANE_HELPER_NO_S
> CALING,
> + DRM_PLANE_HELPER_NO_S
> CALING,
> + false, true);
> + if (ret)
> + return ret;
> +
> + if (!plane_state->base.visible)
> + return 0;
> +
> + ret = intel_plane_check_src_coordinates(plane_state);
> + if (ret)
> + return ret;
> +
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> + plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
> +
> + return 0;
> +}
> +
> static void i9xx_update_plane(struct intel_plane *plane,
> const struct intel_crtc_state
> *crtc_state,
> const struct intel_plane_state
> *plane_state)
> @@ -9680,6 +9710,11 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> u32 offset;
> int ret;
>
> + if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> + DRM_DEBUG_KMS("cursor cannot be tiled\n");
> + return -EINVAL;
> + }
> +
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> &crtc_state->base,
> DRM_PLANE_HELPER_NO_S
> CALING,
> @@ -9688,13 +9723,12 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - if (!fb)
> + if (!plane_state->base.visible)
> return 0;
>
> - if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> - DRM_DEBUG_KMS("cursor cannot be tiled\n");
> - return -EINVAL;
> - }
> + ret = intel_plane_check_src_coordinates(plane_state);
> + if (ret)
> + return ret;
>
> intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> @@ -9744,8 +9778,7 @@ static bool i845_cursor_size_ok(const struct
> intel_plane_state *plane_state)
> return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width,
> 64);
> }
>
> -static int i845_check_cursor(struct intel_plane *plane,
> - struct intel_crtc_state *crtc_state,
> +static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
You are dropping struct intel_plane *plane from check_plane and in
skl_max_scale(), I think it is a good thing to do but would be better
do it in a previous patch and leave this one just extracting
check_plane().
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> @@ -9943,10 +9976,10 @@ static bool i9xx_cursor_size_ok(const struct
> intel_plane_state *plane_state)
> return true;
> }
>
> -static int i9xx_check_cursor(struct intel_plane *plane,
> - struct intel_crtc_state *crtc_state,
> +static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> + struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> const struct drm_framebuffer *fb = plane_state->base.fb;
> enum pipe pipe = plane->pipe;
> @@ -13193,19 +13226,17 @@ intel_cleanup_plane_fb(struct drm_plane
> *plane,
> }
>
> int
> -skl_max_scale(struct intel_crtc *intel_crtc,
> - struct intel_crtc_state *crtc_state,
> - uint32_t pixel_format)
> +skl_max_scale(const struct intel_crtc_state *crtc_state,
> + u32 pixel_format)
> {
> - struct drm_i915_private *dev_priv;
> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> int max_scale, mult;
> int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
>
> - if (!intel_crtc || !crtc_state->base.enable)
> + if (!crtc_state->base.enable)
> return DRM_PLANE_HELPER_NO_SCALING;
>
> - dev_priv = to_i915(intel_crtc->base.dev);
> -
> crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> >cdclk.logical.cdclk;
>
> @@ -13229,61 +13260,6 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> return max_scale;
> }
>
> -static int
> -intel_check_primary_plane(struct intel_plane *plane,
> - struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *state)
> -{
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - struct drm_crtc *crtc = state->base.crtc;
> - int min_scale = DRM_PLANE_HELPER_NO_SCALING;
> - int max_scale = DRM_PLANE_HELPER_NO_SCALING;
> - bool can_position = false;
> - int ret;
> - uint32_t pixel_format = 0;
> -
> - if (INTEL_GEN(dev_priv) >= 9) {
> - /* use scaler when colorkey is not required */
> - if (!state->ckey.flags) {
> - min_scale = 1;
> - if (state->base.fb)
> - pixel_format = state->base.fb->format-
> >format;
> - max_scale = skl_max_scale(to_intel_crtc(crtc),
> - crtc_state,
> pixel_format);
> - }
> - can_position = true;
> - }
> -
> - ret = drm_atomic_helper_check_plane_state(&state->base,
> - &crtc_state->base,
> - min_scale, max_scale,
> - can_position, true);
> - if (ret)
> - return ret;
> -
> - if (!state->base.fb)
> - return 0;
> -
> - if (INTEL_GEN(dev_priv) >= 9) {
> - ret = skl_check_plane_surface(crtc_state, state);
> - if (ret)
> - return ret;
> -
> - state->ctl = skl_plane_ctl(crtc_state, state);
> - } else {
> - ret = i9xx_check_plane_surface(state);
> - if (ret)
> - return ret;
> -
> - state->ctl = i9xx_plane_ctl(crtc_state, state);
> - }
> -
> - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> - state->color_ctl = glk_plane_color_ctl(crtc_state,
> state);
> -
> - return 0;
> -}
> -
> static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> struct drm_crtc_state
> *old_crtc_state)
> {
> @@ -13736,8 +13712,6 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> fbc->possible_framebuffer_bits |= primary-
> >frontbuffer_bit;
> }
>
> - primary->check_plane = intel_check_primary_plane;
> -
> if (INTEL_GEN(dev_priv) >= 9) {
> primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> PLANE_PRIMARY);
> @@ -13759,6 +13733,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> primary->update_plane = skl_update_plane;
> primary->disable_plane = skl_disable_plane;
> primary->get_hw_state = skl_plane_get_hw_state;
> + primary->check_plane = skl_plane_check;
>
> plane_funcs = &skl_plane_funcs;
> } else if (INTEL_GEN(dev_priv) >= 4) {
> @@ -13770,6 +13745,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> primary->update_plane = i9xx_update_plane;
> primary->disable_plane = i9xx_disable_plane;
> primary->get_hw_state = i9xx_plane_get_hw_state;
> + primary->check_plane = i9xx_plane_check;
>
> plane_funcs = &i965_plane_funcs;
> } else {
> @@ -13781,6 +13757,7 @@ intel_primary_plane_create(struct
> drm_i915_private *dev_priv, enum pipe pipe)
> primary->update_plane = i9xx_update_plane;
> primary->disable_plane = i9xx_disable_plane;
> primary->get_hw_state = i9xx_plane_get_hw_state;
> + primary->check_plane = i9xx_plane_check;
>
> plane_funcs = &i8xx_plane_funcs;
> }
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index c6c782e14897..6d57c6a508d4 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -973,9 +973,8 @@ struct intel_plane {
> void (*disable_plane)(struct intel_plane *plane,
> struct intel_crtc *crtc);
> bool (*get_hw_state)(struct intel_plane *plane, enum pipe
> *pipe);
> - int (*check_plane)(struct intel_plane *plane,
> - struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *state);
> + int (*check_plane)(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> };
>
> struct intel_watermark_params {
> @@ -1637,8 +1636,8 @@ void intel_crtc_arm_fifo_underrun(struct
> intel_crtc *crtc,
>
> u16 skl_scaler_calc_phase(int sub, bool chroma_center);
> int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> -int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> *crtc_state,
> - uint32_t pixel_format);
> +int skl_max_scale(const struct intel_crtc_state *crtc_state,
> + u32 pixel_format);
>
> static inline u32 intel_plane_ggtt_offset(const struct
> intel_plane_state *state)
> {
> @@ -2112,7 +2111,9 @@ bool skl_plane_has_planar(struct
> drm_i915_private *dev_priv,
> unsigned int skl_plane_max_stride(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> unsigned int rotation);
> -
> +int skl_plane_check(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state);
> +int intel_plane_check_src_coordinates(struct intel_plane_state
> *plane_state);
>
> /* intel_tv.c */
> void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 0d3931b8a981..36e150885897 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -228,6 +228,39 @@ void intel_pipe_update_end(struct
> intel_crtc_state *new_crtc_state)
> #endif
> }
>
> +int intel_plane_check_src_coordinates(struct intel_plane_state
> *plane_state)
> +{
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + struct drm_rect *src = &plane_state->base.src;
> + u32 src_x, src_y, src_w, src_h;
> +
> + /*
> + * Hardware doesn't handle subpixel coordinates.
> + * Adjust to (macro)pixel boundary, but be careful not to
> + * increase the source viewport size, because that could
> + * push the downscaling factor out of bounds.
> + */
> + src_x = src->x1 >> 16;
> + src_w = drm_rect_width(src) >> 16;
> + src_y = src->y1 >> 16;
> + src_h = drm_rect_height(src) >> 16;
> +
> + src->x1 = src_x << 16;
> + src->x2 = (src_x + src_w) << 16;
> + src->y1 = src_y << 16;
> + src->y2 = (src_y + src_h) << 16;
> +
> + if (fb->format->is_yuv &&
> + fb->format->format != DRM_FORMAT_NV12 &&
> + (src_x & 1 || src_w & 1)) {
> + DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2
> for YUV planes\n",
> + src_x, src_w);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> unsigned int
> skl_plane_max_stride(struct intel_plane *plane,
> u32 pixel_format, u64 modifier,
> @@ -983,146 +1016,189 @@ g4x_plane_get_hw_state(struct intel_plane
> *plane,
> }
>
> static int
> -intel_check_sprite_plane(struct intel_plane *plane,
> - struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *state)
> +g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> {
> - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> - struct drm_framebuffer *fb = state->base.fb;
> - int max_scale, min_scale;
> - int ret;
> - uint32_t pixel_format = 0;
> -
> - if (!fb) {
> - state->base.visible = false;
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + const struct drm_rect *src = &plane_state->base.src;
> + const struct drm_rect *dst = &plane_state->base.dst;
> + int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->base.adjusted_mode;
> + unsigned int cpp = fb->format->cpp[0];
> + unsigned int width_bytes;
> + int min_width, min_height;
> +
> + crtc_w = drm_rect_width(dst);
> + crtc_h = drm_rect_height(dst);
> +
> + src_x = src->x1 >> 16;
> + src_y = src->y1 >> 16;
> + src_w = drm_rect_width(src) >> 16;
> + src_h = drm_rect_height(src) >> 16;
> +
> + if (src_w == crtc_w && src_h == crtc_h)
> return 0;
> +
> + min_width = 3;
> +
> + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> + if (src_h & 1) {
> + DRM_DEBUG_KMS("Source height must be even with
> interlaced modes\n");
> + return -EINVAL;
> + }
> + min_height = 6;
> + } else {
> + min_height = 3;
> }
>
> - /* Don't modify another pipe's plane */
> - if (plane->pipe != crtc->pipe) {
> - DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
> + width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
> +
> + if (src_w < min_width || src_h < min_height ||
> + src_w > 2048 || src_h > 2048) {
> + DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed
> hardware limits (%dx%d - %dx%d)\n",
> + src_w, src_h, min_width, min_height,
> 2048, 2048);
> return -EINVAL;
> }
>
> - /* FIXME check all gen limits */
> - if (fb->width < 3 || fb->height < 3 ||
> - fb->pitches[0] > plane->max_stride(plane, fb->format-
> >format,
> - fb->modifier,
> DRM_MODE_ROTATE_0)) {
> - DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
> + if (width_bytes > 4096) {
> + DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max
> with scaling (%u)\n",
> + width_bytes, 4096);
> return -EINVAL;
> }
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> - if (state->base.fb)
> - pixel_format = state->base.fb->format->format;
> - /* use scaler when colorkey is not required */
> - if (!state->ckey.flags) {
> - min_scale = 1;
> - max_scale =
> - skl_max_scale(crtc, crtc_state,
> pixel_format);
> - } else {
> - min_scale = DRM_PLANE_HELPER_NO_SCALING;
> - max_scale = DRM_PLANE_HELPER_NO_SCALING;
> - }
> + if (width_bytes > 4096 || fb->pitches[0] > 4096) {
> + DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with
> scaling (%u)\n",
> + fb->pitches[0], 4096);
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> +static int
> +g4x_sprite_check(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + int max_scale, min_scale;
> + int ret;
> +
> + if (INTEL_GEN(dev_priv) < 7) {
> + min_scale = 1;
> + max_scale = 16 << 16;
> + } else if (IS_IVYBRIDGE(dev_priv)) {
> + min_scale = 1;
> + max_scale = 2 << 16;
> } else {
> - if (INTEL_GEN(dev_priv) < 7) {
> - min_scale = 1;
> - max_scale = 16 << 16;
> - } else if (IS_IVYBRIDGE(dev_priv)) {
> - min_scale = 1;
> - max_scale = 2 << 16;
> - } else {
> - min_scale = DRM_PLANE_HELPER_NO_SCALING;
> - max_scale = DRM_PLANE_HELPER_NO_SCALING;
> - }
> + min_scale = DRM_PLANE_HELPER_NO_SCALING;
> + max_scale = DRM_PLANE_HELPER_NO_SCALING;
> }
>
> - ret = drm_atomic_helper_check_plane_state(&state->base,
> + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> &crtc_state->base,
> min_scale, max_scale,
> true, true);
> if (ret)
> return ret;
>
> - if (state->base.visible) {
> - struct drm_rect *src = &state->base.src;
> - struct drm_rect *dst = &state->base.dst;
> - unsigned int crtc_w = drm_rect_width(dst);
> - unsigned int crtc_h = drm_rect_height(dst);
> - uint32_t src_x, src_y, src_w, src_h;
> + if (!plane_state->base.visible)
> + return 0;
>
> - /*
> - * Hardware doesn't handle subpixel coordinates.
> - * Adjust to (macro)pixel boundary, but be careful not
> to
> - * increase the source viewport size, because that
> could
> - * push the downscaling factor out of bounds.
> - */
> - src_x = src->x1 >> 16;
> - src_w = drm_rect_width(src) >> 16;
> - src_y = src->y1 >> 16;
> - src_h = drm_rect_height(src) >> 16;
> -
> - src->x1 = src_x << 16;
> - src->x2 = (src_x + src_w) << 16;
> - src->y1 = src_y << 16;
> - src->y2 = (src_y + src_h) << 16;
> -
> - if (fb->format->is_yuv &&
> - fb->format->format != DRM_FORMAT_NV12 &&
> - (src_x % 2 || src_w % 2)) {
> - DRM_DEBUG_KMS("src x/w (%u, %u) must be a
> multiple of 2 for YUV planes\n",
> - src_x, src_w);
> - return -EINVAL;
> - }
> + ret = intel_plane_check_src_coordinates(plane_state);
> + if (ret)
> + return ret;
>
> - /* Check size restrictions when scaling */
> - if (src_w != crtc_w || src_h != crtc_h) {
> - unsigned int width_bytes;
> - int cpp = fb->format->cpp[0];
> -
> - width_bytes = ((src_x * cpp) & 63) + src_w *
> cpp;
> -
> - /* FIXME interlacing min height is 6 */
> - if (INTEL_GEN(dev_priv) < 9 && (
> - src_w < 3 || src_h < 3 ||
> - src_w > 2048 || src_h > 2048 ||
> - crtc_w < 3 || crtc_h < 3 ||
> - width_bytes > 4096 || fb->pitches[0] >
> 4096)) {
> - DRM_DEBUG_KMS("Source dimensions exceed
> hardware limits\n");
> - return -EINVAL;
> - }
> - }
> - }
> + ret = g4x_sprite_check_scaling(crtc_state, plane_state);
> + if (ret)
> + return ret;
>
> - if (INTEL_GEN(dev_priv) >= 9) {
> - ret = skl_check_plane_surface(crtc_state, state);
> - if (ret)
> - return ret;
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
>
> - state->ctl = skl_plane_ctl(crtc_state, state);
> - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> {
> - ret = i9xx_check_plane_surface(state);
> - if (ret)
> - return ret;
> + if (INTEL_GEN(dev_priv) >= 7)
> + plane_state->ctl = ivb_sprite_ctl(crtc_state,
> plane_state);
> + else
> + plane_state->ctl = g4x_sprite_ctl(crtc_state,
> plane_state);
>
> - state->ctl = vlv_sprite_ctl(crtc_state, state);
> - } else if (INTEL_GEN(dev_priv) >= 7) {
> - ret = i9xx_check_plane_surface(state);
> - if (ret)
> - return ret;
> + return 0;
> +}
>
> - state->ctl = ivb_sprite_ctl(crtc_state, state);
> - } else {
> - ret = i9xx_check_plane_surface(state);
> - if (ret)
> - return ret;
> +static int
> +vlv_sprite_check(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> +{
> + int ret;
> +
> + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> + &crtc_state->base,
> + DRM_PLANE_HELPER_NO_S
> CALING,
> + DRM_PLANE_HELPER_NO_S
> CALING,
> + true, true);
> + if (ret)
> + return ret;
> +
> + if (!plane_state->base.visible)
> + return 0;
> +
> + ret = intel_plane_check_src_coordinates(plane_state);
> + if (ret)
> + return ret;
Looks like it is missing a g4x_sprite_check_scaling() call for VLV/CHV.
Other than the 2 comments above:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> +
> + ret = i9xx_check_plane_surface(plane_state);
> + if (ret)
> + return ret;
> +
> + plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
>
> - state->ctl = g4x_sprite_ctl(crtc_state, state);
> + return 0;
> +}
> +
> +int skl_plane_check(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + int max_scale, min_scale;
> + int ret;
> +
> + /* use scaler when colorkey is not required */
> + if (!plane_state->ckey.flags) {
> + const struct drm_framebuffer *fb = plane_state-
> >base.fb;
> +
> + min_scale = 1;
> + max_scale = skl_max_scale(crtc_state,
> + fb ? fb->format->format : 0);
> + } else {
> + min_scale = DRM_PLANE_HELPER_NO_SCALING;
> + max_scale = DRM_PLANE_HELPER_NO_SCALING;
> }
>
> + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> + &crtc_state->base,
> + min_scale, max_scale,
> + true, true);
> + if (ret)
> + return ret;
> +
> + if (!plane_state->base.visible)
> + return 0;
> +
> + ret = intel_plane_check_src_coordinates(plane_state);
> + if (ret)
> + return ret;
> +
> + ret = skl_check_plane_surface(crtc_state, plane_state);
> + if (ret)
> + return ret;
> +
> + plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> +
> if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> - state->color_ctl = glk_plane_color_ctl(crtc_state,
> state);
> + plane_state->color_ctl =
> glk_plane_color_ctl(crtc_state,
> + plane_stat
> e);
>
> return 0;
> }
> @@ -1559,6 +1635,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->update_plane = skl_update_plane;
> intel_plane->disable_plane = skl_disable_plane;
> intel_plane->get_hw_state = skl_plane_get_hw_state;
> + intel_plane->check_plane = skl_plane_check;
>
> if (skl_plane_has_planar(dev_priv, pipe,
> PLANE_SPRITE0 + plane)) {
> @@ -1580,6 +1657,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->update_plane = vlv_update_plane;
> intel_plane->disable_plane = vlv_disable_plane;
> intel_plane->get_hw_state = vlv_plane_get_hw_state;
> + intel_plane->check_plane = vlv_sprite_check;
>
> plane_formats = vlv_plane_formats;
> num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> @@ -1591,6 +1669,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->update_plane = ivb_update_plane;
> intel_plane->disable_plane = ivb_disable_plane;
> intel_plane->get_hw_state = ivb_plane_get_hw_state;
> + intel_plane->check_plane = g4x_sprite_check;
>
> plane_formats = snb_plane_formats;
> num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> @@ -1602,6 +1681,7 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->update_plane = g4x_update_plane;
> intel_plane->disable_plane = g4x_disable_plane;
> intel_plane->get_hw_state = g4x_plane_get_hw_state;
> + intel_plane->check_plane = g4x_sprite_check;
>
> modifiers = i9xx_plane_format_modifiers;
> if (IS_GEN6(dev_priv)) {
> @@ -1634,7 +1714,6 @@ intel_sprite_plane_create(struct
> drm_i915_private *dev_priv,
> intel_plane->i9xx_plane = plane;
> intel_plane->id = PLANE_SPRITE0 + plane;
> intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe,
> intel_plane->id);
> - intel_plane->check_plane = intel_check_sprite_plane;
>
> possible_crtcs = (1 << pipe);
>
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions
2018-08-24 1:01 ` Souza, Jose
@ 2018-08-24 12:03 ` Ville Syrjälä
0 siblings, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-08-24 12:03 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Fri, Aug 24, 2018 at 01:01:36AM +0000, Souza, Jose wrote:
> On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Split up intel_check_primary_plane() and intel_check_sprite_plane()
> > into per-platform variants. This way we can get a unified behaviour
> > between the SKL universal planes, and we stop checking for non-SKL
> > specific scaling limits for the "sprite" planes. And we now get
> > a natural place where to add more plarform specific checks.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_atomic_plane.c | 2 +-
> > drivers/gpu/drm/i915/intel_display.c | 123 +++++-------
> > drivers/gpu/drm/i915/intel_drv.h | 13 +-
> > drivers/gpu/drm/i915/intel_sprite.c | 303 +++++++++++++++++++-
> > ----------
> > 4 files changed, 249 insertions(+), 192 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index dcba645cabb8..eddcdd6e4b3b 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -159,7 +159,7 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> > }
> >
> > intel_state->base.visible = false;
> > - ret = intel_plane->check_plane(intel_plane, crtc_state,
> > intel_state);
> > + ret = intel_plane->check_plane(crtc_state, intel_state);
> > if (ret)
> > return ret;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index fdc5bedc5135..9b9eaeda15dd 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3350,6 +3350,36 @@ int i9xx_check_plane_surface(struct
> > intel_plane_state *plane_state)
> > return 0;
> > }
> >
> > +static int
> > +i9xx_plane_check(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state)
> > +{
> > + int ret;
> > +
> > + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> > + &crtc_state->base,
> > + DRM_PLANE_HELPER_NO_S
> > CALING,
> > + DRM_PLANE_HELPER_NO_S
> > CALING,
> > + false, true);
> > + if (ret)
> > + return ret;
> > +
> > + if (!plane_state->base.visible)
> > + return 0;
> > +
> > + ret = intel_plane_check_src_coordinates(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + plane_state->ctl = i9xx_plane_ctl(crtc_state, plane_state);
> > +
> > + return 0;
> > +}
> > +
> > static void i9xx_update_plane(struct intel_plane *plane,
> > const struct intel_crtc_state
> > *crtc_state,
> > const struct intel_plane_state
> > *plane_state)
> > @@ -9680,6 +9710,11 @@ static int intel_check_cursor(struct
> > intel_crtc_state *crtc_state,
> > u32 offset;
> > int ret;
> >
> > + if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> > + DRM_DEBUG_KMS("cursor cannot be tiled\n");
> > + return -EINVAL;
> > + }
> > +
> > ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> > &crtc_state->base,
> > DRM_PLANE_HELPER_NO_S
> > CALING,
> > @@ -9688,13 +9723,12 @@ static int intel_check_cursor(struct
> > intel_crtc_state *crtc_state,
> > if (ret)
> > return ret;
> >
> > - if (!fb)
> > + if (!plane_state->base.visible)
> > return 0;
> >
> > - if (fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> > - DRM_DEBUG_KMS("cursor cannot be tiled\n");
> > - return -EINVAL;
> > - }
> > + ret = intel_plane_check_src_coordinates(plane_state);
> > + if (ret)
> > + return ret;
> >
> > intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> > rotation);
> > @@ -9744,8 +9778,7 @@ static bool i845_cursor_size_ok(const struct
> > intel_plane_state *plane_state)
> > return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width,
> > 64);
> > }
> >
> > -static int i845_check_cursor(struct intel_plane *plane,
> > - struct intel_crtc_state *crtc_state,
> > +static int i845_check_cursor(struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state)
>
> You are dropping struct intel_plane *plane from check_plane and in
> skl_max_scale(), I think it is a good thing to do but would be better
> do it in a previous patch and leave this one just extracting
> check_plane().
Yeah, I can yank that out easily enough.
>
> > {
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > @@ -9943,10 +9976,10 @@ static bool i9xx_cursor_size_ok(const struct
> > intel_plane_state *plane_state)
> > return true;
> > }
> >
> > -static int i9xx_check_cursor(struct intel_plane *plane,
> > - struct intel_crtc_state *crtc_state,
> > +static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state)
> > {
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >base.plane);
> > struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > const struct drm_framebuffer *fb = plane_state->base.fb;
> > enum pipe pipe = plane->pipe;
> > @@ -13193,19 +13226,17 @@ intel_cleanup_plane_fb(struct drm_plane
> > *plane,
> > }
> >
> > int
> > -skl_max_scale(struct intel_crtc *intel_crtc,
> > - struct intel_crtc_state *crtc_state,
> > - uint32_t pixel_format)
> > +skl_max_scale(const struct intel_crtc_state *crtc_state,
> > + u32 pixel_format)
> > {
> > - struct drm_i915_private *dev_priv;
> > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > + struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
> > int max_scale, mult;
> > int crtc_clock, max_dotclk, tmpclk1, tmpclk2;
> >
> > - if (!intel_crtc || !crtc_state->base.enable)
> > + if (!crtc_state->base.enable)
> > return DRM_PLANE_HELPER_NO_SCALING;
> >
> > - dev_priv = to_i915(intel_crtc->base.dev);
> > -
> > crtc_clock = crtc_state->base.adjusted_mode.crtc_clock;
> > max_dotclk = to_intel_atomic_state(crtc_state->base.state)-
> > >cdclk.logical.cdclk;
> >
> > @@ -13229,61 +13260,6 @@ skl_max_scale(struct intel_crtc *intel_crtc,
> > return max_scale;
> > }
> >
> > -static int
> > -intel_check_primary_plane(struct intel_plane *plane,
> > - struct intel_crtc_state *crtc_state,
> > - struct intel_plane_state *state)
> > -{
> > - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > - struct drm_crtc *crtc = state->base.crtc;
> > - int min_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - int max_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - bool can_position = false;
> > - int ret;
> > - uint32_t pixel_format = 0;
> > -
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - /* use scaler when colorkey is not required */
> > - if (!state->ckey.flags) {
> > - min_scale = 1;
> > - if (state->base.fb)
> > - pixel_format = state->base.fb->format-
> > >format;
> > - max_scale = skl_max_scale(to_intel_crtc(crtc),
> > - crtc_state,
> > pixel_format);
> > - }
> > - can_position = true;
> > - }
> > -
> > - ret = drm_atomic_helper_check_plane_state(&state->base,
> > - &crtc_state->base,
> > - min_scale, max_scale,
> > - can_position, true);
> > - if (ret)
> > - return ret;
> > -
> > - if (!state->base.fb)
> > - return 0;
> > -
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - ret = skl_check_plane_surface(crtc_state, state);
> > - if (ret)
> > - return ret;
> > -
> > - state->ctl = skl_plane_ctl(crtc_state, state);
> > - } else {
> > - ret = i9xx_check_plane_surface(state);
> > - if (ret)
> > - return ret;
> > -
> > - state->ctl = i9xx_plane_ctl(crtc_state, state);
> > - }
> > -
> > - if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > - state->color_ctl = glk_plane_color_ctl(crtc_state,
> > state);
> > -
> > - return 0;
> > -}
> > -
> > static void intel_begin_crtc_commit(struct drm_crtc *crtc,
> > struct drm_crtc_state
> > *old_crtc_state)
> > {
> > @@ -13736,8 +13712,6 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > fbc->possible_framebuffer_bits |= primary-
> > >frontbuffer_bit;
> > }
> >
> > - primary->check_plane = intel_check_primary_plane;
> > -
> > if (INTEL_GEN(dev_priv) >= 9) {
> > primary->has_ccs = skl_plane_has_ccs(dev_priv, pipe,
> > PLANE_PRIMARY);
> > @@ -13759,6 +13733,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > primary->update_plane = skl_update_plane;
> > primary->disable_plane = skl_disable_plane;
> > primary->get_hw_state = skl_plane_get_hw_state;
> > + primary->check_plane = skl_plane_check;
> >
> > plane_funcs = &skl_plane_funcs;
> > } else if (INTEL_GEN(dev_priv) >= 4) {
> > @@ -13770,6 +13745,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > + primary->check_plane = i9xx_plane_check;
> >
> > plane_funcs = &i965_plane_funcs;
> > } else {
> > @@ -13781,6 +13757,7 @@ intel_primary_plane_create(struct
> > drm_i915_private *dev_priv, enum pipe pipe)
> > primary->update_plane = i9xx_update_plane;
> > primary->disable_plane = i9xx_disable_plane;
> > primary->get_hw_state = i9xx_plane_get_hw_state;
> > + primary->check_plane = i9xx_plane_check;
> >
> > plane_funcs = &i8xx_plane_funcs;
> > }
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > b/drivers/gpu/drm/i915/intel_drv.h
> > index c6c782e14897..6d57c6a508d4 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -973,9 +973,8 @@ struct intel_plane {
> > void (*disable_plane)(struct intel_plane *plane,
> > struct intel_crtc *crtc);
> > bool (*get_hw_state)(struct intel_plane *plane, enum pipe
> > *pipe);
> > - int (*check_plane)(struct intel_plane *plane,
> > - struct intel_crtc_state *crtc_state,
> > - struct intel_plane_state *state);
> > + int (*check_plane)(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state);
> > };
> >
> > struct intel_watermark_params {
> > @@ -1637,8 +1636,8 @@ void intel_crtc_arm_fifo_underrun(struct
> > intel_crtc *crtc,
> >
> > u16 skl_scaler_calc_phase(int sub, bool chroma_center);
> > int skl_update_scaler_crtc(struct intel_crtc_state *crtc_state);
> > -int skl_max_scale(struct intel_crtc *crtc, struct intel_crtc_state
> > *crtc_state,
> > - uint32_t pixel_format);
> > +int skl_max_scale(const struct intel_crtc_state *crtc_state,
> > + u32 pixel_format);
> >
> > static inline u32 intel_plane_ggtt_offset(const struct
> > intel_plane_state *state)
> > {
> > @@ -2112,7 +2111,9 @@ bool skl_plane_has_planar(struct
> > drm_i915_private *dev_priv,
> > unsigned int skl_plane_max_stride(struct intel_plane *plane,
> > u32 pixel_format, u64 modifier,
> > unsigned int rotation);
> > -
> > +int skl_plane_check(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state);
> > +int intel_plane_check_src_coordinates(struct intel_plane_state
> > *plane_state);
> >
> > /* intel_tv.c */
> > void intel_tv_init(struct drm_i915_private *dev_priv);
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 0d3931b8a981..36e150885897 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -228,6 +228,39 @@ void intel_pipe_update_end(struct
> > intel_crtc_state *new_crtc_state)
> > #endif
> > }
> >
> > +int intel_plane_check_src_coordinates(struct intel_plane_state
> > *plane_state)
> > +{
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + struct drm_rect *src = &plane_state->base.src;
> > + u32 src_x, src_y, src_w, src_h;
> > +
> > + /*
> > + * Hardware doesn't handle subpixel coordinates.
> > + * Adjust to (macro)pixel boundary, but be careful not to
> > + * increase the source viewport size, because that could
> > + * push the downscaling factor out of bounds.
> > + */
> > + src_x = src->x1 >> 16;
> > + src_w = drm_rect_width(src) >> 16;
> > + src_y = src->y1 >> 16;
> > + src_h = drm_rect_height(src) >> 16;
> > +
> > + src->x1 = src_x << 16;
> > + src->x2 = (src_x + src_w) << 16;
> > + src->y1 = src_y << 16;
> > + src->y2 = (src_y + src_h) << 16;
> > +
> > + if (fb->format->is_yuv &&
> > + fb->format->format != DRM_FORMAT_NV12 &&
> > + (src_x & 1 || src_w & 1)) {
> > + DRM_DEBUG_KMS("src x/w (%u, %u) must be a multiple of 2
> > for YUV planes\n",
> > + src_x, src_w);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > unsigned int
> > skl_plane_max_stride(struct intel_plane *plane,
> > u32 pixel_format, u64 modifier,
> > @@ -983,146 +1016,189 @@ g4x_plane_get_hw_state(struct intel_plane
> > *plane,
> > }
> >
> > static int
> > -intel_check_sprite_plane(struct intel_plane *plane,
> > - struct intel_crtc_state *crtc_state,
> > - struct intel_plane_state *state)
> > +g4x_sprite_check_scaling(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state)
> > {
> > - struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > - struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
> > - struct drm_framebuffer *fb = state->base.fb;
> > - int max_scale, min_scale;
> > - int ret;
> > - uint32_t pixel_format = 0;
> > -
> > - if (!fb) {
> > - state->base.visible = false;
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + const struct drm_rect *src = &plane_state->base.src;
> > + const struct drm_rect *dst = &plane_state->base.dst;
> > + int src_x, src_y, src_w, src_h, crtc_w, crtc_h;
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->base.adjusted_mode;
> > + unsigned int cpp = fb->format->cpp[0];
> > + unsigned int width_bytes;
> > + int min_width, min_height;
> > +
> > + crtc_w = drm_rect_width(dst);
> > + crtc_h = drm_rect_height(dst);
> > +
> > + src_x = src->x1 >> 16;
> > + src_y = src->y1 >> 16;
> > + src_w = drm_rect_width(src) >> 16;
> > + src_h = drm_rect_height(src) >> 16;
> > +
> > + if (src_w == crtc_w && src_h == crtc_h)
> > return 0;
> > +
> > + min_width = 3;
> > +
> > + if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > + if (src_h & 1) {
> > + DRM_DEBUG_KMS("Source height must be even with
> > interlaced modes\n");
> > + return -EINVAL;
> > + }
> > + min_height = 6;
> > + } else {
> > + min_height = 3;
> > }
> >
> > - /* Don't modify another pipe's plane */
> > - if (plane->pipe != crtc->pipe) {
> > - DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
> > + width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
> > +
> > + if (src_w < min_width || src_h < min_height ||
> > + src_w > 2048 || src_h > 2048) {
> > + DRM_DEBUG_KMS("Source dimensions (%dx%d) exceed
> > hardware limits (%dx%d - %dx%d)\n",
> > + src_w, src_h, min_width, min_height,
> > 2048, 2048);
> > return -EINVAL;
> > }
> >
> > - /* FIXME check all gen limits */
> > - if (fb->width < 3 || fb->height < 3 ||
> > - fb->pitches[0] > plane->max_stride(plane, fb->format-
> > >format,
> > - fb->modifier,
> > DRM_MODE_ROTATE_0)) {
> > - DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
> > + if (width_bytes > 4096) {
> > + DRM_DEBUG_KMS("Fetch width (%d) exceeds hardware max
> > with scaling (%u)\n",
> > + width_bytes, 4096);
> > return -EINVAL;
> > }
> >
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - if (state->base.fb)
> > - pixel_format = state->base.fb->format->format;
> > - /* use scaler when colorkey is not required */
> > - if (!state->ckey.flags) {
> > - min_scale = 1;
> > - max_scale =
> > - skl_max_scale(crtc, crtc_state,
> > pixel_format);
> > - } else {
> > - min_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - max_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - }
> > + if (width_bytes > 4096 || fb->pitches[0] > 4096) {
> > + DRM_DEBUG_KMS("Stride (%u) exceeds hardware max with
> > scaling (%u)\n",
> > + fb->pitches[0], 4096);
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static int
> > +g4x_sprite_check(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >base.plane);
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + int max_scale, min_scale;
> > + int ret;
> > +
> > + if (INTEL_GEN(dev_priv) < 7) {
> > + min_scale = 1;
> > + max_scale = 16 << 16;
> > + } else if (IS_IVYBRIDGE(dev_priv)) {
> > + min_scale = 1;
> > + max_scale = 2 << 16;
> > } else {
> > - if (INTEL_GEN(dev_priv) < 7) {
> > - min_scale = 1;
> > - max_scale = 16 << 16;
> > - } else if (IS_IVYBRIDGE(dev_priv)) {
> > - min_scale = 1;
> > - max_scale = 2 << 16;
> > - } else {
> > - min_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - max_scale = DRM_PLANE_HELPER_NO_SCALING;
> > - }
> > + min_scale = DRM_PLANE_HELPER_NO_SCALING;
> > + max_scale = DRM_PLANE_HELPER_NO_SCALING;
> > }
> >
> > - ret = drm_atomic_helper_check_plane_state(&state->base,
> > + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> > &crtc_state->base,
> > min_scale, max_scale,
> > true, true);
> > if (ret)
> > return ret;
> >
> > - if (state->base.visible) {
> > - struct drm_rect *src = &state->base.src;
> > - struct drm_rect *dst = &state->base.dst;
> > - unsigned int crtc_w = drm_rect_width(dst);
> > - unsigned int crtc_h = drm_rect_height(dst);
> > - uint32_t src_x, src_y, src_w, src_h;
> > + if (!plane_state->base.visible)
> > + return 0;
> >
> > - /*
> > - * Hardware doesn't handle subpixel coordinates.
> > - * Adjust to (macro)pixel boundary, but be careful not
> > to
> > - * increase the source viewport size, because that
> > could
> > - * push the downscaling factor out of bounds.
> > - */
> > - src_x = src->x1 >> 16;
> > - src_w = drm_rect_width(src) >> 16;
> > - src_y = src->y1 >> 16;
> > - src_h = drm_rect_height(src) >> 16;
> > -
> > - src->x1 = src_x << 16;
> > - src->x2 = (src_x + src_w) << 16;
> > - src->y1 = src_y << 16;
> > - src->y2 = (src_y + src_h) << 16;
> > -
> > - if (fb->format->is_yuv &&
> > - fb->format->format != DRM_FORMAT_NV12 &&
> > - (src_x % 2 || src_w % 2)) {
> > - DRM_DEBUG_KMS("src x/w (%u, %u) must be a
> > multiple of 2 for YUV planes\n",
> > - src_x, src_w);
> > - return -EINVAL;
> > - }
> > + ret = intel_plane_check_src_coordinates(plane_state);
> > + if (ret)
> > + return ret;
> >
> > - /* Check size restrictions when scaling */
> > - if (src_w != crtc_w || src_h != crtc_h) {
> > - unsigned int width_bytes;
> > - int cpp = fb->format->cpp[0];
> > -
> > - width_bytes = ((src_x * cpp) & 63) + src_w *
> > cpp;
> > -
> > - /* FIXME interlacing min height is 6 */
> > - if (INTEL_GEN(dev_priv) < 9 && (
> > - src_w < 3 || src_h < 3 ||
> > - src_w > 2048 || src_h > 2048 ||
> > - crtc_w < 3 || crtc_h < 3 ||
> > - width_bytes > 4096 || fb->pitches[0] >
> > 4096)) {
> > - DRM_DEBUG_KMS("Source dimensions exceed
> > hardware limits\n");
> > - return -EINVAL;
> > - }
> > - }
> > - }
> > + ret = g4x_sprite_check_scaling(crtc_state, plane_state);
> > + if (ret)
> > + return ret;
> >
> > - if (INTEL_GEN(dev_priv) >= 9) {
> > - ret = skl_check_plane_surface(crtc_state, state);
> > - if (ret)
> > - return ret;
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> >
> > - state->ctl = skl_plane_ctl(crtc_state, state);
> > - } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > {
> > - ret = i9xx_check_plane_surface(state);
> > - if (ret)
> > - return ret;
> > + if (INTEL_GEN(dev_priv) >= 7)
> > + plane_state->ctl = ivb_sprite_ctl(crtc_state,
> > plane_state);
> > + else
> > + plane_state->ctl = g4x_sprite_ctl(crtc_state,
> > plane_state);
> >
> > - state->ctl = vlv_sprite_ctl(crtc_state, state);
> > - } else if (INTEL_GEN(dev_priv) >= 7) {
> > - ret = i9xx_check_plane_surface(state);
> > - if (ret)
> > - return ret;
> > + return 0;
> > +}
> >
> > - state->ctl = ivb_sprite_ctl(crtc_state, state);
> > - } else {
> > - ret = i9xx_check_plane_surface(state);
> > - if (ret)
> > - return ret;
> > +static int
> > +vlv_sprite_check(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state)
> > +{
> > + int ret;
> > +
> > + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> > + &crtc_state->base,
> > + DRM_PLANE_HELPER_NO_S
> > CALING,
> > + DRM_PLANE_HELPER_NO_S
> > CALING,
> > + true, true);
> > + if (ret)
> > + return ret;
> > +
> > + if (!plane_state->base.visible)
> > + return 0;
> > +
> > + ret = intel_plane_check_src_coordinates(plane_state);
> > + if (ret)
> > + return ret;
>
> Looks like it is missing a g4x_sprite_check_scaling() call for VLV/CHV.
Not needed since VLV/CHV sprites can't scale.
>
>
> Other than the 2 comments above:
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > +
> > + ret = i9xx_check_plane_surface(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + plane_state->ctl = vlv_sprite_ctl(crtc_state, plane_state);
> >
> > - state->ctl = g4x_sprite_ctl(crtc_state, state);
> > + return 0;
> > +}
> > +
> > +int skl_plane_check(struct intel_crtc_state *crtc_state,
> > + struct intel_plane_state *plane_state)
> > +{
> > + struct intel_plane *plane = to_intel_plane(plane_state-
> > >base.plane);
> > + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> > + int max_scale, min_scale;
> > + int ret;
> > +
> > + /* use scaler when colorkey is not required */
> > + if (!plane_state->ckey.flags) {
> > + const struct drm_framebuffer *fb = plane_state-
> > >base.fb;
> > +
> > + min_scale = 1;
> > + max_scale = skl_max_scale(crtc_state,
> > + fb ? fb->format->format : 0);
> > + } else {
> > + min_scale = DRM_PLANE_HELPER_NO_SCALING;
> > + max_scale = DRM_PLANE_HELPER_NO_SCALING;
> > }
> >
> > + ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> > + &crtc_state->base,
> > + min_scale, max_scale,
> > + true, true);
> > + if (ret)
> > + return ret;
> > +
> > + if (!plane_state->base.visible)
> > + return 0;
> > +
> > + ret = intel_plane_check_src_coordinates(plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + ret = skl_check_plane_surface(crtc_state, plane_state);
> > + if (ret)
> > + return ret;
> > +
> > + plane_state->ctl = skl_plane_ctl(crtc_state, plane_state);
> > +
> > if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv))
> > - state->color_ctl = glk_plane_color_ctl(crtc_state,
> > state);
> > + plane_state->color_ctl =
> > glk_plane_color_ctl(crtc_state,
> > + plane_stat
> > e);
> >
> > return 0;
> > }
> > @@ -1559,6 +1635,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->update_plane = skl_update_plane;
> > intel_plane->disable_plane = skl_disable_plane;
> > intel_plane->get_hw_state = skl_plane_get_hw_state;
> > + intel_plane->check_plane = skl_plane_check;
> >
> > if (skl_plane_has_planar(dev_priv, pipe,
> > PLANE_SPRITE0 + plane)) {
> > @@ -1580,6 +1657,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->update_plane = vlv_update_plane;
> > intel_plane->disable_plane = vlv_disable_plane;
> > intel_plane->get_hw_state = vlv_plane_get_hw_state;
> > + intel_plane->check_plane = vlv_sprite_check;
> >
> > plane_formats = vlv_plane_formats;
> > num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
> > @@ -1591,6 +1669,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->update_plane = ivb_update_plane;
> > intel_plane->disable_plane = ivb_disable_plane;
> > intel_plane->get_hw_state = ivb_plane_get_hw_state;
> > + intel_plane->check_plane = g4x_sprite_check;
> >
> > plane_formats = snb_plane_formats;
> > num_plane_formats = ARRAY_SIZE(snb_plane_formats);
> > @@ -1602,6 +1681,7 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->update_plane = g4x_update_plane;
> > intel_plane->disable_plane = g4x_disable_plane;
> > intel_plane->get_hw_state = g4x_plane_get_hw_state;
> > + intel_plane->check_plane = g4x_sprite_check;
> >
> > modifiers = i9xx_plane_format_modifiers;
> > if (IS_GEN6(dev_priv)) {
> > @@ -1634,7 +1714,6 @@ intel_sprite_plane_create(struct
> > drm_i915_private *dev_priv,
> > intel_plane->i9xx_plane = plane;
> > intel_plane->id = PLANE_SPRITE0 + plane;
> > intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER(pipe,
> > intel_plane->id);
> > - intel_plane->check_plane = intel_check_sprite_plane;
> >
> > possible_crtcs = (1 << pipe);
> >
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place
2018-07-19 18:22 ` [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place Ville Syrjala
@ 2018-08-24 19:56 ` Souza, Jose
2018-08-27 11:48 ` Ville Syrjälä
0 siblings, 1 reply; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 19:56 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the skl+ specific framebuffer related checks from
> intel_plane_atomic_check_with_state() into a new function
> (skl_plane_check_fb()) which we'll simply call from the skl
> plane->check() hook.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 42 --------------------
> drivers/gpu/drm/i915/intel_display.c | 12 ------
> drivers/gpu/drm/i915/intel_sprite.c | 66
> +++++++++++++++++++++++++++++++
> 3 files changed, 66 insertions(+), 54 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index eddcdd6e4b3b..7c0873060934 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -116,40 +116,11 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
> struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_plane_state *state = &intel_state->base;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->base.adjusted_mode;
> int ret;
>
> if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> return 0;
>
> - if (state->fb && drm_rotation_90_or_270(state->rotation)) {
> - struct drm_format_name_buf format_name;
> -
> - if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> - state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> - DRM_DEBUG_KMS("Y/Yf tiling required for
> 90/270!\n");
> - return -EINVAL;
> - }
> -
> - /*
> - * 90/270 is not allowed with RGB64 16:16:16:16,
> - * RGB 16-bit 5:6:5, and Indexed 8-bit.
> - * TBD: Add RGB64 case once its added in supported
> format list.
> - */
> - switch (state->fb->format->format) {
> - case DRM_FORMAT_C8:
> - case DRM_FORMAT_RGB565:
> - DRM_DEBUG_KMS("Unsupported pixel format %s for
> 90/270!\n",
> - drm_get_format_name(state->fb-
> >format->format,
> - &format_name)
> );
> - return -EINVAL;
> -
> - default:
> - break;
> - }
> - }
> -
> /* CHV ignores the mirror bit when the rotate bit is set :( */
> if (IS_CHERRYVIEW(dev_priv) &&
> state->rotation & DRM_MODE_ROTATE_180 &&
> @@ -163,19 +134,6 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
> if (ret)
> return ret;
>
> - /*
> - * Y-tiling is not supported in IF-ID Interlace mode in
> - * GEN9 and above.
> - */
> - if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state-
> >base.enable &&
> - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> - if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> - state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> - DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-
> ID mode\n");
> - return -EINVAL;
> - }
> - }
> -
> /* FIXME pre-g4x don't work like this */
> if (state->visible)
> crtc_state->active_planes |= BIT(intel_plane->id);
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 9b9eaeda15dd..2381b762d109 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3151,12 +3151,6 @@ static int skl_check_ccs_aux_surface(struct
> intel_plane_state *plane_state)
> int y = src_y / vsub;
> u32 offset;
>
> - if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 |
> DRM_MODE_ROTATE_180)) {
> - DRM_DEBUG_KMS("RC support only with 0/180 degree
> rotation %x\n",
> - plane_state->base.rotation);
> - return -EINVAL;
> - }
> -
> intel_add_fb_offsets(&x, &y, plane_state, 1);
> offset = intel_plane_compute_aligned_offset(&x, &y,
> plane_state, 1);
>
> @@ -3178,12 +3172,6 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> rotation);
>
> - if (rotation & DRM_MODE_REFLECT_X &&
> - fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> - DRM_DEBUG_KMS("horizontal flip is not supported with
> linear surface formats\n");
> - return -EINVAL;
> - }
> -
> if (!plane_state->base.visible)
> return 0;
>
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index 36e150885897..041b8921f4fe 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1156,6 +1156,68 @@ vlv_sprite_check(struct intel_crtc_state
> *crtc_state,
> return 0;
> }
>
> +static int skl_plane_check_fb(const struct intel_crtc_state
> *crtc_state,
> + const struct intel_plane_state
> *plane_state)
> +{
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> + unsigned int rotation = plane_state->base.rotation;
> + struct drm_format_name_buf format_name;
> +
> + if (!fb)
> + return 0;
> +
> + if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
> + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS &&
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> + DRM_DEBUG_KMS("RC support only with 0/180 degree
> rotation (%x)\n",
> + rotation);
> + return -EINVAL;
> + }
> +
> + if (rotation & DRM_MODE_REFLECT_X &&
> + fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> + DRM_DEBUG_KMS("horizontal flip is not supported with
> linear surface formats\n");
> + return -EINVAL;
> + }
> +
> + if (drm_rotation_90_or_270(rotation)) {
> + if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> + fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> + DRM_DEBUG_KMS("Y/Yf tiling required for
> 90/270!\n");
> + return -EINVAL;
> + }
> +
> + /*
> + * 90/270 is not allowed with RGB64 16:16:16:16,
> + * RGB 16-bit 5:6:5, and Indexed 8-bit.
> + * TBD: Add RGB64 case once its added in supported
> format list.
> + */
> + switch (fb->format->format) {
> + case DRM_FORMAT_C8:
> + case DRM_FORMAT_RGB565:
> + DRM_DEBUG_KMS("Unsupported pixel format %s for
> 90/270!\n",
> + drm_get_format_name(fb->format-
> >format,
> + &format_name)
> );
> + return -EINVAL;
> + default:
> + break;
> + }
> + }
> +
> + /* Y-tiling is not supported in IF-ID Interlace mode */
> + if (crtc_state->base.enable &&
> + crtc_state->base.adjusted_mode.flags &
> DRM_MODE_FLAG_INTERLACE &&
> + (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
I guess this 2 checks bellow are new? It was not being handled in
skl_check_ccs_aux_surface() or else where.
Other than this everything else looks good.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> + fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> + DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> mode\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> int skl_plane_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> @@ -1164,6 +1226,10 @@ int skl_plane_check(struct intel_crtc_state
> *crtc_state,
> int max_scale, min_scale;
> int ret;
>
> + ret = skl_plane_check_fb(crtc_state, plane_state);
> + if (ret)
> + return ret;
> +
> /* use scaler when colorkey is not required */
> if (!plane_state->ckey.flags) {
> const struct drm_framebuffer *fb = plane_state-
> >base.fb;
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check()
2018-07-19 18:22 ` [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check() Ville Syrjala
@ 2018-08-24 20:04 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 20:04 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Move the chv rotation vs. reflections checks to the plane->check()
> hook,
> away from the (now) platform agnostic
> intel_plane_atomic_check_with_state().
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_atomic_plane.c | 9 ---------
> drivers/gpu/drm/i915/intel_display.c | 4 ++++
> drivers/gpu/drm/i915/intel_drv.h | 1 +
> drivers/gpu/drm/i915/intel_sprite.c | 21 +++++++++++++++++++++
> 4 files changed, 26 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> b/drivers/gpu/drm/i915/intel_atomic_plane.c
> index 7c0873060934..aabebe0d2e9b 100644
> --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> @@ -113,7 +113,6 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
> struct intel_plane_state
> *intel_state)
> {
> struct drm_plane *plane = intel_state->base.plane;
> - struct drm_i915_private *dev_priv = to_i915(plane->dev);
> struct drm_plane_state *state = &intel_state->base;
> struct intel_plane *intel_plane = to_intel_plane(plane);
> int ret;
> @@ -121,14 +120,6 @@ int intel_plane_atomic_check_with_state(const
> struct intel_crtc_state *old_crtc_
> if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> return 0;
>
> - /* CHV ignores the mirror bit when the rotate bit is set :( */
> - if (IS_CHERRYVIEW(dev_priv) &&
> - state->rotation & DRM_MODE_ROTATE_180 &&
> - state->rotation & DRM_MODE_REFLECT_X) {
> - DRM_DEBUG_KMS("Cannot rotate and reflect at the same
> time\n");
> - return -EINVAL;
> - }
> -
> intel_state->base.visible = false;
> ret = intel_plane->check_plane(crtc_state, intel_state);
> if (ret)
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index dbcc9a23eefa..b0e39dcf2fb8 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -3318,6 +3318,10 @@ i9xx_plane_check(struct intel_crtc_state
> *crtc_state,
> {
> int ret;
>
> + ret = chv_plane_check_rotation(plane_state);
> + if (ret)
> + return ret;
> +
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> &crtc_state->base,
> DRM_PLANE_HELPER_NO_S
> CALING,
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 55f3537ba8f8..91b7fb6a07e1 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -2113,6 +2113,7 @@ unsigned int skl_plane_max_stride(struct
> intel_plane *plane,
> int skl_plane_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state);
> int intel_plane_check_src_coordinates(struct intel_plane_state
> *plane_state);
> +int chv_plane_check_rotation(const struct intel_plane_state
> *plane_state);
>
> /* intel_tv.c */
> void intel_tv_init(struct drm_i915_private *dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> b/drivers/gpu/drm/i915/intel_sprite.c
> index f43884f76212..93aa355f00e3 100644
> --- a/drivers/gpu/drm/i915/intel_sprite.c
> +++ b/drivers/gpu/drm/i915/intel_sprite.c
> @@ -1126,12 +1126,33 @@ g4x_sprite_check(struct intel_crtc_state
> *crtc_state,
> return 0;
> }
>
> +int chv_plane_check_rotation(const struct intel_plane_state
> *plane_state)
> +{
> + struct intel_plane *plane = to_intel_plane(plane_state-
> >base.plane);
> + struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
> + unsigned int rotation = plane_state->base.rotation;
> +
> + /* CHV ignores the mirror bit when the rotate bit is set :( */
> + if (IS_CHERRYVIEW(dev_priv) &&
> + rotation & DRM_MODE_ROTATE_180 &&
> + rotation & DRM_MODE_REFLECT_X) {
> + DRM_DEBUG_KMS("Cannot rotate and reflect at the same
> time\n");
> + return -EINVAL;
> + }
> +
> + return 0;
> +}
> +
> static int
> vlv_sprite_check(struct intel_crtc_state *crtc_state,
> struct intel_plane_state *plane_state)
> {
> int ret;
>
> + ret = chv_plane_check_rotation(plane_state);
> + if (ret)
> + return ret;
> +
> ret = drm_atomic_helper_check_plane_state(&plane_state->base,
> &crtc_state->base,
> DRM_PLANE_HELPER_NO_S
> CALING,
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface()
2018-07-19 18:22 ` [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface() Ville Syrjala
@ 2018-08-24 20:08 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 20:08 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Extract intel_cursor_check_surface() to better match the code layout
> of the other plane types.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 47 ++++++++++++++++++++++--
> ------------
> 1 file changed, 29 insertions(+), 18 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index b0e39dcf2fb8..b39c941b4791 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -9667,13 +9667,37 @@ static bool intel_cursor_size_ok(const struct
> intel_plane_state *plane_state)
> height > 0 && height <= config->cursor_height;
> }
>
> -static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> - struct intel_plane_state *plane_state)
> +static int intel_cursor_check_surface(struct intel_plane_state
> *plane_state)
> {
> const struct drm_framebuffer *fb = plane_state->base.fb;
> unsigned int rotation = plane_state->base.rotation;
> int src_x, src_y;
> u32 offset;
> +
> + intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> + plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> +
> + src_x = plane_state->base.src_x >> 16;
> + src_y = plane_state->base.src_y >> 16;
> +
> + intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> + offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> + plane_state, 0);
> +
> + if (src_x != 0 || src_y != 0) {
> + DRM_DEBUG_KMS("Arbitrary cursor panning not
> supported\n");
> + return -EINVAL;
> + }
> +
> + plane_state->color_plane[0].offset = offset;
> +
> + return 0;
> +}
> +
> +static int intel_check_cursor(struct intel_crtc_state *crtc_state,
> + struct intel_plane_state *plane_state)
> +{
> + const struct drm_framebuffer *fb = plane_state->base.fb;
> int ret;
>
> if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
> @@ -9696,22 +9720,9 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> if (ret)
> return ret;
>
> - intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> - plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> -
> - src_x = plane_state->base.src_x >> 16;
> - src_y = plane_state->base.src_y >> 16;
> -
> - intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> - offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
> - plane_state, 0);
> -
> - if (src_x != 0 || src_y != 0) {
> - DRM_DEBUG_KMS("Arbitrary cursor panning not
> supported\n");
> - return -EINVAL;
> - }
> -
> - plane_state->color_plane[0].offset = offset;
> + ret = intel_cursor_check_surface(plane_state);
> + if (ret)
> + return ret;
>
> return 0;
> }
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 07/18] drm/i915: Store ggtt_view in plane_state
2018-07-19 18:22 ` [PATCH 07/18] drm/i915: Store ggtt_view " Ville Syrjala
@ 2018-08-24 20:13 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 20:13 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Stash the gtt_view structure into the plane state. This will become
> useful when we do GTT remapping as the gtt_view will not come
> directly
> from the fb anymore.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 16 +++++++++-------
> drivers/gpu/drm/i915/intel_drv.h | 3 ++-
> drivers/gpu/drm/i915/intel_fbdev.c | 6 ++++--
> 3 files changed, 15 insertions(+), 10 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index eadb8b20d504..e6cb8238f257 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2079,14 +2079,13 @@ static bool intel_plane_uses_fence(const
> struct intel_plane_state *plane_state)
>
> struct i915_vma *
> intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> - unsigned int rotation,
> + const struct i915_ggtt_view *view,
> bool uses_fence,
> unsigned long *out_flags)
> {
> struct drm_device *dev = fb->dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_i915_gem_object *obj = intel_fb_obj(fb);
> - struct i915_ggtt_view view;
> struct i915_vma *vma;
> unsigned int pinctl;
> u32 alignment;
> @@ -2095,8 +2094,6 @@ intel_pin_and_fence_fb_obj(struct
> drm_framebuffer *fb,
>
> alignment = intel_surf_alignment(fb, 0);
>
> - intel_fill_fb_ggtt_view(&view, fb, rotation);
> -
> /* Note that the w/a also requires 64 PTE of padding following
> the
> * bo. We currently fill all unused PTE with the shadow page
> and so
> * we should always have valid PTE following the scanout
> preventing
> @@ -2129,7 +2126,7 @@ intel_pin_and_fence_fb_obj(struct
> drm_framebuffer *fb,
> pinctl |= PIN_MAPPABLE;
>
> vma = i915_gem_object_pin_to_display_plane(obj,
> - alignment, &view,
> pinctl);
> + alignment, view,
> pinctl);
> if (IS_ERR(vma))
> goto err;
>
> @@ -2851,13 +2848,15 @@ intel_find_initial_plane_obj(struct
> intel_crtc *intel_crtc,
> return;
>
> valid_fb:
> + intel_fill_fb_ggtt_view(&intel_state->view, fb,
> + intel_state->base.rotation);
> intel_state->color_plane[0].stride =
> intel_fb_pitch(fb, 0, intel_state->base.rotation);
>
> mutex_lock(&dev->struct_mutex);
> intel_state->vma =
> intel_pin_and_fence_fb_obj(fb,
> - primary->state->rotation,
> + &intel_state->view,
> intel_plane_uses_fence(intel
> _state),
> &intel_state->flags);
> mutex_unlock(&dev->struct_mutex);
> @@ -3171,6 +3170,7 @@ int skl_check_plane_surface(const struct
> intel_crtc_state *crtc_state,
> unsigned int rotation = plane_state->base.rotation;
> int ret;
>
> + intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
> plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> rotation);
>
> @@ -3315,6 +3315,7 @@ int i9xx_check_plane_surface(struct
> intel_plane_state *plane_state)
> int src_y = plane_state->base.src.y1 >> 16;
> u32 offset;
>
> + intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
>
> intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
> @@ -9691,6 +9692,7 @@ static int intel_check_cursor(struct
> intel_crtc_state *crtc_state,
> return -EINVAL;
> }
>
> + intel_fill_fb_ggtt_view(&plane_state->view, fb, rotation);
> plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> rotation);
>
> src_x = plane_state->base.src_x >> 16;
> @@ -13029,7 +13031,7 @@ static int intel_plane_pin_fb(struct
> intel_plane_state *plane_state)
> }
>
> vma = intel_pin_and_fence_fb_obj(fb,
> - plane_state->base.rotation,
> + &plane_state->view,
> intel_plane_uses_fence(plane_s
> tate),
> &plane_state->flags);
> if (IS_ERR(vma))
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index f647f9e1f671..d70276ff3d0e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -494,6 +494,7 @@ struct intel_atomic_state {
>
> struct intel_plane_state {
> struct drm_plane_state base;
> + struct i915_ggtt_view view;
> struct i915_vma *vma;
> unsigned long flags;
> #define PLANE_HAS_FENCE BIT(0)
> @@ -1560,7 +1561,7 @@ void intel_release_load_detect_pipe(struct
> drm_connector *connector,
> struct drm_modeset_acquire_ctx
> *ctx);
> struct i915_vma *
> intel_pin_and_fence_fb_obj(struct drm_framebuffer *fb,
> - unsigned int rotation,
> + const struct i915_ggtt_view *view,
> bool uses_fence,
> unsigned long *out_flags);
> void intel_unpin_fb_vma(struct i915_vma *vma, unsigned long flags);
> diff --git a/drivers/gpu/drm/i915/intel_fbdev.c
> b/drivers/gpu/drm/i915/intel_fbdev.c
> index fb2f9fce34cd..f99332972b7a 100644
> --- a/drivers/gpu/drm/i915/intel_fbdev.c
> +++ b/drivers/gpu/drm/i915/intel_fbdev.c
> @@ -175,6 +175,9 @@ static int intelfb_create(struct drm_fb_helper
> *helper,
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct pci_dev *pdev = dev_priv->drm.pdev;
> struct i915_ggtt *ggtt = &dev_priv->ggtt;
> + const struct i915_ggtt_view view = {
> + .type = I915_GGTT_VIEW_NORMAL,
> + };
> struct fb_info *info;
> struct drm_framebuffer *fb;
> struct i915_vma *vma;
> @@ -214,8 +217,7 @@ static int intelfb_create(struct drm_fb_helper
> *helper,
> * BIOS is suitable for own access.
> */
> vma = intel_pin_and_fence_fb_obj(&ifbdev->fb->base,
> - DRM_MODE_ROTATE_0,
> - false, &flags);
> + &view, false, &flags);
> if (IS_ERR(vma)) {
> ret = PTR_ERR(vma);
> goto out_unlock;
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k
2018-07-19 18:22 ` [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k Ville Syrjala
@ 2018-08-24 20:49 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 20:49 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With gtt remapping in place we can use arbitraily large framebuffers.
> Let's bump the limits as high as we can (32k-1). Going beyond that
> would require switching out s16.16 src coordinate representation to
> something with more spare bits.
With someone else review in patch 15 and 16:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index fa199f469e81..8aa2a61d2943 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15429,8 +15429,8 @@ int intel_modeset_init(struct drm_device
> *dev)
> dev->mode_config.max_width = 4096;
> dev->mode_config.max_height = 4096;
> } else {
> - dev->mode_config.max_width = 8192;
> - dev->mode_config.max_height = 8192;
> + dev->mode_config.max_width = 32767;
> + dev->mode_config.max_height = 32767;
> }
>
> if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB
2018-07-19 18:22 ` [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
@ 2018-08-24 20:49 ` Souza, Jose
0 siblings, 0 replies; 59+ messages in thread
From: Souza, Jose @ 2018-08-24 20:49 UTC (permalink / raw)
To: ville.syrjala, intel-gfx
On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> With gtt remapping plugged in we can simply raise the stride
> limit on gen4+. Let's just arbitraily pick 256 KiB as the limit.
>
> No remapping CCS because the virtual address of each page actually
> matters due to the new hash mode
> (WaCompressedResourceDisplayNewHashMode:skl,kbl etc.), and no
> remapping
> on gen2/3 due to lack of fence on the remapped vma.
With someone else review in patch 15 and 16:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_display.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c
> b/drivers/gpu/drm/i915/intel_display.c
> index 8fb78214b4be..fa199f469e81 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -2505,6 +2505,19 @@ static
> u32 intel_fb_max_stride(struct drm_i915_private *dev_priv,
> u32 pixel_format, u64 modifier)
> {
> + /*
> + * Arbitrary limit for gen4+. We can deal with any page
> + * aligned stride via GTT remapping. Gen2/3 need a fence
> + * for tiled scanout which the remapped vma won't have,
> + * so we don't allow remapping on those platforms.
> + *
> + * Also the new hash mode we use for CCS isn't compatible
> + * with remapping as the virtual address of the pages
> + * affects the compressed data.
> + */
> + if (INTEL_GEN(dev_priv) >= 4 &&
> !intel_modifier_has_ccs(modifier))
> + return 256*1024;
> +
> return intel_plane_fb_max_stride(dev_priv, pixel_format,
> modifier);
> }
>
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^ permalink raw reply [flat|nested] 59+ messages in thread
* Re: [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place
2018-08-24 19:56 ` Souza, Jose
@ 2018-08-27 11:48 ` Ville Syrjälä
0 siblings, 0 replies; 59+ messages in thread
From: Ville Syrjälä @ 2018-08-27 11:48 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
On Fri, Aug 24, 2018 at 07:56:34PM +0000, Souza, Jose wrote:
> On Thu, 2018-07-19 at 21:22 +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Move the skl+ specific framebuffer related checks from
> > intel_plane_atomic_check_with_state() into a new function
> > (skl_plane_check_fb()) which we'll simply call from the skl
> > plane->check() hook.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_atomic_plane.c | 42 --------------------
> > drivers/gpu/drm/i915/intel_display.c | 12 ------
> > drivers/gpu/drm/i915/intel_sprite.c | 66
> > +++++++++++++++++++++++++++++++
> > 3 files changed, 66 insertions(+), 54 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > index eddcdd6e4b3b..7c0873060934 100644
> > --- a/drivers/gpu/drm/i915/intel_atomic_plane.c
> > +++ b/drivers/gpu/drm/i915/intel_atomic_plane.c
> > @@ -116,40 +116,11 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> > struct drm_i915_private *dev_priv = to_i915(plane->dev);
> > struct drm_plane_state *state = &intel_state->base;
> > struct intel_plane *intel_plane = to_intel_plane(plane);
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->base.adjusted_mode;
> > int ret;
> >
> > if (!intel_state->base.crtc && !old_plane_state->base.crtc)
> > return 0;
> >
> > - if (state->fb && drm_rotation_90_or_270(state->rotation)) {
> > - struct drm_format_name_buf format_name;
> > -
> > - if (state->fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> > - state->fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> > - DRM_DEBUG_KMS("Y/Yf tiling required for
> > 90/270!\n");
> > - return -EINVAL;
> > - }
> > -
> > - /*
> > - * 90/270 is not allowed with RGB64 16:16:16:16,
> > - * RGB 16-bit 5:6:5, and Indexed 8-bit.
> > - * TBD: Add RGB64 case once its added in supported
> > format list.
> > - */
> > - switch (state->fb->format->format) {
> > - case DRM_FORMAT_C8:
> > - case DRM_FORMAT_RGB565:
> > - DRM_DEBUG_KMS("Unsupported pixel format %s for
> > 90/270!\n",
> > - drm_get_format_name(state->fb-
> > >format->format,
> > - &format_name)
> > );
> > - return -EINVAL;
> > -
> > - default:
> > - break;
> > - }
> > - }
> > -
> > /* CHV ignores the mirror bit when the rotate bit is set :( */
> > if (IS_CHERRYVIEW(dev_priv) &&
> > state->rotation & DRM_MODE_ROTATE_180 &&
> > @@ -163,19 +134,6 @@ int intel_plane_atomic_check_with_state(const
> > struct intel_crtc_state *old_crtc_
> > if (ret)
> > return ret;
> >
> > - /*
> > - * Y-tiling is not supported in IF-ID Interlace mode in
> > - * GEN9 and above.
> > - */
> > - if (state->fb && INTEL_GEN(dev_priv) >= 9 && crtc_state-
> > >base.enable &&
> > - adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
> > - if (state->fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> > - state->fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
> > - DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-
> > ID mode\n");
> > - return -EINVAL;
> > - }
> > - }
> > -
> > /* FIXME pre-g4x don't work like this */
> > if (state->visible)
> > crtc_state->active_planes |= BIT(intel_plane->id);
> > diff --git a/drivers/gpu/drm/i915/intel_display.c
> > b/drivers/gpu/drm/i915/intel_display.c
> > index 9b9eaeda15dd..2381b762d109 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -3151,12 +3151,6 @@ static int skl_check_ccs_aux_surface(struct
> > intel_plane_state *plane_state)
> > int y = src_y / vsub;
> > u32 offset;
> >
> > - if (plane_state->base.rotation & ~(DRM_MODE_ROTATE_0 |
> > DRM_MODE_ROTATE_180)) {
> > - DRM_DEBUG_KMS("RC support only with 0/180 degree
> > rotation %x\n",
> > - plane_state->base.rotation);
> > - return -EINVAL;
> > - }
> > -
> > intel_add_fb_offsets(&x, &y, plane_state, 1);
> > offset = intel_plane_compute_aligned_offset(&x, &y,
> > plane_state, 1);
> >
> > @@ -3178,12 +3172,6 @@ int skl_check_plane_surface(const struct
> > intel_crtc_state *crtc_state,
> > plane_state->color_plane[0].stride = intel_fb_pitch(fb, 0,
> > rotation);
> > plane_state->color_plane[1].stride = intel_fb_pitch(fb, 1,
> > rotation);
> >
> > - if (rotation & DRM_MODE_REFLECT_X &&
> > - fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> > - DRM_DEBUG_KMS("horizontal flip is not supported with
> > linear surface formats\n");
> > - return -EINVAL;
> > - }
> > -
> > if (!plane_state->base.visible)
> > return 0;
> >
> > diff --git a/drivers/gpu/drm/i915/intel_sprite.c
> > b/drivers/gpu/drm/i915/intel_sprite.c
> > index 36e150885897..041b8921f4fe 100644
> > --- a/drivers/gpu/drm/i915/intel_sprite.c
> > +++ b/drivers/gpu/drm/i915/intel_sprite.c
> > @@ -1156,6 +1156,68 @@ vlv_sprite_check(struct intel_crtc_state
> > *crtc_state,
> > return 0;
> > }
> >
> > +static int skl_plane_check_fb(const struct intel_crtc_state
> > *crtc_state,
> > + const struct intel_plane_state
> > *plane_state)
> > +{
> > + const struct drm_framebuffer *fb = plane_state->base.fb;
> > + unsigned int rotation = plane_state->base.rotation;
> > + struct drm_format_name_buf format_name;
> > +
> > + if (!fb)
> > + return 0;
> > +
> > + if (rotation & ~(DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180) &&
> > + (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS &&
> > + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> > + DRM_DEBUG_KMS("RC support only with 0/180 degree
> > rotation (%x)\n",
> > + rotation);
> > + return -EINVAL;
> > + }
> > +
> > + if (rotation & DRM_MODE_REFLECT_X &&
> > + fb->modifier == DRM_FORMAT_MOD_LINEAR) {
> > + DRM_DEBUG_KMS("horizontal flip is not supported with
> > linear surface formats\n");
> > + return -EINVAL;
> > + }
> > +
> > + if (drm_rotation_90_or_270(rotation)) {
> > + if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
> > + fb->modifier != I915_FORMAT_MOD_Yf_TILED) {
> > + DRM_DEBUG_KMS("Y/Yf tiling required for
> > 90/270!\n");
> > + return -EINVAL;
> > + }
> > +
> > + /*
> > + * 90/270 is not allowed with RGB64 16:16:16:16,
> > + * RGB 16-bit 5:6:5, and Indexed 8-bit.
> > + * TBD: Add RGB64 case once its added in supported
> > format list.
> > + */
> > + switch (fb->format->format) {
> > + case DRM_FORMAT_C8:
> > + case DRM_FORMAT_RGB565:
> > + DRM_DEBUG_KMS("Unsupported pixel format %s for
> > 90/270!\n",
> > + drm_get_format_name(fb->format-
> > >format,
> > + &format_name)
> > );
> > + return -EINVAL;
> > + default:
> > + break;
> > + }
> > + }
> > +
> > + /* Y-tiling is not supported in IF-ID Interlace mode */
> > + if (crtc_state->base.enable &&
> > + crtc_state->base.adjusted_mode.flags &
> > DRM_MODE_FLAG_INTERLACE &&
> > + (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
> > + fb->modifier == I915_FORMAT_MOD_Yf_TILED ||
>
> I guess this 2 checks bellow are new? It was not being handled in
> skl_check_ccs_aux_surface() or else where.
Right. The old code missed the compressed Y tiled cases. Should have
really split that change into a separate patch.
>
> Other than this everything else looks good.
>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > + fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS ||
> > + fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) {
> > + DRM_DEBUG_KMS("Y/Yf tiling not supported in IF-ID
> > mode\n");
> > + return -EINVAL;
> > + }
> > +
> > + return 0;
> > +}
> > +
> > int skl_plane_check(struct intel_crtc_state *crtc_state,
> > struct intel_plane_state *plane_state)
> > {
> > @@ -1164,6 +1226,10 @@ int skl_plane_check(struct intel_crtc_state
> > *crtc_state,
> > int max_scale, min_scale;
> > int ret;
> >
> > + ret = skl_plane_check_fb(crtc_state, plane_state);
> > + if (ret)
> > + return ret;
> > +
> > /* use scaler when colorkey is not required */
> > if (!plane_state->ckey.flags) {
> > const struct drm_framebuffer *fb = plane_state-
> > >base.fb;
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
* ✗ Fi.CI.IGT: failure for drm/i915: GTT remapping for display
2019-01-11 19:46 [PATCH v2 0/6] drm/i915: GTT remapping for display Ville Syrjala
@ 2019-01-12 2:57 ` Patchwork
0 siblings, 0 replies; 59+ messages in thread
From: Patchwork @ 2019-01-12 2:57 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: GTT remapping for display
URL : https://patchwork.freedesktop.org/series/55095/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_5405_full -> Patchwork_11285_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_11285_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_11285_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_11285_full:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@mock_vma:
- shard-iclb: PASS -> INCOMPLETE
Known issues
------------
Here are the changes found in Patchwork_11285_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_schedule@pi-ringfull-bsd:
- shard-skl: NOTRUN -> FAIL [fdo#103158] +1
* igt@gem_exec_schedule@pi-ringfull-vebox:
- shard-kbl: NOTRUN -> FAIL [fdo#103158] +4
* igt@i915_selftest@mock_vma:
- shard-hsw: PASS -> INCOMPLETE [fdo#103540]
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
- shard-glk: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
- shard-snb: PASS -> INCOMPLETE [fdo#105411]
* igt@i915_suspend@shrink:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#109244]
* igt@kms_available_modes_crc@available_mode_test_crc:
- shard-kbl: NOTRUN -> FAIL [fdo#106641]
* igt@kms_busy@extended-modeset-hang-newfb-render-a:
- shard-iclb: NOTRUN -> DMESG-WARN [fdo#107956]
* igt@kms_busy@extended-modeset-hang-newfb-with-reset-render-c:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#107956] +2
* igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-c:
- shard-kbl: NOTRUN -> DMESG-WARN [fdo#107956] +8
* igt@kms_chv_cursor_fail@pipe-a-256x256-bottom-edge:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] / [fdo#108336] +1
* igt@kms_chv_cursor_fail@pipe-c-128x128-top-edge:
- shard-skl: PASS -> FAIL [fdo#104671]
* igt@kms_color@pipe-c-ctm-blue-to-red:
- shard-skl: PASS -> FAIL [fdo#107201]
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> FAIL [fdo#108597] +1
* igt@kms_cursor_crc@cursor-128x128-onscreen:
- shard-kbl: NOTRUN -> FAIL [fdo#103232] +1
* igt@kms_cursor_crc@cursor-256x256-random:
- shard-iclb: NOTRUN -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-256x85-random:
- shard-apl: PASS -> FAIL [fdo#103232] +5
- shard-glk: PASS -> FAIL [fdo#103232]
* igt@kms_cursor_crc@cursor-64x64-suspend:
- shard-kbl: NOTRUN -> FAIL [fdo#103191] / [fdo#103232]
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-skl: NOTRUN -> FAIL [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
- shard-iclb: PASS -> FAIL [fdo#103167] +6
- shard-apl: PASS -> FAIL [fdo#103167] +3
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-move:
- shard-kbl: NOTRUN -> FAIL [fdo#103167]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-glk: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-shrfb-draw-mmap-cpu:
- shard-iclb: PASS -> DMESG-FAIL [fdo#107724] +2
* igt@kms_plane@pixel-format-pipe-b-planes:
- shard-skl: NOTRUN -> DMESG-WARN [fdo#106885] +2
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparant-fb:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] +8
* igt@kms_plane_alpha_blend@pipe-c-alpha-7efc:
- shard-kbl: NOTRUN -> FAIL [fdo#108145] / [fdo#108590] +5
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +2
* igt@kms_plane_multiple@atomic-pipe-a-tiling-yf:
- shard-glk: PASS -> FAIL [fdo#103166]
* igt@kms_plane_multiple@atomic-pipe-b-tiling-none:
- shard-apl: PASS -> FAIL [fdo#103166] +1
* igt@kms_plane_multiple@atomic-pipe-b-tiling-y:
- shard-iclb: PASS -> FAIL [fdo#103166] +4
* igt@kms_plane_multiple@atomic-pipe-c-tiling-x:
- shard-kbl: NOTRUN -> FAIL [fdo#103166] +1
* igt@kms_rmfb@close-fd:
- shard-iclb: PASS -> DMESG-WARN [fdo#107724] +13
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_sysfs_edid_timing:
- shard-kbl: NOTRUN -> FAIL [fdo#100047]
- shard-skl: NOTRUN -> FAIL [fdo#100047]
* igt@kms_vblank@pipe-b-ts-continuation-suspend:
- shard-hsw: PASS -> FAIL [fdo#104894]
* igt@pm_backlight@fade_with_dpms:
- shard-iclb: PASS -> INCOMPLETE [fdo#107820]
#### Possible fixes ####
* igt@gem_eio@in-flight-suspend:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS
* igt@kms_atomic_transition@plane-all-transition:
- shard-iclb: INCOMPLETE [fdo#109225] -> PASS
* igt@kms_color@pipe-b-ctm-max:
- shard-apl: FAIL [fdo#108147] -> PASS
* igt@kms_cursor_crc@cursor-64x21-onscreen:
- shard-apl: FAIL [fdo#103232] -> PASS +1
* igt@kms_flip_tiling@flip-x-tiled:
- shard-skl: FAIL [fdo#108145] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-wc:
- shard-glk: FAIL [fdo#103167] -> PASS +1
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-render:
- shard-apl: FAIL [fdo#103167] -> PASS +2
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-move:
- shard-iclb: FAIL [fdo#103167] -> PASS
* igt@kms_plane@plane-position-covered-pipe-c-planes:
- shard-apl: FAIL [fdo#103166] -> PASS +4
* igt@kms_plane_multiple@atomic-pipe-c-tiling-none:
- shard-iclb: FAIL [fdo#103166] -> PASS +1
* igt@kms_psr@suspend:
- shard-iclb: INCOMPLETE [fdo#107713] -> PASS
* igt@kms_rmfb@rmfb-ioctl:
- shard-iclb: DMESG-WARN [fdo#107724] -> PASS
* igt@kms_rotation_crc@multiplane-rotation-cropping-top:
- shard-glk: DMESG-WARN [fdo#105763] / [fdo#106538] -> PASS
* igt@pm_rpm@fences:
- shard-skl: INCOMPLETE [fdo#107807] -> PASS +2
* igt@pm_rpm@gem-execbuf-stress-extra-wait:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
#### Warnings ####
* igt@i915_suspend@shrink:
- shard-skl: INCOMPLETE [fdo#106886] -> DMESG-WARN [fdo#107886] / [fdo#109244]
- shard-glk: INCOMPLETE [fdo#103359] / [fdo#106886] / [k.org#198133] -> DMESG-WARN [fdo#109244]
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic:
- shard-iclb: FAIL [fdo#107725] -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> DMESG-FAIL [fdo#107724]
* igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-onoff:
- shard-iclb: FAIL [fdo#103167] -> DMESG-WARN [fdo#107724] / [fdo#108336]
* igt@pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-iclb: {SKIP} [fdo#109308] -> INCOMPLETE [fdo#108840]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103158]: https://bugs.freedesktop.org/show_bug.cgi?id=103158
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103232]: https://bugs.freedesktop.org/show_bug.cgi?id=103232
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103540]: https://bugs.freedesktop.org/show_bug.cgi?id=103540
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#104671]: https://bugs.freedesktop.org/show_bug.cgi?id=104671
[fdo#104894]: https://bugs.freedesktop.org/show_bug.cgi?id=104894
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105411]: https://bugs.freedesktop.org/show_bug.cgi?id=105411
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106538]: https://bugs.freedesktop.org/show_bug.cgi?id=106538
[fdo#106641]: https://bugs.freedesktop.org/show_bug.cgi?id=106641
[fdo#106885]: https://bugs.freedesktop.org/show_bug.cgi?id=106885
[fdo#106886]: https://bugs.freedesktop.org/show_bug.cgi?id=106886
[fdo#107201]: https://bugs.freedesktop.org/show_bug.cgi?id=107201
[fdo#107713]: https://bugs.freedesktop.org/show_bug.cgi?id=107713
[fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
[fdo#107725]: https://bugs.freedesktop.org/show_bug.cgi?id=107725
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#107820]: https://bugs.freedesktop.org/show_bug.cgi?id=107820
[fdo#107886]: https://bugs.freedesktop.org/show_bug.cgi?id=107886
[fdo#107956]: https://bugs.freedesktop.org/show_bug.cgi?id=107956
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108147]: https://bugs.freedesktop.org/show_bug.cgi?id=108147
[fdo#108336]: https://bugs.freedesktop.org/show_bug.cgi?id=108336
[fdo#108590]: https://bugs.freedesktop.org/show_bug.cgi?id=108590
[fdo#108597]: https://bugs.freedesktop.org/show_bug.cgi?id=108597
[fdo#108840]: https://bugs.freedesktop.org/show_bug.cgi?id=108840
[fdo#109225]: https://bugs.freedesktop.org/show_bug.cgi?id=109225
[fdo#109244]: https://bugs.freedesktop.org/show_bug.cgi?id=109244
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109281]: https://bugs.freedesktop.org/show_bug.cgi?id=109281
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109286]: https://bugs.freedesktop.org/show_bug.cgi?id=109286
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (6 -> 7)
------------------------------
Additional (1): shard-kbl
Build changes
-------------
* Linux: CI_DRM_5405 -> Patchwork_11285
CI_DRM_5405: 92073deda0323ec6b2dd4066dd253235a54afa74 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4763: 805a99409542d7d72dda3b6dcd284a8869a3de16 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_11285: 8de5d269d35a7b61cbcb16e99f2e5b83bea04917 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_11285/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 59+ messages in thread
end of thread, other threads:[~2019-01-12 2:57 UTC | newest]
Thread overview: 59+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-19 18:21 [PATCH 00/18] drm/i915: GTT remapping for display Ville Syrjala
2018-07-19 18:21 ` [PATCH 01/18] drm/i915: Fix glk/cnl display w/a #1175 Ville Syrjala
2018-07-20 10:55 ` Imre Deak
2018-07-19 18:21 ` [PATCH 02/18] drm/i915: s/tile_offset/aligned_offset/ Ville Syrjala
2018-08-22 21:55 ` Souza, Jose
2018-07-19 18:21 ` [PATCH 03/18] drm/i915: Add .max_stride() plane hook Ville Syrjala
2018-08-22 22:03 ` Souza, Jose
2018-08-22 22:19 ` Souza, Jose
2018-08-23 14:48 ` Ville Syrjälä
2018-08-23 14:52 ` Ville Syrjälä
2018-07-19 18:22 ` [PATCH 04/18] drm/i915: Use pipe A primary plane .max_stride() as the global stride limit Ville Syrjala
2018-08-22 22:22 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 05/18] drm/i915: Rename the plane_state->main/aux to plane_state->color_plane[] Ville Syrjala
2018-08-22 23:02 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 06/18] drm/i915: Store the final plane stride in plane_state Ville Syrjala
2018-07-20 11:06 ` [PATCH v2 " Ville Syrjala
2018-08-22 23:44 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 07/18] drm/i915: Store ggtt_view " Ville Syrjala
2018-08-24 20:13 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 08/18] drm/i915: s/int plane/int color_plane/ Ville Syrjala
2018-08-23 1:14 ` Rodrigo Vivi
2018-08-24 0:05 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 09/18] drm/i915: Nuke plane->can_scale/min_downscale Ville Syrjala
2018-08-24 0:32 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 10/18] drm/i915: Extract per-platform plane->check() functions Ville Syrjala
2018-08-24 1:01 ` Souza, Jose
2018-08-24 12:03 ` Ville Syrjälä
2018-07-19 18:22 ` [PATCH 11/18] drm/i915: Move skl plane fb related checks into a better place Ville Syrjala
2018-08-24 19:56 ` Souza, Jose
2018-08-27 11:48 ` Ville Syrjälä
2018-07-19 18:22 ` [PATCH 12/18] drm/i915: Move display w/a #1175 Ville Syrjala
2018-08-23 1:09 ` Rodrigo Vivi
2018-07-19 18:22 ` [PATCH 13/18] drm/i915: Move chv rotation checks to plane->check() Ville Syrjala
2018-08-24 20:04 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 14/18] drm/i915: Extract intel_cursor_check_surface() Ville Syrjala
2018-08-24 20:08 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 15/18] drm/i915: Add a new "remapped" gtt_view Ville Syrjala
2018-07-19 18:59 ` Chris Wilson
2018-07-19 19:33 ` Ville Syrjälä
2018-07-19 19:46 ` Chris Wilson
2018-07-19 19:55 ` Ville Syrjälä
2018-07-19 20:16 ` Ville Syrjälä
2018-07-19 20:25 ` Chris Wilson
2018-07-19 18:22 ` [PATCH 16/18] drm/i915: Overcome display engine stride limits via GTT remapping Ville Syrjala
2018-07-19 19:01 ` Chris Wilson
2018-07-19 19:20 ` Ville Syrjälä
2018-07-19 18:22 ` [PATCH 17/18] drm/i915: Bump gen4+ fb stride limit to 256KiB Ville Syrjala
2018-08-24 20:49 ` Souza, Jose
2018-07-19 18:22 ` [PATCH 18/18] drm/i915: Bump gen4+ fb size limits to 32kx32k Ville Syrjala
2018-08-24 20:49 ` Souza, Jose
2018-07-19 18:52 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display Patchwork
2018-07-19 19:00 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-19 19:15 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-20 0:02 ` ✗ Fi.CI.IGT: failure " Patchwork
2018-07-20 11:15 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: GTT remapping for display (rev2) Patchwork
2018-07-20 11:23 ` ✗ Fi.CI.SPARSE: " Patchwork
2018-07-20 11:37 ` ✓ Fi.CI.BAT: success " Patchwork
2018-07-21 14:16 ` ✓ Fi.CI.IGT: " Patchwork
2019-01-11 19:46 [PATCH v2 0/6] drm/i915: GTT remapping for display Ville Syrjala
2019-01-12 2:57 ` ✗ Fi.CI.IGT: failure for " Patchwork
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