* [PATCH 1/4] drm/amdgpu: clean up coding style a bit
@ 2018-07-23 15:14 Christian König
[not found] ` <20180723151441.46790-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2018-07-23 15:14 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
No need to bitcast a boolean and even if we should use "!!" instead.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index 258b6f73cbdf..e451a3f25beb 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -328,35 +328,35 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
case AMDGPU_HW_IP_GFX:
type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_gfx_rings; i++)
- ring_mask |= ((adev->gfx.gfx_ring[i].ready ? 1 : 0) << i);
+ ring_mask |= adev->gfx.gfx_ring[i].ready << i;
ib_start_alignment = 32;
ib_size_alignment = 32;
break;
case AMDGPU_HW_IP_COMPUTE:
type = AMD_IP_BLOCK_TYPE_GFX;
for (i = 0; i < adev->gfx.num_compute_rings; i++)
- ring_mask |= ((adev->gfx.compute_ring[i].ready ? 1 : 0) << i);
+ ring_mask |= adev->gfx.compute_ring[i].ready << i;
ib_start_alignment = 32;
ib_size_alignment = 32;
break;
case AMDGPU_HW_IP_DMA:
type = AMD_IP_BLOCK_TYPE_SDMA;
for (i = 0; i < adev->sdma.num_instances; i++)
- ring_mask |= ((adev->sdma.instance[i].ring.ready ? 1 : 0) << i);
+ ring_mask |= adev->sdma.instance[i].ring.ready << i;
ib_start_alignment = 256;
ib_size_alignment = 4;
break;
case AMDGPU_HW_IP_UVD:
type = AMD_IP_BLOCK_TYPE_UVD;
for (i = 0; i < adev->uvd.num_uvd_inst; i++)
- ring_mask |= ((adev->uvd.inst[i].ring.ready ? 1 : 0) << i);
+ ring_mask |= adev->uvd.inst[i].ring.ready << i;
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
case AMDGPU_HW_IP_VCE:
type = AMD_IP_BLOCK_TYPE_VCE;
for (i = 0; i < adev->vce.num_rings; i++)
- ring_mask |= ((adev->vce.ring[i].ready ? 1 : 0) << i);
+ ring_mask |= adev->vce.ring[i].ready << i;
ib_start_alignment = 4;
ib_size_alignment = 1;
break;
@@ -365,27 +365,27 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
for (i = 0; i < adev->uvd.num_uvd_inst; i++)
for (j = 0; j < adev->uvd.num_enc_rings; j++)
ring_mask |=
- ((adev->uvd.inst[i].ring_enc[j].ready ? 1 : 0) <<
- (j + i * adev->uvd.num_enc_rings));
+ adev->uvd.inst[i].ring_enc[j].ready <<
+ (j + i * adev->uvd.num_enc_rings);
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
case AMDGPU_HW_IP_VCN_DEC:
type = AMD_IP_BLOCK_TYPE_VCN;
- ring_mask = adev->vcn.ring_dec.ready ? 1 : 0;
+ ring_mask = adev->vcn.ring_dec.ready;
ib_start_alignment = 16;
ib_size_alignment = 16;
break;
case AMDGPU_HW_IP_VCN_ENC:
type = AMD_IP_BLOCK_TYPE_VCN;
for (i = 0; i < adev->vcn.num_enc_rings; i++)
- ring_mask |= ((adev->vcn.ring_enc[i].ready ? 1 : 0) << i);
+ ring_mask |= adev->vcn.ring_enc[i].ready << i;
ib_start_alignment = 64;
ib_size_alignment = 1;
break;
case AMDGPU_HW_IP_VCN_JPEG:
type = AMD_IP_BLOCK_TYPE_VCN;
- ring_mask = adev->vcn.ring_jpeg.ready ? 1 : 0;
+ ring_mask = adev->vcn.ring_jpeg.ready;
ib_start_alignment = 16;
ib_size_alignment = 16;
break;
--
2.14.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/4] drm/amdgpu: expose only the first UVD instance for now
[not found] ` <20180723151441.46790-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-07-23 15:14 ` Christian König
2018-07-23 15:14 ` [PATCH 3/4] drm/amdgpu: add support for inplace IB patching for MM engines Christian König
2018-07-23 15:14 ` [PATCH 4/4] drm/amdgpu: patch the IBs for the second UVD instance v2 Christian König
2 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2018-07-23 15:14 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Going to completely rework the context to ring mapping with Nayan's GSoC
work, but for now just stopping to expose the second UVD instance should
do it.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c | 13 +++++--------
drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c | 9 ++-------
2 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
index e451a3f25beb..75da3c41f3b3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_kms.c
@@ -286,7 +286,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
struct drm_crtc *crtc;
uint32_t ui32 = 0;
uint64_t ui64 = 0;
- int i, j, found;
+ int i, found;
int ui32_size = sizeof(ui32);
if (!info->return_size || !info->return_pointer)
@@ -348,8 +348,7 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
break;
case AMDGPU_HW_IP_UVD:
type = AMD_IP_BLOCK_TYPE_UVD;
- for (i = 0; i < adev->uvd.num_uvd_inst; i++)
- ring_mask |= adev->uvd.inst[i].ring.ready << i;
+ ring_mask |= adev->uvd.inst[0].ring.ready;
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
@@ -362,11 +361,9 @@ static int amdgpu_info_ioctl(struct drm_device *dev, void *data, struct drm_file
break;
case AMDGPU_HW_IP_UVD_ENC:
type = AMD_IP_BLOCK_TYPE_UVD;
- for (i = 0; i < adev->uvd.num_uvd_inst; i++)
- for (j = 0; j < adev->uvd.num_enc_rings; j++)
- ring_mask |=
- adev->uvd.inst[i].ring_enc[j].ready <<
- (j + i * adev->uvd.num_enc_rings);
+ for (i = 0; i < adev->uvd.num_enc_rings; i++)
+ ring_mask |=
+ adev->uvd.inst[0].ring_enc[i].ready << i;
ib_start_alignment = 64;
ib_size_alignment = 64;
break;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
index ea9850c9224d..d8357290ad09 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_queue_mgr.c
@@ -66,8 +66,6 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
u32 ring,
struct amdgpu_ring **out_ring)
{
- u32 instance;
-
switch (mapper->hw_ip) {
case AMDGPU_HW_IP_GFX:
*out_ring = &adev->gfx.gfx_ring[ring];
@@ -79,16 +77,13 @@ static int amdgpu_identity_map(struct amdgpu_device *adev,
*out_ring = &adev->sdma.instance[ring].ring;
break;
case AMDGPU_HW_IP_UVD:
- instance = ring;
- *out_ring = &adev->uvd.inst[instance].ring;
+ *out_ring = &adev->uvd.inst[0].ring;
break;
case AMDGPU_HW_IP_VCE:
*out_ring = &adev->vce.ring[ring];
break;
case AMDGPU_HW_IP_UVD_ENC:
- instance = ring / adev->uvd.num_enc_rings;
- *out_ring =
- &adev->uvd.inst[instance].ring_enc[ring%adev->uvd.num_enc_rings];
+ *out_ring = &adev->uvd.inst[0].ring_enc[ring];
break;
case AMDGPU_HW_IP_VCN_DEC:
*out_ring = &adev->vcn.ring_dec;
--
2.14.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 3/4] drm/amdgpu: add support for inplace IB patching for MM engines
[not found] ` <20180723151441.46790-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-07-23 15:14 ` [PATCH 2/4] drm/amdgpu: expose only the first UVD instance for now Christian König
@ 2018-07-23 15:14 ` Christian König
[not found] ` <20180723151441.46790-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-07-23 15:14 ` [PATCH 4/4] drm/amdgpu: patch the IBs for the second UVD instance v2 Christian König
2 siblings, 1 reply; 5+ messages in thread
From: Christian König @ 2018-07-23 15:14 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
We are going to need that for the second UVD instance on Vega20.
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 22 +++++++++++++++-------
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
3 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index a9f09daeffa3..73f2f8d987cc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -1751,6 +1751,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
#define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
#define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
#define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
+#define amdgpu_ring_patch_cs(r, p, ib) ((r)->funcs->patch_cs((p), (ib)))
#define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
#define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
#define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 7c5cc33d0cda..b7840e4bb958 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -916,7 +916,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
int r;
/* Only for UVD/VCE VM emulation */
- if (p->ring->funcs->parse_cs) {
+ if (p->ring->funcs->parse_cs || p->ring->funcs->patch_cs) {
unsigned i, j;
for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
@@ -957,12 +957,20 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
offset = m->start * AMDGPU_GPU_PAGE_SIZE;
kptr += va_start - offset;
- memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
- amdgpu_bo_kunmap(aobj);
-
- r = amdgpu_ring_parse_cs(ring, p, j);
- if (r)
- return r;
+ if (p->ring->funcs->parse_cs) {
+ memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
+ amdgpu_bo_kunmap(aobj);
+
+ r = amdgpu_ring_parse_cs(ring, p, j);
+ if (r)
+ return r;
+ } else {
+ ib->ptr = (uint32_t *)kptr;
+ r = amdgpu_ring_patch_cs(ring, p, j);
+ amdgpu_bo_kunmap(aobj);
+ if (r)
+ return r;
+ }
j++;
}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 5018c0b6bf1a..24c082381488 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -123,6 +123,7 @@ struct amdgpu_ring_funcs {
void (*set_wptr)(struct amdgpu_ring *ring);
/* validating and patching of IBs */
int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
+ int (*patch_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
/* constants to calculate how many DW are needed for an emit */
unsigned emit_frame_size;
unsigned emit_ib_size;
--
2.14.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 4/4] drm/amdgpu: patch the IBs for the second UVD instance v2
[not found] ` <20180723151441.46790-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-07-23 15:14 ` [PATCH 2/4] drm/amdgpu: expose only the first UVD instance for now Christian König
2018-07-23 15:14 ` [PATCH 3/4] drm/amdgpu: add support for inplace IB patching for MM engines Christian König
@ 2018-07-23 15:14 ` Christian König
2 siblings, 0 replies; 5+ messages in thread
From: Christian König @ 2018-07-23 15:14 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW
Patch the IBs for the second UVD instance so that userspace don't need
to care about the instance they submit to.
v2: use direct IB patching
Signed-off-by: Christian König <christian.koenig@amd.com>
---
drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index db5f3d78ab12..0895b80fcd37 100644
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1205,6 +1205,32 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
return r;
}
+/**
+ * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
+ *
+ * @ring: the engine to test on
+ *
+ */
+static int uvd_v7_0_ring_patch_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx)
+{
+ struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
+ unsigned i;
+
+ /* No patching necessary for the first instance */
+ if (!p->ring->me)
+ return 0;
+
+ for (i = 0; i < ib->length_dw; i += 2) {
+ uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
+
+ reg -= p->adev->reg_offset[UVD_HWIP][0][1];
+ reg += p->adev->reg_offset[UVD_HWIP][1][1];
+
+ amdgpu_set_ib_value(p, ib_idx, i, reg);
+ }
+ return 0;
+}
+
/**
* uvd_v7_0_ring_emit_ib - execute indirect buffer
*
@@ -1697,6 +1723,7 @@ static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
.get_rptr = uvd_v7_0_ring_get_rptr,
.get_wptr = uvd_v7_0_ring_get_wptr,
.set_wptr = uvd_v7_0_ring_set_wptr,
+ .patch_cs = uvd_v7_0_ring_patch_cs,
.emit_frame_size =
6 + /* hdp invalidate */
SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
--
2.14.1
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https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH 3/4] drm/amdgpu: add support for inplace IB patching for MM engines
[not found] ` <20180723151441.46790-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
@ 2018-07-23 15:52 ` Alex Deucher
0 siblings, 0 replies; 5+ messages in thread
From: Alex Deucher @ 2018-07-23 15:52 UTC (permalink / raw)
To: Christian König; +Cc: amd-gfx list
On Mon, Jul 23, 2018 at 11:14 AM, Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
> We are going to need that for the second UVD instance on Vega20.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
A couple of nits below. Patches 1, 2, 4 are:
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/amdgpu.h | 1 +
> drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 22 +++++++++++++++-------
> drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h | 1 +
> 3 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> index a9f09daeffa3..73f2f8d987cc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
> @@ -1751,6 +1751,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
> #define amdgpu_vm_write_pte(adev, ib, pe, value, count, incr) ((adev)->vm_manager.vm_pte_funcs->write_pte((ib), (pe), (value), (count), (incr)))
> #define amdgpu_vm_set_pte_pde(adev, ib, pe, addr, count, incr, flags) ((adev)->vm_manager.vm_pte_funcs->set_pte_pde((ib), (pe), (addr), (count), (incr), (flags)))
> #define amdgpu_ring_parse_cs(r, p, ib) ((r)->funcs->parse_cs((p), (ib)))
> +#define amdgpu_ring_patch_cs(r, p, ib) ((r)->funcs->patch_cs((p), (ib)))
> #define amdgpu_ring_test_ring(r) (r)->funcs->test_ring((r))
> #define amdgpu_ring_test_ib(r, t) (r)->funcs->test_ib((r), (t))
> #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 7c5cc33d0cda..b7840e4bb958 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -916,7 +916,7 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
> int r;
>
> /* Only for UVD/VCE VM emulation */
> - if (p->ring->funcs->parse_cs) {
> + if (p->ring->funcs->parse_cs || p->ring->funcs->patch_cs) {
> unsigned i, j;
>
> for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
> @@ -957,12 +957,20 @@ static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
> offset = m->start * AMDGPU_GPU_PAGE_SIZE;
> kptr += va_start - offset;
>
> - memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> - amdgpu_bo_kunmap(aobj);
> -
> - r = amdgpu_ring_parse_cs(ring, p, j);
> - if (r)
> - return r;
> + if (p->ring->funcs->parse_cs) {
> + memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> + amdgpu_bo_kunmap(aobj);
> +
> + r = amdgpu_ring_parse_cs(ring, p, j);
> + if (r)
> + return r;
> + } else {
Maybe make this if (p->ring->funcs->patch_cs) {? Not a big deal
either way. I doubt we'd every have both callbacks defined.
> + ib->ptr = (uint32_t *)kptr;
> + r = amdgpu_ring_patch_cs(ring, p, j);
> + amdgpu_bo_kunmap(aobj);
> + if (r)
> + return r;
> + }
>
> j++;
> }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> index 5018c0b6bf1a..24c082381488 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
> @@ -123,6 +123,7 @@ struct amdgpu_ring_funcs {
> void (*set_wptr)(struct amdgpu_ring *ring);
> /* validating and patching of IBs */
> int (*parse_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
> + int (*patch_cs)(struct amdgpu_cs_parser *p, uint32_t ib_idx);
Can we come up with a better name? parse_vm_cs() or
patch_in_place_cs() or something like that for consistency?
Alex
> /* constants to calculate how many DW are needed for an emit */
> unsigned emit_frame_size;
> unsigned emit_ib_size;
> --
> 2.14.1
>
> _______________________________________________
> amd-gfx mailing list
> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
_______________________________________________
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^ permalink raw reply [flat|nested] 5+ messages in thread
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2018-07-23 15:14 [PATCH 1/4] drm/amdgpu: clean up coding style a bit Christian König
[not found] ` <20180723151441.46790-1-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-07-23 15:14 ` [PATCH 2/4] drm/amdgpu: expose only the first UVD instance for now Christian König
2018-07-23 15:14 ` [PATCH 3/4] drm/amdgpu: add support for inplace IB patching for MM engines Christian König
[not found] ` <20180723151441.46790-3-christian.koenig-5C7GfCeVMHo@public.gmane.org>
2018-07-23 15:52 ` Alex Deucher
2018-07-23 15:14 ` [PATCH 4/4] drm/amdgpu: patch the IBs for the second UVD instance v2 Christian König
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