* [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines @ 2018-07-27 20:04 Paulo Zanoni 2018-07-27 20:04 ` [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL Paulo Zanoni ` (4 more replies) 0 siblings, 5 replies; 8+ messages in thread From: Paulo Zanoni @ 2018-07-27 20:04 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni From: Manasi Navare <manasi.d.navare@intel.com> The register value of Divider Ratio for high speed divider (hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the actual numerical value of the divider. So this patch implements separate divider value defines for that field. icl_mg_pll_find_divisors() can use these defines instead of magic register values. The new defines are going to be used in the next patch. v2 (from Paulo): * Rebase. * Make it look a little more like the rest of our code. Cc: James Ausmus <james.ausmus@intel.com> Suggested-by: James Ausmus <james.ausmus@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 ++++- drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++----- 2 files changed, 9 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 5530c470f30d..e04ac47d53db 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9452,8 +9452,11 @@ enum skl_power_gate { #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c index 7e5e6eb5dfe2..300c374fc721 100644 --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c @@ -2662,16 +2662,16 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, MISSING_CASE(div1); /* fall through */ case 2: - hsdiv = 0; + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2; break; case 3: - hsdiv = 1; + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3; break; case 5: - hsdiv = 2; + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5; break; case 7: - hsdiv = 3; + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7; break; } @@ -2685,7 +2685,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, state->mg_clktop2_hsclkctl = MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) | MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) | - MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) | + hsdiv | MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2); return true; -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni @ 2018-07-27 20:04 ` Paulo Zanoni 2018-08-13 22:19 ` Souza, Jose 2018-07-27 22:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Patchwork ` (3 subsequent siblings) 4 siblings, 1 reply; 8+ messages in thread From: Paulo Zanoni @ 2018-07-27 20:04 UTC (permalink / raw) To: intel-gfx; +Cc: Paulo Zanoni From: Manasi Navare <manasi.d.navare@intel.com> PLLs are the source clocks for the DDIs so in order to determine the ddi clock we need to check the PLL configuration. For MG PHy Ports (C - F), depending on whether it is a TBT PLL or MG PLL the link lock can be obtained from the the PLL divisors based on the specification. v2 (from Paulo): * Make the algorithm look more like what's in the spec, also document where we differ form the spec and why. * Make the code a little more consistent with our coding style. Cc: James Ausmus <james.ausmus@intel.com> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> --- drivers/gpu/drm/i915/i915_reg.h | 5 ++ drivers/gpu/drm/i915/intel_ddi.c | 81 +++++++++++++++++++++++++++++++- 2 files changed, 84 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e04ac47d53db..cd37e76d4d19 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -9458,6 +9458,7 @@ enum skl_power_gate { #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ _MG_CLKTOP2_HSCLKCTL_PORT1, \ @@ -9468,7 +9469,10 @@ enum skl_power_gate { #define _MG_PLL_DIV0_PORT3 0x16AA00 #define _MG_PLL_DIV0_PORT4 0x16BA00 #define MG_PLL_DIV0_FRACNEN_H (1 << 30) +#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fffff << 8) +#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) +#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV0_PORT1, \ _MG_PLL_DIV0_PORT2) @@ -9483,6 +9487,7 @@ enum skl_power_gate { #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) +#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, _MG_PLL_DIV1_PORT1, \ _MG_PLL_DIV1_PORT2) diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c index 0adc043529f2..a18d57046bcc 100644 --- a/drivers/gpu/drm/i915/intel_ddi.c +++ b/drivers/gpu/drm/i915/intel_ddi.c @@ -1427,6 +1427,81 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv, return dco_freq / (p0 * p1 * p2 * 5); } +static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, + enum port port) +{ + u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; + + switch (val) { + case DDI_CLK_SEL_NONE: + return 0; + case DDI_CLK_SEL_TBT_162: + return 162000; + case DDI_CLK_SEL_TBT_270: + return 270000; + case DDI_CLK_SEL_TBT_540: + return 540000; + case DDI_CLK_SEL_TBT_810: + return 810000; + default: + MISSING_CASE(val); + return 0; + } +} + +static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, + enum port port) +{ + u32 mg_pll_div0, mg_clktop_hsclkctl; + u32 m1, m2_int, m2_frac, div1, div2, refclk; + u64 tmp; + + refclk = dev_priv->cdclk.hw.ref; + + mg_pll_div0 = I915_READ(MG_PLL_DIV0(port)); + mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port)); + + m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK; + m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; + m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? + (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> + MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0; + + switch (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: + div1 = 2; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: + div1 = 3; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: + div1 = 5; + break; + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: + div1 = 7; + break; + default: + MISSING_CASE(mg_clktop_hsclkctl); + return 0; + } + + div2 = (mg_clktop_hsclkctl & MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; + /* div2 value of 0 is same as 1 means no div */ + if (div2 == 0) + div2 = 1; + + /* + * Adjust the original formula to delay the division by 2^22 in order to + * minimize possible rounding errors. + */ + tmp = (u64)m1 * m2_int * refclk + + (((u64)m1 * m2_frac * refclk) >> 22); + tmp = div_u64(tmp, 5 * div1 * div2); + + return tmp; +} + static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) { int dotclock; @@ -1467,8 +1542,10 @@ static void icl_ddi_clock_get(struct intel_encoder *encoder, link_clock = icl_calc_dp_combo_pll_link(dev_priv, pll_id); } else { - /* FIXME - Add for MG PLL */ - WARN(1, "MG PLL clock_get code not implemented yet\n"); + if (pll_id == DPLL_ID_ICL_TBTPLL) + link_clock = icl_calc_tbt_pll_link(dev_priv, port); + else + link_clock = icl_calc_mg_pll_link(dev_priv, port); } pipe_config->port_clock = link_clock; -- 2.17.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL 2018-07-27 20:04 ` [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL Paulo Zanoni @ 2018-08-13 22:19 ` Souza, Jose 2018-08-14 20:06 ` Souza, Jose 0 siblings, 1 reply; 8+ messages in thread From: Souza, Jose @ 2018-08-13 22:19 UTC (permalink / raw) To: intel-gfx, Zanoni, Paulo R On Fri, 2018-07-27 at 13:04 -0700, Paulo Zanoni wrote: > From: Manasi Navare <manasi.d.navare@intel.com> > > PLLs are the source clocks for the DDIs so in order to determine the > ddi clock we need to check the PLL configuration. > > For MG PHy Ports (C - F), depending on whether it is a TBT PLL or MG > PLL the link lock can be obtained from the the PLL divisors based on > the specification. > > v2 (from Paulo): > * Make the algorithm look more like what's in the spec, also > document > where we differ form the spec and why. > * Make the code a little more consistent with our coding style. > > Cc: James Ausmus <james.ausmus@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 ++ > drivers/gpu/drm/i915/intel_ddi.c | 81 > +++++++++++++++++++++++++++++++- > 2 files changed, 84 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index e04ac47d53db..cd37e76d4d19 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9458,6 +9458,7 @@ enum skl_power_gate { > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) > +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << > 8) > #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ > _MG_CLKTOP2_HSCLKCTL_PORT1 > , \ > @@ -9468,7 +9469,10 @@ enum skl_power_gate { > #define _MG_PLL_DIV0_PORT3 0x16AA00 > #define _MG_PLL_DIV0_PORT4 0x16BA00 > #define MG_PLL_DIV0_FRACNEN_H (1 << > 30) > +#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fff > ff << 8) > +#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 > #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << 8) > +#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff << 0) > #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) > #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, > _MG_PLL_DIV0_PORT1, \ > _MG_PLL_DIV0_PORT2) > @@ -9483,6 +9487,7 @@ enum skl_power_gate { > #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) > #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) > #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) > +#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << 0) > #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) > #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, > _MG_PLL_DIV1_PORT1, \ > _MG_PLL_DIV1_PORT2) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > b/drivers/gpu/drm/i915/intel_ddi.c > index 0adc043529f2..a18d57046bcc 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1427,6 +1427,81 @@ static int cnl_calc_wrpll_link(struct > drm_i915_private *dev_priv, > return dco_freq / (p0 * p1 * p2 * 5); > } > > +static int icl_calc_tbt_pll_link(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; > + > + switch (val) { > + case DDI_CLK_SEL_NONE: > + return 0; > + case DDI_CLK_SEL_TBT_162: > + return 162000; > + case DDI_CLK_SEL_TBT_270: > + return 270000; > + case DDI_CLK_SEL_TBT_540: > + return 540000; > + case DDI_CLK_SEL_TBT_810: > + return 810000; > + default: > + MISSING_CASE(val); > + return 0; > + } > +} > + > +static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, > + enum port port) > +{ > + u32 mg_pll_div0, mg_clktop_hsclkctl; > + u32 m1, m2_int, m2_frac, div1, div2, refclk; > + u64 tmp; > + > + refclk = dev_priv->cdclk.hw.ref; > + > + mg_pll_div0 = I915_READ(MG_PLL_DIV0(port)); > + mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port)); > + > + m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK; > + m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; > + m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? > + (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> > + MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0; > + > + switch (mg_clktop_hsclkctl & > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: > + div1 = 2; > + break; > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: > + div1 = 3; > + break; > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: > + div1 = 5; > + break; > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: > + div1 = 7; > + break; > + default: > + MISSING_CASE(mg_clktop_hsclkctl); > + return 0; > + } > + > + div2 = (mg_clktop_hsclkctl & > MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> > + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; > + /* div2 value of 0 is same as 1 means no div */ > + if (div2 == 0) > + div2 = 1; > + > + /* > + * Adjust the original formula to delay the division by 2^22 in > order to > + * minimize possible rounding errors. > + */ > + tmp = (u64)m1 * m2_int * refclk + > + (((u64)m1 * m2_frac * refclk) >> 22); In my calculations this is not the same as: M1 * M2 * refclk As M2 is = m2_int + (m2_frac/2^22) Other than that everything else looks good. > + tmp = div_u64(tmp, 5 * div1 * div2); > + > + return tmp; > +} > + > static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) > { > int dotclock; > @@ -1467,8 +1542,10 @@ static void icl_ddi_clock_get(struct > intel_encoder *encoder, > link_clock = > icl_calc_dp_combo_pll_link(dev_priv, > pll_id) > ; > } else { > - /* FIXME - Add for MG PLL */ > - WARN(1, "MG PLL clock_get code not implemented yet\n"); > + if (pll_id == DPLL_ID_ICL_TBTPLL) > + link_clock = icl_calc_tbt_pll_link(dev_priv, > port); > + else > + link_clock = icl_calc_mg_pll_link(dev_priv, > port); > } > > pipe_config->port_clock = link_clock; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL 2018-08-13 22:19 ` Souza, Jose @ 2018-08-14 20:06 ` Souza, Jose 0 siblings, 0 replies; 8+ messages in thread From: Souza, Jose @ 2018-08-14 20:06 UTC (permalink / raw) To: intel-gfx, Zanoni, Paulo R On Mon, 2018-08-13 at 22:19 +0000, Souza, Jose wrote: > On Fri, 2018-07-27 at 13:04 -0700, Paulo Zanoni wrote: > > From: Manasi Navare <manasi.d.navare@intel.com> > > > > PLLs are the source clocks for the DDIs so in order to determine > > the > > ddi clock we need to check the PLL configuration. > > > > For MG PHy Ports (C - F), depending on whether it is a TBT PLL or > > MG > > PLL the link lock can be obtained from the the PLL divisors based > > on > > the specification. > > > > v2 (from Paulo): > > * Make the algorithm look more like what's in the spec, also > > document > > where we differ form the spec and why. > > * Make the code a little more consistent with our coding style. > > > > Cc: James Ausmus <james.ausmus@intel.com> > > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > > --- > > drivers/gpu/drm/i915/i915_reg.h | 5 ++ > > drivers/gpu/drm/i915/intel_ddi.c | 81 > > +++++++++++++++++++++++++++++++- > > 2 files changed, 84 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > > b/drivers/gpu/drm/i915/i915_reg.h > > index e04ac47d53db..cd37e76d4d19 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -9458,6 +9458,7 @@ enum skl_power_gate { > > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << > > 12) > > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << > > 12) > > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << > > 8) > > +#define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT 8 > > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << > > 8) > > #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ > > _MG_CLKTOP2_HSCLKCTL_PORT1 > > , \ > > @@ -9468,7 +9469,10 @@ enum skl_power_gate { > > #define _MG_PLL_DIV0_PORT3 0x16AA00 > > #define _MG_PLL_DIV0_PORT4 0x16BA00 > > #define MG_PLL_DIV0_FRACNEN_H (1 << > > 30) > > +#define MG_PLL_DIV0_FBDIV_FRAC_MASK (0x3fff > > ff << 8) > > +#define MG_PLL_DIV0_FBDIV_FRAC_SHIFT 8 > > #define MG_PLL_DIV0_FBDIV_FRAC(x) ((x) << > > 8) > > +#define MG_PLL_DIV0_FBDIV_INT_MASK (0xff > > << 0) > > #define MG_PLL_DIV0_FBDIV_INT(x) ((x) << 0) > > #define MG_PLL_DIV0(port) _MMIO_PORT((port) - PORT_C, > > _MG_PLL_DIV0_PORT1, \ > > _MG_PLL_DIV0_PORT2) > > @@ -9483,6 +9487,7 @@ enum skl_power_gate { > > #define MG_PLL_DIV1_DITHER_DIV_4 (2 << 12) > > #define MG_PLL_DIV1_DITHER_DIV_8 (3 << 12) > > #define MG_PLL_DIV1_NDIVRATIO(x) ((x) << 4) > > +#define MG_PLL_DIV1_FBPREDIV_MASK (0xf << > > 0) > > #define MG_PLL_DIV1_FBPREDIV(x) ((x) << 0) > > #define MG_PLL_DIV1(port) _MMIO_PORT((port) - PORT_C, > > _MG_PLL_DIV1_PORT1, \ > > _MG_PLL_DIV1_PORT2) > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c > > b/drivers/gpu/drm/i915/intel_ddi.c > > index 0adc043529f2..a18d57046bcc 100644 > > --- a/drivers/gpu/drm/i915/intel_ddi.c > > +++ b/drivers/gpu/drm/i915/intel_ddi.c > > @@ -1427,6 +1427,81 @@ static int cnl_calc_wrpll_link(struct > > drm_i915_private *dev_priv, > > return dco_freq / (p0 * p1 * p2 * 5); > > } > > > > +static int icl_calc_tbt_pll_link(struct drm_i915_private > > *dev_priv, > > + enum port port) > > +{ > > + u32 val = I915_READ(DDI_CLK_SEL(port)) & DDI_CLK_SEL_MASK; > > + > > + switch (val) { > > + case DDI_CLK_SEL_NONE: > > + return 0; > > + case DDI_CLK_SEL_TBT_162: > > + return 162000; > > + case DDI_CLK_SEL_TBT_270: > > + return 270000; > > + case DDI_CLK_SEL_TBT_540: > > + return 540000; > > + case DDI_CLK_SEL_TBT_810: > > + return 810000; > > + default: > > + MISSING_CASE(val); > > + return 0; > > + } > > +} > > + > > +static int icl_calc_mg_pll_link(struct drm_i915_private *dev_priv, > > + enum port port) > > +{ > > + u32 mg_pll_div0, mg_clktop_hsclkctl; > > + u32 m1, m2_int, m2_frac, div1, div2, refclk; > > + u64 tmp; > > + > > + refclk = dev_priv->cdclk.hw.ref; > > + > > + mg_pll_div0 = I915_READ(MG_PLL_DIV0(port)); > > + mg_clktop_hsclkctl = I915_READ(MG_CLKTOP2_HSCLKCTL(port)); > > + > > + m1 = I915_READ(MG_PLL_DIV1(port)) & MG_PLL_DIV1_FBPREDIV_MASK; > > + m2_int = mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK; > > + m2_frac = (mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) ? > > + (mg_pll_div0 & MG_PLL_DIV0_FBDIV_FRAC_MASK) >> > > + MG_PLL_DIV0_FBDIV_FRAC_SHIFT : 0; > > + > > + switch (mg_clktop_hsclkctl & > > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) { > > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2: > > + div1 = 2; > > + break; > > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3: > > + div1 = 3; > > + break; > > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5: > > + div1 = 5; > > + break; > > + case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7: > > + div1 = 7; > > + break; > > + default: > > + MISSING_CASE(mg_clktop_hsclkctl); > > + return 0; > > + } > > + > > + div2 = (mg_clktop_hsclkctl & > > MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >> > > + MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT; > > + /* div2 value of 0 is same as 1 means no div */ > > + if (div2 == 0) > > + div2 = 1; > > + > > + /* > > + * Adjust the original formula to delay the division by 2^22 in > > order to > > + * minimize possible rounding errors. > > + */ > > + tmp = (u64)m1 * m2_int * refclk + > > + (((u64)m1 * m2_frac * refclk) >> 22); > > In my calculations this is not the same as: M1 * M2 * refclk > > As M2 is = m2_int + (m2_frac/2^22) > > Other than that everything else looks good. Please disconsider that, I did the calculations again and this new formula matches spec. Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > > > > + tmp = div_u64(tmp, 5 * div1 * div2); > > + > > + return tmp; > > +} > > + > > static void ddi_dotclock_get(struct intel_crtc_state *pipe_config) > > { > > int dotclock; > > @@ -1467,8 +1542,10 @@ static void icl_ddi_clock_get(struct > > intel_encoder *encoder, > > link_clock = > > icl_calc_dp_combo_pll_link(dev_priv, > > pll_id) > > ; > > } else { > > - /* FIXME - Add for MG PLL */ > > - WARN(1, "MG PLL clock_get code not implemented yet\n"); > > + if (pll_id == DPLL_ID_ICL_TBTPLL) > > + link_clock = icl_calc_tbt_pll_link(dev_priv, > > port); > > + else > > + link_clock = icl_calc_mg_pll_link(dev_priv, > > port); > > } > > > > pipe_config->port_clock = link_clock; > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni 2018-07-27 20:04 ` [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL Paulo Zanoni @ 2018-07-27 22:25 ` Patchwork 2018-07-28 1:29 ` ✓ Fi.CI.IGT: " Patchwork ` (2 subsequent siblings) 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2018-07-27 22:25 UTC (permalink / raw) To: Paulo Zanoni; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines URL : https://patchwork.freedesktop.org/series/47368/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4568 -> Patchwork_9798 = == Summary - SUCCESS == No regressions found. External URL: https://patchwork.freedesktop.org/api/1.0/series/47368/revisions/1/mbox/ == Known issues == Here are the changes found in Patchwork_9798 that come from known issues: === IGT changes === ==== Possible fixes ==== igt@drv_selftest@live_workarounds: fi-cfl-8700k: DMESG-FAIL (fdo#107292) -> PASS ==== Warnings ==== {igt@kms_psr@primary_page_flip}: fi-cnl-psr: DMESG-WARN (fdo#107372) -> DMESG-FAIL (fdo#107372) {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292 fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372 == Participating hosts (52 -> 46) == Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper == Build changes == * Linux: CI_DRM_4568 -> Patchwork_9798 CI_DRM_4568: f679d412a2fad0988a8e7335942fd9fb47d323b8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9798: ccc91452f663059fde0b9ecdaf8d70d38ac3bb4a @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == ccc91452f663 drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL 2775367376cc drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9798/issues.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni 2018-07-27 20:04 ` [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL Paulo Zanoni 2018-07-27 22:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Patchwork @ 2018-07-28 1:29 ` Patchwork 2018-07-28 5:13 ` [PATCH 1/2] " Rodrigo Vivi 2018-08-13 22:10 ` Souza, Jose 4 siblings, 0 replies; 8+ messages in thread From: Patchwork @ 2018-07-28 1:29 UTC (permalink / raw) To: Paulo Zanoni; +Cc: intel-gfx == Series Details == Series: series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines URL : https://patchwork.freedesktop.org/series/47368/ State : success == Summary == = CI Bug Log - changes from CI_DRM_4568_full -> Patchwork_9798_full = == Summary - SUCCESS == No regressions found. == Known issues == Here are the changes found in Patchwork_9798_full that come from known issues: === IGT changes === ==== Issues hit ==== igt@kms_flip@2x-plain-flip-fb-recreate-interruptible: shard-glk: PASS -> FAIL (fdo#100368) igt@kms_rotation_crc@sprite-rotation-180: shard-hsw: PASS -> FAIL (fdo#103925) ==== Possible fixes ==== igt@kms_flip@2x-flip-vs-expired-vblank-interruptible: shard-hsw: FAIL (fdo#102887) -> PASS igt@kms_flip@modeset-vs-vblank-race-interruptible: shard-glk: FAIL (fdo#103060) -> PASS shard-hsw: FAIL (fdo#103060) -> PASS igt@kms_flip@plain-flip-fb-recreate-interruptible: shard-hsw: FAIL (fdo#100368) -> PASS igt@kms_setmode@basic: shard-kbl: FAIL (fdo#99912) -> PASS fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368 fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887 fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060 fdo#103925 https://bugs.freedesktop.org/show_bug.cgi?id=103925 fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912 == Participating hosts (5 -> 5) == No changes in participating hosts == Build changes == * Linux: CI_DRM_4568 -> Patchwork_9798 CI_DRM_4568: f679d412a2fad0988a8e7335942fd9fb47d323b8 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_9798: ccc91452f663059fde0b9ecdaf8d70d38ac3bb4a @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9798/shards.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni ` (2 preceding siblings ...) 2018-07-28 1:29 ` ✓ Fi.CI.IGT: " Patchwork @ 2018-07-28 5:13 ` Rodrigo Vivi 2018-08-13 22:10 ` Souza, Jose 4 siblings, 0 replies; 8+ messages in thread From: Rodrigo Vivi @ 2018-07-28 5:13 UTC (permalink / raw) To: Paulo Zanoni; +Cc: intel-gfx On Fri, Jul 27, 2018 at 01:04:56PM -0700, Paulo Zanoni wrote: > From: Manasi Navare <manasi.d.navare@intel.com> > > The register value of Divider Ratio for high speed divider > (hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the > actual numerical value of the divider. So this patch implements > separate divider value defines for that field. > icl_mg_pll_find_divisors() can use these defines instead of magic > register values. > > The new defines are going to be used in the next patch. > > v2 (from Paulo): > * Rebase. > * Make it look a little more like the rest of our code. > > Cc: James Ausmus <james.ausmus@intel.com> > Suggested-by: James Ausmus <james.ausmus@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++----- > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index 5530c470f30d..e04ac47d53db 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9452,8 +9452,11 @@ enum skl_power_gate { > #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) > #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) > #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) > -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << 8) > #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 7e5e6eb5dfe2..300c374fc721 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2662,16 +2662,16 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, > MISSING_CASE(div1); > /* fall through */ > case 2: > - hsdiv = 0; > + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2; > break; > case 3: > - hsdiv = 1; > + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3; > break; > case 5: > - hsdiv = 2; > + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5; > break; > case 7: > - hsdiv = 3; > + hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7; > break; > } > > @@ -2685,7 +2685,7 @@ static bool icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc, > state->mg_clktop2_hsclkctl = > MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) | > MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) | > - MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) | > + hsdiv | > MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2); > > return true; > -- > 2.17.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni ` (3 preceding siblings ...) 2018-07-28 5:13 ` [PATCH 1/2] " Rodrigo Vivi @ 2018-08-13 22:10 ` Souza, Jose 4 siblings, 0 replies; 8+ messages in thread From: Souza, Jose @ 2018-08-13 22:10 UTC (permalink / raw) To: intel-gfx, Zanoni, Paulo R On Fri, 2018-07-27 at 13:04 -0700, Paulo Zanoni wrote: > From: Manasi Navare <manasi.d.navare@intel.com> > > The register value of Divider Ratio for high speed divider > (hsdiv_ratio) in MG_CLKTOP2_HSCLKCTL_PORT register is not same as the > actual numerical value of the divider. So this patch implements > separate divider value defines for that field. > icl_mg_pll_find_divisors() can use these defines instead of magic > register values. > > The new defines are going to be used in the next patch. > > v2 (from Paulo): > * Rebase. > * Make it look a little more like the rest of our code. > > Cc: James Ausmus <james.ausmus@intel.com> > Suggested-by: James Ausmus <james.ausmus@intel.com> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com> > --- > drivers/gpu/drm/i915/i915_reg.h | 5 ++++- > drivers/gpu/drm/i915/intel_dpll_mgr.c | 10 +++++----- > 2 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h > b/drivers/gpu/drm/i915/i915_reg.h > index 5530c470f30d..e04ac47d53db 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -9452,8 +9452,11 @@ enum skl_power_gate { > #define MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK (0x1 << 16) > #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(x) ((x) << 14) > #define MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK (0x3 << 14) > -#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(x) ((x) << 12) > #define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK (0x3 << > 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2 (0 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3 (1 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5 (2 << 12) > +#define MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7 (3 << 12) > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(x) ((x) << 8) > #define MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK (0xf << > 8) > #define MG_CLKTOP2_HSCLKCTL(port) _MMIO_PORT((port) - PORT_C, \ > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c > b/drivers/gpu/drm/i915/intel_dpll_mgr.c > index 7e5e6eb5dfe2..300c374fc721 100644 > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c > @@ -2662,16 +2662,16 @@ static bool icl_mg_pll_find_divisors(int > clock_khz, bool is_dp, bool use_ssc, > MISSING_CASE(div1); > /* fall through */ > case 2: > - hsdiv = 0; > + hsdiv = > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2; > break; > case 3: > - hsdiv = 1; > + hsdiv = > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3; > break; > case 5: > - hsdiv = 2; > + hsdiv = > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5; > break; > case 7: > - hsdiv = 3; > + hsdiv = > MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7; I hsdiv should have its type changed to u32 as it is now a bit field not a divider number, with that: Reviewed-by: José Roberto de Souza <jose.souza@intel.com> > break; > } > > @@ -2685,7 +2685,7 @@ static bool icl_mg_pll_find_divisors(int > clock_khz, bool is_dp, bool use_ssc, > state->mg_clktop2_hsclkctl = > MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tli > nedrv) | > MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(input > sel) | > - MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO(hsdiv) > | > + hsdiv | > MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2); > > return true; _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2018-08-14 20:07 UTC | newest] Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2018-07-27 20:04 [PATCH 1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Paulo Zanoni 2018-07-27 20:04 ` [PATCH 2/2] drm/i915/icl: Get DDI clock for ICL for MG PLL and TBT PLL Paulo Zanoni 2018-08-13 22:19 ` Souza, Jose 2018-08-14 20:06 ` Souza, Jose 2018-07-27 22:25 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Implement HSDIV_RATIO of MG_CLKTOP2_HSCLKCTL_PORT reg as separate divider value defines Patchwork 2018-07-28 1:29 ` ✓ Fi.CI.IGT: " Patchwork 2018-07-28 5:13 ` [PATCH 1/2] " Rodrigo Vivi 2018-08-13 22:10 ` Souza, Jose
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