* [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
@ 2018-07-27 23:36 José Roberto de Souza
2018-07-27 23:36 ` [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions José Roberto de Souza
` (4 more replies)
0 siblings, 5 replies; 11+ messages in thread
From: José Roberto de Souza @ 2018-07-27 23:36 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
When returning from low power states the CSR firmware was not being
loaded again in CNL and ICL.
Also taking the opportunity to share the load call for gen >= 9,
instead of calling it from each display_core_init() function.
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++---------
2 files changed, 10 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 18a45e7a3d7c..a42f0dfe19da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
- if (dev_priv->csr.dmc_payload &&
- (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
- gen9_enable_dc5(dev_priv);
+ if (dev_priv->csr.dmc_payload) {
+ intel_csr_load_program(dev_priv);
+ if (dev_priv->csr.allowed_dc_mask &
+ DC_STATE_EN_UPTO_DC5)
+ gen9_enable_dc5(dev_priv);
+ }
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
hsw_disable_pc8(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf89141b2281..8fdcffe023fe 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3561,6 +3552,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
/* For now, we need the power well to be always enabled. */
intel_display_set_init_power(dev_priv, true);
+
+ if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv->csr.dmc_payload)
+ intel_csr_load_program(dev_priv);
+
/* Disable power support if the user asked so. */
if (!i915_modparams.disable_power_well)
intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
--
2.18.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
@ 2018-07-27 23:36 ` José Roberto de Souza
2018-07-28 5:21 ` Rodrigo Vivi
2018-07-27 23:36 ` [PATCH 3/3] drm/i915: Keep overlay functions naming consistent José Roberto de Souza
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: José Roberto de Souza @ 2018-07-27 23:36 UTC (permalink / raw)
To: intel-gfx
It is not used anymore after 'drm/i915/cnl+: Reload CSR firmware when
coming back from low power state'.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++-----------
3 files changed, 10 insertions(+), 13 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index a42f0dfe19da..3aefaa6c9483 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2698,7 +2698,7 @@ static int intel_runtime_resume(struct device *kdev)
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
- bxt_display_core_init(dev_priv, true);
+ bxt_display_core_init(dev_priv);
if (dev_priv->csr.dmc_payload) {
intel_csr_load_program(dev_priv);
if (dev_priv->csr.allowed_dc_mask &
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 99a5f5be5b82..c96f3b7b3eda 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1950,7 +1950,7 @@ void intel_power_domains_fini(struct drm_i915_private *);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
-void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
+void bxt_display_core_init(struct drm_i915_private *dev_priv);
void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
const char *
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 8fdcffe023fe..d435476a6003 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3048,8 +3048,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
I915_WRITE(MBUS_ABOX_CTL, val);
}
-static void skl_display_core_init(struct drm_i915_private *dev_priv,
- bool resume)
+static void skl_display_core_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
@@ -3107,8 +3106,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
usleep_range(10, 30); /* 10 us delay per Bspec */
}
-void bxt_display_core_init(struct drm_i915_private *dev_priv,
- bool resume)
+void bxt_display_core_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
@@ -3233,7 +3231,7 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
}
-static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
+static void cnl_display_core_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
@@ -3313,8 +3311,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
I915_WRITE(CHICKEN_MISC_2, val);
}
-static void icl_display_core_init(struct drm_i915_private *dev_priv,
- bool resume)
+static void icl_display_core_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
struct i915_power_well *well;
@@ -3533,13 +3530,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
power_domains->initializing = true;
if (IS_ICELAKE(dev_priv)) {
- icl_display_core_init(dev_priv, resume);
+ icl_display_core_init(dev_priv);
} else if (IS_CANNONLAKE(dev_priv)) {
- cnl_display_core_init(dev_priv, resume);
+ cnl_display_core_init(dev_priv);
} else if (IS_GEN9_BC(dev_priv)) {
- skl_display_core_init(dev_priv, resume);
+ skl_display_core_init(dev_priv);
} else if (IS_GEN9_LP(dev_priv)) {
- bxt_display_core_init(dev_priv, resume);
+ bxt_display_core_init(dev_priv);
} else if (IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&power_domains->lock);
chv_phy_control_init(dev_priv);
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH 3/3] drm/i915: Keep overlay functions naming consistent
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
2018-07-27 23:36 ` [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions José Roberto de Souza
@ 2018-07-27 23:36 ` José Roberto de Souza
2018-07-28 5:22 ` Rodrigo Vivi
2018-07-28 0:19 ` [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states Souza, Jose
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: José Roberto de Souza @ 2018-07-27 23:36 UTC (permalink / raw)
To: intel-gfx
All other overlay functions(almost all other functions in i915) follow
intel_overlay_verb, so renaming the ones that do not match that.
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 2 +-
drivers/gpu/drm/i915/intel_display.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 4 ++--
drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
4 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 3aefaa6c9483..b0c062636801 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -687,7 +687,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
if (ret)
goto cleanup_modeset;
- intel_setup_overlay(dev_priv);
+ intel_overlay_setup(dev_priv);
if (INTEL_INFO(dev_priv)->num_pipes == 0)
return 0;
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 577b30dde45b..2c03fd82d36e 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -15998,7 +15998,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
drm_mode_config_cleanup(dev);
- intel_cleanup_overlay(dev_priv);
+ intel_overlay_cleanup(dev_priv);
intel_cleanup_gt_powersave(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index c96f3b7b3eda..59caed2e6273 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1863,8 +1863,8 @@ void intel_attach_aspect_ratio_property(struct drm_connector *connector);
/* intel_overlay.c */
-void intel_setup_overlay(struct drm_i915_private *dev_priv);
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
+void intel_overlay_setup(struct drm_i915_private *dev_priv);
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
int intel_overlay_switch_off(struct intel_overlay *overlay);
int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index c2f10d899329..a1daedefa0aa 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -1386,7 +1386,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
return ret;
}
-void intel_setup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_setup(struct drm_i915_private *dev_priv)
{
struct intel_overlay *overlay;
struct drm_i915_gem_object *reg_bo;
@@ -1475,7 +1475,7 @@ void intel_setup_overlay(struct drm_i915_private *dev_priv)
return;
}
-void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
+void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
{
if (!dev_priv->overlay)
return;
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
2018-07-27 23:36 ` [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions José Roberto de Souza
2018-07-27 23:36 ` [PATCH 3/3] drm/i915: Keep overlay functions naming consistent José Roberto de Souza
@ 2018-07-28 0:19 ` Souza, Jose
2018-07-28 0:26 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2018-07-28 5:19 ` [PATCH 1/3] " Rodrigo Vivi
4 siblings, 0 replies; 11+ messages in thread
From: Souza, Jose @ 2018-07-28 0:19 UTC (permalink / raw)
To: intel-gfx; +Cc: Zanoni, Paulo R
When returning from low power states the CSR firmware was not being
loaded again in CNL and ICL.
Also taking the opportunity to share the load call for gen >= 9,
instead of calling it from each display_core_init() function.
Changes from v1:
Calling intel_csr_load_program() right after display_core_init().
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
drivers/gpu/drm/i915/intel_runtime_pm.c | 12 +++---------
2 files changed, 9 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c
b/drivers/gpu/drm/i915/i915_drv.c
index 18a45e7a3d7c..a42f0dfe19da 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct device
*kdev)
if (IS_GEN9_LP(dev_priv)) {
bxt_disable_dc9(dev_priv);
bxt_display_core_init(dev_priv, true);
- if (dev_priv->csr.dmc_payload &&
- (dev_priv->csr.allowed_dc_mask &
DC_STATE_EN_UPTO_DC5))
- gen9_enable_dc5(dev_priv);
+ if (dev_priv->csr.dmc_payload) {
+ intel_csr_load_program(dev_priv);
+ if (dev_priv->csr.allowed_dc_mask &
+ DC_STATE_EN_UPTO_DC5)
+ gen9_enable_dc5(dev_priv);
+ }
} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
hsw_disable_pc8(dev_priv);
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
{
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
b/drivers/gpu/drm/i915/intel_runtime_pm.c
index cf89141b2281..ebc084d90136 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct
drm_i915_private *dev_priv,
skl_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct
drm_i915_private *dev_priv,
bxt_init_cdclk(dev_priv);
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct
drm_i915_private *dev_priv, bool resume
/* 6. Enable DBUF */
gen9_dbuf_enable(dev_priv);
-
- if (resume && dev_priv->csr.dmc_payload)
- intel_csr_load_program(dev_priv);
}
static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
@@ -3559,6 +3550,9 @@ void intel_power_domains_init_hw(struct
drm_i915_private *dev_priv, bool resume)
mutex_unlock(&power_domains->lock);
}
+ if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv-
>csr.dmc_payload)
+ intel_csr_load_program(dev_priv);
+
/* For now, we need the power well to be always enabled. */
intel_display_set_init_power(dev_priv, true);
/* Disable power support if the user asked so. */
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 11+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
` (2 preceding siblings ...)
2018-07-28 0:19 ` [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states Souza, Jose
@ 2018-07-28 0:26 ` Patchwork
2018-07-28 5:19 ` [PATCH 1/3] " Rodrigo Vivi
4 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2018-07-28 0:26 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
URL : https://patchwork.freedesktop.org/series/47376/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4570 -> Patchwork_9800 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/47376/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9800 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-wf_vblank:
fi-glk-dsi: PASS -> FAIL (fdo#100368)
==== Possible fixes ====
igt@drv_selftest@live_workarounds:
{fi-bsw-kefka}: DMESG-FAIL (fdo#107292) -> PASS
==== Warnings ====
igt@drv_selftest@live_workarounds:
fi-cnl-psr: DMESG-WARN (fdo#105395) -> DMESG-FAIL (fdo#107292)
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL (fdo#107372) -> DMESG-WARN (fdo#107372)
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105395 https://bugs.freedesktop.org/show_bug.cgi?id=105395
fdo#107292 https://bugs.freedesktop.org/show_bug.cgi?id=107292
fdo#107372 https://bugs.freedesktop.org/show_bug.cgi?id=107372
== Participating hosts (52 -> 46) ==
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper
== Build changes ==
* Linux: CI_DRM_4570 -> Patchwork_9800
CI_DRM_4570: 747b2062e7a35c80e26653fcdfc90cde6e85e9bb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4580: f1c868dae24056ebc27e4f3c197724ce9b956a8a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9800: 74e343a50636246847d0ace08dfff87fe8811efd @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
74e343a50636 drm/i915: Keep overlay functions naming consistent
ad8a27d7cba1 drm/i915: Remove resume parameter from display_core_init functions
b4731c21fc76 drm/i915/cnl+: Reload CSR firmware when coming back from low power states
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9800/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
` (3 preceding siblings ...)
2018-07-28 0:26 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
@ 2018-07-28 5:19 ` Rodrigo Vivi
2018-07-28 8:40 ` Imre Deak
4 siblings, 1 reply; 11+ messages in thread
From: Rodrigo Vivi @ 2018-07-28 5:19 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx, Paulo Zanoni
On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza wrote:
> When returning from low power states the CSR firmware was not being
> loaded again in CNL and ICL.
> Also taking the opportunity to share the load call for gen >= 9,
> instead of calling it from each display_core_init() function.
>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Cc: Imre Deak <imre.deak@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
> drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++---------
> 2 files changed, 10 insertions(+), 12 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 18a45e7a3d7c..a42f0dfe19da 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct device *kdev)
> if (IS_GEN9_LP(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> bxt_display_core_init(dev_priv, true);
> - if (dev_priv->csr.dmc_payload &&
> - (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> - gen9_enable_dc5(dev_priv);
> + if (dev_priv->csr.dmc_payload) {
> + intel_csr_load_program(dev_priv);
> + if (dev_priv->csr.allowed_dc_mask &
> + DC_STATE_EN_UPTO_DC5)
> + gen9_enable_dc5(dev_priv);
> + }
> } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> hsw_disable_pc8(dev_priv);
> } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index cf89141b2281..8fdcffe023fe 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> skl_init_cdclk(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
> -
> - if (resume && dev_priv->csr.dmc_payload)
> - intel_csr_load_program(dev_priv);
and resume becomes unsed, so please kill it.
> }
>
> static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> @@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> bxt_init_cdclk(dev_priv);
>
> gen9_dbuf_enable(dev_priv);
> -
> - if (resume && dev_priv->csr.dmc_payload)
> - intel_csr_load_program(dev_priv);
same
> }
>
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> @@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
>
> /* 6. Enable DBUF */
> gen9_dbuf_enable(dev_priv);
> -
> - if (resume && dev_priv->csr.dmc_payload)
> - intel_csr_load_program(dev_priv);
same
> }
>
> static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> @@ -3561,6 +3552,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
>
> /* For now, we need the power well to be always enabled. */
> intel_display_set_init_power(dev_priv, true);
> +
> + if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv->csr.dmc_payload)
> + intel_csr_load_program(dev_priv);
> +
> /* Disable power support if the user asked so. */
> if (!i915_modparams.disable_power_well)
> intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions
2018-07-27 23:36 ` [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions José Roberto de Souza
@ 2018-07-28 5:21 ` Rodrigo Vivi
0 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2018-07-28 5:21 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Jul 27, 2018 at 04:36:25PM -0700, José Roberto de Souza wrote:
> It is not used anymore after 'drm/i915/cnl+: Reload CSR firmware when
> coming back from low power state'.
Oh! I saw now...
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 19 ++++++++-----------
> 3 files changed, 10 insertions(+), 13 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index a42f0dfe19da..3aefaa6c9483 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -2698,7 +2698,7 @@ static int intel_runtime_resume(struct device *kdev)
>
> if (IS_GEN9_LP(dev_priv)) {
> bxt_disable_dc9(dev_priv);
> - bxt_display_core_init(dev_priv, true);
> + bxt_display_core_init(dev_priv);
> if (dev_priv->csr.dmc_payload) {
> intel_csr_load_program(dev_priv);
> if (dev_priv->csr.allowed_dc_mask &
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index 99a5f5be5b82..c96f3b7b3eda 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1950,7 +1950,7 @@ void intel_power_domains_fini(struct drm_i915_private *);
> void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
> void intel_power_domains_suspend(struct drm_i915_private *dev_priv);
> void intel_power_domains_verify_state(struct drm_i915_private *dev_priv);
> -void bxt_display_core_init(struct drm_i915_private *dev_priv, bool resume);
> +void bxt_display_core_init(struct drm_i915_private *dev_priv);
> void bxt_display_core_uninit(struct drm_i915_private *dev_priv);
> void intel_runtime_pm_enable(struct drm_i915_private *dev_priv);
> const char *
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 8fdcffe023fe..d435476a6003 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -3048,8 +3048,7 @@ static void icl_mbus_init(struct drm_i915_private *dev_priv)
> I915_WRITE(MBUS_ABOX_CTL, val);
> }
>
> -static void skl_display_core_init(struct drm_i915_private *dev_priv,
> - bool resume)
> +static void skl_display_core_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> @@ -3107,8 +3106,7 @@ static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> usleep_range(10, 30); /* 10 us delay per Bspec */
> }
>
> -void bxt_display_core_init(struct drm_i915_private *dev_priv,
> - bool resume)
> +void bxt_display_core_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> @@ -3233,7 +3231,7 @@ static void cnl_set_procmon_ref_values(struct drm_i915_private *dev_priv,
> I915_WRITE(ICL_PORT_COMP_DW10(port), procmon->dw10);
> }
>
> -static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume)
> +static void cnl_display_core_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> @@ -3313,8 +3311,7 @@ static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> I915_WRITE(CHICKEN_MISC_2, val);
> }
>
> -static void icl_display_core_init(struct drm_i915_private *dev_priv,
> - bool resume)
> +static void icl_display_core_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv->power_domains;
> struct i915_power_well *well;
> @@ -3533,13 +3530,13 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> power_domains->initializing = true;
>
> if (IS_ICELAKE(dev_priv)) {
> - icl_display_core_init(dev_priv, resume);
> + icl_display_core_init(dev_priv);
> } else if (IS_CANNONLAKE(dev_priv)) {
> - cnl_display_core_init(dev_priv, resume);
> + cnl_display_core_init(dev_priv);
> } else if (IS_GEN9_BC(dev_priv)) {
> - skl_display_core_init(dev_priv, resume);
> + skl_display_core_init(dev_priv);
> } else if (IS_GEN9_LP(dev_priv)) {
> - bxt_display_core_init(dev_priv, resume);
> + bxt_display_core_init(dev_priv);
> } else if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&power_domains->lock);
> chv_phy_control_init(dev_priv);
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 3/3] drm/i915: Keep overlay functions naming consistent
2018-07-27 23:36 ` [PATCH 3/3] drm/i915: Keep overlay functions naming consistent José Roberto de Souza
@ 2018-07-28 5:22 ` Rodrigo Vivi
0 siblings, 0 replies; 11+ messages in thread
From: Rodrigo Vivi @ 2018-07-28 5:22 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: intel-gfx
On Fri, Jul 27, 2018 at 04:36:26PM -0700, José Roberto de Souza wrote:
> All other overlay functions(almost all other functions in i915) follow
> intel_overlay_verb, so renaming the ones that do not match that.
>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 2 +-
> drivers/gpu/drm/i915/intel_display.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 4 ++--
> drivers/gpu/drm/i915/intel_overlay.c | 4 ++--
> 4 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 3aefaa6c9483..b0c062636801 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -687,7 +687,7 @@ static int i915_load_modeset_init(struct drm_device *dev)
> if (ret)
> goto cleanup_modeset;
>
> - intel_setup_overlay(dev_priv);
> + intel_overlay_setup(dev_priv);
>
> if (INTEL_INFO(dev_priv)->num_pipes == 0)
> return 0;
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 577b30dde45b..2c03fd82d36e 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -15998,7 +15998,7 @@ void intel_modeset_cleanup(struct drm_device *dev)
>
> drm_mode_config_cleanup(dev);
>
> - intel_cleanup_overlay(dev_priv);
> + intel_overlay_cleanup(dev_priv);
>
> intel_cleanup_gt_powersave(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index c96f3b7b3eda..59caed2e6273 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1863,8 +1863,8 @@ void intel_attach_aspect_ratio_property(struct drm_connector *connector);
>
>
> /* intel_overlay.c */
> -void intel_setup_overlay(struct drm_i915_private *dev_priv);
> -void intel_cleanup_overlay(struct drm_i915_private *dev_priv);
> +void intel_overlay_setup(struct drm_i915_private *dev_priv);
> +void intel_overlay_cleanup(struct drm_i915_private *dev_priv);
> int intel_overlay_switch_off(struct intel_overlay *overlay);
> int intel_overlay_put_image_ioctl(struct drm_device *dev, void *data,
> struct drm_file *file_priv);
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index c2f10d899329..a1daedefa0aa 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -1386,7 +1386,7 @@ int intel_overlay_attrs_ioctl(struct drm_device *dev, void *data,
> return ret;
> }
>
> -void intel_setup_overlay(struct drm_i915_private *dev_priv)
> +void intel_overlay_setup(struct drm_i915_private *dev_priv)
> {
> struct intel_overlay *overlay;
> struct drm_i915_gem_object *reg_bo;
> @@ -1475,7 +1475,7 @@ void intel_setup_overlay(struct drm_i915_private *dev_priv)
> return;
> }
>
> -void intel_cleanup_overlay(struct drm_i915_private *dev_priv)
> +void intel_overlay_cleanup(struct drm_i915_private *dev_priv)
> {
> if (!dev_priv->overlay)
> return;
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-28 5:19 ` [PATCH 1/3] " Rodrigo Vivi
@ 2018-07-28 8:40 ` Imre Deak
2018-07-30 17:23 ` Souza, Jose
0 siblings, 1 reply; 11+ messages in thread
From: Imre Deak @ 2018-07-28 8:40 UTC (permalink / raw)
To: Rodrigo Vivi; +Cc: intel-gfx, Paulo Zanoni
On Fri, Jul 27, 2018 at 10:19:42PM -0700, Rodrigo Vivi wrote:
> On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza wrote:
> > When returning from low power states the CSR firmware was not being
> > loaded again in CNL and ICL.
Which power states are you referring to? We should already restore the
firmware from all relevant states in i915_drm_resume_early(). The patch
to load the firmware on ICL is not yet merged to drm-tip.
> > Also taking the opportunity to share the load call for gen >= 9,
> > instead of calling it from each display_core_init() function.
> >
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>
> Cc: Imre Deak <imre.deak@intel.com>
>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > ---
> > drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
> > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++---------
> > 2 files changed, 10 insertions(+), 12 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 18a45e7a3d7c..a42f0dfe19da 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct device *kdev)
> > if (IS_GEN9_LP(dev_priv)) {
> > bxt_disable_dc9(dev_priv);
> > bxt_display_core_init(dev_priv, true);
> > - if (dev_priv->csr.dmc_payload &&
> > - (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5))
> > - gen9_enable_dc5(dev_priv);
> > + if (dev_priv->csr.dmc_payload) {
> > + intel_csr_load_program(dev_priv);
> > + if (dev_priv->csr.allowed_dc_mask &
> > + DC_STATE_EN_UPTO_DC5)
> > + gen9_enable_dc5(dev_priv);
> > + }
> > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > hsw_disable_pc8(dev_priv);
> > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > index cf89141b2281..8fdcffe023fe 100644
> > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > @@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct drm_i915_private *dev_priv,
> > skl_init_cdclk(dev_priv);
> >
> > gen9_dbuf_enable(dev_priv);
> > -
> > - if (resume && dev_priv->csr.dmc_payload)
> > - intel_csr_load_program(dev_priv);
>
> and resume becomes unsed, so please kill it.
>
> > }
> >
> > static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
> > @@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct drm_i915_private *dev_priv,
> > bxt_init_cdclk(dev_priv);
> >
> > gen9_dbuf_enable(dev_priv);
> > -
> > - if (resume && dev_priv->csr.dmc_payload)
> > - intel_csr_load_program(dev_priv);
>
> same
>
> > }
> >
> > void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> > @@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct drm_i915_private *dev_priv, bool resume
> >
> > /* 6. Enable DBUF */
> > gen9_dbuf_enable(dev_priv);
> > -
> > - if (resume && dev_priv->csr.dmc_payload)
> > - intel_csr_load_program(dev_priv);
>
> same
>
> > }
> >
> > static void cnl_display_core_uninit(struct drm_i915_private *dev_priv)
> > @@ -3561,6 +3552,10 @@ void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
> >
> > /* For now, we need the power well to be always enabled. */
> > intel_display_set_init_power(dev_priv, true);
> > +
> > + if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv->csr.dmc_payload)
> > + intel_csr_load_program(dev_priv);
> > +
> > /* Disable power support if the user asked so. */
> > if (!i915_modparams.disable_power_well)
> > intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> > --
> > 2.18.0
> >
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-28 8:40 ` Imre Deak
@ 2018-07-30 17:23 ` Souza, Jose
2018-07-30 18:44 ` Imre Deak
0 siblings, 1 reply; 11+ messages in thread
From: Souza, Jose @ 2018-07-30 17:23 UTC (permalink / raw)
To: Vivi, Rodrigo, Deak, Imre; +Cc: intel-gfx, Zanoni, Paulo R
On Sat, 2018-07-28 at 11:40 +0300, Imre Deak wrote:
> On Fri, Jul 27, 2018 at 10:19:42PM -0700, Rodrigo Vivi wrote:
> > On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza
> > wrote:
> > > When returning from low power states the CSR firmware was not
> > > being
> > > loaded again in CNL and ICL.
>
> Which power states are you referring to? We should already restore
> the
> firmware from all relevant states in i915_drm_resume_early(). The
> patch
> to load the firmware on ICL is not yet merged to drm-tip.
Exactly this one, i915_drm_resume_early() calls
intel_power_domains_init_hw().
Yes it is still not loading becasue the firmware name is missing for
ICL but everything else is there.
>
> > > Also taking the opportunity to share the load call for gen >= 9,
> > > instead of calling it from each display_core_init() function.
> > >
> > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> >
> > Cc: Imre Deak <imre.deak@intel.com>
> >
> > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
> > > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++---------
> > > 2 files changed, 10 insertions(+), 12 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > b/drivers/gpu/drm/i915/i915_drv.c
> > > index 18a45e7a3d7c..a42f0dfe19da 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > @@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct
> > > device *kdev)
> > > if (IS_GEN9_LP(dev_priv)) {
> > > bxt_disable_dc9(dev_priv);
> > > bxt_display_core_init(dev_priv, true);
> > > - if (dev_priv->csr.dmc_payload &&
> > > - (dev_priv->csr.allowed_dc_mask &
> > > DC_STATE_EN_UPTO_DC5))
> > > - gen9_enable_dc5(dev_priv);
> > > + if (dev_priv->csr.dmc_payload) {
> > > + intel_csr_load_program(dev_priv);
> > > + if (dev_priv->csr.allowed_dc_mask &
> > > + DC_STATE_EN_UPTO_DC5)
> > > + gen9_enable_dc5(dev_priv);
> > > + }
> > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > hsw_disable_pc8(dev_priv);
> > > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > {
> > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > index cf89141b2281..8fdcffe023fe 100644
> > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > @@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct
> > > drm_i915_private *dev_priv,
> > > skl_init_cdclk(dev_priv);
> > >
> > > gen9_dbuf_enable(dev_priv);
> > > -
> > > - if (resume && dev_priv->csr.dmc_payload)
> > > - intel_csr_load_program(dev_priv);
> >
> > and resume becomes unsed, so please kill it.
> >
> > > }
> > >
> > > static void skl_display_core_uninit(struct drm_i915_private
> > > *dev_priv)
> > > @@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct
> > > drm_i915_private *dev_priv,
> > > bxt_init_cdclk(dev_priv);
> > >
> > > gen9_dbuf_enable(dev_priv);
> > > -
> > > - if (resume && dev_priv->csr.dmc_payload)
> > > - intel_csr_load_program(dev_priv);
> >
> > same
> >
> > > }
> > >
> > > void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> > > @@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct
> > > drm_i915_private *dev_priv, bool resume
> > >
> > > /* 6. Enable DBUF */
> > > gen9_dbuf_enable(dev_priv);
> > > -
> > > - if (resume && dev_priv->csr.dmc_payload)
> > > - intel_csr_load_program(dev_priv);
> >
> > same
> >
> > > }
> > >
> > > static void cnl_display_core_uninit(struct drm_i915_private
> > > *dev_priv)
> > > @@ -3561,6 +3552,10 @@ void intel_power_domains_init_hw(struct
> > > drm_i915_private *dev_priv, bool resume)
> > >
> > > /* For now, we need the power well to be always enabled. */
> > > intel_display_set_init_power(dev_priv, true);
> > > +
> > > + if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv-
> > > >csr.dmc_payload)
> > > + intel_csr_load_program(dev_priv);
> > > +
> > > /* Disable power support if the user asked so. */
> > > if (!i915_modparams.disable_power_well)
> > > intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> > > --
> > > 2.18.0
> > >
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states
2018-07-30 17:23 ` Souza, Jose
@ 2018-07-30 18:44 ` Imre Deak
0 siblings, 0 replies; 11+ messages in thread
From: Imre Deak @ 2018-07-30 18:44 UTC (permalink / raw)
To: Souza, Jose; +Cc: intel-gfx, Zanoni, Paulo R, Vivi, Rodrigo
On Mon, Jul 30, 2018 at 08:23:08PM +0300, Souza, Jose wrote:
> On Sat, 2018-07-28 at 11:40 +0300, Imre Deak wrote:
> > On Fri, Jul 27, 2018 at 10:19:42PM -0700, Rodrigo Vivi wrote:
> > > On Fri, Jul 27, 2018 at 04:36:24PM -0700, José Roberto de Souza
> > > wrote:
> > > > When returning from low power states the CSR firmware was not
> > > > being
> > > > loaded again in CNL and ICL.
> >
> > Which power states are you referring to? We should already restore
> > the
> > firmware from all relevant states in i915_drm_resume_early(). The
> > patch
> > to load the firmware on ICL is not yet merged to drm-tip.
>
> Exactly this one, i915_drm_resume_early() calls
> intel_power_domains_init_hw().
> Yes it is still not loading becasue the firmware name is missing for
> ICL but everything else is there.
I still don't understand how this fixes things. CNL already reloads the
firmware via i915_drm_resume_early() -> cnl_display_core_init(). On
ICL the same will happen once support for loading the firmware is added.
That same patch should also add the call to intel_csr_load_program() from
icl_display_core_init().
I would prefer to keep the call to intel_csr_load_program() in
*_display_core_init() functions to keep the runtime and system suspend
paths similar.
>
> >
> > > > Also taking the opportunity to share the load call for gen >= 9,
> > > > instead of calling it from each display_core_init() function.
> > > >
> > > > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > > > Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> > >
> > > Cc: Imre Deak <imre.deak@intel.com>
> > >
> > > > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/i915_drv.c | 9 ++++++---
> > > > drivers/gpu/drm/i915/intel_runtime_pm.c | 13 ++++---------
> > > > 2 files changed, 10 insertions(+), 12 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.c
> > > > b/drivers/gpu/drm/i915/i915_drv.c
> > > > index 18a45e7a3d7c..a42f0dfe19da 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.c
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > > > @@ -2699,9 +2699,12 @@ static int intel_runtime_resume(struct
> > > > device *kdev)
> > > > if (IS_GEN9_LP(dev_priv)) {
> > > > bxt_disable_dc9(dev_priv);
> > > > bxt_display_core_init(dev_priv, true);
> > > > - if (dev_priv->csr.dmc_payload &&
> > > > - (dev_priv->csr.allowed_dc_mask &
> > > > DC_STATE_EN_UPTO_DC5))
> > > > - gen9_enable_dc5(dev_priv);
> > > > + if (dev_priv->csr.dmc_payload) {
> > > > + intel_csr_load_program(dev_priv);
> > > > + if (dev_priv->csr.allowed_dc_mask &
> > > > + DC_STATE_EN_UPTO_DC5)
> > > > + gen9_enable_dc5(dev_priv);
> > > > + }
> > > > } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
> > > > hsw_disable_pc8(dev_priv);
> > > > } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > > {
> > > > diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > index cf89141b2281..8fdcffe023fe 100644
> > > > --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> > > > @@ -3075,9 +3075,6 @@ static void skl_display_core_init(struct
> > > > drm_i915_private *dev_priv,
> > > > skl_init_cdclk(dev_priv);
> > > >
> > > > gen9_dbuf_enable(dev_priv);
> > > > -
> > > > - if (resume && dev_priv->csr.dmc_payload)
> > > > - intel_csr_load_program(dev_priv);
> > >
> > > and resume becomes unsed, so please kill it.
> > >
> > > > }
> > > >
> > > > static void skl_display_core_uninit(struct drm_i915_private
> > > > *dev_priv)
> > > > @@ -3140,9 +3137,6 @@ void bxt_display_core_init(struct
> > > > drm_i915_private *dev_priv,
> > > > bxt_init_cdclk(dev_priv);
> > > >
> > > > gen9_dbuf_enable(dev_priv);
> > > > -
> > > > - if (resume && dev_priv->csr.dmc_payload)
> > > > - intel_csr_load_program(dev_priv);
> > >
> > > same
> > >
> > > > }
> > > >
> > > > void bxt_display_core_uninit(struct drm_i915_private *dev_priv)
> > > > @@ -3283,9 +3277,6 @@ static void cnl_display_core_init(struct
> > > > drm_i915_private *dev_priv, bool resume
> > > >
> > > > /* 6. Enable DBUF */
> > > > gen9_dbuf_enable(dev_priv);
> > > > -
> > > > - if (resume && dev_priv->csr.dmc_payload)
> > > > - intel_csr_load_program(dev_priv);
> > >
> > > same
> > >
> > > > }
> > > >
> > > > static void cnl_display_core_uninit(struct drm_i915_private
> > > > *dev_priv)
> > > > @@ -3561,6 +3552,10 @@ void intel_power_domains_init_hw(struct
> > > > drm_i915_private *dev_priv, bool resume)
> > > >
> > > > /* For now, we need the power well to be always enabled. */
> > > > intel_display_set_init_power(dev_priv, true);
> > > > +
> > > > + if (INTEL_GEN(dev_priv) >= 9 && resume && dev_priv-
> > > > >csr.dmc_payload)
> > > > + intel_csr_load_program(dev_priv);
> > > > +
> > > > /* Disable power support if the user asked so. */
> > > > if (!i915_modparams.disable_power_well)
> > > > intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
> > > > --
> > > > 2.18.0
> > > >
> > > > _______________________________________________
> > > > Intel-gfx mailing list
> > > > Intel-gfx@lists.freedesktop.org
> > > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-07-30 18:45 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-27 23:36 [PATCH 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states José Roberto de Souza
2018-07-27 23:36 ` [PATCH 2/3] drm/i915: Remove resume parameter from display_core_init functions José Roberto de Souza
2018-07-28 5:21 ` Rodrigo Vivi
2018-07-27 23:36 ` [PATCH 3/3] drm/i915: Keep overlay functions naming consistent José Roberto de Souza
2018-07-28 5:22 ` Rodrigo Vivi
2018-07-28 0:19 ` [PATCH v2 1/3] drm/i915/cnl+: Reload CSR firmware when coming back from low power states Souza, Jose
2018-07-28 0:26 ` ✓ Fi.CI.BAT: success for series starting with [1/3] " Patchwork
2018-07-28 5:19 ` [PATCH 1/3] " Rodrigo Vivi
2018-07-28 8:40 ` Imre Deak
2018-07-30 17:23 ` Souza, Jose
2018-07-30 18:44 ` Imre Deak
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