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From: Christoph Hellwig <hch@lst.de>
To: okaya@codeaurora.org
Cc: Christoph Hellwig <hch@lst.de>, Tony Luck <tony.luck@intel.com>,
	Fenghua Yu <fenghua.yu@intel.com>, Arnd Bergmann <arnd@arndb.de>,
	linux-ia64@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	okaya@kernel.org
Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping
Date: Wed, 1 Aug 2018 09:29:47 +0200	[thread overview]
Message-ID: <20180801072947.GD20224@lst.de> (raw)
In-Reply-To: <c7ecb31e9a79d26ce9edb15f58e0880f@codeaurora.org>

On Tue, Jul 31, 2018 at 11:41:23PM -0700, okaya@codeaurora.org wrote:
> I asked this question to Tony Luck before. If I remember right,
> his answer was:
>
> CPU guarantees outstanding writes to be flushed when a register write
> instruction is executed and an additional barrier instruction is not
> needed.

That would be great.  It still doesn't explain the barriers in the
dma sync routines.  Those have been there since the following commit
in the history tree:

commit 66b99421d118a5ddd98a72913670b0fcf0a38d45
Author: Andrew Morton <akpm@osdl.org>
Date:   Sat Mar 13 17:05:37 2004 -0800

    [PATCH] DMA: Fill gaping hole in DMA API interfaces.

    From: "David S. Miller" <davem@redhat.com>

which in fact only added them for the HP zx1 platform, and doesn't
contain any good explanation of why we need a barrier.

So I guess the right answer might be to just remove these barriers
without replacement.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: okaya@codeaurora.org
Cc: Christoph Hellwig <hch@lst.de>, Tony Luck <tony.luck@intel.com>,
	Fenghua Yu <fenghua.yu@intel.com>, Arnd Bergmann <arnd@arndb.de>,
	linux-ia64@vger.kernel.org, linux-arch@vger.kernel.org,
	linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	okaya@kernel.org
Subject: Re: [PATCH] ia64: fix barrier placement for write* / dma mapping
Date: Wed, 01 Aug 2018 07:29:47 +0000	[thread overview]
Message-ID: <20180801072947.GD20224@lst.de> (raw)
In-Reply-To: <c7ecb31e9a79d26ce9edb15f58e0880f@codeaurora.org>

On Tue, Jul 31, 2018 at 11:41:23PM -0700, okaya@codeaurora.org wrote:
> I asked this question to Tony Luck before. If I remember right,
> his answer was:
>
> CPU guarantees outstanding writes to be flushed when a register write
> instruction is executed and an additional barrier instruction is not
> needed.

That would be great.  It still doesn't explain the barriers in the
dma sync routines.  Those have been there since the following commit
in the history tree:

commit 66b99421d118a5ddd98a72913670b0fcf0a38d45
Author: Andrew Morton <akpm@osdl.org>
Date:   Sat Mar 13 17:05:37 2004 -0800

    [PATCH] DMA: Fill gaping hole in DMA API interfaces.

    From: "David S. Miller" <davem@redhat.com>

which in fact only added them for the HP zx1 platform, and doesn't
contain any good explanation of why we need a barrier.

So I guess the right answer might be to just remove these barriers
without replacement.

  reply	other threads:[~2018-08-01  7:25 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-31 17:20 barriers vs I/O and DMA for ia64 Christoph Hellwig
2018-07-31 17:20 ` [PATCH] ia64: fix barrier placement for write* / dma mapping Christoph Hellwig
2018-07-31 17:20   ` Christoph Hellwig
2018-08-01  6:41   ` okaya
2018-08-01  6:41     ` okaya
2018-08-01  6:41     ` okaya-sgV2jX0FEOL9JmXXK+q4OQ
2018-08-01  7:29     ` Christoph Hellwig [this message]
2018-08-01  7:29       ` Christoph Hellwig
2018-08-01  8:00       ` Sinan Kaya
2018-08-01  8:00         ` Sinan Kaya

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