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From: Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org
Cc: alexander.deucher-5C7GfCeVMHo@public.gmane.org
Subject: [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3)
Date: Wed,  1 Aug 2018 10:25:04 +0200	[thread overview]
Message-ID: <20180801082506.17184-2-issor.oruam@gmail.com> (raw)
In-Reply-To: <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>

SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 already listed in amd/display/dc/dc_hw_types.h
and the necessary crossbars register controls to swap red and blue channels
are already implemented in drm/amd/display/dc/dce/dce_mem_input.c

Logic to handle new formats is added in amdgpu_dm and dce 8.0, 10.0, 11.0 modules.

Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
---
 drivers/gpu/drm/amd/amdgpu/dce_v10_0.c            | 9 +++++++++
 drivers/gpu/drm/amd/amdgpu/dce_v11_0.c            | 9 +++++++++
 drivers/gpu/drm/amd/amdgpu/dce_v8_0.c             | 8 ++++++++
 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++
 4 files changed, 32 insertions(+)

diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index ada241bfeee9..ffb112ed825b 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -1941,6 +1941,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
 		bypass_lut = true;
 		break;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
+#ifdef __BIG_ENDIAN
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
+					ENDIAN_8IN32);
+#endif
+		break;
 	default:
 		DRM_ERROR("Unsupported screen format %s\n",
 		          drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index a5b96eac3033..283d8ce9dd7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -1983,6 +1983,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
 		bypass_lut = true;
 		break;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+		fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0);
+#ifdef __BIG_ENDIAN
+		fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
+					ENDIAN_8IN32);
+#endif
+		break;
 	default:
 		DRM_ERROR("Unsupported screen format %s\n",
 		          drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index c9b9ab8f1b05..2c96fb811083 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1865,6 +1865,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
 		/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
 		bypass_lut = true;
 		break;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
+		             (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT));
+#ifdef __BIG_ENDIAN
+		fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
+#endif
+		break;
 	default:
 		DRM_ERROR("Unsupported screen format %s\n",
 		          drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 770c6b24be0b..4f689f47d7c3 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1892,6 +1892,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
 	case DRM_FORMAT_ABGR2101010:
 		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
 		break;
+	case DRM_FORMAT_XBGR8888:
+	case DRM_FORMAT_ABGR8888:
+		plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
+		break;
 	case DRM_FORMAT_NV21:
 		plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
 		break;
@@ -3190,6 +3194,8 @@ static const uint32_t rgb_formats[] = {
 	DRM_FORMAT_XBGR2101010,
 	DRM_FORMAT_ARGB2101010,
 	DRM_FORMAT_ABGR2101010,
+	DRM_FORMAT_XBGR8888,
+	DRM_FORMAT_ABGR8888,
 };
 
 static const uint32_t yuv_formats[] = {
-- 
2.17.1

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  parent reply	other threads:[~2018-08-01  8:25 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-16  2:03 [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) Mauro Rossi
2018-07-17 13:43 ` Alex Deucher
     [not found]   ` <CADnq5_P0_pLHZ+9ccQ6hro9NBBuqL-G8UjYp3NTr-Oka+0KYAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-17 18:38     ` Mauro Rossi
     [not found]       ` <CAEQFVGbAQ+1BbdhC+4sGiFukH-JVSui9Y+ZhxPswCVHw+rcbFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-24 20:41         ` Alex Deucher
     [not found]           ` <CADnq5_PAtdwddz1ctBSixX9AqgY3pq=vryBMsSvytw8=JG+8Rw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-08-01  8:25             ` drm/radeon,amdgpu,dc: enable ABGR and XBGR formats Mauro Rossi
     [not found]               ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01  8:25                 ` Mauro Rossi [this message]
     [not found]                   ` <20180801082506.17184-2-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01 16:08                     ` [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) Alex Deucher
2018-08-01  8:25                 ` [PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats Mauro Rossi
2018-08-01  8:25                 ` [PATCH 3/3] drm/radeon: " Mauro Rossi
     [not found]                   ` <20180801082506.17184-4-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01 16:11                     ` Alex Deucher

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