* [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2)
@ 2018-07-16 2:03 Mauro Rossi
2018-07-17 13:43 ` Alex Deucher
0 siblings, 1 reply; 10+ messages in thread
From: Mauro Rossi @ 2018-07-16 2:03 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Mauro Rossi
From: Mauro Rossi <issor.oruam@gmail.com>
(v1) {A,X}BGR8888 code paths are added in amdgpu_dm, by using an fb_format
already listed in dc/dc_hw_types.h (SURFACE_PIXEL_FORMAT_GRPH_ABGR8888),
and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later.
GRPH_FORMAT_ARGB8888 is used due to lack of specific GRPH_FORMAT_ABGR8888
(v2) support for {A,X}BGR8888 in atombios_crtc (now in dce4 path, to be refined)
to initialize frame buffer device and avoid following dmesg error:
"[drm] Cannot find any crtc or sizes"
Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv)
SurfaceFlinger can now select RGBA_8888 format for HWC_FRAMEBUFFER_TARGET
No major regression or crash observed so far, but some android 2D overlay
may be affected by color artifacts. Kind feedback requested.
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
---
drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++
drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++
drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++++++
5 files changed, 40 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
index 022f303463fc..d4280d2e7737 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c
@@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
index 800a9f36ab4f..d48ee8f2e192 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c
@@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2);
+ fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP,
+ ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
index 012e0a9ae0ff..0e2fc1ac475f 100644
--- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c
@@ -1929,6 +1929,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) |
+ (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); /* Hack */
+#ifdef __BIG_ENDIAN
+ fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 63c67346d316..6c10fa291150 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1824,6 +1824,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev,
case DRM_FORMAT_ABGR2101010:
plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888;
+ break;
case DRM_FORMAT_NV21:
plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr;
break;
@@ -3115,6 +3119,8 @@ static const uint32_t rgb_formats[] = {
DRM_FORMAT_XBGR2101010,
DRM_FORMAT_ARGB2101010,
DRM_FORMAT_ABGR2101010,
+ DRM_FORMAT_XBGR8888,
+ DRM_FORMAT_ABGR8888,
};
static const uint32_t yuv_formats[] = {
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 02baaaf20e9d..b954b3658a33 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1259,6 +1259,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc,
/* Greater 8 bpc fb needs to bypass hw-lut to retain precision */
bypass_lut = true;
break;
+ case DRM_FORMAT_XBGR8888:
+ case DRM_FORMAT_ABGR8888:
+ fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) |
+ EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
+#ifdef __BIG_ENDIAN
+ fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
+#endif
+ break;
default:
DRM_ERROR("Unsupported screen format %s\n",
drm_get_format_name(target_fb->format->format, &format_name));
--
2.17.1
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amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) 2018-07-16 2:03 [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) Mauro Rossi @ 2018-07-17 13:43 ` Alex Deucher [not found] ` <CADnq5_P0_pLHZ+9ccQ6hro9NBBuqL-G8UjYp3NTr-Oka+0KYAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Alex Deucher @ 2018-07-17 13:43 UTC (permalink / raw) To: Mauro Rossi; +Cc: amd-gfx list On Sun, Jul 15, 2018 at 10:03 PM, Mauro Rossi <issor.oruam@gmail.com> wrote: > From: Mauro Rossi <issor.oruam@gmail.com> > > (v1) {A,X}BGR8888 code paths are added in amdgpu_dm, by using an fb_format > already listed in dc/dc_hw_types.h (SURFACE_PIXEL_FORMAT_GRPH_ABGR8888), > and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later. > GRPH_FORMAT_ARGB8888 is used due to lack of specific GRPH_FORMAT_ABGR8888 > > (v2) support for {A,X}BGR8888 in atombios_crtc (now in dce4 path, to be refined) > to initialize frame buffer device and avoid following dmesg error: > "[drm] Cannot find any crtc or sizes" > > Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv) > SurfaceFlinger can now select RGBA_8888 format for HWC_FRAMEBUFFER_TARGET > No major regression or crash observed so far, but some android 2D overlay > may be affected by color artifacts. Kind feedback requested. > > Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> Please split the patch in three (one for radeon and one for amdgpu dc and one for amdgpu non-dc). Also the GRPH_SWAP_CONTROL register has a crossbar where you can change the channel routing. You may need that for the channel routing to work correctly. Alex > --- > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++ > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ > drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++++++ > 5 files changed, 40 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > index 022f303463fc..d4280d2e7737 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > @@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); /* Hack */ > +#ifdef __BIG_ENDIAN > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, > + ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > index 800a9f36ab4f..d48ee8f2e192 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > @@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); /* Hack */ > +#ifdef __BIG_ENDIAN > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, > + ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > index 012e0a9ae0ff..0e2fc1ac475f 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > @@ -1929,6 +1929,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | > + (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); /* Hack */ > +#ifdef __BIG_ENDIAN > + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 63c67346d316..6c10fa291150 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1824,6 +1824,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, > case DRM_FORMAT_ABGR2101010: > plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; > + break; > case DRM_FORMAT_NV21: > plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; > break; > @@ -3115,6 +3119,8 @@ static const uint32_t rgb_formats[] = { > DRM_FORMAT_XBGR2101010, > DRM_FORMAT_ARGB2101010, > DRM_FORMAT_ABGR2101010, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_ABGR8888, > }; > > static const uint32_t yuv_formats[] = { > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c > index 02baaaf20e9d..b954b3658a33 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1259,6 +1259,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | > + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); > +#ifdef __BIG_ENDIAN > + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <CADnq5_P0_pLHZ+9ccQ6hro9NBBuqL-G8UjYp3NTr-Oka+0KYAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) [not found] ` <CADnq5_P0_pLHZ+9ccQ6hro9NBBuqL-G8UjYp3NTr-Oka+0KYAA-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-07-17 18:38 ` Mauro Rossi [not found] ` <CAEQFVGbAQ+1BbdhC+4sGiFukH-JVSui9Y+ZhxPswCVHw+rcbFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Mauro Rossi @ 2018-07-17 18:38 UTC (permalink / raw) To: alexdeucher-Re5JQEeQqe8AvxtiuMwx3w Cc: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW [-- Attachment #1.1: Type: text/plain, Size: 8973 bytes --] Hi Alex, Il giorno mar 17 lug 2018 alle ore 15:43 Alex Deucher <alexdeucher-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> ha scritto: > On Sun, Jul 15, 2018 at 10:03 PM, Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > wrote: > > From: Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > > > > (v1) {A,X}BGR8888 code paths are added in amdgpu_dm, by using an > fb_format > > already listed in dc/dc_hw_types.h > (SURFACE_PIXEL_FORMAT_GRPH_ABGR8888), > > and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later. > > GRPH_FORMAT_ARGB8888 is used due to lack of specific > GRPH_FORMAT_ABGR8888 > > > > (v2) support for {A,X}BGR8888 in atombios_crtc (now in dce4 path, to be > refined) > > to initialize frame buffer device and avoid following dmesg error: > > "[drm] Cannot find any crtc or sizes" > > > > Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv) > > SurfaceFlinger can now select RGBA_8888 format for HWC_FRAMEBUFFER_TARGET > > No major regression or crash observed so far, but some android 2D overlay > > may be affected by color artifacts. Kind feedback requested. > > > > Signed-off-by: Mauro Rossi <issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> > > Please split the patch in three (one for radeon and one for amdgpu dc > and one for amdgpu non-dc). Also the GRPH_SWAP_CONTROL register has a > crossbar where you can change the channel routing. You may need that > for the channel routing to work correctly. > > Alex > Thanks for your suggestion and guidance! :-) I may need some time to assimilate the suggestions and some confirmations, as I am an amateur in AMD GPU coding, to be honest, I should have mentioned that before. Regarding the radeon scope of changes, do you recommend to keep the enablement of {A,X}BGR8888 for dce4 and later, or to extend the enablement of {A,X}BGR8888 to older families of radeon gpus/chipsets? What is the lower radeon family where {A,X}BGR8888 can be natively supported by HW, by means of swap control registers for channel routing configuration? Based on the scope of {A,X}BGR8888 support in final patches, I may need to add handling in other dce code and maybe other modules, could you please provide information in terms of necessary changes/high level steps to follow? Do you have some pointer to documentation on swap control registers for the families that may be considered as 'safe to be kept in scope' for {A,X}BGR8888 support? Last but not least I would like to ask you about how to test no-regression, even if this will come later, when patches will be in good shape for further evaluation, do you have tools and samples for conformance/no-regression testing? I am asking because I don't have samples for all families. Kind regards Mauro > > > > --- > > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ > > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ > > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++ > > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ > > drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++++++ > > 5 files changed, 40 insertions(+) > > > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > > index 022f303463fc..d4280d2e7737 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > > @@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct > drm_crtc *crtc, > > /* Greater 8 bpc fb needs to bypass hw-lut to retain > precision */ > > bypass_lut = true; > > break; > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ABGR8888: > > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, > 2); > > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, > GRPH_FORMAT, 0); /* Hack */ > > +#ifdef __BIG_ENDIAN > > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, > GRPH_ENDIAN_SWAP, > > + ENDIAN_8IN32); > > +#endif > > + break; > > default: > > DRM_ERROR("Unsupported screen format %s\n", > > drm_get_format_name(target_fb->format->format, > &format_name)); > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > > index 800a9f36ab4f..d48ee8f2e192 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > > @@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct > drm_crtc *crtc, > > /* Greater 8 bpc fb needs to bypass hw-lut to retain > precision */ > > bypass_lut = true; > > break; > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ABGR8888: > > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, > 2); > > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, > GRPH_FORMAT, 0); /* Hack */ > > +#ifdef __BIG_ENDIAN > > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, > GRPH_ENDIAN_SWAP, > > + ENDIAN_8IN32); > > +#endif > > + break; > > default: > > DRM_ERROR("Unsupported screen format %s\n", > > drm_get_format_name(target_fb->format->format, > &format_name)); > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > > index 012e0a9ae0ff..0e2fc1ac475f 100644 > > --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > > @@ -1929,6 +1929,14 @@ static int dce_v8_0_crtc_do_set_base(struct > drm_crtc *crtc, > > /* Greater 8 bpc fb needs to bypass hw-lut to retain > precision */ > > bypass_lut = true; > > break; > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ABGR8888: > > + fb_format = ((GRPH_DEPTH_32BPP << > GRPH_CONTROL__GRPH_DEPTH__SHIFT) | > > + (GRPH_FORMAT_ARGB8888 << > GRPH_CONTROL__GRPH_FORMAT__SHIFT)); /* Hack */ > > +#ifdef __BIG_ENDIAN > > + fb_swap = (GRPH_ENDIAN_8IN32 << > GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); > > +#endif > > + break; > > default: > > DRM_ERROR("Unsupported screen format %s\n", > > drm_get_format_name(target_fb->format->format, > &format_name)); > > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > index 63c67346d316..6c10fa291150 100644 > > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > > @@ -1824,6 +1824,10 @@ static int fill_plane_attributes_from_fb(struct > amdgpu_device *adev, > > case DRM_FORMAT_ABGR2101010: > > plane_state->format = > SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; > > break; > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ABGR8888: > > + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; > > + break; > > case DRM_FORMAT_NV21: > > plane_state->format = > SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; > > break; > > @@ -3115,6 +3119,8 @@ static const uint32_t rgb_formats[] = { > > DRM_FORMAT_XBGR2101010, > > DRM_FORMAT_ARGB2101010, > > DRM_FORMAT_ABGR2101010, > > + DRM_FORMAT_XBGR8888, > > + DRM_FORMAT_ABGR8888, > > }; > > > > static const uint32_t yuv_formats[] = { > > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c > b/drivers/gpu/drm/radeon/atombios_crtc.c > > index 02baaaf20e9d..b954b3658a33 100644 > > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > > @@ -1259,6 +1259,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc > *crtc, > > /* Greater 8 bpc fb needs to bypass hw-lut to retain > precision */ > > bypass_lut = true; > > break; > > + case DRM_FORMAT_XBGR8888: > > + case DRM_FORMAT_ABGR8888: > > + fb_format = > (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | > > + > EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); > > +#ifdef __BIG_ENDIAN > > + fb_swap = > EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); > > +#endif > > + break; > > default: > > DRM_ERROR("Unsupported screen format %s\n", > > drm_get_format_name(target_fb->format->format, > &format_name)); > > -- > > 2.17.1 > > > > _______________________________________________ > > amd-gfx mailing list > > amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org > > https://lists.freedesktop.org/mailman/listinfo/amd-gfx > [-- Attachment #1.2: Type: text/html, Size: 14565 bytes --] [-- Attachment #2: Type: text/plain, Size: 154 bytes --] _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <CAEQFVGbAQ+1BbdhC+4sGiFukH-JVSui9Y+ZhxPswCVHw+rcbFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* Re: [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) [not found] ` <CAEQFVGbAQ+1BbdhC+4sGiFukH-JVSui9Y+ZhxPswCVHw+rcbFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-07-24 20:41 ` Alex Deucher [not found] ` <CADnq5_PAtdwddz1ctBSixX9AqgY3pq=vryBMsSvytw8=JG+8Rw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Alex Deucher @ 2018-07-24 20:41 UTC (permalink / raw) To: Mauro Rossi; +Cc: amd-gfx list On Tue, Jul 17, 2018 at 2:38 PM, Mauro Rossi <issor.oruam@gmail.com> wrote: > Hi Alex, > > Il giorno mar 17 lug 2018 alle ore 15:43 Alex Deucher > <alexdeucher@gmail.com> ha scritto: >> >> On Sun, Jul 15, 2018 at 10:03 PM, Mauro Rossi <issor.oruam@gmail.com> >> wrote: >> > From: Mauro Rossi <issor.oruam@gmail.com> >> > >> > (v1) {A,X}BGR8888 code paths are added in amdgpu_dm, by using an >> > fb_format >> > already listed in dc/dc_hw_types.h >> > (SURFACE_PIXEL_FORMAT_GRPH_ABGR8888), >> > and in dce 8.0, 10.0 and 11.0, i.e. Bonaire and later. >> > GRPH_FORMAT_ARGB8888 is used due to lack of specific >> > GRPH_FORMAT_ABGR8888 >> > >> > (v2) support for {A,X}BGR8888 in atombios_crtc (now in dce4 path, to be >> > refined) >> > to initialize frame buffer device and avoid following dmesg error: >> > "[drm] Cannot find any crtc or sizes" >> > >> > Tested with oreo-x86 (hwcomposer.drm + gralloc.gbm + mesa-dev/radv) >> > SurfaceFlinger can now select RGBA_8888 format for >> > HWC_FRAMEBUFFER_TARGET >> > No major regression or crash observed so far, but some android 2D >> > overlay >> > may be affected by color artifacts. Kind feedback requested. >> > >> > Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> >> >> Please split the patch in three (one for radeon and one for amdgpu dc >> and one for amdgpu non-dc). Also the GRPH_SWAP_CONTROL register has a >> crossbar where you can change the channel routing. You may need that >> for the channel routing to work correctly. >> >> Alex > > > Thanks for your suggestion and guidance! :-) > > I may need some time to assimilate the suggestions and some confirmations, > as I am an amateur in AMD GPU coding, to be honest, I should have mentioned > that before. > > Regarding the radeon scope of changes, > do you recommend to keep the enablement of {A,X}BGR8888 for dce4 and later, > or to extend the enablement of {A,X}BGR8888 to older families of radeon > gpus/chipsets? If you are motivated to enable it on older asics, go for it. > > What is the lower radeon family where {A,X}BGR8888 can be natively > supported by HW, > by means of swap control registers for channel routing configuration? > Back to the AVIVO family (DCE1, r5xx). > Based on the scope of {A,X}BGR8888 support in final patches, > I may need to add handling in other dce code and maybe other modules, > could you please provide information in terms of necessary changes/high > level steps to follow? > > Do you have some pointer to documentation on swap control registers for the > families > that may be considered as 'safe to be kept in scope' for {A,X}BGR8888 > support? For DCE1 (r5xx chips), there was a swap bit in the D1GRPH_CONTROL/D2GRPH_CONTROL registers. Bit 16 (D1GRPH_SWAP_RB), if set, swaps the R and B components. See r500_reg.h. For DCE2 (r6xx chips) and newer, they use the RGB crossbars GRPH_SWAP_CONTROL (see r600_reg.h and evergreen_reg.h) DCE1: http://developer.amd.com/wordpress/media/2012/10/RRG-216M56-03oOEM.pdf DCE2+: http://developer.amd.com/wordpress/media/2012/10/42590_m76_rrg_1.01o.pdf > > Last but not least I would like to ask you about how to test no-regression, > even if this will come later, > when patches will be in good shape for further evaluation, do you have tools > and samples for conformance/no-regression testing? > I am asking because I don't have samples for all families. I have samples for most families. Alex > > Kind regards > > Mauro > > > >> >> >> >> > --- >> > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ >> > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ >> > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++ >> > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ >> > drivers/gpu/drm/radeon/atombios_crtc.c | 8 ++++++++ >> > 5 files changed, 40 insertions(+) >> > >> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c >> > b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c >> > index 022f303463fc..d4280d2e7737 100644 >> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c >> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c >> > @@ -2005,6 +2005,15 @@ static int dce_v10_0_crtc_do_set_base(struct >> > drm_crtc *crtc, >> > /* Greater 8 bpc fb needs to bypass hw-lut to retain >> > precision */ >> > bypass_lut = true; >> > break; >> > + case DRM_FORMAT_XBGR8888: >> > + case DRM_FORMAT_ABGR8888: >> > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, >> > 2); >> > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, >> > GRPH_FORMAT, 0); /* Hack */ >> > +#ifdef __BIG_ENDIAN >> > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, >> > GRPH_ENDIAN_SWAP, >> > + ENDIAN_8IN32); >> > +#endif >> > + break; >> > default: >> > DRM_ERROR("Unsupported screen format %s\n", >> > drm_get_format_name(target_fb->format->format, >> > &format_name)); >> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c >> > b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c >> > index 800a9f36ab4f..d48ee8f2e192 100644 >> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c >> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c >> > @@ -2044,6 +2044,15 @@ static int dce_v11_0_crtc_do_set_base(struct >> > drm_crtc *crtc, >> > /* Greater 8 bpc fb needs to bypass hw-lut to retain >> > precision */ >> > bypass_lut = true; >> > break; >> > + case DRM_FORMAT_XBGR8888: >> > + case DRM_FORMAT_ABGR8888: >> > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, >> > 2); >> > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, >> > GRPH_FORMAT, 0); /* Hack */ >> > +#ifdef __BIG_ENDIAN >> > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, >> > GRPH_ENDIAN_SWAP, >> > + ENDIAN_8IN32); >> > +#endif >> > + break; >> > default: >> > DRM_ERROR("Unsupported screen format %s\n", >> > drm_get_format_name(target_fb->format->format, >> > &format_name)); >> > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c >> > b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c >> > index 012e0a9ae0ff..0e2fc1ac475f 100644 >> > --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c >> > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c >> > @@ -1929,6 +1929,14 @@ static int dce_v8_0_crtc_do_set_base(struct >> > drm_crtc *crtc, >> > /* Greater 8 bpc fb needs to bypass hw-lut to retain >> > precision */ >> > bypass_lut = true; >> > break; >> > + case DRM_FORMAT_XBGR8888: >> > + case DRM_FORMAT_ABGR8888: >> > + fb_format = ((GRPH_DEPTH_32BPP << >> > GRPH_CONTROL__GRPH_DEPTH__SHIFT) | >> > + (GRPH_FORMAT_ARGB8888 << >> > GRPH_CONTROL__GRPH_FORMAT__SHIFT)); /* Hack */ >> > +#ifdef __BIG_ENDIAN >> > + fb_swap = (GRPH_ENDIAN_8IN32 << >> > GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); >> > +#endif >> > + break; >> > default: >> > DRM_ERROR("Unsupported screen format %s\n", >> > drm_get_format_name(target_fb->format->format, >> > &format_name)); >> > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> > b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> > index 63c67346d316..6c10fa291150 100644 >> > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c >> > @@ -1824,6 +1824,10 @@ static int fill_plane_attributes_from_fb(struct >> > amdgpu_device *adev, >> > case DRM_FORMAT_ABGR2101010: >> > plane_state->format = >> > SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; >> > break; >> > + case DRM_FORMAT_XBGR8888: >> > + case DRM_FORMAT_ABGR8888: >> > + plane_state->format = >> > SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; >> > + break; >> > case DRM_FORMAT_NV21: >> > plane_state->format = >> > SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; >> > break; >> > @@ -3115,6 +3119,8 @@ static const uint32_t rgb_formats[] = { >> > DRM_FORMAT_XBGR2101010, >> > DRM_FORMAT_ARGB2101010, >> > DRM_FORMAT_ABGR2101010, >> > + DRM_FORMAT_XBGR8888, >> > + DRM_FORMAT_ABGR8888, >> > }; >> > >> > static const uint32_t yuv_formats[] = { >> > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c >> > b/drivers/gpu/drm/radeon/atombios_crtc.c >> > index 02baaaf20e9d..b954b3658a33 100644 >> > --- a/drivers/gpu/drm/radeon/atombios_crtc.c >> > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c >> > @@ -1259,6 +1259,14 @@ static int dce4_crtc_do_set_base(struct drm_crtc >> > *crtc, >> > /* Greater 8 bpc fb needs to bypass hw-lut to retain >> > precision */ >> > bypass_lut = true; >> > break; >> > + case DRM_FORMAT_XBGR8888: >> > + case DRM_FORMAT_ABGR8888: >> > + fb_format = >> > (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | >> > + >> > EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); >> > +#ifdef __BIG_ENDIAN >> > + fb_swap = >> > EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); >> > +#endif >> > + break; >> > default: >> > DRM_ERROR("Unsupported screen format %s\n", >> > drm_get_format_name(target_fb->format->format, >> > &format_name)); >> > -- >> > 2.17.1 >> > >> > _______________________________________________ >> > amd-gfx mailing list >> > amd-gfx@lists.freedesktop.org >> > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <CADnq5_PAtdwddz1ctBSixX9AqgY3pq=vryBMsSvytw8=JG+8Rw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>]
* drm/radeon,amdgpu,dc: enable ABGR and XBGR formats [not found] ` <CADnq5_PAtdwddz1ctBSixX9AqgY3pq=vryBMsSvytw8=JG+8Rw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org> @ 2018-08-01 8:25 ` Mauro Rossi [not found] ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 0 siblings, 1 reply; 10+ messages in thread From: Mauro Rossi @ 2018-08-01 8:25 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: alexander.deucher-5C7GfCeVMHo Sending a respin for support of {A,X}RGB pixel formats in DCE1 and later, with separate patches for amd dc, amdgpu and radeon Please review taking in to account following doubts I have: For amd dc crossbars register controls to swap red and blue channels are already implemented in drm/amd/display/dc/dce/dce_mem_input.c Do we need them also in dce 8, 10, 11 modules? For amdgpu: What are the necessary *_reg.h header to consider for crossbars register controls in amdgpu in order to cover all parts (si, cik and later) with amd dc disabled? [PATCH v2 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) [PATCH v2 2/3] drm/amdgpu: enable enable ABGR and XBGR formats [PATCH v2 3/3] drm/radeon: enable ABGR and XBGR formats _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
[parent not found: <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) [not found] ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-08-01 8:25 ` Mauro Rossi [not found] ` <20180801082506.17184-2-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-08-01 8:25 ` [PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats Mauro Rossi 2018-08-01 8:25 ` [PATCH 3/3] drm/radeon: " Mauro Rossi 2 siblings, 1 reply; 10+ messages in thread From: Mauro Rossi @ 2018-08-01 8:25 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: alexander.deucher-5C7GfCeVMHo SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 already listed in amd/display/dc/dc_hw_types.h and the necessary crossbars register controls to swap red and blue channels are already implemented in drm/amd/display/dc/dce/dce_mem_input.c Logic to handle new formats is added in amdgpu_dm and dce 8.0, 10.0, 11.0 modules. Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> --- drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++ drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ 4 files changed, 32 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c index ada241bfeee9..ffb112ed825b 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c @@ -1941,6 +1941,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c index a5b96eac3033..283d8ce9dd7e 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c @@ -1983,6 +1983,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); +#ifdef __BIG_ENDIAN + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, + ENDIAN_8IN32); +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c index c9b9ab8f1b05..2c96fb811083 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c @@ -1865,6 +1865,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | + (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); +#ifdef __BIG_ENDIAN + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c index 770c6b24be0b..4f689f47d7c3 100644 --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c @@ -1892,6 +1892,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, case DRM_FORMAT_ABGR2101010: plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; + break; case DRM_FORMAT_NV21: plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; break; @@ -3190,6 +3194,8 @@ static const uint32_t rgb_formats[] = { DRM_FORMAT_XBGR2101010, DRM_FORMAT_ARGB2101010, DRM_FORMAT_ABGR2101010, + DRM_FORMAT_XBGR8888, + DRM_FORMAT_ABGR8888, }; static const uint32_t yuv_formats[] = { -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <20180801082506.17184-2-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) [not found] ` <20180801082506.17184-2-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-08-01 16:08 ` Alex Deucher 0 siblings, 0 replies; 10+ messages in thread From: Alex Deucher @ 2018-08-01 16:08 UTC (permalink / raw) To: Mauro Rossi; +Cc: Deucher, Alexander, amd-gfx list On Wed, Aug 1, 2018 at 4:25 AM, Mauro Rossi <issor.oruam@gmail.com> wrote: > SURFACE_PIXEL_FORMAT_GRPH_ABGR8888 already listed in amd/display/dc/dc_hw_types.h > and the necessary crossbars register controls to swap red and blue channels > are already implemented in drm/amd/display/dc/dce/dce_mem_input.c > > Logic to handle new formats is added in amdgpu_dm and dce 8.0, 10.0, 11.0 modules. > > Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> > --- > drivers/gpu/drm/amd/amdgpu/dce_v10_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/dce_v11_0.c | 9 +++++++++ > drivers/gpu/drm/amd/amdgpu/dce_v8_0.c | 8 ++++++++ You need to set the fb_swap crossbar bits in these files. These are part of the non-DC code. Also please combine these changes with the patch 2. > drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 6 ++++++ This change should be a standalone patch for dc. Other than that, looks good. Alex > 4 files changed, 32 insertions(+) > > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > index ada241bfeee9..ffb112ed825b 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v10_0.c > @@ -1941,6 +1941,15 @@ static int dce_v10_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); > +#ifdef __BIG_ENDIAN > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, > + ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > index a5b96eac3033..283d8ce9dd7e 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v11_0.c > @@ -1983,6 +1983,15 @@ static int dce_v11_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = REG_SET_FIELD(0, GRPH_CONTROL, GRPH_DEPTH, 2); > + fb_format = REG_SET_FIELD(fb_format, GRPH_CONTROL, GRPH_FORMAT, 0); > +#ifdef __BIG_ENDIAN > + fb_swap = REG_SET_FIELD(fb_swap, GRPH_SWAP_CNTL, GRPH_ENDIAN_SWAP, > + ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > index c9b9ab8f1b05..2c96fb811083 100644 > --- a/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > +++ b/drivers/gpu/drm/amd/amdgpu/dce_v8_0.c > @@ -1865,6 +1865,14 @@ static int dce_v8_0_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = ((GRPH_DEPTH_32BPP << GRPH_CONTROL__GRPH_DEPTH__SHIFT) | > + (GRPH_FORMAT_ARGB8888 << GRPH_CONTROL__GRPH_FORMAT__SHIFT)); > +#ifdef __BIG_ENDIAN > + fb_swap = (GRPH_ENDIAN_8IN32 << GRPH_SWAP_CNTL__GRPH_ENDIAN_SWAP__SHIFT); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > index 770c6b24be0b..4f689f47d7c3 100644 > --- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > +++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c > @@ -1892,6 +1892,10 @@ static int fill_plane_attributes_from_fb(struct amdgpu_device *adev, > case DRM_FORMAT_ABGR2101010: > plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR2101010; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + plane_state->format = SURFACE_PIXEL_FORMAT_GRPH_ABGR8888; > + break; > case DRM_FORMAT_NV21: > plane_state->format = SURFACE_PIXEL_FORMAT_VIDEO_420_YCbCr; > break; > @@ -3190,6 +3194,8 @@ static const uint32_t rgb_formats[] = { > DRM_FORMAT_XBGR2101010, > DRM_FORMAT_ARGB2101010, > DRM_FORMAT_ABGR2101010, > + DRM_FORMAT_XBGR8888, > + DRM_FORMAT_ABGR8888, > }; > > static const uint32_t yuv_formats[] = { > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats [not found] ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-08-01 8:25 ` [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) Mauro Rossi @ 2018-08-01 8:25 ` Mauro Rossi 2018-08-01 8:25 ` [PATCH 3/3] drm/radeon: " Mauro Rossi 2 siblings, 0 replies; 10+ messages in thread From: Mauro Rossi @ 2018-08-01 8:25 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: alexander.deucher-5C7GfCeVMHo Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu, for si and amd dc disabled Here is it necessary to define and set crossbar registers to swap red and blue channels Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> --- drivers/gpu/drm/amd/amdgpu/dce_v6_0.c | 10 ++++++++++ drivers/gpu/drm/amd/amdgpu/si_enums.h | 20 ++++++++++++++++++++ drivers/gpu/drm/amd/amdgpu/sid.h | 20 ++++++++++++++++++++ 3 files changed, 50 insertions(+) diff --git a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c index 394cc1e8fe20..f2c3f6676352 100644 --- a/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c +++ b/drivers/gpu/drm/amd/amdgpu/dce_v6_0.c @@ -1888,6 +1888,16 @@ static int dce_v6_0_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = (GRPH_DEPTH(GRPH_DEPTH_32BPP) | + GRPH_FORMAT(GRPH_FORMAT_ARGB8888)); + fb_swap = (GRPH_RED_CROSSBAR(GRPH_RED_SEL_B) | + GRPH_BLUE_CROSSBAR(GRPH_BLUE_SEL_R)); +#ifdef __BIG_ENDIAN + fb_swap = GRPH_ENDIAN_SWAP(GRPH_ENDIAN_8IN32); +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); diff --git a/drivers/gpu/drm/amd/amdgpu/si_enums.h b/drivers/gpu/drm/amd/amdgpu/si_enums.h index dc9e0e6b4558..790ba46eaebb 100644 --- a/drivers/gpu/drm/amd/amdgpu/si_enums.h +++ b/drivers/gpu/drm/amd/amdgpu/si_enums.h @@ -46,6 +46,26 @@ #define GRPH_ENDIAN_8IN16 1 #define GRPH_ENDIAN_8IN32 2 #define GRPH_ENDIAN_8IN64 3 +#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +#define GRPH_RED_SEL_R 0 +#define GRPH_RED_SEL_G 1 +#define GRPH_RED_SEL_B 2 +#define GRPH_RED_SEL_A 3 +#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +#define GRPH_GREEN_SEL_G 0 +#define GRPH_GREEN_SEL_B 1 +#define GRPH_GREEN_SEL_A 2 +#define GRPH_GREEN_SEL_R 3 +#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +#define GRPH_BLUE_SEL_B 0 +#define GRPH_BLUE_SEL_A 1 +#define GRPH_BLUE_SEL_R 2 +#define GRPH_BLUE_SEL_G 3 +#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +#define GRPH_ALPHA_SEL_A 0 +#define GRPH_ALPHA_SEL_R 1 +#define GRPH_ALPHA_SEL_G 2 +#define GRPH_ALPHA_SEL_B 3 #define GRPH_DEPTH(x) (((x) & 0x3) << 0) #define GRPH_DEPTH_8BPP 0 diff --git a/drivers/gpu/drm/amd/amdgpu/sid.h b/drivers/gpu/drm/amd/amdgpu/sid.h index c57eff159374..7cf12adb3915 100644 --- a/drivers/gpu/drm/amd/amdgpu/sid.h +++ b/drivers/gpu/drm/amd/amdgpu/sid.h @@ -2201,6 +2201,26 @@ # define EVERGREEN_GRPH_ENDIAN_8IN16 1 # define EVERGREEN_GRPH_ENDIAN_8IN32 2 # define EVERGREEN_GRPH_ENDIAN_8IN64 3 +#define EVERGREEN_GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +# define EVERGREEN_GRPH_RED_SEL_R 0 +# define EVERGREEN_GRPH_RED_SEL_G 1 +# define EVERGREEN_GRPH_RED_SEL_B 2 +# define EVERGREEN_GRPH_RED_SEL_A 3 +#define EVERGREEN_GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +# define EVERGREEN_GRPH_GREEN_SEL_G 0 +# define EVERGREEN_GRPH_GREEN_SEL_B 1 +# define EVERGREEN_GRPH_GREEN_SEL_A 2 +# define EVERGREEN_GRPH_GREEN_SEL_R 3 +#define EVERGREEN_GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +# define EVERGREEN_GRPH_BLUE_SEL_B 0 +# define EVERGREEN_GRPH_BLUE_SEL_A 1 +# define EVERGREEN_GRPH_BLUE_SEL_R 2 +# define EVERGREEN_GRPH_BLUE_SEL_G 3 +#define EVERGREEN_GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +# define EVERGREEN_GRPH_ALPHA_SEL_A 0 +# define EVERGREEN_GRPH_ALPHA_SEL_R 1 +# define EVERGREEN_GRPH_ALPHA_SEL_G 2 +# define EVERGREEN_GRPH_ALPHA_SEL_B 3 #define EVERGREEN_D3VGA_CONTROL 0xf8 #define EVERGREEN_D4VGA_CONTROL 0xf9 -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH 3/3] drm/radeon: enable ABGR and XBGR formats [not found] ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2018-08-01 8:25 ` [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) Mauro Rossi 2018-08-01 8:25 ` [PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats Mauro Rossi @ 2018-08-01 8:25 ` Mauro Rossi [not found] ` <20180801082506.17184-4-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> 2 siblings, 1 reply; 10+ messages in thread From: Mauro Rossi @ 2018-08-01 8:25 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: alexander.deucher-5C7GfCeVMHo Add support for DRM_FORMAT_{A,X}BGR8888 in atombios_crtc R6xx crossbar registers are defined and used based on ASIC_IS_DCE2 condition, for DCE1/R5xx AVIVO_D1GRPH_SWAP_RB bit is used to swap red and blue channels. Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> --- drivers/gpu/drm/radeon/atombios_crtc.c | 25 +++++++++++++++++++++ drivers/gpu/drm/radeon/r600_reg.h | 31 +++++++++++++++++++++----- 2 files changed, 51 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c index efbd5816082d..a06ad6ab24a6 100644 --- a/drivers/gpu/drm/radeon/atombios_crtc.c +++ b/drivers/gpu/drm/radeon/atombios_crtc.c @@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); + fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) | + EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R)); +#ifdef __BIG_ENDIAN + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); @@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ bypass_lut = true; break; + case DRM_FORMAT_XBGR8888: + case DRM_FORMAT_ABGR8888: + fb_format = + AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | + AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; + if (ASIC_IS_DCE2(rdev)) + fb_swap = + (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) | + R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_B)); + else /* DCE1 */ + fb_swap = AVIVO_D1GRPH_SWAP_RB; +#ifdef __BIG_ENDIAN + fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; +#endif + break; default: DRM_ERROR("Unsupported screen format %s\n", drm_get_format_name(target_fb->format->format, &format_name)); diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h index 3ef202629e7e..85e85ac3ba4d 100644 --- a/drivers/gpu/drm/radeon/r600_reg.h +++ b/drivers/gpu/drm/radeon/r600_reg.h @@ -87,11 +87,32 @@ #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 -#define R600_D1GRPH_SWAP_CONTROL 0x610C -# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) -# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) +#define R600_D1GRPH_SWAP_CONTROL 0x610C +# define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) +# define R600_D1GRPH_SWAP_ENDIAN_NONE 0 +# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1 +# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2 +# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3 +# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) +# define R600_D1GRPH_RED_SEL_R 0 +# define R600_D1GRPH_RED_SEL_G 1 +# define R600_D1GRPH_RED_SEL_B 2 +# define R600_D1GRPH_RED_SEL_A 3 +# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) +# define R600_D1GRPH_GREEN_SEL_G 0 +# define R600_D1GRPH_GREEN_SEL_B 1 +# define R600_D1GRPH_GREEN_SEL_A 2 +# define R600_D1GRPH_GREEN_SEL_R 3 +# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) +# define R600_D1GRPH_BLUE_SEL_B 0 +# define R600_D1GRPH_BLUE_SEL_A 1 +# define R600_D1GRPH_BLUE_SEL_R 2 +# define R600_D1GRPH_BLUE_SEL_G 3 +# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) +# define R600_D1GRPH_ALPHA_SEL_A 0 +# define R600_D1GRPH_ALPHA_SEL_R 1 +# define R600_D1GRPH_ALPHA_SEL_G 2 +# define R600_D1GRPH_ALPHA_SEL_B 3 #define R600_HDP_NONSURFACE_BASE 0x2c04 -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 10+ messages in thread
[parent not found: <20180801082506.17184-4-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>]
* Re: [PATCH 3/3] drm/radeon: enable ABGR and XBGR formats [not found] ` <20180801082506.17184-4-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org> @ 2018-08-01 16:11 ` Alex Deucher 0 siblings, 0 replies; 10+ messages in thread From: Alex Deucher @ 2018-08-01 16:11 UTC (permalink / raw) To: Mauro Rossi; +Cc: Deucher, Alexander, amd-gfx list On Wed, Aug 1, 2018 at 4:25 AM, Mauro Rossi <issor.oruam@gmail.com> wrote: > Add support for DRM_FORMAT_{A,X}BGR8888 in atombios_crtc > R6xx crossbar registers are defined and used based on ASIC_IS_DCE2 condition, > for DCE1/R5xx AVIVO_D1GRPH_SWAP_RB bit is used to swap red and blue channels. > > Signed-off-by: Mauro Rossi <issor.oruam@gmail.com> > --- > drivers/gpu/drm/radeon/atombios_crtc.c | 25 +++++++++++++++++++++ > drivers/gpu/drm/radeon/r600_reg.h | 31 +++++++++++++++++++++----- > 2 files changed, 51 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c > index efbd5816082d..a06ad6ab24a6 100644 > --- a/drivers/gpu/drm/radeon/atombios_crtc.c > +++ b/drivers/gpu/drm/radeon/atombios_crtc.c > @@ -1254,6 +1254,16 @@ static int dce4_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP) | > + EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888)); > + fb_swap = (EVERGREEN_GRPH_RED_CROSSBAR(EVERGREEN_GRPH_RED_SEL_B) | > + EVERGREEN_GRPH_BLUE_CROSSBAR(EVERGREEN_GRPH_BLUE_SEL_R)); > +#ifdef __BIG_ENDIAN > + fb_swap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32); > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > @@ -1551,6 +1561,21 @@ static int avivo_crtc_do_set_base(struct drm_crtc *crtc, > /* Greater 8 bpc fb needs to bypass hw-lut to retain precision */ > bypass_lut = true; > break; > + case DRM_FORMAT_XBGR8888: > + case DRM_FORMAT_ABGR8888: > + fb_format = > + AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | > + AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; > + if (ASIC_IS_DCE2(rdev)) > + fb_swap = > + (R600_D1GRPH_RED_CROSSBAR(R600_D1GRPH_RED_SEL_B) | > + R600_D1GRPH_BLUE_CROSSBAR(R600_D1GRPH_BLUE_SEL_B)); > + else /* DCE1 */ > + fb_swap = AVIVO_D1GRPH_SWAP_RB; This should be: fb_format |= AVIVO_D1GRPH_SWAP_RB; Other than that, looks good. Alex > +#ifdef __BIG_ENDIAN > + fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; > +#endif > + break; > default: > DRM_ERROR("Unsupported screen format %s\n", > drm_get_format_name(target_fb->format->format, &format_name)); > diff --git a/drivers/gpu/drm/radeon/r600_reg.h b/drivers/gpu/drm/radeon/r600_reg.h > index 3ef202629e7e..85e85ac3ba4d 100644 > --- a/drivers/gpu/drm/radeon/r600_reg.h > +++ b/drivers/gpu/drm/radeon/r600_reg.h > @@ -87,11 +87,32 @@ > #define R600_MEDIUM_VID_LOWER_GPIO_CNTL 0x720 > #define R600_LOW_VID_LOWER_GPIO_CNTL 0x724 > > -#define R600_D1GRPH_SWAP_CONTROL 0x610C > -# define R600_D1GRPH_SWAP_ENDIAN_NONE (0 << 0) > -# define R600_D1GRPH_SWAP_ENDIAN_16BIT (1 << 0) > -# define R600_D1GRPH_SWAP_ENDIAN_32BIT (2 << 0) > -# define R600_D1GRPH_SWAP_ENDIAN_64BIT (3 << 0) > +#define R600_D1GRPH_SWAP_CONTROL 0x610C > +# define R600_D1GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0) > +# define R600_D1GRPH_SWAP_ENDIAN_NONE 0 > +# define R600_D1GRPH_SWAP_ENDIAN_16BIT 1 > +# define R600_D1GRPH_SWAP_ENDIAN_32BIT 2 > +# define R600_D1GRPH_SWAP_ENDIAN_64BIT 3 > +# define R600_D1GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4) > +# define R600_D1GRPH_RED_SEL_R 0 > +# define R600_D1GRPH_RED_SEL_G 1 > +# define R600_D1GRPH_RED_SEL_B 2 > +# define R600_D1GRPH_RED_SEL_A 3 > +# define R600_D1GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6) > +# define R600_D1GRPH_GREEN_SEL_G 0 > +# define R600_D1GRPH_GREEN_SEL_B 1 > +# define R600_D1GRPH_GREEN_SEL_A 2 > +# define R600_D1GRPH_GREEN_SEL_R 3 > +# define R600_D1GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8) > +# define R600_D1GRPH_BLUE_SEL_B 0 > +# define R600_D1GRPH_BLUE_SEL_A 1 > +# define R600_D1GRPH_BLUE_SEL_R 2 > +# define R600_D1GRPH_BLUE_SEL_G 3 > +# define R600_D1GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10) > +# define R600_D1GRPH_ALPHA_SEL_A 0 > +# define R600_D1GRPH_ALPHA_SEL_R 1 > +# define R600_D1GRPH_ALPHA_SEL_G 2 > +# define R600_D1GRPH_ALPHA_SEL_B 3 > > #define R600_HDP_NONSURFACE_BASE 0x2c04 > > -- > 2.17.1 > > _______________________________________________ > amd-gfx mailing list > amd-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/amd-gfx _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply [flat|nested] 10+ messages in thread
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Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
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2018-07-16 2:03 [PATCH] RFC: drm/amd/display: enable ABGR and XBGR formats (v2) Mauro Rossi
2018-07-17 13:43 ` Alex Deucher
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2018-07-17 18:38 ` Mauro Rossi
[not found] ` <CAEQFVGbAQ+1BbdhC+4sGiFukH-JVSui9Y+ZhxPswCVHw+rcbFw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-07-24 20:41 ` Alex Deucher
[not found] ` <CADnq5_PAtdwddz1ctBSixX9AqgY3pq=vryBMsSvytw8=JG+8Rw-JsoAwUIsXosN+BqQ9rBEUg@public.gmane.org>
2018-08-01 8:25 ` drm/radeon,amdgpu,dc: enable ABGR and XBGR formats Mauro Rossi
[not found] ` <20180801082506.17184-1-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01 8:25 ` [PATCH 1/3] drm/amd/display: enable ABGR and XBGR formats (v3) Mauro Rossi
[not found] ` <20180801082506.17184-2-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01 16:08 ` Alex Deucher
2018-08-01 8:25 ` [PATCH 2/3] drm/amdgpu: enable enable ABGR and XBGR formats Mauro Rossi
2018-08-01 8:25 ` [PATCH 3/3] drm/radeon: " Mauro Rossi
[not found] ` <20180801082506.17184-4-issor.oruam-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>
2018-08-01 16:11 ` Alex Deucher
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