* [U-Boot] sunxi: SPI: reset bus when enabling clock
@ 2018-08-04 12:23 Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 2/2] sunxi: SPI: reset bus when enabling clock Fahad Sadah
0 siblings, 2 replies; 4+ messages in thread
From: Fahad Sadah @ 2018-08-04 12:23 UTC (permalink / raw)
To: u-boot
Hi all,
The sun6i SPI peripheral needs to be reset before it can be used. Add
the necessary offset #defines and perform this reset.
Applies to the allwinner-spi head on the u-boot-spi tree. Tested on
Orange Pi R1 (Allwinner H2+ / sun8i) and successfully booted from SPI
Thanks,
Signed-off-by: Fahad Sadah <fahad@sadah.uk>
Fahad Sadah (2):
sunxi: SPI: add AHB gate and reset offsets
sunxi: SPI: reset bus when enabling clock
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ++++
drivers/spi/sun6i_spi.c | 1 +
2 files changed, 5 insertions(+)
--
2.14.1
^ permalink raw reply [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets
2018-08-04 12:23 [U-Boot] sunxi: SPI: reset bus when enabling clock Fahad Sadah
@ 2018-08-04 12:23 ` Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 2/2] sunxi: SPI: reset bus when enabling clock Fahad Sadah
1 sibling, 0 replies; 4+ messages in thread
From: Fahad Sadah @ 2018-08-04 12:23 UTC (permalink / raw)
To: u-boot
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9597..71a1673fa8 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -290,6 +290,8 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB0 25
#define AHB_GATE_OFFSET_SATA 24
#endif
+#define AHB_GATE_OFFSET_SPI1 21
+#define AHB_GATE_OFFSET_SPI0 20
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_NAND0 13
@@ -436,6 +438,8 @@ struct sunxi_ccm_reg {
#ifdef CONFIG_MACH_SUN8I_R40
#define AHB_RESET_OFFSET_SATA 24
#endif
+#define AHB_RESET_OFFSET_SPI1 21
+#define AHB_RESET_OFFSET_SPI0 20
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
--
2.14.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 2/2] sunxi: SPI: reset bus when enabling clock
2018-08-04 12:23 [U-Boot] sunxi: SPI: reset bus when enabling clock Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets Fahad Sadah
@ 2018-08-04 12:23 ` Fahad Sadah
1 sibling, 0 replies; 4+ messages in thread
From: Fahad Sadah @ 2018-08-04 12:23 UTC (permalink / raw)
To: u-boot
---
drivers/spi/sun6i_spi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/spi/sun6i_spi.c b/drivers/spi/sun6i_spi.c
index 3192548e83..3c6a13e40e 100644
--- a/drivers/spi/sun6i_spi.c
+++ b/drivers/spi/sun6i_spi.c
@@ -215,6 +215,7 @@ static inline void sun6i_spi_enable_clock(void)
struct sunxi_ccm_reg *const ccm =
(struct sunxi_ccm_reg *const)SUNXI_CCM_BASE;
+ setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_RESET_OFFSET_SPI0));
setbits_le32(&ccm->ahb_gate0, (1 << AHB_GATE_OFFSET_SPI0));
writel((1 << 31), &ccm->spi0_clk_cfg);
}
--
2.14.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
* [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets
2018-08-03 23:24 [U-Boot] [PATCH 0/2] " Fahad Sadah
@ 2018-08-03 23:24 ` Fahad Sadah
0 siblings, 0 replies; 4+ messages in thread
From: Fahad Sadah @ 2018-08-03 23:24 UTC (permalink / raw)
To: u-boot
---
arch/arm/include/asm/arch-sunxi/clock_sun6i.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
index d328df9597..71a1673fa8 100644
--- a/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
+++ b/arch/arm/include/asm/arch-sunxi/clock_sun6i.h
@@ -290,6 +290,8 @@ struct sunxi_ccm_reg {
#define AHB_GATE_OFFSET_USB0 25
#define AHB_GATE_OFFSET_SATA 24
#endif
+#define AHB_GATE_OFFSET_SPI1 21
+#define AHB_GATE_OFFSET_SPI0 20
#define AHB_GATE_OFFSET_MCTL 14
#define AHB_GATE_OFFSET_GMAC 17
#define AHB_GATE_OFFSET_NAND0 13
@@ -436,6 +438,8 @@ struct sunxi_ccm_reg {
#ifdef CONFIG_MACH_SUN8I_R40
#define AHB_RESET_OFFSET_SATA 24
#endif
+#define AHB_RESET_OFFSET_SPI1 21
+#define AHB_RESET_OFFSET_SPI0 20
#define AHB_RESET_OFFSET_GMAC 17
#define AHB_RESET_OFFSET_MCTL 14
#define AHB_RESET_OFFSET_MMC3 11
--
2.14.1
^ permalink raw reply related [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-08-04 12:23 UTC | newest]
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2018-08-04 12:23 [U-Boot] sunxi: SPI: reset bus when enabling clock Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets Fahad Sadah
2018-08-04 12:23 ` [U-Boot] [PATCH 2/2] sunxi: SPI: reset bus when enabling clock Fahad Sadah
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2018-08-03 23:24 [U-Boot] [PATCH 0/2] " Fahad Sadah
2018-08-03 23:24 ` [U-Boot] [PATCH 1/2] sunxi: SPI: add AHB gate and reset offsets Fahad Sadah
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