* [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
@ 2018-08-03 9:22 Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 2/5] drm/vc4: Define missing PITCH0_SINK_PIX field Boris Brezillon
` (6 more replies)
0 siblings, 7 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-03 9:22 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, Boris Brezillon, dri-devel
From: Eric Anholt <eric@anholt.net>
Y_OFFSET field starts at bit 8 not 7.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- None
---
drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index d6864fa4bd14..ccbd6b377ffe 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
#define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
#define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
/* Y offset within a tile. */
-#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
-#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
+#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
+#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
#define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
#define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
--
2.14.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/5] drm/vc4: Define missing PITCH0_SINK_PIX field
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
@ 2018-08-03 9:22 ` Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 3/5] drm/vc4: Use drm_atomic_helper_check_plane_state() to simplify the logic Boris Brezillon
` (5 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-03 9:22 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, Boris Brezillon, dri-devel
From: Eric Anholt <eric@anholt.net>
This is needed to support X/Y negative placement of planes using
T-format buffers.
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- Fixed typo in commit subject line
---
drivers/gpu/drm/vc4/vc4_regs.h | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
index ccbd6b377ffe..931088014272 100644
--- a/drivers/gpu/drm/vc4/vc4_regs.h
+++ b/drivers/gpu/drm/vc4/vc4_regs.h
@@ -1037,6 +1037,10 @@ enum hvs_pixel_format {
#define SCALER_TILE_HEIGHT_MASK VC4_MASK(15, 0)
#define SCALER_TILE_HEIGHT_SHIFT 0
+/* Common PITCH0 fields */
+#define SCALER_PITCH0_SINK_PIX_MASK VC4_MASK(31, 26)
+#define SCALER_PITCH0_SINK_PIX_SHIFT 26
+
/* PITCH0 fields for T-tiled. */
#define SCALER_PITCH0_TILE_WIDTH_L_MASK VC4_MASK(22, 16)
#define SCALER_PITCH0_TILE_WIDTH_L_SHIFT 16
--
2.14.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/5] drm/vc4: Use drm_atomic_helper_check_plane_state() to simplify the logic
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 2/5] drm/vc4: Define missing PITCH0_SINK_PIX field Boris Brezillon
@ 2018-08-03 9:22 ` Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 4/5] drm/vc4: Move ->offsets[] adjustment out of setup_clipping_and_scaling() Boris Brezillon
` (4 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-03 9:22 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, Boris Brezillon, dri-devel
drm_atomic_helper_check_plane_state() takes care of checking the
scaling capabilities and calculating the clipped X/Y offsets for us.
Rely on this function instead of open-coding the logic.
Incidentally, it seems to fix a problem we had with negative X/Y
positioning of YUV planes.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- Grabbed authorship and dropped Eric's SoB
- Re-introduced vc4_state->crtc/src_x/y/w/h fields
---
drivers/gpu/drm/vc4/vc4_plane.c | 102 ++++++++++++++++++++--------------------
1 file changed, 52 insertions(+), 50 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index a3275fa66b7b..269a5f46b35f 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -267,30 +267,59 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
u32 subpixel_src_mask = (1 << 16) - 1;
u32 format = fb->format->format;
int num_planes = fb->format->num_planes;
- u32 h_subsample = 1;
- u32 v_subsample = 1;
- int i;
+ int min_scale = 1, max_scale = INT_MAX;
+ struct drm_crtc_state *crtc_state;
+ u32 h_subsample, v_subsample;
+ int i, ret;
+
+ crtc_state = drm_atomic_get_existing_crtc_state(state->state,
+ state->crtc);
+ if (!crtc_state) {
+ DRM_DEBUG_KMS("Invalid crtc state\n");
+ return -EINVAL;
+ }
+
+ /* No configuring scaling on the cursor plane, since it gets
+ * non-vblank-synced updates, and scaling requires LBM changes which
+ * have to be vblank-synced.
+ */
+ if (plane->type == DRM_PLANE_TYPE_CURSOR) {
+ min_scale = DRM_PLANE_HELPER_NO_SCALING;
+ max_scale = DRM_PLANE_HELPER_NO_SCALING;
+ } else {
+ min_scale = 1;
+ max_scale = INT_MAX;
+ }
+
+ ret = drm_atomic_helper_check_plane_state(state, crtc_state,
+ min_scale, max_scale,
+ true, true);
+ if (ret)
+ return ret;
+
+ h_subsample = drm_format_horz_chroma_subsampling(format);
+ v_subsample = drm_format_vert_chroma_subsampling(format);
for (i = 0; i < num_planes; i++)
vc4_state->offsets[i] = bo->paddr + fb->offsets[i];
/* We don't support subpixel source positioning for scaling. */
- if ((state->src_x & subpixel_src_mask) ||
- (state->src_y & subpixel_src_mask) ||
- (state->src_w & subpixel_src_mask) ||
- (state->src_h & subpixel_src_mask)) {
+ if ((state->src.x1 & subpixel_src_mask) ||
+ (state->src.x2 & subpixel_src_mask) ||
+ (state->src.y1 & subpixel_src_mask) ||
+ (state->src.y2 & subpixel_src_mask)) {
return -EINVAL;
}
- vc4_state->src_x = state->src_x >> 16;
- vc4_state->src_y = state->src_y >> 16;
- vc4_state->src_w[0] = state->src_w >> 16;
- vc4_state->src_h[0] = state->src_h >> 16;
+ vc4_state->src_x = state->src.x1 >> 16;
+ vc4_state->src_y = state->src.y1 >> 16;
+ vc4_state->src_w[0] = (state->src.x2 - state->src.x1) >> 16;
+ vc4_state->src_h[0] = (state->src.y2 - state->src.y1) >> 16;
- vc4_state->crtc_x = state->crtc_x;
- vc4_state->crtc_y = state->crtc_y;
- vc4_state->crtc_w = state->crtc_w;
- vc4_state->crtc_h = state->crtc_h;
+ vc4_state->crtc_x = state->dst.x1;
+ vc4_state->crtc_y = state->dst.y1;
+ vc4_state->crtc_w = state->dst.x2 - state->dst.x1;
+ vc4_state->crtc_h = state->dst.y2 - state->dst.y1;
vc4_state->x_scaling[0] = vc4_get_scaling_mode(vc4_state->src_w[0],
vc4_state->crtc_w);
@@ -303,8 +332,6 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
if (num_planes > 1) {
vc4_state->is_yuv = true;
- h_subsample = drm_format_horz_chroma_subsampling(format);
- v_subsample = drm_format_vert_chroma_subsampling(format);
vc4_state->src_w[1] = vc4_state->src_w[0] / h_subsample;
vc4_state->src_h[1] = vc4_state->src_h[0] / v_subsample;
@@ -326,39 +353,14 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
vc4_state->y_scaling[1] = VC4_SCALING_NONE;
}
- /* No configuring scaling on the cursor plane, since it gets
- non-vblank-synced updates, and scaling requires requires
- LBM changes which have to be vblank-synced.
- */
- if (plane->type == DRM_PLANE_TYPE_CURSOR && !vc4_state->is_unity)
- return -EINVAL;
-
- /* Clamp the on-screen start x/y to 0. The hardware doesn't
- * support negative y, and negative x wastes bandwidth.
- */
- if (vc4_state->crtc_x < 0) {
- for (i = 0; i < num_planes; i++) {
- u32 cpp = fb->format->cpp[i];
- u32 subs = ((i == 0) ? 1 : h_subsample);
-
- vc4_state->offsets[i] += (cpp *
- (-vc4_state->crtc_x) / subs);
- }
- vc4_state->src_w[0] += vc4_state->crtc_x;
- vc4_state->src_w[1] += vc4_state->crtc_x / h_subsample;
- vc4_state->crtc_x = 0;
- }
-
- if (vc4_state->crtc_y < 0) {
- for (i = 0; i < num_planes; i++) {
- u32 subs = ((i == 0) ? 1 : v_subsample);
-
- vc4_state->offsets[i] += (fb->pitches[i] *
- (-vc4_state->crtc_y) / subs);
- }
- vc4_state->src_h[0] += vc4_state->crtc_y;
- vc4_state->src_h[1] += vc4_state->crtc_y / v_subsample;
- vc4_state->crtc_y = 0;
+ /* Adjust the base pointer to the first pixel to be scanned out. */
+ for (i = 0; i < num_planes; i++) {
+ vc4_state->offsets[i] += (vc4_state->src_y /
+ (i ? v_subsample : 1)) *
+ fb->pitches[i];
+ vc4_state->offsets[i] += (vc4_state->src_x /
+ (i ? h_subsample : 1)) *
+ fb->format->cpp[i];
}
return 0;
--
2.14.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/5] drm/vc4: Move ->offsets[] adjustment out of setup_clipping_and_scaling()
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 2/5] drm/vc4: Define missing PITCH0_SINK_PIX field Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 3/5] drm/vc4: Use drm_atomic_helper_check_plane_state() to simplify the logic Boris Brezillon
@ 2018-08-03 9:22 ` Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 5/5] drm/vc4: Fix X/Y positioning of planes using T_TILES modifier Boris Brezillon
` (3 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-03 9:22 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, Boris Brezillon, dri-devel
The offset adjustment depends on the framebuffer modified, so let's
just move this operation in the DRM_FORMAT_MOD_LINEAR case inside
vc4_plane_mode_set().
This we'll be able to fix offset calculation for
DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED and DRM_FORMAT_MOD_BROADCOM_SANDXXX.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
---
Changes in v2:
- Fixed a typo in the commit message
---
drivers/gpu/drm/vc4/vc4_plane.c | 26 ++++++++++++++++----------
1 file changed, 16 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 269a5f46b35f..8b61574744bf 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -353,16 +353,6 @@ static int vc4_plane_setup_clipping_and_scaling(struct drm_plane_state *state)
vc4_state->y_scaling[1] = VC4_SCALING_NONE;
}
- /* Adjust the base pointer to the first pixel to be scanned out. */
- for (i = 0; i < num_planes; i++) {
- vc4_state->offsets[i] += (vc4_state->src_y /
- (i ? v_subsample : 1)) *
- fb->pitches[i];
- vc4_state->offsets[i] += (vc4_state->src_x /
- (i ? h_subsample : 1)) *
- fb->format->cpp[i];
- }
-
return 0;
}
@@ -470,6 +460,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
const struct hvs_format *format = vc4_get_hvs_format(fb->format->format);
u64 base_format_mod = fourcc_mod_broadcom_mod(fb->modifier);
int num_planes = drm_format_num_planes(format->drm);
+ u32 h_subsample, v_subsample;
bool mix_plane_alpha;
bool covers_screen;
u32 scl0, scl1, pitch0;
@@ -515,10 +506,25 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
scl1 = vc4_get_scl_field(state, 0);
}
+ h_subsample = drm_format_horz_chroma_subsampling(format->drm);
+ v_subsample = drm_format_vert_chroma_subsampling(format->drm);
+
switch (base_format_mod) {
case DRM_FORMAT_MOD_LINEAR:
tiling = SCALER_CTL0_TILING_LINEAR;
pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
+
+ /* Adjust the base pointer to the first pixel to be scanned
+ * out.
+ */
+ for (i = 0; i < num_planes; i++) {
+ vc4_state->offsets[i] += vc4_state->src_y /
+ (i ? v_subsample : 1) *
+ fb->pitches[i];
+ vc4_state->offsets[i] += vc4_state->src_x /
+ (i ? h_subsample : 1) *
+ fb->format->cpp[i];
+ }
break;
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
--
2.14.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 5/5] drm/vc4: Fix X/Y positioning of planes using T_TILES modifier
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
` (2 preceding siblings ...)
2018-08-03 9:22 ` [PATCH v2 4/5] drm/vc4: Move ->offsets[] adjustment out of setup_clipping_and_scaling() Boris Brezillon
@ 2018-08-03 9:22 ` Boris Brezillon
2018-08-06 20:02 ` [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Eric Anholt
` (2 subsequent siblings)
6 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-03 9:22 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, Boris Brezillon, dri-devel
X/Y positioning of T-format buffers is quite tricky and the current
implementation was failing to position a plane using this format
correctly when the CRTC X, Y or both X and Y offsets were negative.
It was also failing when the SRC X/Y offsets were != 0.
Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
---
Changes in v2:
- Adjusted the commit message
- Fixed the comment explaining why h_mask is 63
- Dropped Eric's SoB and grabbed authorship
---
drivers/gpu/drm/vc4/vc4_plane.c | 50 +++++++++++++++++++++++++++++++++++------
1 file changed, 43 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c
index 8b61574744bf..651f503c209a 100644
--- a/drivers/gpu/drm/vc4/vc4_plane.c
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
@@ -525,22 +525,58 @@ static int vc4_plane_mode_set(struct drm_plane *plane,
(i ? h_subsample : 1) *
fb->format->cpp[i];
}
+
break;
case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
- /* For T-tiled, the FB pitch is "how many bytes from
- * one row to the next, such that pitch * tile_h ==
- * tile_size * tiles_per_row."
- */
u32 tile_size_shift = 12; /* T tiles are 4kb */
+ /* Whole-tile offsets, mostly for setting the pitch. */
+ u32 tile_w_shift = fb->format->cpp[0] == 2 ? 6 : 5;
u32 tile_h_shift = 5; /* 16 and 32bpp are 32 pixels high */
+ u32 tile_w_mask = (1 << tile_w_shift) - 1;
+ /* The height mask on 32-bit-per-pixel tiles is 63, i.e. twice
+ * the height (in pixels) of a 4k tile.
+ */
+ u32 tile_h_mask = (2 << tile_h_shift) - 1;
+ /* For T-tiled, the FB pitch is "how many bytes from one row to
+ * the next, such that
+ *
+ * pitch * tile_h == tile_size * tiles_per_row
+ */
u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
+ u32 tiles_l = vc4_state->src_x >> tile_w_shift;
+ u32 tiles_r = tiles_w - tiles_l;
+ u32 tiles_t = vc4_state->src_y >> tile_h_shift;
+ /* Intra-tile offsets, which modify the base address (the
+ * SCALER_PITCH0_TILE_Y_OFFSET tells HVS how to walk from that
+ * base address).
+ */
+ u32 tile_y = (vc4_state->src_y >> 4) & 1;
+ u32 subtile_y = (vc4_state->src_y >> 2) & 3;
+ u32 utile_y = vc4_state->src_y & 3;
+ u32 x_off = vc4_state->src_x & tile_w_mask;
+ u32 y_off = vc4_state->src_y & tile_h_mask;
tiling = SCALER_CTL0_TILING_256B_OR_T;
+ pitch0 = (VC4_SET_FIELD(x_off, SCALER_PITCH0_SINK_PIX) |
+ VC4_SET_FIELD(y_off, SCALER_PITCH0_TILE_Y_OFFSET) |
+ VC4_SET_FIELD(tiles_l, SCALER_PITCH0_TILE_WIDTH_L) |
+ VC4_SET_FIELD(tiles_r, SCALER_PITCH0_TILE_WIDTH_R));
+ vc4_state->offsets[0] += tiles_t * (tiles_w << tile_size_shift);
+ vc4_state->offsets[0] += subtile_y << 8;
+ vc4_state->offsets[0] += utile_y << 4;
+
+ /* Rows of tiles alternate left-to-right and right-to-left. */
+ if (tiles_t & 1) {
+ pitch0 |= SCALER_PITCH0_TILE_INITIAL_LINE_DIR;
+ vc4_state->offsets[0] += (tiles_w - tiles_l) <<
+ tile_size_shift;
+ vc4_state->offsets[0] -= (1 + !tile_y) << 10;
+ } else {
+ vc4_state->offsets[0] += tiles_l << tile_size_shift;
+ vc4_state->offsets[0] += tile_y << 10;
+ }
- pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
- VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
- VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
break;
}
--
2.14.1
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^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
` (3 preceding siblings ...)
2018-08-03 9:22 ` [PATCH v2 5/5] drm/vc4: Fix X/Y positioning of planes using T_TILES modifier Boris Brezillon
@ 2018-08-06 20:02 ` Eric Anholt
2018-08-06 20:12 ` Boris Brezillon
2018-08-24 7:09 ` Boris Brezillon
2018-08-27 19:09 ` Boris Brezillon
6 siblings, 1 reply; 11+ messages in thread
From: Eric Anholt @ 2018-08-06 20:02 UTC (permalink / raw)
Cc: David Airlie, Boris Brezillon, dri-devel
[-- Attachment #1.1: Type: text/plain, Size: 350 bytes --]
Boris Brezillon <boris.brezillon@bootlin.com> writes:
> From: Eric Anholt <eric@anholt.net>
>
> Y_OFFSET field starts at bit 8 not 7.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Your changes in this series have my r-b. Time to add your ack to my
changes in this series and push?
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 832 bytes --]
[-- Attachment #2: Type: text/plain, Size: 160 bytes --]
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-06 20:02 ` [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Eric Anholt
@ 2018-08-06 20:12 ` Boris Brezillon
2018-08-07 0:41 ` Eric Anholt
0 siblings, 1 reply; 11+ messages in thread
From: Boris Brezillon @ 2018-08-06 20:12 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, dri-devel
On Mon, 06 Aug 2018 13:02:48 -0700
Eric Anholt <eric@anholt.net> wrote:
> Boris Brezillon <boris.brezillon@bootlin.com> writes:
>
> > From: Eric Anholt <eric@anholt.net>
> >
> > Y_OFFSET field starts at bit 8 not 7.
> >
> > Signed-off-by: Eric Anholt <eric@anholt.net>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
>
> Your changes in this series have my r-b. Time to add your ack to my
Adding SoB implicitly means A-b for me, but I can add them if you
prefer.
> changes in this series and push?
Sure, I was just waiting for your green light after the changes I've
done in patch 3.
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-06 20:12 ` Boris Brezillon
@ 2018-08-07 0:41 ` Eric Anholt
0 siblings, 0 replies; 11+ messages in thread
From: Eric Anholt @ 2018-08-07 0:41 UTC (permalink / raw)
To: Boris Brezillon; +Cc: David Airlie, dri-devel
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Boris Brezillon <boris.brezillon@bootlin.com> writes:
> On Mon, 06 Aug 2018 13:02:48 -0700
> Eric Anholt <eric@anholt.net> wrote:
>
>> Boris Brezillon <boris.brezillon@bootlin.com> writes:
>>
>> > From: Eric Anholt <eric@anholt.net>
>> >
>> > Y_OFFSET field starts at bit 8 not 7.
>> >
>> > Signed-off-by: Eric Anholt <eric@anholt.net>
>> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
>>
>> Your changes in this series have my r-b. Time to add your ack to my
>
> Adding SoB implicitly means A-b for me, but I can add them if you
> prefer.
Yeah, I guess that does, you're right.
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
` (4 preceding siblings ...)
2018-08-06 20:02 ` [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Eric Anholt
@ 2018-08-24 7:09 ` Boris Brezillon
2018-08-24 7:42 ` Boris Brezillon
2018-08-27 19:09 ` Boris Brezillon
6 siblings, 1 reply; 11+ messages in thread
From: Boris Brezillon @ 2018-08-24 7:09 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, dri-devel
On Fri, 3 Aug 2018 11:22:27 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> From: Eric Anholt <eric@anholt.net>
>
> Y_OFFSET field starts at bit 8 not 7.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
As discussed with Eric 2 weeks ago, I'm about to apply this series to
drm-misc-fixes. The rational behind this decision is that those patches
are actually fixing the driver, even though they don't all have Fixes
and Cc-stable tags.
Daniel, any objection?
> ---
> Changes in v2:
> - None
> ---
> drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> index d6864fa4bd14..ccbd6b377ffe 100644
> --- a/drivers/gpu/drm/vc4/vc4_regs.h
> +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
> #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
> #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
> /* Y offset within a tile. */
> -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
> -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
> +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
> +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
> #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
> #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-24 7:09 ` Boris Brezillon
@ 2018-08-24 7:42 ` Boris Brezillon
0 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-24 7:42 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, dri-devel
On Fri, 24 Aug 2018 09:09:26 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> On Fri, 3 Aug 2018 11:22:27 +0200
> Boris Brezillon <boris.brezillon@bootlin.com> wrote:
>
> > From: Eric Anholt <eric@anholt.net>
> >
> > Y_OFFSET field starts at bit 8 not 7.
> >
> > Signed-off-by: Eric Anholt <eric@anholt.net>
> > Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
>
> As discussed with Eric 2 weeks ago, I'm about to apply this series to
> drm-misc-fixes. The rational behind this decision is that those patches
> are actually fixing the driver, even though they don't all have Fixes
> and Cc-stable tags.
>
> Daniel, any objection?
Actually it conflicts in a few places because this series was based on
drm-misc-next, so I'll wait for 4.19-rc1 to be back-merged in
drm-misc-fixes before applying the patchset.
>
> > ---
> > Changes in v2:
> > - None
> > ---
> > drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
> > 1 file changed, 2 insertions(+), 2 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> > index d6864fa4bd14..ccbd6b377ffe 100644
> > --- a/drivers/gpu/drm/vc4/vc4_regs.h
> > +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> > @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
> > #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
> > #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
> > /* Y offset within a tile. */
> > -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
> > -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
> > +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
> > +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
> > #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
> > #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
> >
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
` (5 preceding siblings ...)
2018-08-24 7:09 ` Boris Brezillon
@ 2018-08-27 19:09 ` Boris Brezillon
6 siblings, 0 replies; 11+ messages in thread
From: Boris Brezillon @ 2018-08-27 19:09 UTC (permalink / raw)
To: Eric Anholt; +Cc: David Airlie, dri-devel
On Fri, 3 Aug 2018 11:22:27 +0200
Boris Brezillon <boris.brezillon@bootlin.com> wrote:
> From: Eric Anholt <eric@anholt.net>
>
> Y_OFFSET field starts at bit 8 not 7.
>
> Signed-off-by: Eric Anholt <eric@anholt.net>
> Signed-off-by: Boris Brezillon <boris.brezillon@bootlin.com>
Queued the series to drm-misc-fixes.
> ---
> Changes in v2:
> - None
> ---
> drivers/gpu/drm/vc4/vc4_regs.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h
> index d6864fa4bd14..ccbd6b377ffe 100644
> --- a/drivers/gpu/drm/vc4/vc4_regs.h
> +++ b/drivers/gpu/drm/vc4/vc4_regs.h
> @@ -1043,8 +1043,8 @@ enum hvs_pixel_format {
> #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
> #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)
> /* Y offset within a tile. */
> -#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 7)
> -#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 7
> +#define SCALER_PITCH0_TILE_Y_OFFSET_MASK VC4_MASK(13, 8)
> +#define SCALER_PITCH0_TILE_Y_OFFSET_SHIFT 8
> #define SCALER_PITCH0_TILE_WIDTH_R_MASK VC4_MASK(6, 0)
> #define SCALER_PITCH0_TILE_WIDTH_R_SHIFT 0
>
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-08-27 19:09 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-03 9:22 [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 2/5] drm/vc4: Define missing PITCH0_SINK_PIX field Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 3/5] drm/vc4: Use drm_atomic_helper_check_plane_state() to simplify the logic Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 4/5] drm/vc4: Move ->offsets[] adjustment out of setup_clipping_and_scaling() Boris Brezillon
2018-08-03 9:22 ` [PATCH v2 5/5] drm/vc4: Fix X/Y positioning of planes using T_TILES modifier Boris Brezillon
2018-08-06 20:02 ` [PATCH v2 1/5] drm/vc4: Fix TILE_Y_OFFSET definitions Eric Anholt
2018-08-06 20:12 ` Boris Brezillon
2018-08-07 0:41 ` Eric Anholt
2018-08-24 7:09 ` Boris Brezillon
2018-08-24 7:42 ` Boris Brezillon
2018-08-27 19:09 ` Boris Brezillon
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