* [PATCH 1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
@ 2018-08-16 1:05 Dhinakaran Pandiyan
2018-08-16 1:05 ` [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts Dhinakaran Pandiyan
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Dhinakaran Pandiyan @ 2018-08-16 1:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
We print the last attempted entry and last exit timestamps only when
IRQ debug is requested. This check was missed when new debug flags were
added in 'commit c44301fce614 ("drm/i915: Allow control of PSR at
runtime through debugfs, v6")
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 26b7e5276b15..374b550d9a4f 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2735,7 +2735,7 @@ static int i915_edp_psr_status(struct seq_file *m, void *data)
psr_source_status(dev_priv, m);
mutex_unlock(&dev_priv->psr.lock);
- if (READ_ONCE(dev_priv->psr.debug)) {
+ if (READ_ONCE(dev_priv->psr.debug) & I915_PSR_DEBUG_IRQ) {
seq_printf(m, "Last attempted entry at: %lld\n",
dev_priv->psr.last_entry_attempt);
seq_printf(m, "Last exit at: %lld\n",
--
2.14.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts.
2018-08-16 1:05 [PATCH 1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Dhinakaran Pandiyan
@ 2018-08-16 1:05 ` Dhinakaran Pandiyan
2018-08-20 23:16 ` Dhinakaran Pandiyan
2018-08-16 1:32 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Patchwork
2018-08-16 6:43 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 1 reply; 5+ messages in thread
From: Dhinakaran Pandiyan @ 2018-08-16 1:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Dhinakaran Pandiyan
gen8_de_irq_postinstall() wasn't masking the IRQ bit before passing the
debug flag to psr_irq_control(). This check was missed when new debug bits
were defined in 'commit c44301fce614 ("drm/i915: Allow control of PSR at
runtime through debugfs, v6")'. Instead of ANDing the irq bit in all the
callers, move it to the callee.
Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 2 +-
drivers/gpu/drm/i915/intel_drv.h | 2 +-
drivers/gpu/drm/i915/intel_psr.c | 6 +++---
3 files changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b2c9838442bc..8084e35b25c5 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct drm_device *dev)
if (IS_HASWELL(dev_priv)) {
gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ);
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
display_mask |= DE_EDP_PSR_INT_HSW;
}
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 7b984aefce98..bc1c53c5f4dd 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -1944,7 +1944,7 @@ void intel_psr_flush(struct drm_i915_private *dev_priv,
void intel_psr_init(struct drm_i915_private *dev_priv);
void intel_psr_compute_config(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state);
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug);
+void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug);
void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32 psr_iir);
void intel_psr_short_pulse(struct intel_dp *intel_dp);
int intel_psr_wait_for_idle(const struct intel_crtc_state *new_crtc_state);
diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 7560c65f50ad..df79020045a5 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -79,7 +79,7 @@ static bool intel_psr2_enabled(struct drm_i915_private *dev_priv,
}
}
-void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
+void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32 debug)
{
u32 debug_mask, mask;
@@ -100,7 +100,7 @@ void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool debug)
EDP_PSR_PRE_ENTRY(TRANSCODER_C);
}
- if (debug)
+ if (debug & I915_PSR_DEBUG_IRQ)
mask |= debug_mask;
I915_WRITE(EDP_PSR_IMR, ~mask);
@@ -901,7 +901,7 @@ int intel_psr_set_debugfs_mode(struct drm_i915_private *dev_priv,
if (crtc)
dev_priv->psr.psr2_enabled = intel_psr2_enabled(dev_priv, crtc_state);
- intel_psr_irq_control(dev_priv, dev_priv->psr.debug & I915_PSR_DEBUG_IRQ);
+ intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
if (dev_priv->psr.prepared && enable)
intel_psr_enable_locked(dev_priv, crtc_state);
--
2.14.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
2018-08-16 1:05 [PATCH 1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Dhinakaran Pandiyan
2018-08-16 1:05 ` [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts Dhinakaran Pandiyan
@ 2018-08-16 1:32 ` Patchwork
2018-08-16 6:43 ` ✓ Fi.CI.IGT: " Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-08-16 1:32 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
URL : https://patchwork.freedesktop.org/series/48291/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4676 -> Patchwork_9959 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48291/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9959 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_chamelium@dp-edid-read:
fi-kbl-7500u: PASS -> FAIL (fdo#106766)
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
{fi-byt-clapper}: PASS -> FAIL (fdo#103191, fdo#107362)
==== Possible fixes ====
igt@drv_selftest@live_coherency:
fi-gdg-551: DMESG-FAIL (fdo#107164) -> PASS
igt@drv_selftest@live_hangcheck:
fi-kbl-7567u: DMESG-FAIL (fdo#106947, fdo#106560) -> PASS
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
fi-snb-2520m: INCOMPLETE (fdo#103713) -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#106766 https://bugs.freedesktop.org/show_bug.cgi?id=106766
fdo#106947 https://bugs.freedesktop.org/show_bug.cgi?id=106947
fdo#107164 https://bugs.freedesktop.org/show_bug.cgi?id=107164
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
== Participating hosts (53 -> 48) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4676 -> Patchwork_9959
CI_DRM_4676: 8171ee8227a2633ffb5808841f08cc1a3bfaffbb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4599: 940cb5f46433a8ae48d21c6672e4d8ecd1358bbf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9959: fbec1e114dac6cb4f7a3beff89271b5a7650a63d @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
fbec1e114dac drm/i915/psr: Mask PSR irq bits when re-enabling interrupts.
d9cc16e9b591 drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9959/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
2018-08-16 1:05 [PATCH 1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Dhinakaran Pandiyan
2018-08-16 1:05 ` [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts Dhinakaran Pandiyan
2018-08-16 1:32 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Patchwork
@ 2018-08-16 6:43 ` Patchwork
2 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-08-16 6:43 UTC (permalink / raw)
To: Dhinakaran Pandiyan; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit
URL : https://patchwork.freedesktop.org/series/48291/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4676_full -> Patchwork_9959_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_9959_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_softpin@noreloc-s3:
shard-kbl: PASS -> INCOMPLETE (fdo#107556, fdo#103665)
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-glk: PASS -> FAIL (fdo#102887, fdo#105363)
igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-draw-mmap-cpu:
shard-glk: PASS -> FAIL (fdo#103167)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
igt@perf@short-reads:
shard-apl: PASS -> FAIL (fdo#103183)
fdo#102887 https://bugs.freedesktop.org/show_bug.cgi?id=102887
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103183 https://bugs.freedesktop.org/show_bug.cgi?id=103183
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4676 -> Patchwork_9959
CI_DRM_4676: 8171ee8227a2633ffb5808841f08cc1a3bfaffbb @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4599: 940cb5f46433a8ae48d21c6672e4d8ecd1358bbf @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9959: fbec1e114dac6cb4f7a3beff89271b5a7650a63d @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9959/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts.
2018-08-16 1:05 ` [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts Dhinakaran Pandiyan
@ 2018-08-20 23:16 ` Dhinakaran Pandiyan
0 siblings, 0 replies; 5+ messages in thread
From: Dhinakaran Pandiyan @ 2018-08-20 23:16 UTC (permalink / raw)
To: intel-gfx
On Wed, 2018-08-15 at 18:05 -0700, Dhinakaran Pandiyan wrote:
> gen8_de_irq_postinstall() wasn't masking the IRQ bit before passing
> the
> debug flag to psr_irq_control(). This check was missed when new debug
> bits
> were defined in 'commit c44301fce614 ("drm/i915: Allow control of
> PSR at
> runtime through debugfs, v6")'. Instead of ANDing the irq bit in all
> the
> callers, move it to the callee.
>
> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> via IRC "[8/20/18 11:58] <mlankhorst> or irc r-b"
> Signed-off-by: Dhinakaran Pandiyan <dhinakaran.pandiyan@intel.com>
> ---
> drivers/gpu/drm/i915/i915_irq.c | 2 +-
> drivers/gpu/drm/i915/intel_drv.h | 2 +-
> drivers/gpu/drm/i915/intel_psr.c | 6 +++---
> 3 files changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_irq.c
> b/drivers/gpu/drm/i915/i915_irq.c
> index b2c9838442bc..8084e35b25c5 100644
> --- a/drivers/gpu/drm/i915/i915_irq.c
> +++ b/drivers/gpu/drm/i915/i915_irq.c
> @@ -4048,7 +4048,7 @@ static int ironlake_irq_postinstall(struct
> drm_device *dev)
>
> if (IS_HASWELL(dev_priv)) {
> gen3_assert_iir_is_zero(dev_priv, EDP_PSR_IIR);
> - intel_psr_irq_control(dev_priv, dev_priv->psr.debug
> & I915_PSR_DEBUG_IRQ);
> + intel_psr_irq_control(dev_priv, dev_priv-
> >psr.debug);
> display_mask |= DE_EDP_PSR_INT_HSW;
> }
>
> diff --git a/drivers/gpu/drm/i915/intel_drv.h
> b/drivers/gpu/drm/i915/intel_drv.h
> index 7b984aefce98..bc1c53c5f4dd 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -1944,7 +1944,7 @@ void intel_psr_flush(struct drm_i915_private
> *dev_priv,
> void intel_psr_init(struct drm_i915_private *dev_priv);
> void intel_psr_compute_config(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state);
> -void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug);
> +void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> debug);
> void intel_psr_irq_handler(struct drm_i915_private *dev_priv, u32
> psr_iir);
> void intel_psr_short_pulse(struct intel_dp *intel_dp);
> int intel_psr_wait_for_idle(const struct intel_crtc_state
> *new_crtc_state);
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 7560c65f50ad..df79020045a5 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -79,7 +79,7 @@ static bool intel_psr2_enabled(struct
> drm_i915_private *dev_priv,
> }
> }
>
> -void intel_psr_irq_control(struct drm_i915_private *dev_priv, bool
> debug)
> +void intel_psr_irq_control(struct drm_i915_private *dev_priv, u32
> debug)
> {
> u32 debug_mask, mask;
>
> @@ -100,7 +100,7 @@ void intel_psr_irq_control(struct
> drm_i915_private *dev_priv, bool debug)
> EDP_PSR_PRE_ENTRY(TRANSCODER_C);
> }
>
> - if (debug)
> + if (debug & I915_PSR_DEBUG_IRQ)
> mask |= debug_mask;
>
> I915_WRITE(EDP_PSR_IMR, ~mask);
> @@ -901,7 +901,7 @@ int intel_psr_set_debugfs_mode(struct
> drm_i915_private *dev_priv,
> if (crtc)
> dev_priv->psr.psr2_enabled =
> intel_psr2_enabled(dev_priv, crtc_state);
>
> - intel_psr_irq_control(dev_priv, dev_priv->psr.debug &
> I915_PSR_DEBUG_IRQ);
> + intel_psr_irq_control(dev_priv, dev_priv->psr.debug);
>
> if (dev_priv->psr.prepared && enable)
> intel_psr_enable_locked(dev_priv, crtc_state);
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-08-20 23:16 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-16 1:05 [PATCH 1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Dhinakaran Pandiyan
2018-08-16 1:05 ` [PATCH 2/2] drm/i915/psr: Mask PSR irq bits when re-enabling interrupts Dhinakaran Pandiyan
2018-08-20 23:16 ` Dhinakaran Pandiyan
2018-08-16 1:32 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/psr: Add missing check for I915_PSR_DEBUG_IRQ bit Patchwork
2018-08-16 6:43 ` ✓ Fi.CI.IGT: " Patchwork
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