[PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[Christian König]

Just another leftover from radeon.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
 2 files changed, 1 insertion(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 662aec5c81d4..73b8dcaf66e6 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 {
 	struct amdgpu_bo_param bp;
 	struct amdgpu_bo *root;
-	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
-		AMDGPU_VM_PTE_COUNT(adev) * 8);
 	unsigned long size;
 	uint64_t flags;
 	int r, i;
@@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
 	memset(&bp, 0, sizeof(bp));
 	bp.size = size;
-	bp.byte_align = align;
+	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
 	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
 	bp.flags = flags;
 	bp.type = ttm_bo_type_kernel;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
index 1162c2bf3138..1c9049feaaea 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
@@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
 /* number of entries in page table */
 #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
 
-/* PTBs (Page Table Blocks) need to be aligned to 32K */
-#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
-
 #define AMDGPU_PTE_VALID	(1ULL << 0)
 #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
 #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
-- 
2.17.1

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[PATCH 02/11] drm/amdgpu: validate the VM root PD from the VM code

[Christian König]

Preparation for following changes. This validates the root PD twice,
but the overhead of that should be minimal.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 73b8dcaf66e6..53ce9982a5ee 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -291,11 +291,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
 		struct amdgpu_bo *bo = bo_base->bo;
 
-		if (bo->parent) {
-			r = validate(param, bo);
-			if (r)
-				break;
+		r = validate(param, bo);
+		if (r)
+			break;
 
+		if (bo->parent) {
 			spin_lock(&glob->lru_lock);
 			ttm_bo_move_to_lru_tail(&bo->tbo);
 			if (bo->shadow)
-- 
2.17.1

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[PATCH 03/11] drm/amdgpu: cleanup VM handling in the CS a bit

[Christian König]

Add a helper function for getting the root PD addr and cleanup join the
two VM related functions and cleanup the function name.

No functional change.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 160 ++++++++++++-------------
 1 file changed, 74 insertions(+), 86 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index d42d1c8f78f6..17bf63f93c93 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -804,8 +804,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
 	amdgpu_bo_unref(&parser->uf_entry.robj);
 }
 
-static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
+static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 {
+	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
 	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 	struct amdgpu_device *adev = p->adev;
 	struct amdgpu_vm *vm = &fpriv->vm;
@@ -814,6 +815,71 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 	struct amdgpu_bo *bo;
 	int r;
 
+	/* Only for UVD/VCE VM emulation */
+	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
+		unsigned i, j;
+
+		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
+			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
+			struct amdgpu_bo_va_mapping *m;
+			struct amdgpu_bo *aobj = NULL;
+			struct amdgpu_cs_chunk *chunk;
+			uint64_t offset, va_start;
+			struct amdgpu_ib *ib;
+			uint8_t *kptr;
+
+			chunk = &p->chunks[i];
+			ib = &p->job->ibs[j];
+			chunk_ib = chunk->kdata;
+
+			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
+				continue;
+
+			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
+			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
+			if (r) {
+				DRM_ERROR("IB va_start is invalid\n");
+				return r;
+			}
+
+			if ((va_start + chunk_ib->ib_bytes) >
+			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
+				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
+				return -EINVAL;
+			}
+
+			/* the IB should be reserved at this point */
+			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
+			if (r) {
+				return r;
+			}
+
+			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
+			kptr += va_start - offset;
+
+			if (ring->funcs->parse_cs) {
+				memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
+				amdgpu_bo_kunmap(aobj);
+
+				r = amdgpu_ring_parse_cs(ring, p, j);
+				if (r)
+					return r;
+			} else {
+				ib->ptr = (uint32_t *)kptr;
+				r = amdgpu_ring_patch_cs_in_place(ring, p, j);
+				amdgpu_bo_kunmap(aobj);
+				if (r)
+					return r;
+			}
+
+			j++;
+		}
+	}
+
+	if (!p->job->vm)
+		return amdgpu_cs_sync_rings(p);
+
+
 	r = amdgpu_vm_clear_freed(adev, vm, NULL);
 	if (r)
 		return r;
@@ -876,6 +942,12 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 	if (r)
 		return r;
 
+	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
+	if (r)
+		return r;
+
+	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
+
 	if (amdgpu_vm_debug) {
 		/* Invalidate all BOs to test for userspace bugs */
 		amdgpu_bo_list_for_each_entry(e, p->bo_list) {
@@ -887,90 +959,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
 		}
 	}
 
-	return r;
-}
-
-static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
-				 struct amdgpu_cs_parser *p)
-{
-	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
-	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
-	struct amdgpu_vm *vm = &fpriv->vm;
-	int r;
-
-	/* Only for UVD/VCE VM emulation */
-	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
-		unsigned i, j;
-
-		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
-			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
-			struct amdgpu_bo_va_mapping *m;
-			struct amdgpu_bo *aobj = NULL;
-			struct amdgpu_cs_chunk *chunk;
-			uint64_t offset, va_start;
-			struct amdgpu_ib *ib;
-			uint8_t *kptr;
-
-			chunk = &p->chunks[i];
-			ib = &p->job->ibs[j];
-			chunk_ib = chunk->kdata;
-
-			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
-				continue;
-
-			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
-			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
-			if (r) {
-				DRM_ERROR("IB va_start is invalid\n");
-				return r;
-			}
-
-			if ((va_start + chunk_ib->ib_bytes) >
-			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
-				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
-				return -EINVAL;
-			}
-
-			/* the IB should be reserved at this point */
-			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
-			if (r) {
-				return r;
-			}
-
-			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
-			kptr += va_start - offset;
-
-			if (ring->funcs->parse_cs) {
-				memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
-				amdgpu_bo_kunmap(aobj);
-
-				r = amdgpu_ring_parse_cs(ring, p, j);
-				if (r)
-					return r;
-			} else {
-				ib->ptr = (uint32_t *)kptr;
-				r = amdgpu_ring_patch_cs_in_place(ring, p, j);
-				amdgpu_bo_kunmap(aobj);
-				if (r)
-					return r;
-			}
-
-			j++;
-		}
-	}
-
-	if (p->job->vm) {
-		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
-
-		r = amdgpu_bo_vm_update_pte(p);
-		if (r)
-			return r;
-
-		r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
-		if (r)
-			return r;
-	}
-
 	return amdgpu_cs_sync_rings(p);
 }
 
@@ -1307,7 +1295,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 	for (i = 0; i < parser.job->num_ibs; i++)
 		trace_amdgpu_cs(&parser, i);
 
-	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
+	r = amdgpu_cs_vm_handling(&parser);
 	if (r)
 		goto out;
 
-- 
2.17.1

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[PATCH 04/11] drm/amdgpu: move setting the GART addr into TTM

[Christian König]

Move setting the GART addr for window based copies into the TTM code who
uses it.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 --
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++-
 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index 391e2f7c03aa..239ccbae09bc 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -82,8 +82,6 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
 	r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
 	if (r)
 		kfree(*job);
-	else
-		(*job)->vm_pd_addr = adev->gart.table_addr;
 
 	return r;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index c6611cff64c8..b4333f60ed8b 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2048,7 +2048,10 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
 	if (r)
 		return r;
 
-	job->vm_needs_flush = vm_needs_flush;
+	if (vm_needs_flush) {
+		job->vm_pd_addr = adev->gart.table_addr;
+		job->vm_needs_flush = true;
+	}
 	if (resv) {
 		r = amdgpu_sync_resv(adev, &job->sync, resv,
 				     AMDGPU_FENCE_OWNER_UNDEFINED,
-- 
2.17.1

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[PATCH 05/11] drm/amdgpu: rename gart.robj into gart.bo

[Christian König]

sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.h

Just cleaning up radeon leftovers.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 32 ++++++++++++------------
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h |  2 +-
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |  4 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |  4 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |  4 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  4 +--
 6 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index a54d5655a191..f5cb5e2856c1 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -112,7 +112,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		struct amdgpu_bo_param bp;
 
 		memset(&bp, 0, sizeof(bp));
@@ -123,7 +123,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
 			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
 		bp.type = ttm_bo_type_kernel;
 		bp.resv = NULL;
-		r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
+		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
 		if (r) {
 			return r;
 		}
@@ -145,19 +145,19 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
 {
 	int r;
 
-	r = amdgpu_bo_reserve(adev->gart.robj, false);
+	r = amdgpu_bo_reserve(adev->gart.bo, false);
 	if (unlikely(r != 0))
 		return r;
-	r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
+	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
 	if (r) {
-		amdgpu_bo_unreserve(adev->gart.robj);
+		amdgpu_bo_unreserve(adev->gart.bo);
 		return r;
 	}
-	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
+	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
 	if (r)
-		amdgpu_bo_unpin(adev->gart.robj);
-	amdgpu_bo_unreserve(adev->gart.robj);
-	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
+		amdgpu_bo_unpin(adev->gart.bo);
+	amdgpu_bo_unreserve(adev->gart.bo);
+	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	return r;
 }
 
@@ -173,14 +173,14 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		return;
 	}
-	r = amdgpu_bo_reserve(adev->gart.robj, true);
+	r = amdgpu_bo_reserve(adev->gart.bo, true);
 	if (likely(r == 0)) {
-		amdgpu_bo_kunmap(adev->gart.robj);
-		amdgpu_bo_unpin(adev->gart.robj);
-		amdgpu_bo_unreserve(adev->gart.robj);
+		amdgpu_bo_kunmap(adev->gart.bo);
+		amdgpu_bo_unpin(adev->gart.bo);
+		amdgpu_bo_unreserve(adev->gart.bo);
 		adev->gart.ptr = NULL;
 	}
 }
@@ -196,10 +196,10 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
  */
 void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
 {
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		return;
 	}
-	amdgpu_bo_unref(&adev->gart.robj);
+	amdgpu_bo_unref(&adev->gart.bo);
 }
 
 /*
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index 9f9e9dc87da1..d7b7c2d408d5 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -41,7 +41,7 @@ struct amdgpu_bo;
 
 struct amdgpu_gart {
 	u64				table_addr;
-	struct amdgpu_bo		*robj;
+	struct amdgpu_bo		*bo;
 	void				*ptr;
 	unsigned			num_gpu_pages;
 	unsigned			num_cpu_pages;
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c14cf1c5bf57..c50bd0c46508 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -497,7 +497,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 	int r, i;
 	u32 field;
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
@@ -588,7 +588,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj) {
+	if (adev->gart.bo) {
 		dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index 0c3a1618c3b7..c7cbd9f06892 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -607,7 +607,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 	int r, i;
 	u32 tmp, field;
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
@@ -708,7 +708,7 @@ static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj) {
+	if (adev->gart.bo) {
 		WARN(1, "R600 PCIE GART already initialized\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 274c9321d06c..21e3d9af370d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -809,7 +809,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 	int r, i;
 	u32 tmp, field;
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
@@ -927,7 +927,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj) {
+	if (adev->gart.bo) {
 		WARN(1, "R600 PCIE GART already initialized\n");
 		return 0;
 	}
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 25f614b91a9b..eb1936223748 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -843,7 +843,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
 {
 	int r;
 
-	if (adev->gart.robj) {
+	if (adev->gart.bo) {
 		WARN(1, "VEGA10 PCIE GART already initialized\n");
 		return 0;
 	}
@@ -1081,7 +1081,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 						golden_settings_vega10_hdp,
 						ARRAY_SIZE(golden_settings_vega10_hdp));
 
-	if (adev->gart.robj == NULL) {
+	if (adev->gart.bo == NULL) {
 		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
 		return -EINVAL;
 	}
-- 
2.17.1

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[PATCH 06/11] drm/amdgpu: remove gart.table_addr

[Christian König]

We can easily figure out the address on the fly.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h | 1 -
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c  | 4 ++--
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c | 7 +++----
 drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    | 9 +++++----
 drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    | 9 +++++----
 drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    | 9 +++++----
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    | 2 +-
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c  | 7 +++----
 9 files changed, 24 insertions(+), 25 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
index f5cb5e2856c1..11fea28f8ad3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
@@ -157,7 +157,6 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
 	if (r)
 		amdgpu_bo_unpin(adev->gart.bo);
 	amdgpu_bo_unreserve(adev->gart.bo);
-	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	return r;
 }
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
index d7b7c2d408d5..9ff62887e4e3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
@@ -40,7 +40,6 @@ struct amdgpu_bo;
 #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE)
 
 struct amdgpu_gart {
-	u64				table_addr;
 	struct amdgpu_bo		*bo;
 	void				*ptr;
 	unsigned			num_gpu_pages;
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index b4333f60ed8b..e7f73deed975 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1988,7 +1988,7 @@ static int amdgpu_map_buffer(struct ttm_buffer_object *bo,
 	src_addr = num_dw * 4;
 	src_addr += job->ibs[0].gpu_addr;
 
-	dst_addr = adev->gart.table_addr;
+	dst_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	dst_addr += window * AMDGPU_GTT_MAX_TRANSFER_SIZE * 8;
 	amdgpu_emit_copy_buffer(adev, &job->ibs[0], src_addr,
 				dst_addr, num_bytes);
@@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
 		return r;
 
 	if (vm_needs_flush) {
-		job->vm_pd_addr = adev->gart.table_addr;
+		job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 		job->vm_needs_flush = true;
 	}
 	if (resv) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index acfbd2d749cf..2baab7e69ef5 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -37,11 +37,10 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-	uint64_t value;
+	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
 
-	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-	value = adev->gart.table_addr - adev->gmc.vram_start
-		+ adev->vm_manager.vram_base_offset;
+	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
 	value &= 0x0000FFFFFFFFF000ULL;
 	value |= 0x1; /*valid bit*/
 
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
index c50bd0c46508..8b313cd00b7e 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
@@ -494,6 +494,7 @@ static void gmc_v6_0_set_prt(struct amdgpu_device *adev, bool enable)
 
 static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 {
+	uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	int r, i;
 	u32 field;
 
@@ -532,7 +533,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 	/* setup context0 */
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 			(u32)(adev->dummy_page_addr >> 12));
 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -556,10 +557,10 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 	for (i = 1; i < 16; i++) {
 		if (i < 8)
 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 		else
 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 	}
 
 	/* enable context1-15 */
@@ -579,7 +580,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
 	gmc_v6_0_flush_gpu_tlb(adev, 0);
 	dev_info(adev->dev, "PCIE GART of %uM enabled (table at 0x%016llX).\n",
 		 (unsigned)(adev->gmc.gart_size >> 20),
-		 (unsigned long long)adev->gart.table_addr);
+		 (unsigned long long)table_addr);
 	adev->gart.ready = true;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
index c7cbd9f06892..c32d1d20f657 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
@@ -604,6 +604,7 @@ static void gmc_v7_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 {
+	uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	int r, i;
 	u32 tmp, field;
 
@@ -645,7 +646,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 	/* setup context0 */
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 			(u32)(adev->dummy_page_addr >> 12));
 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -669,10 +670,10 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 	for (i = 1; i < 16; i++) {
 		if (i < 8)
 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 		else
 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 	}
 
 	/* enable context1-15 */
@@ -699,7 +700,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
 	gmc_v7_0_flush_gpu_tlb(adev, 0);
 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 		 (unsigned)(adev->gmc.gart_size >> 20),
-		 (unsigned long long)adev->gart.table_addr);
+		 (unsigned long long)table_addr);
 	adev->gart.ready = true;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
index 21e3d9af370d..056cc20c2bfb 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
@@ -806,6 +806,7 @@ static void gmc_v8_0_set_prt(struct amdgpu_device *adev, bool enable)
  */
 static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 {
+	uint64_t table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
 	int r, i;
 	u32 tmp, field;
 
@@ -863,7 +864,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 	/* setup context0 */
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12);
 	WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12);
-	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, adev->gart.table_addr >> 12);
+	WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR, table_addr >> 12);
 	WREG32(mmVM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 			(u32)(adev->dummy_page_addr >> 12));
 	WREG32(mmVM_CONTEXT0_CNTL2, 0);
@@ -887,10 +888,10 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 	for (i = 1; i < 16; i++) {
 		if (i < 8)
 			WREG32(mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + i,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 		else
 			WREG32(mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + i - 8,
-			       adev->gart.table_addr >> 12);
+			       table_addr >> 12);
 	}
 
 	/* enable context1-15 */
@@ -918,7 +919,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
 	gmc_v8_0_flush_gpu_tlb(adev, 0);
 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 		 (unsigned)(adev->gmc.gart_size >> 20),
-		 (unsigned long long)adev->gart.table_addr);
+		 (unsigned long long)table_addr);
 	adev->gart.ready = true;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index eb1936223748..e412eb8e347c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -1125,7 +1125,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
 
 	DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n",
 		 (unsigned)(adev->gmc.gart_size >> 20),
-		 (unsigned long long)adev->gart.table_addr);
+		 (unsigned long long)amdgpu_bo_gpu_offset(adev->gart.bo));
 	adev->gart.ready = true;
 	return 0;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index e70a0d4d6db4..800ec4687f13 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -47,11 +47,10 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
 
 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-	uint64_t value;
+	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
 
-	BUG_ON(adev->gart.table_addr & (~0x0000FFFFFFFFF000ULL));
-	value = adev->gart.table_addr - adev->gmc.vram_start +
-		adev->vm_manager.vram_base_offset;
+	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
+	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
 	value &= 0x0000FFFFFFFFF000ULL;
 	value |= 0x1; /* valid bit */
 
-- 
2.17.1

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[PATCH 07/11] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Christian König]

Add the necessary handling.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index e412eb8e347c..3393a329fc9c 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -571,7 +571,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
 static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
 				uint64_t *addr, uint64_t *flags)
 {
-	if (!(*flags & AMDGPU_PDE_PTE))
+	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
 		*addr = adev->vm_manager.vram_base_offset + *addr -
 			adev->gmc.vram_start;
 	BUG_ON(*addr & 0xFFFF00000000003FULL);
-- 
2.17.1

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[PATCH 08/11] drm/amdgpu: add amdgpu_gmc_pd_addr helper

[Christian König]

Add a helper to get the root PD address and remove the workarounds from
the GMC9 code for that.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/Makefile           |  3 +-
 .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  2 +-
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 47 +++++++++++++++++++
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  2 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  2 +-
 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c      |  7 +--
 drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 --
 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  7 +--
 9 files changed, 56 insertions(+), 23 deletions(-)
 create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c

diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
index 860cb8731c7c..d2bafabe585d 100644
--- a/drivers/gpu/drm/amd/amdgpu/Makefile
+++ b/drivers/gpu/drm/amd/amdgpu/Makefile
@@ -51,7 +51,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
 	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
 	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
 	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
-	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
+	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
+	amdgpu_gmc.o
 
 # add asic specific block
 amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
index 7eadc58231f2..2e2393fe09b2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
@@ -364,7 +364,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 	struct amdgpu_bo *pd = vm->root.base.bo;
 	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
 	struct amdgpu_vm_parser param;
-	uint64_t addr, flags = AMDGPU_PTE_VALID;
 	int ret;
 
 	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
@@ -383,9 +382,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
 		return ret;
 	}
 
-	addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
-	amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
-	vm->pd_phys_addr = addr;
+	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 
 	if (vm->use_cpu_for_update) {
 		ret = amdgpu_bo_kmap(pd, NULL);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
index 17bf63f93c93..d268035cf2f3 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
@@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
 	if (r)
 		return r;
 
-	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
+	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
 
 	if (amdgpu_vm_debug) {
 		/* Invalidate all BOs to test for userspace bugs */
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
new file mode 100644
index 000000000000..36058feac64f
--- /dev/null
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -0,0 +1,47 @@
+/*
+ * Copyright 2018 Advanced Micro Devices, Inc.
+ * All Rights Reserved.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the
+ * "Software"), to deal in the Software without restriction, including
+ * without limitation the rights to use, copy, modify, merge, publish,
+ * distribute, sub license, and/or sell copies of the Software, and to
+ * permit persons to whom the Software is furnished to do so, subject to
+ * the following conditions:
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
+ * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
+ * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
+ * USE OR OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * The above copyright notice and this permission notice (including the
+ * next paragraph) shall be included in all copies or substantial portions
+ * of the Software.
+ *
+ */
+
+#include "amdgpu.h"
+
+/**
+ * amdgpu_gmc_pd_addr - return the address of the root directory
+ *
+ */
+uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	uint64_t pd_addr;
+
+	pd_addr = amdgpu_bo_gpu_offset(bo);
+	/* TODO: move that into ASIC specific code */
+	if (adev->asic_type >= CHIP_VEGA10) {
+		uint64_t flags = AMDGPU_PTE_VALID;
+
+		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
+		pd_addr |= flags;
+	}
+	return pd_addr;
+}
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index f3ea0a6d4660..7c469cce0498 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -131,4 +131,6 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 	return (gmc->real_vram_size == gmc->visible_vram_size);
 }
 
+uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
+
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index e7f73deed975..eb08a03b82a0 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
 		return r;
 
 	if (vm_needs_flush) {
-		job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
+		job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
 		job->vm_needs_flush = true;
 	}
 	if (resv) {
diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index 2baab7e69ef5..3403ded39d13 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
 
 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
-
-	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
-	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
-	value &= 0x0000FFFFFFFFF000ULL;
-	value |= 0x1; /*valid bit*/
+	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
 
 	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 		     lower_32_bits(value));
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 3393a329fc9c..e12e007cf7d9 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -436,12 +436,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
 	struct amdgpu_device *adev = ring->adev;
 	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
 	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
-	uint64_t flags = AMDGPU_PTE_VALID;
 	unsigned eng = ring->vm_inv_eng;
 
-	amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
-	pd_addr |= flags;
-
 	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
 			      lower_32_bits(pd_addr));
 
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
index 800ec4687f13..5f6a9c85488f 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
@@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
 
 static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
 {
-	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
-
-	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
-	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
-	value &= 0x0000FFFFFFFFF000ULL;
-	value |= 0x1; /* valid bit */
+	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
 
 	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
 		     lower_32_bits(value));
-- 
2.17.1

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[PATCH 09/11] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Christian König]

Helper to get the PDE for a PD/PT.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++++++++++++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++--
 drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
 5 files changed, 57 insertions(+), 8 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
index 36058feac64f..6f79ce108728 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
@@ -26,6 +26,38 @@
 
 #include "amdgpu.h"
 
+/**
+ * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
+ *
+ * @bo: the BO to get the PDE for
+ * @level: the level in the PD hirarchy
+ * @addr: resulting addr
+ * @flags: resulting flags
+ *
+ * Get the address and flags to be used for a PDE.
+ */
+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+			       uint64_t *addr, uint64_t *flags)
+{
+	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
+	struct ttm_dma_tt *ttm;
+
+	switch (bo->tbo.mem.mem_type) {
+	case TTM_PL_TT:
+		ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
+		*addr = ttm->dma_address[0];
+		break;
+	case TTM_PL_VRAM:
+		*addr = amdgpu_bo_gpu_offset(bo);
+		break;
+	default:
+		*addr = 0;
+		break;
+	}
+	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
+	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
+}
+
 /**
  * amdgpu_gmc_pd_addr - return the address of the root directory
  *
@@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
 	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
 	uint64_t pd_addr;
 
-	pd_addr = amdgpu_bo_gpu_offset(bo);
 	/* TODO: move that into ASIC specific code */
 	if (adev->asic_type >= CHIP_VEGA10) {
 		uint64_t flags = AMDGPU_PTE_VALID;
 
-		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
+		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
 		pd_addr |= flags;
+	} else {
+		pd_addr = amdgpu_bo_gpu_offset(bo);
 	}
 	return pd_addr;
 }
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
index 7c469cce0498..0d2c9f65ca13 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
@@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
 	return (gmc->real_vram_size == gmc->visible_vram_size);
 }
 
+void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
+			       uint64_t *addr, uint64_t *flags);
 uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
 
 #endif
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
index eb08a03b82a0..72366643e3c2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
@@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
 }
 
 /**
- * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
  *
  * @ttm: The ttm_tt object to compute the flags for
  * @mem: The memory registry backing this ttm_tt object
+ *
+ * Figure out the flags to use for a VM PDE.
  */
-uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
-				 struct ttm_mem_reg *mem)
+uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
 {
 	uint64_t flags = 0;
 
@@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 			flags |= AMDGPU_PTE_SNOOPED;
 	}
 
+	return flags;
+}
+
+/**
+ * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
+ *
+ * @ttm: The ttm_tt object to compute the flags for
+ * @mem: The memory registry backing this ttm_tt object
+ */
+uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
+				 struct ttm_mem_reg *mem)
+{
+	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
+
 	flags |= adev->gart.gart_pte_flags;
 	flags |= AMDGPU_PTE_READABLE;
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
index 8b3cc6687769..fe8f276e9811 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
@@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
 				       int *last_invalidated);
 bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
 bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
+uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
 uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
 				 struct ttm_mem_reg *mem);
 
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 53ce9982a5ee..87e3d44b0a3f 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -982,9 +982,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
 		pbo = pbo->parent;
 
 	level += params->adev->vm_manager.root_level;
-	pt = amdgpu_bo_gpu_offset(entry->base.bo);
-	flags = AMDGPU_PTE_VALID;
-	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
+	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
 	pde = (entry - parent->entries) * 8;
 	if (bo->shadow)
 		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
-- 
2.17.1

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[PATCH 10/11] drm/amdgpu: add helper for VM PD/PT allocation parameters

[Christian König]

Add a helper function to figure them out only once.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
 1 file changed, 28 insertions(+), 33 deletions(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 87e3d44b0a3f..928fdae0dab4 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 	return r;
 }
 
+/**
+ * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
+ *
+ * @adev: amdgpu_device pointer
+ * @vm: requesting vm
+ * @bp: resulting BO allocation parameters
+ */
+static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
+			       int level, struct amdgpu_bo_param *bp)
+{
+	memset(&bp, 0, sizeof(bp));
+
+	bp->size = amdgpu_vm_bo_size(adev, level);
+	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
+	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
+	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	if (vm->use_cpu_for_update)
+		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
+	else
+		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
+	bp->type = ttm_bo_type_kernel;
+	if (vm->root.base.bo)
+		bp->resv = vm->root.base.bo->tbo.resv;
+}
+
 /**
  * amdgpu_vm_alloc_levels - allocate the PD/PT levels
  *
@@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
 				  unsigned level, bool ats)
 {
 	unsigned shift = amdgpu_vm_level_shift(adev, level);
+	struct amdgpu_bo_param bp;
 	unsigned pt_idx, from, to;
-	u64 flags;
 	int r;
 
 	if (!parent->entries) {
@@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
 	saddr = saddr & ((1 << shift) - 1);
 	eaddr = eaddr & ((1 << shift) - 1);
 
-	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-	if (vm->use_cpu_for_update)
-		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else
-		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
-				AMDGPU_GEM_CREATE_SHADOW);
+	amdgpu_vm_bo_param(adev, vm, level, &bp);
 
 	/* walk over the address space and allocate the page tables */
 	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
-		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
 		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
 		struct amdgpu_bo *pt;
 
 		if (!entry->base.bo) {
-			struct amdgpu_bo_param bp;
-
-			memset(&bp, 0, sizeof(bp));
-			bp.size = amdgpu_vm_bo_size(adev, level);
-			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
-			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
-			bp.flags = flags;
-			bp.type = ttm_bo_type_kernel;
-			bp.resv = resv;
 			r = amdgpu_bo_create(adev, &bp, &pt);
 			if (r)
 				return r;
@@ -2564,8 +2574,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 {
 	struct amdgpu_bo_param bp;
 	struct amdgpu_bo *root;
-	unsigned long size;
-	uint64_t flags;
 	int r, i;
 
 	vm->va = RB_ROOT_CACHED;
@@ -2602,20 +2610,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 		  "CPU update of VM recommended only for large BAR system\n");
 	vm->last_update = NULL;
 
-	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
-	if (vm->use_cpu_for_update)
-		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
-	else
-		flags |= AMDGPU_GEM_CREATE_SHADOW;
-
-	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
-	memset(&bp, 0, sizeof(bp));
-	bp.size = size;
-	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
-	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
-	bp.flags = flags;
-	bp.type = ttm_bo_type_kernel;
-	bp.resv = NULL;
+	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
 	r = amdgpu_bo_create(adev, &bp, &root);
 	if (r)
 		goto error_free_sched_entity;
-- 
2.17.1

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[PATCH 11/11] drm/amdgpu: enable GTT PD/PT for raven

[Christian König]

Should work on Vega10 as well, but with an obvious performance hit.

Older APUs can be enabled as well, but will probably be more work.

Signed-off-by: Christian König <christian.koenig@amd.com>
---
 drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 928fdae0dab4..670a42729f88 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -308,6 +308,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 			list_move(&bo_base->vm_status, &vm->moved);
 			spin_unlock(&vm->moved_lock);
 		} else {
+			amdgpu_ttm_alloc_gart(&bo->tbo);
 			list_move(&bo_base->vm_status, &vm->relocated);
 		}
 	}
@@ -396,6 +397,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
 	if (r)
 		goto error;
 
+	r = amdgpu_ttm_alloc_gart(&bo->tbo);
+	if (r)
+		return r;
+
 	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
 	if (r)
 		goto error;
@@ -461,7 +466,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
 	bp->size = amdgpu_vm_bo_size(adev, level);
 	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
 	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
-	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
+	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)
+		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
+	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
+	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
+		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
 	if (vm->use_cpu_for_update)
 		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
 	else
-- 
2.17.1

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Re: [PATCH 11/11] drm/amdgpu: enable GTT PD/PT for raven

[Andrey Grodzovsky]

On 08/22/2018 11:05 AM, Christian König wrote:
> Should work on Vega10 as well, but with an obvious performance hit.
>
> Older APUs can be enabled as well, but will probably be more work.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 928fdae0dab4..670a42729f88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -308,6 +308,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   			list_move(&bo_base->vm_status, &vm->moved);
>   			spin_unlock(&vm->moved_lock);
>   		} else {
> +			amdgpu_ttm_alloc_gart(&bo->tbo);

Looks like you forgot to check for return value here.

Andrey

>   			list_move(&bo_base->vm_status, &vm->relocated);
>   		}
>   	}
> @@ -396,6 +397,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>   	if (r)
>   		goto error;
>   
> +	r = amdgpu_ttm_alloc_gart(&bo->tbo);
> +	if (r)
> +		return r;
> +
>   	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
>   	if (r)
>   		goto error;
> @@ -461,7 +466,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	bp->size = amdgpu_vm_bo_size(adev, level);
>   	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
>   	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> -	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)
> +		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
> +	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
> +	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> +		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>   	if (vm->use_cpu_for_update)
>   		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
>   	else

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Re: [PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[Alex Deucher]

On Wed, Aug 22, 2018 at 11:05 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Just another leftover from radeon.

I can't remember exactly what chip this was for.  Are you sure this
isn't still required for SI or something like that?

Alex

>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>  2 files changed, 1 insertion(+), 6 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 662aec5c81d4..73b8dcaf66e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>         struct amdgpu_bo_param bp;
>         struct amdgpu_bo *root;
> -       const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
> -               AMDGPU_VM_PTE_COUNT(adev) * 8);
>         unsigned long size;
>         uint64_t flags;
>         int r, i;
> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>         size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>         memset(&bp, 0, sizeof(bp));
>         bp.size = size;
> -       bp.byte_align = align;
> +       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>         bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>         bp.flags = flags;
>         bp.type = ttm_bo_type_kernel;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 1162c2bf3138..1c9049feaaea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>  /* number of entries in page table */
>  #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>
> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
> -
>  #define AMDGPU_PTE_VALID       (1ULL << 0)
>  #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
>  #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
> --
> 2.17.1
>
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Re: [PATCH 03/11] drm/amdgpu: cleanup VM handling in the CS a bit

[Alex Deucher]

On Wed, Aug 22, 2018 at 11:05 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Add a helper function for getting the root PD addr and cleanup join the
> two VM related functions and cleanup the function name.
>
> No functional change.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 160 ++++++++++++-------------
>  1 file changed, 74 insertions(+), 86 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index d42d1c8f78f6..17bf63f93c93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -804,8 +804,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
>         amdgpu_bo_unref(&parser->uf_entry.robj);
>  }
>
> -static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
> +static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
>  {
> +       struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
>         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
>         struct amdgpu_device *adev = p->adev;
>         struct amdgpu_vm *vm = &fpriv->vm;
> @@ -814,6 +815,71 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>         struct amdgpu_bo *bo;
>         int r;
>
> +       /* Only for UVD/VCE VM emulation */
> +       if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
> +               unsigned i, j;
> +
> +               for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
> +                       struct drm_amdgpu_cs_chunk_ib *chunk_ib;
> +                       struct amdgpu_bo_va_mapping *m;
> +                       struct amdgpu_bo *aobj = NULL;
> +                       struct amdgpu_cs_chunk *chunk;
> +                       uint64_t offset, va_start;
> +                       struct amdgpu_ib *ib;
> +                       uint8_t *kptr;
> +
> +                       chunk = &p->chunks[i];
> +                       ib = &p->job->ibs[j];
> +                       chunk_ib = chunk->kdata;
> +
> +                       if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
> +                               continue;
> +
> +                       va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
> +                       r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
> +                       if (r) {
> +                               DRM_ERROR("IB va_start is invalid\n");
> +                               return r;
> +                       }
> +
> +                       if ((va_start + chunk_ib->ib_bytes) >
> +                           (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
> +                               DRM_ERROR("IB va_start+ib_bytes is invalid\n");
> +                               return -EINVAL;
> +                       }
> +
> +                       /* the IB should be reserved at this point */
> +                       r = amdgpu_bo_kmap(aobj, (void **)&kptr);
> +                       if (r) {
> +                               return r;
> +                       }
> +
> +                       offset = m->start * AMDGPU_GPU_PAGE_SIZE;
> +                       kptr += va_start - offset;
> +
> +                       if (ring->funcs->parse_cs) {
> +                               memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> +                               amdgpu_bo_kunmap(aobj);
> +
> +                               r = amdgpu_ring_parse_cs(ring, p, j);
> +                               if (r)
> +                                       return r;
> +                       } else {
> +                               ib->ptr = (uint32_t *)kptr;
> +                               r = amdgpu_ring_patch_cs_in_place(ring, p, j);
> +                               amdgpu_bo_kunmap(aobj);
> +                               if (r)
> +                                       return r;
> +                       }
> +
> +                       j++;
> +               }
> +       }
> +
> +       if (!p->job->vm)
> +               return amdgpu_cs_sync_rings(p);
> +
> +
>         r = amdgpu_vm_clear_freed(adev, vm, NULL);
>         if (r)
>                 return r;
> @@ -876,6 +942,12 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>         if (r)
>                 return r;
>
> +       r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
> +       if (r)
> +               return r;
> +
> +       p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> +
>         if (amdgpu_vm_debug) {
>                 /* Invalidate all BOs to test for userspace bugs */
>                 amdgpu_bo_list_for_each_entry(e, p->bo_list) {
> @@ -887,90 +959,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>                 }
>         }
>
> -       return r;
> -}
> -
> -static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
> -                                struct amdgpu_cs_parser *p)
> -{
> -       struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
> -       struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> -       struct amdgpu_vm *vm = &fpriv->vm;
> -       int r;
> -
> -       /* Only for UVD/VCE VM emulation */
> -       if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
> -               unsigned i, j;
> -
> -               for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
> -                       struct drm_amdgpu_cs_chunk_ib *chunk_ib;
> -                       struct amdgpu_bo_va_mapping *m;
> -                       struct amdgpu_bo *aobj = NULL;
> -                       struct amdgpu_cs_chunk *chunk;
> -                       uint64_t offset, va_start;
> -                       struct amdgpu_ib *ib;
> -                       uint8_t *kptr;
> -
> -                       chunk = &p->chunks[i];
> -                       ib = &p->job->ibs[j];
> -                       chunk_ib = chunk->kdata;
> -
> -                       if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
> -                               continue;
> -
> -                       va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
> -                       r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
> -                       if (r) {
> -                               DRM_ERROR("IB va_start is invalid\n");
> -                               return r;
> -                       }
> -
> -                       if ((va_start + chunk_ib->ib_bytes) >
> -                           (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
> -                               DRM_ERROR("IB va_start+ib_bytes is invalid\n");
> -                               return -EINVAL;
> -                       }
> -
> -                       /* the IB should be reserved at this point */
> -                       r = amdgpu_bo_kmap(aobj, (void **)&kptr);
> -                       if (r) {
> -                               return r;
> -                       }
> -
> -                       offset = m->start * AMDGPU_GPU_PAGE_SIZE;
> -                       kptr += va_start - offset;
> -
> -                       if (ring->funcs->parse_cs) {
> -                               memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> -                               amdgpu_bo_kunmap(aobj);
> -
> -                               r = amdgpu_ring_parse_cs(ring, p, j);
> -                               if (r)
> -                                       return r;
> -                       } else {
> -                               ib->ptr = (uint32_t *)kptr;
> -                               r = amdgpu_ring_patch_cs_in_place(ring, p, j);
> -                               amdgpu_bo_kunmap(aobj);
> -                               if (r)
> -                                       return r;
> -                       }
> -
> -                       j++;
> -               }
> -       }
> -
> -       if (p->job->vm) {
> -               p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> -
> -               r = amdgpu_bo_vm_update_pte(p);
> -               if (r)
> -                       return r;
> -
> -               r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
> -               if (r)
> -                       return r;
> -       }
> -
>         return amdgpu_cs_sync_rings(p);
>  }
>
> @@ -1307,7 +1295,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
>         for (i = 0; i < parser.job->num_ibs; i++)
>                 trace_amdgpu_cs(&parser, i);
>
> -       r = amdgpu_cs_ib_vm_chunk(adev, &parser);
> +       r = amdgpu_cs_vm_handling(&parser);
>         if (r)
>                 goto out;
>
> --
> 2.17.1
>
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Re: [PATCH 04/11] drm/amdgpu: move setting the GART addr into TTM

[Alex Deucher]

On Wed, Aug 22, 2018 at 11:05 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Move setting the GART addr for window based copies into the TTM code who
> uses it.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++-
>  2 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 391e2f7c03aa..239ccbae09bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -82,8 +82,6 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
>         r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
>         if (r)
>                 kfree(*job);
> -       else
> -               (*job)->vm_pd_addr = adev->gart.table_addr;
>
>         return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index c6611cff64c8..b4333f60ed8b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2048,7 +2048,10 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>         if (r)
>                 return r;
>
> -       job->vm_needs_flush = vm_needs_flush;
> +       if (vm_needs_flush) {
> +               job->vm_pd_addr = adev->gart.table_addr;
> +               job->vm_needs_flush = true;
> +       }
>         if (resv) {
>                 r = amdgpu_sync_resv(adev, &job->sync, resv,
>                                      AMDGPU_FENCE_OWNER_UNDEFINED,
> --
> 2.17.1
>
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Re: [PATCH 05/11] drm/amdgpu: rename gart.robj into gart.bo

[Alex Deucher]

On Wed, Aug 22, 2018 at 11:05 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.c
> sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.h
>
> Just cleaning up radeon leftovers.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 32 ++++++++++++------------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  4 +--
>  6 files changed, 25 insertions(+), 25 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index a54d5655a191..f5cb5e2856c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -112,7 +112,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 struct amdgpu_bo_param bp;
>
>                 memset(&bp, 0, sizeof(bp));
> @@ -123,7 +123,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
>                         AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>                 bp.type = ttm_bo_type_kernel;
>                 bp.resv = NULL;
> -               r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
> +               r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
>                 if (r) {
>                         return r;
>                 }
> @@ -145,19 +145,19 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       r = amdgpu_bo_reserve(adev->gart.robj, false);
> +       r = amdgpu_bo_reserve(adev->gart.bo, false);
>         if (unlikely(r != 0))
>                 return r;
> -       r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
> +       r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
>         if (r) {
> -               amdgpu_bo_unreserve(adev->gart.robj);
> +               amdgpu_bo_unreserve(adev->gart.bo);
>                 return r;
>         }
> -       r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
> +       r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
>         if (r)
> -               amdgpu_bo_unpin(adev->gart.robj);
> -       amdgpu_bo_unreserve(adev->gart.robj);
> -       adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
> +               amdgpu_bo_unpin(adev->gart.bo);
> +       amdgpu_bo_unreserve(adev->gart.bo);
> +       adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
>         return r;
>  }
>
> @@ -173,14 +173,14 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 return;
>         }
> -       r = amdgpu_bo_reserve(adev->gart.robj, true);
> +       r = amdgpu_bo_reserve(adev->gart.bo, true);
>         if (likely(r == 0)) {
> -               amdgpu_bo_kunmap(adev->gart.robj);
> -               amdgpu_bo_unpin(adev->gart.robj);
> -               amdgpu_bo_unreserve(adev->gart.robj);
> +               amdgpu_bo_kunmap(adev->gart.bo);
> +               amdgpu_bo_unpin(adev->gart.bo);
> +               amdgpu_bo_unreserve(adev->gart.bo);
>                 adev->gart.ptr = NULL;
>         }
>  }
> @@ -196,10 +196,10 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
>   */
>  void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
>  {
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 return;
>         }
> -       amdgpu_bo_unref(&adev->gart.robj);
> +       amdgpu_bo_unref(&adev->gart.bo);
>  }
>
>  /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index 9f9e9dc87da1..d7b7c2d408d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -41,7 +41,7 @@ struct amdgpu_bo;
>
>  struct amdgpu_gart {
>         u64                             table_addr;
> -       struct amdgpu_bo                *robj;
> +       struct amdgpu_bo                *bo;
>         void                            *ptr;
>         unsigned                        num_gpu_pages;
>         unsigned                        num_cpu_pages;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index c14cf1c5bf57..c50bd0c46508 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -497,7 +497,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
>         int r, i;
>         u32 field;
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>                 return -EINVAL;
>         }
> @@ -588,7 +588,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj) {
> +       if (adev->gart.bo) {
>                 dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
>                 return 0;
>         }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 0c3a1618c3b7..c7cbd9f06892 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -607,7 +607,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
>         int r, i;
>         u32 tmp, field;
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>                 return -EINVAL;
>         }
> @@ -708,7 +708,7 @@ static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj) {
> +       if (adev->gart.bo) {
>                 WARN(1, "R600 PCIE GART already initialized\n");
>                 return 0;
>         }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 274c9321d06c..21e3d9af370d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -809,7 +809,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
>         int r, i;
>         u32 tmp, field;
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>                 return -EINVAL;
>         }
> @@ -927,7 +927,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj) {
> +       if (adev->gart.bo) {
>                 WARN(1, "R600 PCIE GART already initialized\n");
>                 return 0;
>         }
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 25f614b91a9b..eb1936223748 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -843,7 +843,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
>  {
>         int r;
>
> -       if (adev->gart.robj) {
> +       if (adev->gart.bo) {
>                 WARN(1, "VEGA10 PCIE GART already initialized\n");
>                 return 0;
>         }
> @@ -1081,7 +1081,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>                                                 golden_settings_vega10_hdp,
>                                                 ARRAY_SIZE(golden_settings_vega10_hdp));
>
> -       if (adev->gart.robj == NULL) {
> +       if (adev->gart.bo == NULL) {
>                 dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>                 return -EINVAL;
>         }
> --
> 2.17.1
>
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Re: [PATCH 10/11] drm/amdgpu: add helper for VM PD/PT allocation parameters

[Alex Deucher]

On Wed, Aug 22, 2018 at 11:06 AM Christian König
<ckoenig.leichtzumerken@gmail.com> wrote:
>
> Add a helper function to figure them out only once.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
>  1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 87e3d44b0a3f..928fdae0dab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>         return r;
>  }
>
> +/**
> + * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: requesting vm
> + * @bp: resulting BO allocation parameters
> + */
> +static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> +                              int level, struct amdgpu_bo_param *bp)
> +{
> +       memset(&bp, 0, sizeof(bp));
> +
> +       bp->size = amdgpu_vm_bo_size(adev, level);
> +       bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
> +       bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> +       bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +       if (vm->use_cpu_for_update)
> +               bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> +       else
> +               bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
> +       bp->type = ttm_bo_type_kernel;
> +       if (vm->root.base.bo)
> +               bp->resv = vm->root.base.bo->tbo.resv;
> +}
> +
>  /**
>   * amdgpu_vm_alloc_levels - allocate the PD/PT levels
>   *
> @@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>                                   unsigned level, bool ats)
>  {
>         unsigned shift = amdgpu_vm_level_shift(adev, level);
> +       struct amdgpu_bo_param bp;
>         unsigned pt_idx, from, to;
> -       u64 flags;
>         int r;
>
>         if (!parent->entries) {
> @@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>         saddr = saddr & ((1 << shift) - 1);
>         eaddr = eaddr & ((1 << shift) - 1);
>
> -       flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -       if (vm->use_cpu_for_update)
> -               flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -       else
> -               flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
> -                               AMDGPU_GEM_CREATE_SHADOW);
> +       amdgpu_vm_bo_param(adev, vm, level, &bp);
>
>         /* walk over the address space and allocate the page tables */
>         for (pt_idx = from; pt_idx <= to; ++pt_idx) {
> -               struct reservation_object *resv = vm->root.base.bo->tbo.resv;
>                 struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
>                 struct amdgpu_bo *pt;
>
>                 if (!entry->base.bo) {
> -                       struct amdgpu_bo_param bp;
> -
> -                       memset(&bp, 0, sizeof(bp));
> -                       bp.size = amdgpu_vm_bo_size(adev, level);
> -                       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -                       bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -                       bp.flags = flags;
> -                       bp.type = ttm_bo_type_kernel;
> -                       bp.resv = resv;
>                         r = amdgpu_bo_create(adev, &bp, &pt);
>                         if (r)
>                                 return r;
> @@ -2564,8 +2574,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>         struct amdgpu_bo_param bp;
>         struct amdgpu_bo *root;
> -       unsigned long size;
> -       uint64_t flags;
>         int r, i;
>
>         vm->va = RB_ROOT_CACHED;
> @@ -2602,20 +2610,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>                   "CPU update of VM recommended only for large BAR system\n");
>         vm->last_update = NULL;
>
> -       flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -       if (vm->use_cpu_for_update)
> -               flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -       else
> -               flags |= AMDGPU_GEM_CREATE_SHADOW;
> -
> -       size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
> -       memset(&bp, 0, sizeof(bp));
> -       bp.size = size;
> -       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -       bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -       bp.flags = flags;
> -       bp.type = ttm_bo_type_kernel;
> -       bp.resv = NULL;
> +       amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
>         r = amdgpu_bo_create(adev, &bp, &root);
>         if (r)
>                 goto error_free_sched_entity;
> --
> 2.17.1
>
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Re: [PATCH 08/11] drm/amdgpu: add amdgpu_gmc_pd_addr helper

[Felix Kuehling]

Acked-by: Felix Kuehling <Felix.Kuehling@amd.com>

The amdgpu_amdkfd_gpuvm code looked different than I remembered. There
are some important patches missing upstream that I'll roll into my next
patch series.

Regards,
  Felix


On 2018-08-22 11:05 AM, Christian König wrote:
> Add a helper to get the root PD address and remove the workarounds from
> the GMC9 code for that.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile           |  3 +-
>  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 47 +++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c      |  7 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 --
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  7 +--
>  9 files changed, 56 insertions(+), 23 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 860cb8731c7c..d2bafabe585d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -51,7 +51,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
>  	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
>  	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
>  	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> -	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
> +	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> +	amdgpu_gmc.o
>  
>  # add asic specific block
>  amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 7eadc58231f2..2e2393fe09b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -364,7 +364,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>  	struct amdgpu_bo *pd = vm->root.base.bo;
>  	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
>  	struct amdgpu_vm_parser param;
> -	uint64_t addr, flags = AMDGPU_PTE_VALID;
>  	int ret;
>  
>  	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
> @@ -383,9 +382,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>  		return ret;
>  	}
>  
> -	addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> -	amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
> -	vm->pd_phys_addr = addr;
> +	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>  
>  	if (vm->use_cpu_for_update) {
>  		ret = amdgpu_bo_kmap(pd, NULL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 17bf63f93c93..d268035cf2f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
>  	if (r)
>  		return r;
>  
> -	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> +	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>  
>  	if (amdgpu_vm_debug) {
>  		/* Invalidate all BOs to test for userspace bugs */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> new file mode 100644
> index 000000000000..36058feac64f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
> + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> + * USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +/**
> + * amdgpu_gmc_pd_addr - return the address of the root directory
> + *
> + */
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	uint64_t pd_addr;
> +
> +	pd_addr = amdgpu_bo_gpu_offset(bo);
> +	/* TODO: move that into ASIC specific code */
> +	if (adev->asic_type >= CHIP_VEGA10) {
> +		uint64_t flags = AMDGPU_PTE_VALID;
> +
> +		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +		pd_addr |= flags;
> +	}
> +	return pd_addr;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index f3ea0a6d4660..7c469cce0498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,4 +131,6 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>  	return (gmc->real_vram_size == gmc->visible_vram_size);
>  }
>  
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e7f73deed975..eb08a03b82a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>  		return r;
>  
>  	if (vm_needs_flush) {
> -		job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> +		job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
>  		job->vm_needs_flush = true;
>  	}
>  	if (resv) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 2baab7e69ef5..3403ded39d13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
>  
>  static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>  {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>  
>  	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>  		     lower_32_bits(value));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3393a329fc9c..e12e007cf7d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -436,12 +436,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>  	struct amdgpu_device *adev = ring->adev;
>  	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
> -	uint64_t flags = AMDGPU_PTE_VALID;
>  	unsigned eng = ring->vm_inv_eng;
>  
> -	amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> -	pd_addr |= flags;
> -
>  	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
>  			      lower_32_bits(pd_addr));
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 800ec4687f13..5f6a9c85488f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
>  
>  static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>  {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>  
>  	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>  		     lower_32_bits(value));

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Re: [PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[Zhang, Jerry (Junwei)]

On 08/23/2018 03:46 AM, Alex Deucher wrote:
> On Wed, Aug 22, 2018 at 11:05 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>>
>> Just another leftover from radeon.
>
> I can't remember exactly what chip this was for.  Are you sure this
> isn't still required for SI or something like that?

FYI.

Some projects still use SI with amdgpu.

Regards,
Jerry

>
> Alex
>
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>>   2 files changed, 1 insertion(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 662aec5c81d4..73b8dcaf66e6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>   {
>>          struct amdgpu_bo_param bp;
>>          struct amdgpu_bo *root;
>> -       const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
>> -               AMDGPU_VM_PTE_COUNT(adev) * 8);
>>          unsigned long size;
>>          uint64_t flags;
>>          int r, i;
>> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>          size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>>          memset(&bp, 0, sizeof(bp));
>>          bp.size = size;
>> -       bp.byte_align = align;
>> +       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>>          bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>>          bp.flags = flags;
>>          bp.type = ttm_bo_type_kernel;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 1162c2bf3138..1c9049feaaea 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>>   /* number of entries in page table */
>>   #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>>
>> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
>> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
>> -
>>   #define AMDGPU_PTE_VALID       (1ULL << 0)
>>   #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
>>   #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
>> --
>> 2.17.1
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
>
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Re: [PATCH 02/11] drm/amdgpu: validate the VM root PD from the VM code

[Zhang, Jerry (Junwei)]

Patch 2 ~ 6 are

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

Jerry

On 08/22/2018 11:05 PM, Christian König wrote:
> Preparation for following changes. This validates the root PD twice,
> but the overhead of that should be minimal.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 73b8dcaf66e6..53ce9982a5ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -291,11 +291,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
>   		struct amdgpu_bo *bo = bo_base->bo;
>
> -		if (bo->parent) {
> -			r = validate(param, bo);
> -			if (r)
> -				break;
> +		r = validate(param, bo);
> +		if (r)
> +			break;
>
> +		if (bo->parent) {
>   			spin_lock(&glob->lru_lock);
>   			ttm_bo_move_to_lru_tail(&bo->tbo);
>   			if (bo->shadow)
>
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Re: [PATCH 07/11] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Zhang, Jerry (Junwei)]

On 08/22/2018 11:05 PM, Christian König wrote:
> Add the necessary handling.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>

Looks going to use GTT for page table.
What kind of scenario to use that?
could it be replaced by CPU updating page table in system memory?

Regards,
Jerry

> ---
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>   1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index e412eb8e347c..3393a329fc9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -571,7 +571,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
>   static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
>   				uint64_t *addr, uint64_t *flags)
>   {
> -	if (!(*flags & AMDGPU_PDE_PTE))
> +	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
>   		*addr = adev->vm_manager.vram_base_offset + *addr -
>   			adev->gmc.vram_start;
>   	BUG_ON(*addr & 0xFFFF00000000003FULL);
>
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Re: [PATCH 08/11] drm/amdgpu: add amdgpu_gmc_pd_addr helper

[Zhang, Jerry (Junwei)]

On 08/22/2018 11:05 PM, Christian König wrote:
> Add a helper to get the root PD address and remove the workarounds from
> the GMC9 code for that.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/Makefile           |  3 +-
>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  2 +-
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 47 +++++++++++++++++++
>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  2 +
>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  2 +-
>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c      |  7 +--
>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 --
>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  7 +--
>   9 files changed, 56 insertions(+), 23 deletions(-)
>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 860cb8731c7c..d2bafabe585d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -51,7 +51,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
>   	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
>   	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
>   	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> -	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
> +	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> +	amdgpu_gmc.o
>
>   # add asic specific block
>   amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 7eadc58231f2..2e2393fe09b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -364,7 +364,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>   	struct amdgpu_bo *pd = vm->root.base.bo;
>   	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
>   	struct amdgpu_vm_parser param;
> -	uint64_t addr, flags = AMDGPU_PTE_VALID;
>   	int ret;
>
>   	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
> @@ -383,9 +382,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>   		return ret;
>   	}
>
> -	addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> -	amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
> -	vm->pd_phys_addr = addr;
> +	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>
>   	if (vm->use_cpu_for_update) {
>   		ret = amdgpu_bo_kmap(pd, NULL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 17bf63f93c93..d268035cf2f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
>   	if (r)
>   		return r;
>
> -	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> +	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>
>   	if (amdgpu_vm_debug) {
>   		/* Invalidate all BOs to test for userspace bugs */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> new file mode 100644
> index 000000000000..36058feac64f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
> + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> + * USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +/**
> + * amdgpu_gmc_pd_addr - return the address of the root directory
> + *
> + */
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)

If the func is going to handle all pd address, it's better to be called in gmc6,7,8 as well.

> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	uint64_t pd_addr;
> +
> +	pd_addr = amdgpu_bo_gpu_offset(bo);
> +	/* TODO: move that into ASIC specific code */

Sounds it could be a func(.gmc_pd_addr) in the group of amdgpu_gmc_funcs?

Regards,
Jerry

> +	if (adev->asic_type >= CHIP_VEGA10) {
> +		uint64_t flags = AMDGPU_PTE_VALID;
> +
> +		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +		pd_addr |= flags;
> +	}
> +	return pd_addr;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index f3ea0a6d4660..7c469cce0498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,4 +131,6 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>   	return (gmc->real_vram_size == gmc->visible_vram_size);
>   }
>
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> +
>   #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e7f73deed975..eb08a03b82a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>   		return r;
>
>   	if (vm_needs_flush) {
> -		job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> +		job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
>   		job->vm_needs_flush = true;
>   	}
>   	if (resv) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 2baab7e69ef5..3403ded39d13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
>
>   static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>   {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>
>   	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>   		     lower_32_bits(value));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3393a329fc9c..e12e007cf7d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -436,12 +436,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>   	struct amdgpu_device *adev = ring->adev;
>   	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>   	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
> -	uint64_t flags = AMDGPU_PTE_VALID;
>   	unsigned eng = ring->vm_inv_eng;
>
> -	amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> -	pd_addr |= flags;
> -
>   	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
>   			      lower_32_bits(pd_addr));
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 800ec4687f13..5f6a9c85488f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
>
>   static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>   {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>
>   	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>   		     lower_32_bits(value));
>
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Re: [PATCH 10/11] drm/amdgpu: add helper for VM PD/PT allocation parameters

[Zhang, Jerry (Junwei)]

On 08/22/2018 11:05 PM, Christian König wrote:
> Add a helper function to figure them out only once.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>

> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
>   1 file changed, 28 insertions(+), 33 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 87e3d44b0a3f..928fdae0dab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>   	return r;
>   }
>
> +/**
> + * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: requesting vm
> + * @bp: resulting BO allocation parameters
> + */
> +static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> +			       int level, struct amdgpu_bo_param *bp)
> +{
> +	memset(&bp, 0, sizeof(bp));
> +
> +	bp->size = amdgpu_vm_bo_size(adev, level);
> +	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
> +	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> +	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +	if (vm->use_cpu_for_update)
> +		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> +	else
> +		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
> +	bp->type = ttm_bo_type_kernel;
> +	if (vm->root.base.bo)
> +		bp->resv = vm->root.base.bo->tbo.resv;
> +}
> +
>   /**
>    * amdgpu_vm_alloc_levels - allocate the PD/PT levels
>    *
> @@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>   				  unsigned level, bool ats)
>   {
>   	unsigned shift = amdgpu_vm_level_shift(adev, level);
> +	struct amdgpu_bo_param bp;
>   	unsigned pt_idx, from, to;
> -	u64 flags;
>   	int r;
>
>   	if (!parent->entries) {
> @@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>   	saddr = saddr & ((1 << shift) - 1);
>   	eaddr = eaddr & ((1 << shift) - 1);
>
> -	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -	if (vm->use_cpu_for_update)
> -		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -	else
> -		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
> -				AMDGPU_GEM_CREATE_SHADOW);
> +	amdgpu_vm_bo_param(adev, vm, level, &bp);
>
>   	/* walk over the address space and allocate the page tables */
>   	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
> -		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
>   		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
>   		struct amdgpu_bo *pt;
>
>   		if (!entry->base.bo) {
> -			struct amdgpu_bo_param bp;
> -
> -			memset(&bp, 0, sizeof(bp));
> -			bp.size = amdgpu_vm_bo_size(adev, level);
> -			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -			bp.flags = flags;
> -			bp.type = ttm_bo_type_kernel;
> -			bp.resv = resv;
>   			r = amdgpu_bo_create(adev, &bp, &pt);
>   			if (r)
>   				return r;
> @@ -2564,8 +2574,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   {
>   	struct amdgpu_bo_param bp;
>   	struct amdgpu_bo *root;
> -	unsigned long size;
> -	uint64_t flags;
>   	int r, i;
>
>   	vm->va = RB_ROOT_CACHED;
> @@ -2602,20 +2610,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   		  "CPU update of VM recommended only for large BAR system\n");
>   	vm->last_update = NULL;
>
> -	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -	if (vm->use_cpu_for_update)
> -		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -	else
> -		flags |= AMDGPU_GEM_CREATE_SHADOW;
> -
> -	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
> -	memset(&bp, 0, sizeof(bp));
> -	bp.size = size;
> -	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -	bp.flags = flags;
> -	bp.type = ttm_bo_type_kernel;
> -	bp.resv = NULL;
> +	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
>   	r = amdgpu_bo_create(adev, &bp, &root);
>   	if (r)
>   		goto error_free_sched_entity;
>
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Re: [PATCH 11/11] drm/amdgpu: enable GTT PD/PT for raven

[Zhang, Jerry (Junwei)]

On 08/22/2018 11:05 PM, Christian König wrote:
> Should work on Vega10 as well, but with an obvious performance hit.
>
> Older APUs can be enabled as well, but will probably be more work.
>
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
>   1 file changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 928fdae0dab4..670a42729f88 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -308,6 +308,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   			list_move(&bo_base->vm_status, &vm->moved);
>   			spin_unlock(&vm->moved_lock);
>   		} else {
> +			amdgpu_ttm_alloc_gart(&bo->tbo);
>   			list_move(&bo_base->vm_status, &vm->relocated);
>   		}
>   	}
> @@ -396,6 +397,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>   	if (r)
>   		goto error;
>
> +	r = amdgpu_ttm_alloc_gart(&bo->tbo);
> +	if (r)
> +		return r;
> +
>   	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
>   	if (r)
>   		goto error;
> @@ -461,7 +466,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>   	bp->size = amdgpu_vm_bo_size(adev, level);
>   	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
>   	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> -	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)

Do we need bp->size <= PAGE_SIZE?
Seems it's always less 12 bit for raven?

Regards,
Jerry

> +		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
> +	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
> +	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> +		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>   	if (vm->use_cpu_for_update)
>   		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
>   	else
>
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Re: [PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[Christian König]

Am 22.08.2018 um 21:46 schrieb Alex Deucher:
> On Wed, Aug 22, 2018 at 11:05 AM Christian König
> <ckoenig.leichtzumerken@gmail.com> wrote:
>> Just another leftover from radeon.
> I can't remember exactly what chip this was for.  Are you sure this
> isn't still required for SI or something like that?

Actually as far as I know it is not required at all (even for Radeon).

We just added it as a precaution because the windows driver aligned 
everything to 32K at that time.

Christian.

>
> Alex
>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>>   2 files changed, 1 insertion(+), 6 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 662aec5c81d4..73b8dcaf66e6 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>   {
>>          struct amdgpu_bo_param bp;
>>          struct amdgpu_bo *root;
>> -       const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
>> -               AMDGPU_VM_PTE_COUNT(adev) * 8);
>>          unsigned long size;
>>          uint64_t flags;
>>          int r, i;
>> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>          size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>>          memset(&bp, 0, sizeof(bp));
>>          bp.size = size;
>> -       bp.byte_align = align;
>> +       bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>>          bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>>          bp.flags = flags;
>>          bp.type = ttm_bo_type_kernel;
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> index 1162c2bf3138..1c9049feaaea 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
>> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>>   /* number of entries in page table */
>>   #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>>
>> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
>> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
>> -
>>   #define AMDGPU_PTE_VALID       (1ULL << 0)
>>   #define AMDGPU_PTE_SYSTEM      (1ULL << 1)
>>   #define AMDGPU_PTE_SNOOPED     (1ULL << 2)
>> --
>> 2.17.1
>>
>> _______________________________________________
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>> amd-gfx@lists.freedesktop.org
>> https://lists.freedesktop.org/mailman/listinfo/amd-gfx

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Re: [PATCH 01/11] drm/amdgpu: remove extra root PD alignment

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:07PM +0200, Christian König wrote:
> Just another leftover from radeon.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Acked-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 4 +---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h | 3 ---
>  2 files changed, 1 insertion(+), 6 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 662aec5c81d4..73b8dcaf66e6 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -2566,8 +2566,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>  	struct amdgpu_bo_param bp;
>  	struct amdgpu_bo *root;
> -	const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE,
> -		AMDGPU_VM_PTE_COUNT(adev) * 8);
>  	unsigned long size;
>  	uint64_t flags;
>  	int r, i;
> @@ -2615,7 +2613,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
>  	memset(&bp, 0, sizeof(bp));
>  	bp.size = size;
> -	bp.byte_align = align;
> +	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
>  	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
>  	bp.flags = flags;
>  	bp.type = ttm_bo_type_kernel;
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> index 1162c2bf3138..1c9049feaaea 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.h
> @@ -48,9 +48,6 @@ struct amdgpu_bo_list_entry;
>  /* number of entries in page table */
>  #define AMDGPU_VM_PTE_COUNT(adev) (1 << (adev)->vm_manager.block_size)
>  
> -/* PTBs (Page Table Blocks) need to be aligned to 32K */
> -#define AMDGPU_VM_PTB_ALIGN_SIZE   32768
> -
>  #define AMDGPU_PTE_VALID	(1ULL << 0)
>  #define AMDGPU_PTE_SYSTEM	(1ULL << 1)
>  #define AMDGPU_PTE_SNOOPED	(1ULL << 2)
> -- 
> 2.17.1
> 
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 02/11] drm/amdgpu: validate the VM root PD from the VM code

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:08PM +0200, Christian König wrote:
> Preparation for following changes. This validates the root PD twice,
> but the overhead of that should be minimal.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>
> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 73b8dcaf66e6..53ce9982a5ee 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -291,11 +291,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
>  		struct amdgpu_bo *bo = bo_base->bo;
>  
> -		if (bo->parent) {
> -			r = validate(param, bo);
> -			if (r)
> -				break;
> +		r = validate(param, bo);
> +		if (r)
> +			break;

In orignal case, we skip the root PD. But now, it is validated one time.
May I know where is another time?

Thanks,
Ray

>  
> +		if (bo->parent) {
>  			spin_lock(&glob->lru_lock);
>  			ttm_bo_move_to_lru_tail(&bo->tbo);
>  			if (bo->shadow)
> -- 
> 2.17.1
> 
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 03/11] drm/amdgpu: cleanup VM handling in the CS a bit

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:09PM +0200, Christian König wrote:
> Add a helper function for getting the root PD addr and cleanup join the
> two VM related functions and cleanup the function name.
> 
> No functional change.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 160 ++++++++++++-------------
>  1 file changed, 74 insertions(+), 86 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index d42d1c8f78f6..17bf63f93c93 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -804,8 +804,9 @@ static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error,
>  	amdgpu_bo_unref(&parser->uf_entry.robj);
>  }
>  
> -static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
> +static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
>  {
> +	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
>  	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
>  	struct amdgpu_device *adev = p->adev;
>  	struct amdgpu_vm *vm = &fpriv->vm;
> @@ -814,6 +815,71 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>  	struct amdgpu_bo *bo;
>  	int r;
>  
> +	/* Only for UVD/VCE VM emulation */
> +	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
> +		unsigned i, j;
> +
> +		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
> +			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
> +			struct amdgpu_bo_va_mapping *m;
> +			struct amdgpu_bo *aobj = NULL;
> +			struct amdgpu_cs_chunk *chunk;
> +			uint64_t offset, va_start;
> +			struct amdgpu_ib *ib;
> +			uint8_t *kptr;
> +
> +			chunk = &p->chunks[i];
> +			ib = &p->job->ibs[j];
> +			chunk_ib = chunk->kdata;
> +
> +			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
> +				continue;
> +
> +			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
> +			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
> +			if (r) {
> +				DRM_ERROR("IB va_start is invalid\n");
> +				return r;
> +			}
> +
> +			if ((va_start + chunk_ib->ib_bytes) >
> +			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
> +				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
> +				return -EINVAL;
> +			}
> +
> +			/* the IB should be reserved at this point */
> +			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
> +			if (r) {
> +				return r;
> +			}
> +
> +			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
> +			kptr += va_start - offset;
> +
> +			if (ring->funcs->parse_cs) {
> +				memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> +				amdgpu_bo_kunmap(aobj);
> +
> +				r = amdgpu_ring_parse_cs(ring, p, j);
> +				if (r)
> +					return r;
> +			} else {
> +				ib->ptr = (uint32_t *)kptr;
> +				r = amdgpu_ring_patch_cs_in_place(ring, p, j);
> +				amdgpu_bo_kunmap(aobj);
> +				if (r)
> +					return r;
> +			}
> +
> +			j++;
> +		}
> +	}
> +
> +	if (!p->job->vm)
> +		return amdgpu_cs_sync_rings(p);
> +
> +
>  	r = amdgpu_vm_clear_freed(adev, vm, NULL);
>  	if (r)
>  		return r;
> @@ -876,6 +942,12 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>  	if (r)
>  		return r;
>  
> +	r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
> +	if (r)
> +		return r;
> +
> +	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> +
>  	if (amdgpu_vm_debug) {
>  		/* Invalidate all BOs to test for userspace bugs */
>  		amdgpu_bo_list_for_each_entry(e, p->bo_list) {
> @@ -887,90 +959,6 @@ static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p)
>  		}
>  	}
>  
> -	return r;
> -}
> -
> -static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
> -				 struct amdgpu_cs_parser *p)
> -{
> -	struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
> -	struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
> -	struct amdgpu_vm *vm = &fpriv->vm;
> -	int r;
> -
> -	/* Only for UVD/VCE VM emulation */
> -	if (ring->funcs->parse_cs || ring->funcs->patch_cs_in_place) {
> -		unsigned i, j;
> -
> -		for (i = 0, j = 0; i < p->nchunks && j < p->job->num_ibs; i++) {
> -			struct drm_amdgpu_cs_chunk_ib *chunk_ib;
> -			struct amdgpu_bo_va_mapping *m;
> -			struct amdgpu_bo *aobj = NULL;
> -			struct amdgpu_cs_chunk *chunk;
> -			uint64_t offset, va_start;
> -			struct amdgpu_ib *ib;
> -			uint8_t *kptr;
> -
> -			chunk = &p->chunks[i];
> -			ib = &p->job->ibs[j];
> -			chunk_ib = chunk->kdata;
> -
> -			if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
> -				continue;
> -
> -			va_start = chunk_ib->va_start & AMDGPU_VA_HOLE_MASK;
> -			r = amdgpu_cs_find_mapping(p, va_start, &aobj, &m);
> -			if (r) {
> -				DRM_ERROR("IB va_start is invalid\n");
> -				return r;
> -			}
> -
> -			if ((va_start + chunk_ib->ib_bytes) >
> -			    (m->last + 1) * AMDGPU_GPU_PAGE_SIZE) {
> -				DRM_ERROR("IB va_start+ib_bytes is invalid\n");
> -				return -EINVAL;
> -			}
> -
> -			/* the IB should be reserved at this point */
> -			r = amdgpu_bo_kmap(aobj, (void **)&kptr);
> -			if (r) {
> -				return r;
> -			}
> -
> -			offset = m->start * AMDGPU_GPU_PAGE_SIZE;
> -			kptr += va_start - offset;
> -
> -			if (ring->funcs->parse_cs) {
> -				memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
> -				amdgpu_bo_kunmap(aobj);
> -
> -				r = amdgpu_ring_parse_cs(ring, p, j);
> -				if (r)
> -					return r;
> -			} else {
> -				ib->ptr = (uint32_t *)kptr;
> -				r = amdgpu_ring_patch_cs_in_place(ring, p, j);
> -				amdgpu_bo_kunmap(aobj);
> -				if (r)
> -					return r;
> -			}
> -
> -			j++;
> -		}
> -	}
> -
> -	if (p->job->vm) {
> -		p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> -
> -		r = amdgpu_bo_vm_update_pte(p);
> -		if (r)
> -			return r;
> -
> -		r = reservation_object_reserve_shared(vm->root.base.bo->tbo.resv);
> -		if (r)
> -			return r;
> -	}
> -
>  	return amdgpu_cs_sync_rings(p);
>  }
>  
> @@ -1307,7 +1295,7 @@ int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
>  	for (i = 0; i < parser.job->num_ibs; i++)
>  		trace_amdgpu_cs(&parser, i);
>  
> -	r = amdgpu_cs_ib_vm_chunk(adev, &parser);
> +	r = amdgpu_cs_vm_handling(&parser);
>  	if (r)
>  		goto out;
>  
> -- 
> 2.17.1
> 
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Re: [PATCH 04/11] drm/amdgpu: move setting the GART addr into TTM

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:10PM +0200, Christian König wrote:
> Move setting the GART addr for window based copies into the TTM code who
> uses it.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_job.c | 2 --
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 5 ++++-
>  2 files changed, 4 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> index 391e2f7c03aa..239ccbae09bc 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
> @@ -82,8 +82,6 @@ int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
>  	r = amdgpu_ib_get(adev, NULL, size, &(*job)->ibs[0]);
>  	if (r)
>  		kfree(*job);
> -	else
> -		(*job)->vm_pd_addr = adev->gart.table_addr;
>  
>  	return r;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index c6611cff64c8..b4333f60ed8b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2048,7 +2048,10 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>  	if (r)
>  		return r;
>  
> -	job->vm_needs_flush = vm_needs_flush;
> +	if (vm_needs_flush) {
> +		job->vm_pd_addr = adev->gart.table_addr;
> +		job->vm_needs_flush = true;
> +	}
>  	if (resv) {
>  		r = amdgpu_sync_resv(adev, &job->sync, resv,
>  				     AMDGPU_FENCE_OWNER_UNDEFINED,
> -- 
> 2.17.1
> 
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Re: [PATCH 05/11] drm/amdgpu: rename gart.robj into gart.bo

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:11PM +0200, Christian König wrote:
> sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.c
> sed -i "s/gart.robj/gart.bo/" drivers/gpu/drm/amd/amdgpu/*.h
> 
> Just cleaning up radeon leftovers.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Yes, the 'bo' is the better name of gart table than 'robj'.

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c | 32 ++++++++++++------------
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c    |  4 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c    |  4 +--
>  6 files changed, 25 insertions(+), 25 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> index a54d5655a191..f5cb5e2856c1 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c
> @@ -112,7 +112,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		struct amdgpu_bo_param bp;
>  
>  		memset(&bp, 0, sizeof(bp));
> @@ -123,7 +123,7 @@ int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev)
>  			AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>  		bp.type = ttm_bo_type_kernel;
>  		bp.resv = NULL;
> -		r = amdgpu_bo_create(adev, &bp, &adev->gart.robj);
> +		r = amdgpu_bo_create(adev, &bp, &adev->gart.bo);
>  		if (r) {
>  			return r;
>  		}
> @@ -145,19 +145,19 @@ int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	r = amdgpu_bo_reserve(adev->gart.robj, false);
> +	r = amdgpu_bo_reserve(adev->gart.bo, false);
>  	if (unlikely(r != 0))
>  		return r;
> -	r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
> +	r = amdgpu_bo_pin(adev->gart.bo, AMDGPU_GEM_DOMAIN_VRAM);
>  	if (r) {
> -		amdgpu_bo_unreserve(adev->gart.robj);
> +		amdgpu_bo_unreserve(adev->gart.bo);
>  		return r;
>  	}
> -	r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
> +	r = amdgpu_bo_kmap(adev->gart.bo, &adev->gart.ptr);
>  	if (r)
> -		amdgpu_bo_unpin(adev->gart.robj);
> -	amdgpu_bo_unreserve(adev->gart.robj);
> -	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
> +		amdgpu_bo_unpin(adev->gart.bo);
> +	amdgpu_bo_unreserve(adev->gart.bo);
> +	adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
>  	return r;
>  }
>  
> @@ -173,14 +173,14 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		return;
>  	}
> -	r = amdgpu_bo_reserve(adev->gart.robj, true);
> +	r = amdgpu_bo_reserve(adev->gart.bo, true);
>  	if (likely(r == 0)) {
> -		amdgpu_bo_kunmap(adev->gart.robj);
> -		amdgpu_bo_unpin(adev->gart.robj);
> -		amdgpu_bo_unreserve(adev->gart.robj);
> +		amdgpu_bo_kunmap(adev->gart.bo);
> +		amdgpu_bo_unpin(adev->gart.bo);
> +		amdgpu_bo_unreserve(adev->gart.bo);
>  		adev->gart.ptr = NULL;
>  	}
>  }
> @@ -196,10 +196,10 @@ void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev)
>   */
>  void amdgpu_gart_table_vram_free(struct amdgpu_device *adev)
>  {
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		return;
>  	}
> -	amdgpu_bo_unref(&adev->gart.robj);
> +	amdgpu_bo_unref(&adev->gart.bo);
>  }
>  
>  /*
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> index 9f9e9dc87da1..d7b7c2d408d5 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gart.h
> @@ -41,7 +41,7 @@ struct amdgpu_bo;
>  
>  struct amdgpu_gart {
>  	u64				table_addr;
> -	struct amdgpu_bo		*robj;
> +	struct amdgpu_bo		*bo;
>  	void				*ptr;
>  	unsigned			num_gpu_pages;
>  	unsigned			num_cpu_pages;
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> index c14cf1c5bf57..c50bd0c46508 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v6_0.c
> @@ -497,7 +497,7 @@ static int gmc_v6_0_gart_enable(struct amdgpu_device *adev)
>  	int r, i;
>  	u32 field;
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>  		return -EINVAL;
>  	}
> @@ -588,7 +588,7 @@ static int gmc_v6_0_gart_init(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj) {
> +	if (adev->gart.bo) {
>  		dev_warn(adev->dev, "gmc_v6_0 PCIE GART already initialized\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> index 0c3a1618c3b7..c7cbd9f06892 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v7_0.c
> @@ -607,7 +607,7 @@ static int gmc_v7_0_gart_enable(struct amdgpu_device *adev)
>  	int r, i;
>  	u32 tmp, field;
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>  		return -EINVAL;
>  	}
> @@ -708,7 +708,7 @@ static int gmc_v7_0_gart_init(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj) {
> +	if (adev->gart.bo) {
>  		WARN(1, "R600 PCIE GART already initialized\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> index 274c9321d06c..21e3d9af370d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v8_0.c
> @@ -809,7 +809,7 @@ static int gmc_v8_0_gart_enable(struct amdgpu_device *adev)
>  	int r, i;
>  	u32 tmp, field;
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>  		return -EINVAL;
>  	}
> @@ -927,7 +927,7 @@ static int gmc_v8_0_gart_init(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj) {
> +	if (adev->gart.bo) {
>  		WARN(1, "R600 PCIE GART already initialized\n");
>  		return 0;
>  	}
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 25f614b91a9b..eb1936223748 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -843,7 +843,7 @@ static int gmc_v9_0_gart_init(struct amdgpu_device *adev)
>  {
>  	int r;
>  
> -	if (adev->gart.robj) {
> +	if (adev->gart.bo) {
>  		WARN(1, "VEGA10 PCIE GART already initialized\n");
>  		return 0;
>  	}
> @@ -1081,7 +1081,7 @@ static int gmc_v9_0_gart_enable(struct amdgpu_device *adev)
>  						golden_settings_vega10_hdp,
>  						ARRAY_SIZE(golden_settings_vega10_hdp));
>  
> -	if (adev->gart.robj == NULL) {
> +	if (adev->gart.bo == NULL) {
>  		dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
>  		return -EINVAL;
>  	}
> -- 
> 2.17.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 07/11] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Huang Rui]

On Thu, Aug 23, 2018 at 10:50:49AM +0800, Zhang, Jerry (Junwei) wrote:
> On 08/22/2018 11:05 PM, Christian König wrote:
> >Add the necessary handling.
> >
> >Signed-off-by: Christian König <christian.koenig@amd.com>
> 
> Looks going to use GTT for page table.
> What kind of scenario to use that?
> could it be replaced by CPU updating page table in system memory?

If the system bit is not set in the PTE entry, it will map the page of
video memory.

Thanks,
Ray

> 
> Regards,
> Jerry
> 
> >---
> >  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> >index e412eb8e347c..3393a329fc9c 100644
> >--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> >+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> >@@ -571,7 +571,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
> >  static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
> >  				uint64_t *addr, uint64_t *flags)
> >  {
> >-	if (!(*flags & AMDGPU_PDE_PTE))
> >+	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
> >  		*addr = adev->vm_manager.vram_base_offset + *addr -
> >  			adev->gmc.vram_start;
> >  	BUG_ON(*addr & 0xFFFF00000000003FULL);
> >
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 07/11] drm/amdgpu: add GMC9 support for PDs/PTs in system memory

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:13PM +0200, Christian König wrote:
> Add the necessary handling.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index e412eb8e347c..3393a329fc9c 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -571,7 +571,7 @@ static uint64_t gmc_v9_0_get_vm_pte_flags(struct amdgpu_device *adev,
>  static void gmc_v9_0_get_vm_pde(struct amdgpu_device *adev, int level,
>  				uint64_t *addr, uint64_t *flags)
>  {
> -	if (!(*flags & AMDGPU_PDE_PTE))
> +	if (!(*flags & AMDGPU_PDE_PTE) && !(*flags & AMDGPU_PTE_SYSTEM))
>  		*addr = adev->vm_manager.vram_base_offset + *addr -
>  			adev->gmc.vram_start;
>  	BUG_ON(*addr & 0xFFFF00000000003FULL);
> -- 
> 2.17.1
> 
> _______________________________________________
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> amd-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/amd-gfx
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Re: [PATCH 08/11] drm/amdgpu: add amdgpu_gmc_pd_addr helper

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:14PM +0200, Christian König wrote:
> Add a helper to get the root PD address and remove the workarounds from
> the GMC9 code for that.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/Makefile           |  3 +-
>  .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  2 +-
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 47 +++++++++++++++++++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  2 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  2 +-
>  drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c      |  7 +--
>  drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 --
>  drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  7 +--
>  9 files changed, 56 insertions(+), 23 deletions(-)
>  create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile b/drivers/gpu/drm/amd/amdgpu/Makefile
> index 860cb8731c7c..d2bafabe585d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
> @@ -51,7 +51,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
>  	amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
>  	amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
>  	amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o amdgpu_atomfirmware.o \
> -	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
> +	amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
> +	amdgpu_gmc.o
>  
>  # add asic specific block
>  amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> index 7eadc58231f2..2e2393fe09b2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
> @@ -364,7 +364,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>  	struct amdgpu_bo *pd = vm->root.base.bo;
>  	struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
>  	struct amdgpu_vm_parser param;
> -	uint64_t addr, flags = AMDGPU_PTE_VALID;
>  	int ret;
>  
>  	param.domain = AMDGPU_GEM_DOMAIN_VRAM;
> @@ -383,9 +382,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm *vm)
>  		return ret;
>  	}
>  
> -	addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> -	amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
> -	vm->pd_phys_addr = addr;
> +	vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>  
>  	if (vm->use_cpu_for_update) {
>  		ret = amdgpu_bo_kmap(pd, NULL);
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> index 17bf63f93c93..d268035cf2f3 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
> @@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct amdgpu_cs_parser *p)
>  	if (r)
>  		return r;
>  
> -	p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
> +	p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>  
>  	if (amdgpu_vm_debug) {
>  		/* Invalidate all BOs to test for userspace bugs */
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> new file mode 100644
> index 000000000000..36058feac64f
> --- /dev/null
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -0,0 +1,47 @@
> +/*
> + * Copyright 2018 Advanced Micro Devices, Inc.
> + * All Rights Reserved.
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> + * copy of this software and associated documentation files (the
> + * "Software"), to deal in the Software without restriction, including
> + * without limitation the rights to use, copy, modify, merge, publish,
> + * distribute, sub license, and/or sell copies of the Software, and to
> + * permit persons to whom the Software is furnished to do so, subject to
> + * the following conditions:
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
> + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
> + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> + * USE OR OTHER DEALINGS IN THE SOFTWARE.
> + *
> + * The above copyright notice and this permission notice (including the
> + * next paragraph) shall be included in all copies or substantial portions
> + * of the Software.
> + *
> + */
> +
> +#include "amdgpu.h"
> +
> +/**
> + * amdgpu_gmc_pd_addr - return the address of the root directory
> + *
> + */
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	uint64_t pd_addr;
> +
> +	pd_addr = amdgpu_bo_gpu_offset(bo);
> +	/* TODO: move that into ASIC specific code */
> +	if (adev->asic_type >= CHIP_VEGA10) {
> +		uint64_t flags = AMDGPU_PTE_VALID;
> +
> +		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +		pd_addr |= flags;
> +	}
> +	return pd_addr;
> +}
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index f3ea0a6d4660..7c469cce0498 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,4 +131,6 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>  	return (gmc->real_vram_size == gmc->visible_vram_size);
>  }
>  
> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
> +
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index e7f73deed975..eb08a03b82a0 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
>  		return r;
>  
>  	if (vm_needs_flush) {
> -		job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
> +		job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
>  		job->vm_needs_flush = true;
>  	}
>  	if (resv) {
> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> index 2baab7e69ef5..3403ded39d13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
> @@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
>  
>  static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>  {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /*valid bit*/
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>  
>  	WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>  		     lower_32_bits(value));
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> index 3393a329fc9c..e12e007cf7d9 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
> @@ -436,12 +436,8 @@ static uint64_t gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>  	struct amdgpu_device *adev = ring->adev;
>  	struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>  	uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
> -	uint64_t flags = AMDGPU_PTE_VALID;
>  	unsigned eng = ring->vm_inv_eng;
>  
> -	amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> -	pd_addr |= flags;
> -
>  	amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
>  			      lower_32_bits(pd_addr));
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> index 800ec4687f13..5f6a9c85488f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
> @@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct amdgpu_device *adev)
>  
>  static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>  {
> -	uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
> -
> -	BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
> -	value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
> -	value &= 0x0000FFFFFFFFF000ULL;
> -	value |= 0x1; /* valid bit */
> +	uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>  
>  	WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>  		     lower_32_bits(value));
> -- 
> 2.17.1
> 
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Re: [PATCH 02/11] drm/amdgpu: validate the VM root PD from the VM code

[Christian König]

Am 23.08.2018 um 09:28 schrieb Huang Rui:
> On Wed, Aug 22, 2018 at 05:05:08PM +0200, Christian König wrote:
>> Preparation for following changes. This validates the root PD twice,
>> but the overhead of that should be minimal.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 8 ++++----
>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> index 73b8dcaf66e6..53ce9982a5ee 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>> @@ -291,11 +291,11 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>   	list_for_each_entry_safe(bo_base, tmp, &vm->evicted, vm_status) {
>>   		struct amdgpu_bo *bo = bo_base->bo;
>>   
>> -		if (bo->parent) {
>> -			r = validate(param, bo);
>> -			if (r)
>> -				break;
>> +		r = validate(param, bo);
>> +		if (r)
>> +			break;
> In orignal case, we skip the root PD. But now, it is validated one time.
> May I know where is another time?

That is in the CS code, we add the root PD to the list of BOs which are 
validated there.

Christian.

>
> Thanks,
> Ray
>
>>   
>> +		if (bo->parent) {
>>   			spin_lock(&glob->lru_lock);
>>   			ttm_bo_move_to_lru_tail(&bo->tbo);
>>   			if (bo->shadow)
>> -- 
>> 2.17.1
>>
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>> amd-gfx@lists.freedesktop.org
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Re: [PATCH 08/11] drm/amdgpu: add amdgpu_gmc_pd_addr helper

[Christian König]

Am 23.08.2018 um 05:07 schrieb Zhang, Jerry (Junwei):
> On 08/22/2018 11:05 PM, Christian König wrote:
>> Add a helper to get the root PD address and remove the workarounds from
>> the GMC9 code for that.
>>
>> Signed-off-by: Christian König <christian.koenig@amd.com>
>> ---
>>   drivers/gpu/drm/amd/amdgpu/Makefile           |  3 +-
>>   .../gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c  |  5 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c        |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c       | 47 +++++++++++++++++++
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h       |  2 +
>>   drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c       |  2 +-
>>   drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c      |  7 +--
>>   drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c         |  4 --
>>   drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c       |  7 +--
>>   9 files changed, 56 insertions(+), 23 deletions(-)
>>   create mode 100644 drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/Makefile 
>> b/drivers/gpu/drm/amd/amdgpu/Makefile
>> index 860cb8731c7c..d2bafabe585d 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/Makefile
>> +++ b/drivers/gpu/drm/amd/amdgpu/Makefile
>> @@ -51,7 +51,8 @@ amdgpu-y += amdgpu_device.o amdgpu_kms.o \
>>       amdgpu_prime.o amdgpu_vm.o amdgpu_ib.o amdgpu_pll.o \
>>       amdgpu_ucode.o amdgpu_bo_list.o amdgpu_ctx.o amdgpu_sync.o \
>>       amdgpu_gtt_mgr.o amdgpu_vram_mgr.o amdgpu_virt.o 
>> amdgpu_atomfirmware.o \
>> -    amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o
>> +    amdgpu_vf_error.o amdgpu_sched.o amdgpu_debugfs.o amdgpu_ids.o \
>> +    amdgpu_gmc.o
>>
>>   # add asic specific block
>>   amdgpu-$(CONFIG_DRM_AMDGPU_CIK)+= cik.o cik_ih.o kv_smc.o kv_dpm.o \
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> index 7eadc58231f2..2e2393fe09b2 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
>> @@ -364,7 +364,6 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm 
>> *vm)
>>       struct amdgpu_bo *pd = vm->root.base.bo;
>>       struct amdgpu_device *adev = amdgpu_ttm_adev(pd->tbo.bdev);
>>       struct amdgpu_vm_parser param;
>> -    uint64_t addr, flags = AMDGPU_PTE_VALID;
>>       int ret;
>>
>>       param.domain = AMDGPU_GEM_DOMAIN_VRAM;
>> @@ -383,9 +382,7 @@ static int vm_validate_pt_pd_bos(struct amdgpu_vm 
>> *vm)
>>           return ret;
>>       }
>>
>> -    addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
>> -    amdgpu_gmc_get_vm_pde(adev, -1, &addr, &flags);
>> -    vm->pd_phys_addr = addr;
>> +    vm->pd_phys_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>>
>>       if (vm->use_cpu_for_update) {
>>           ret = amdgpu_bo_kmap(pd, NULL);
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> index 17bf63f93c93..d268035cf2f3 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c
>> @@ -946,7 +946,7 @@ static int amdgpu_cs_vm_handling(struct 
>> amdgpu_cs_parser *p)
>>       if (r)
>>           return r;
>>
>> -    p->job->vm_pd_addr = amdgpu_bo_gpu_offset(vm->root.base.bo);
>> +    p->job->vm_pd_addr = amdgpu_gmc_pd_addr(vm->root.base.bo);
>>
>>       if (amdgpu_vm_debug) {
>>           /* Invalidate all BOs to test for userspace bugs */
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> new file mode 100644
>> index 000000000000..36058feac64f
>> --- /dev/null
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
>> @@ -0,0 +1,47 @@
>> +/*
>> + * Copyright 2018 Advanced Micro Devices, Inc.
>> + * All Rights Reserved.
>> + *
>> + * Permission is hereby granted, free of charge, to any person 
>> obtaining a
>> + * copy of this software and associated documentation files (the
>> + * "Software"), to deal in the Software without restriction, including
>> + * without limitation the rights to use, copy, modify, merge, publish,
>> + * distribute, sub license, and/or sell copies of the Software, and to
>> + * permit persons to whom the Software is furnished to do so, 
>> subject to
>> + * the following conditions:
>> + *
>> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 
>> EXPRESS OR
>> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 
>> MERCHANTABILITY,
>> + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO 
>> EVENT SHALL
>> + * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR 
>> ANY CLAIM,
>> + * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 
>> TORT OR
>> + * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 
>> SOFTWARE OR THE
>> + * USE OR OTHER DEALINGS IN THE SOFTWARE.
>> + *
>> + * The above copyright notice and this permission notice (including the
>> + * next paragraph) shall be included in all copies or substantial 
>> portions
>> + * of the Software.
>> + *
>> + */
>> +
>> +#include "amdgpu.h"
>> +
>> +/**
>> + * amdgpu_gmc_pd_addr - return the address of the root directory
>> + *
>> + */
>> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>
> If the func is going to handle all pd address, it's better to be 
> called in gmc6,7,8 as well.
>
>> +{
>> +    struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>> +    uint64_t pd_addr;
>> +
>> +    pd_addr = amdgpu_bo_gpu_offset(bo);
>> +    /* TODO: move that into ASIC specific code */
>
> Sounds it could be a func(.gmc_pd_addr) in the group of amdgpu_gmc_funcs?

GMC6,7 and 8 want an MC address, but GMC9 uses a PDE for the root PD 
address.

So the idea here is to get all ASIC specific flush functions to accept a 
PDE, cause that includes all the information you need and not only the 
MC address.

Regards,
Christian.

>
> Regards,
> Jerry
>
>> +    if (adev->asic_type >= CHIP_VEGA10) {
>> +        uint64_t flags = AMDGPU_PTE_VALID;
>> +
>> +        amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
>> +        pd_addr |= flags;
>> +    }
>> +    return pd_addr;
>> +}
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> index f3ea0a6d4660..7c469cce0498 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
>> @@ -131,4 +131,6 @@ static inline bool 
>> amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>>       return (gmc->real_vram_size == gmc->visible_vram_size);
>>   }
>>
>> +uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>> +
>>   #endif
>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c 
>> b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> index e7f73deed975..eb08a03b82a0 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
>> @@ -2049,7 +2049,7 @@ int amdgpu_copy_buffer(struct amdgpu_ring 
>> *ring, uint64_t src_offset,
>>           return r;
>>
>>       if (vm_needs_flush) {
>> -        job->vm_pd_addr = amdgpu_bo_gpu_offset(adev->gart.bo);
>> +        job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
>>           job->vm_needs_flush = true;
>>       }
>>       if (resv) {
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> index 2baab7e69ef5..3403ded39d13 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
>> @@ -37,12 +37,7 @@ u64 gfxhub_v1_0_get_mc_fb_offset(struct 
>> amdgpu_device *adev)
>>
>>   static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>>   {
>> -    uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
>> -
>> -    BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
>> -    value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
>> -    value &= 0x0000FFFFFFFFF000ULL;
>> -    value |= 0x1; /*valid bit*/
>> +    uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>>
>>       WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>>                lower_32_bits(value));
>> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> index 3393a329fc9c..e12e007cf7d9 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
>> @@ -436,12 +436,8 @@ static uint64_t 
>> gmc_v9_0_emit_flush_gpu_tlb(struct amdgpu_ring *ring,
>>       struct amdgpu_device *adev = ring->adev;
>>       struct amdgpu_vmhub *hub = &adev->vmhub[ring->funcs->vmhub];
>>       uint32_t req = gmc_v9_0_get_invalidate_req(vmid);
>> -    uint64_t flags = AMDGPU_PTE_VALID;
>>       unsigned eng = ring->vm_inv_eng;
>>
>> -    amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
>> -    pd_addr |= flags;
>> -
>>       amdgpu_ring_emit_wreg(ring, hub->ctx0_ptb_addr_lo32 + (2 * vmid),
>>                     lower_32_bits(pd_addr));
>>
>> diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c 
>> b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> index 800ec4687f13..5f6a9c85488f 100644
>> --- a/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> +++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c
>> @@ -47,12 +47,7 @@ u64 mmhub_v1_0_get_fb_location(struct 
>> amdgpu_device *adev)
>>
>>   static void mmhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
>>   {
>> -    uint64_t value = amdgpu_bo_gpu_offset(adev->gart.bo);
>> -
>> -    BUG_ON(value & (~0x0000FFFFFFFFF000ULL));
>> -    value -= adev->gmc.vram_start + adev->vm_manager.vram_base_offset;
>> -    value &= 0x0000FFFFFFFFF000ULL;
>> -    value |= 0x1; /* valid bit */
>> +    uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
>>
>>       WREG32_SOC15(MMHUB, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
>>                lower_32_bits(value));
>>

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Re: [PATCH 09/11] drm/amdgpu: add amdgpu_gmc_get_pde_for_bo helper

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:15PM +0200, Christian König wrote:
> Helper to get the PDE for a PD/PT.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c | 37 +++++++++++++++++++++++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h |  2 ++
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c | 21 ++++++++++++--
>  drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h |  1 +
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c  |  4 +--
>  5 files changed, 57 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> index 36058feac64f..6f79ce108728 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.c
> @@ -26,6 +26,38 @@
>  
>  #include "amdgpu.h"
>  
> +/**
> + * amdgpu_gmc_get_pde_for_bo - get the PDE for a BO
> + *
> + * @bo: the BO to get the PDE for
> + * @level: the level in the PD hirarchy
> + * @addr: resulting addr
> + * @flags: resulting flags
> + *
> + * Get the address and flags to be used for a PDE.
> + */
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +			       uint64_t *addr, uint64_t *flags)
> +{
> +	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
> +	struct ttm_dma_tt *ttm;
> +
> +	switch (bo->tbo.mem.mem_type) {
> +	case TTM_PL_TT:
> +		ttm = container_of(bo->tbo.ttm, struct ttm_dma_tt, ttm);
> +		*addr = ttm->dma_address[0];
> +		break;
> +	case TTM_PL_VRAM:
> +		*addr = amdgpu_bo_gpu_offset(bo);
> +		break;
> +	default:
> +		*addr = 0;
> +		break;
> +	}
> +	*flags = amdgpu_ttm_tt_pde_flags(bo->tbo.ttm, &bo->tbo.mem);
> +	amdgpu_gmc_get_vm_pde(adev, level, addr, flags);
> +}
> +
>  /**
>   * amdgpu_gmc_pd_addr - return the address of the root directory
>   *
> @@ -35,13 +67,14 @@ uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo)
>  	struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
>  	uint64_t pd_addr;
>  
> -	pd_addr = amdgpu_bo_gpu_offset(bo);
>  	/* TODO: move that into ASIC specific code */
>  	if (adev->asic_type >= CHIP_VEGA10) {
>  		uint64_t flags = AMDGPU_PTE_VALID;
>  
> -		amdgpu_gmc_get_vm_pde(adev, -1, &pd_addr, &flags);
> +		amdgpu_gmc_get_pde_for_bo(bo, -1, &pd_addr, &flags);
>  		pd_addr |= flags;
> +	} else {
> +		pd_addr = amdgpu_bo_gpu_offset(bo);
>  	}
>  	return pd_addr;
>  }
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> index 7c469cce0498..0d2c9f65ca13 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.h
> @@ -131,6 +131,8 @@ static inline bool amdgpu_gmc_vram_full_visible(struct amdgpu_gmc *gmc)
>  	return (gmc->real_vram_size == gmc->visible_vram_size);
>  }
>  
> +void amdgpu_gmc_get_pde_for_bo(struct amdgpu_bo *bo, int level,
> +			       uint64_t *addr, uint64_t *flags);
>  uint64_t amdgpu_gmc_pd_addr(struct amdgpu_bo *bo);
>  
>  #endif
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> index eb08a03b82a0..72366643e3c2 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.c
> @@ -1428,13 +1428,14 @@ bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm)
>  }
>  
>  /**
> - * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + * amdgpu_ttm_tt_pde_flags - Compute PDE flags for ttm_tt object
>   *
>   * @ttm: The ttm_tt object to compute the flags for
>   * @mem: The memory registry backing this ttm_tt object
> + *
> + * Figure out the flags to use for a VM PDE.
>   */
> -uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> -				 struct ttm_mem_reg *mem)
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem)
>  {
>  	uint64_t flags = 0;
>  
> @@ -1448,6 +1449,20 @@ uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>  			flags |= AMDGPU_PTE_SNOOPED;
>  	}
>  
> +	return flags;
> +}
> +
> +/**
> + * amdgpu_ttm_tt_pte_flags - Compute PTE flags for ttm_tt object
> + *
> + * @ttm: The ttm_tt object to compute the flags for
> + * @mem: The memory registry backing this ttm_tt object
> + */
> +uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
> +				 struct ttm_mem_reg *mem)
> +{
> +	uint64_t flags = amdgpu_ttm_tt_pde_flags(ttm, mem);
> +
>  	flags |= adev->gart.gart_pte_flags;
>  	flags |= AMDGPU_PTE_READABLE;
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> index 8b3cc6687769..fe8f276e9811 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.h
> @@ -116,6 +116,7 @@ bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
>  				       int *last_invalidated);
>  bool amdgpu_ttm_tt_userptr_needs_pages(struct ttm_tt *ttm);
>  bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
> +uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_mem_reg *mem);
>  uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
>  				 struct ttm_mem_reg *mem);
>  
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 53ce9982a5ee..87e3d44b0a3f 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -982,9 +982,7 @@ static void amdgpu_vm_update_pde(struct amdgpu_pte_update_params *params,
>  		pbo = pbo->parent;
>  
>  	level += params->adev->vm_manager.root_level;
> -	pt = amdgpu_bo_gpu_offset(entry->base.bo);
> -	flags = AMDGPU_PTE_VALID;
> -	amdgpu_gmc_get_vm_pde(params->adev, level, &pt, &flags);
> +	amdgpu_gmc_get_pde_for_bo(entry->base.bo, level, &pt, &flags);
>  	pde = (entry - parent->entries) * 8;
>  	if (bo->shadow)
>  		params->func(params, bo->shadow, pde, pt, 1, 0, flags);
> -- 
> 2.17.1
> 
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Re: [PATCH 10/11] drm/amdgpu: add helper for VM PD/PT allocation parameters

[Huang Rui]

On Wed, Aug 22, 2018 at 05:05:16PM +0200, Christian König wrote:
> Add a helper function to figure them out only once.
> 
> Signed-off-by: Christian König <christian.koenig@amd.com>

Reviewed-by: Huang Rui <ray.huang@amd.com>

> ---
>  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 61 ++++++++++++--------------
>  1 file changed, 28 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> index 87e3d44b0a3f..928fdae0dab4 100644
> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> @@ -446,6 +446,31 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>  	return r;
>  }
>  
> +/**
> + * amdgpu_vm_bo_param - fill in parameters for PD/PT allocation
> + *
> + * @adev: amdgpu_device pointer
> + * @vm: requesting vm
> + * @bp: resulting BO allocation parameters
> + */
> +static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> +			       int level, struct amdgpu_bo_param *bp)
> +{
> +	memset(&bp, 0, sizeof(bp));
> +
> +	bp->size = amdgpu_vm_bo_size(adev, level);
> +	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
> +	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> +	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> +	if (vm->use_cpu_for_update)
> +		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> +	else
> +		bp->flags |= AMDGPU_GEM_CREATE_SHADOW;
> +	bp->type = ttm_bo_type_kernel;
> +	if (vm->root.base.bo)
> +		bp->resv = vm->root.base.bo->tbo.resv;
> +}
> +
>  /**
>   * amdgpu_vm_alloc_levels - allocate the PD/PT levels
>   *
> @@ -469,8 +494,8 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>  				  unsigned level, bool ats)
>  {
>  	unsigned shift = amdgpu_vm_level_shift(adev, level);
> +	struct amdgpu_bo_param bp;
>  	unsigned pt_idx, from, to;
> -	u64 flags;
>  	int r;
>  
>  	if (!parent->entries) {
> @@ -494,29 +519,14 @@ static int amdgpu_vm_alloc_levels(struct amdgpu_device *adev,
>  	saddr = saddr & ((1 << shift) - 1);
>  	eaddr = eaddr & ((1 << shift) - 1);
>  
> -	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -	if (vm->use_cpu_for_update)
> -		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -	else
> -		flags |= (AMDGPU_GEM_CREATE_NO_CPU_ACCESS |
> -				AMDGPU_GEM_CREATE_SHADOW);
> +	amdgpu_vm_bo_param(adev, vm, level, &bp);
>  
>  	/* walk over the address space and allocate the page tables */
>  	for (pt_idx = from; pt_idx <= to; ++pt_idx) {
> -		struct reservation_object *resv = vm->root.base.bo->tbo.resv;
>  		struct amdgpu_vm_pt *entry = &parent->entries[pt_idx];
>  		struct amdgpu_bo *pt;
>  
>  		if (!entry->base.bo) {
> -			struct amdgpu_bo_param bp;
> -
> -			memset(&bp, 0, sizeof(bp));
> -			bp.size = amdgpu_vm_bo_size(adev, level);
> -			bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -			bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -			bp.flags = flags;
> -			bp.type = ttm_bo_type_kernel;
> -			bp.resv = resv;
>  			r = amdgpu_bo_create(adev, &bp, &pt);
>  			if (r)
>  				return r;
> @@ -2564,8 +2574,6 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  {
>  	struct amdgpu_bo_param bp;
>  	struct amdgpu_bo *root;
> -	unsigned long size;
> -	uint64_t flags;
>  	int r, i;
>  
>  	vm->va = RB_ROOT_CACHED;
> @@ -2602,20 +2610,7 @@ int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>  		  "CPU update of VM recommended only for large BAR system\n");
>  	vm->last_update = NULL;
>  
> -	flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> -	if (vm->use_cpu_for_update)
> -		flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> -	else
> -		flags |= AMDGPU_GEM_CREATE_SHADOW;
> -
> -	size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
> -	memset(&bp, 0, sizeof(bp));
> -	bp.size = size;
> -	bp.byte_align = AMDGPU_GPU_PAGE_SIZE;
> -	bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
> -	bp.flags = flags;
> -	bp.type = ttm_bo_type_kernel;
> -	bp.resv = NULL;
> +	amdgpu_vm_bo_param(adev, vm, adev->vm_manager.root_level, &bp);
>  	r = amdgpu_bo_create(adev, &bp, &root);
>  	if (r)
>  		goto error_free_sched_entity;
> -- 
> 2.17.1
> 
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Re: [PATCH 11/11] drm/amdgpu: enable GTT PD/PT for raven

[Huang Rui]

On Wed, Aug 22, 2018 at 11:44:04AM -0400, Andrey Grodzovsky wrote:
> 
> 
> On 08/22/2018 11:05 AM, Christian König wrote:
> >Should work on Vega10 as well, but with an obvious performance hit.
> >
> >Older APUs can be enabled as well, but will probably be more work.

Raven's VRAM is actually the system memory. May I know the benefit if we
switch the PD/PT BO from vram to gart?

> >
> >Signed-off-by: Christian König <christian.koenig@amd.com>
> >---
> >  drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
> >  1 file changed, 10 insertions(+), 1 deletion(-)
> >
> >diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >index 928fdae0dab4..670a42729f88 100644
> >--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
> >@@ -308,6 +308,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> >  			list_move(&bo_base->vm_status, &vm->moved);
> >  			spin_unlock(&vm->moved_lock);
> >  		} else {
> >+			amdgpu_ttm_alloc_gart(&bo->tbo);
> 
> Looks like you forgot to check for return value here.
> 

Yes, the same comment with me. 

Thanks,
Ray

> Andrey
> 
> >  			list_move(&bo_base->vm_status, &vm->relocated);
> >  		}
> >  	}
> >@@ -396,6 +397,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
> >  	if (r)
> >  		goto error;
> >+	r = amdgpu_ttm_alloc_gart(&bo->tbo);
> >+	if (r)
> >+		return r;
> >+
> >  	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
> >  	if (r)
> >  		goto error;
> >@@ -461,7 +466,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
> >  	bp->size = amdgpu_vm_bo_size(adev, level);
> >  	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
> >  	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
> >-	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
> >+	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)
> >+		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
> >+	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
> >+	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
> >+		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
> >  	if (vm->use_cpu_for_update)
> >  		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
> >  	else
> 
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Re: [PATCH 11/11] drm/amdgpu: enable GTT PD/PT for raven

[Christian König]

Am 23.08.2018 um 14:54 schrieb Huang Rui:
> On Wed, Aug 22, 2018 at 11:44:04AM -0400, Andrey Grodzovsky wrote:
>>
>> On 08/22/2018 11:05 AM, Christian König wrote:
>>> Should work on Vega10 as well, but with an obvious performance hit.
>>>
>>> Older APUs can be enabled as well, but will probably be more work.
> Raven's VRAM is actually the system memory. May I know the benefit if we
> switch the PD/PT BO from vram to gart?

We want to reduce VRAM usage as much as possible on APUs.

The end goal is that it should work with only 16MB (or was it 32MB?) 
stolen VRAM.

That is the recommended setting for newer OSes on that hardware.

Christian.

>
>>> Signed-off-by: Christian König <christian.koenig@amd.com>
>>> ---
>>>   drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c | 11 ++++++++++-
>>>   1 file changed, 10 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> index 928fdae0dab4..670a42729f88 100644
>>> --- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> +++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
>>> @@ -308,6 +308,7 @@ int amdgpu_vm_validate_pt_bos(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>>   			list_move(&bo_base->vm_status, &vm->moved);
>>>   			spin_unlock(&vm->moved_lock);
>>>   		} else {
>>> +			amdgpu_ttm_alloc_gart(&bo->tbo);
>> Looks like you forgot to check for return value here.
>>
> Yes, the same comment with me.
>
> Thanks,
> Ray
>
>> Andrey
>>
>>>   			list_move(&bo_base->vm_status, &vm->relocated);
>>>   		}
>>>   	}
>>> @@ -396,6 +397,10 @@ static int amdgpu_vm_clear_bo(struct amdgpu_device *adev,
>>>   	if (r)
>>>   		goto error;
>>> +	r = amdgpu_ttm_alloc_gart(&bo->tbo);
>>> +	if (r)
>>> +		return r;
>>> +
>>>   	r = amdgpu_job_alloc_with_ib(adev, 64, &job);
>>>   	if (r)
>>>   		goto error;
>>> @@ -461,7 +466,11 @@ static void amdgpu_vm_bo_param(struct amdgpu_device *adev, struct amdgpu_vm *vm,
>>>   	bp->size = amdgpu_vm_bo_size(adev, level);
>>>   	bp->byte_align = AMDGPU_GPU_PAGE_SIZE;
>>>   	bp->domain = AMDGPU_GEM_DOMAIN_VRAM;
>>> -	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
>>> +	if (bp->size <= PAGE_SIZE && adev->asic_type == CHIP_RAVEN)
>>> +		bp->domain |= AMDGPU_GEM_DOMAIN_GTT;
>>> +	bp->domain = amdgpu_bo_get_preferred_pin_domain(adev, bp->domain);
>>> +	bp->flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS |
>>> +		AMDGPU_GEM_CREATE_CPU_GTT_USWC;
>>>   	if (vm->use_cpu_for_update)
>>>   		bp->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
>>>   	else
>> _______________________________________________
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