* [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
@ 2018-08-24 1:48 Manasi Navare
2018-08-24 2:09 ` ✓ Fi.CI.BAT: success for " Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Manasi Navare @ 2018-08-24 1:48 UTC (permalink / raw)
To: intel-gfx
This patch fixes the PPS4 and PPS register definition macros that were
resulting into an incorect MMIO address.
Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 41ab5b56ee52..64d7e675f7e8 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -10488,7 +10488,7 @@ enum skl_power_gate {
_ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
_ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
#define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
#define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
#define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
@@ -10503,7 +10503,7 @@ enum skl_power_gate {
_ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
_ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
#define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
- _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
+ _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
#define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
#define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
--
2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 5+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
@ 2018-08-24 2:09 ` Patchwork
2018-08-24 2:59 ` ✓ Fi.CI.IGT: " Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-08-24 2:09 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
URL : https://patchwork.freedesktop.org/series/48648/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4703 -> Patchwork_10003 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/48648/revisions/1/mbox/
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10003:
=== IGT changes ===
==== Warnings ====
{igt@kms_psr@primary_page_flip}:
fi-cnl-psr: DMESG-FAIL -> DMESG-WARN
== Known issues ==
Here are the changes found in Patchwork_10003 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_frontbuffer_tracking@basic:
{fi-byt-clapper}: PASS -> FAIL (fdo#103167)
igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
fi-skl-guc: PASS -> FAIL (fdo#103191)
{igt@pm_rpm@module-reload}:
fi-cnl-psr: PASS -> WARN (fdo#107602)
==== Possible fixes ====
igt@drv_selftest@live_hangcheck:
{fi-bdw-samus}: DMESG-FAIL (fdo#106560) -> PASS
igt@gem_sync@basic-many-each:
{fi-byt-clapper}: FAIL -> PASS
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
== Participating hosts (53 -> 48) ==
Missing (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4703 -> Patchwork_10003
CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10003: 014ec179c9e9db7d80b9a4e9913945ab0cf8e311 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
014ec179c9e9 drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10003/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* ✓ Fi.CI.IGT: success for drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
2018-08-24 2:09 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2018-08-24 2:59 ` Patchwork
2018-08-24 6:07 ` [PATCH] " Rodrigo Vivi
2018-08-24 17:14 ` Srivatsa, Anusha
3 siblings, 0 replies; 5+ messages in thread
From: Patchwork @ 2018-08-24 2:59 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
URL : https://patchwork.freedesktop.org/series/48648/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4703_full -> Patchwork_10003_full =
== Summary - SUCCESS ==
No regressions found.
== Known issues ==
Here are the changes found in Patchwork_10003_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_suspend@shrink:
shard-snb: PASS -> INCOMPLETE (fdo#106886, fdo#105411)
igt@kms_busy@basic-modeset-a:
shard-glk: PASS -> DMESG-WARN (fdo#105763) +2
igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
shard-glk: PASS -> FAIL (fdo#103184)
igt@kms_flip@modeset-vs-vblank-race:
shard-apl: PASS -> FAIL (fdo#103060)
==== Possible fixes ====
igt@gem_ctx_isolation@bcs0-s3:
shard-kbl: INCOMPLETE (fdo#103665) -> PASS
igt@gem_exec_big:
shard-hsw: INCOMPLETE (fdo#103540) -> PASS
igt@kms_setmode@basic:
shard-kbl: FAIL (fdo#99912) -> PASS
fdo#103060 https://bugs.freedesktop.org/show_bug.cgi?id=103060
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#106886 https://bugs.freedesktop.org/show_bug.cgi?id=106886
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (5 -> 5) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_4703 -> Patchwork_10003
CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10003: 014ec179c9e9db7d80b9a4e9913945ab0cf8e311 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10003/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
2018-08-24 2:09 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-08-24 2:59 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-08-24 6:07 ` Rodrigo Vivi
2018-08-24 17:14 ` Srivatsa, Anusha
3 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2018-08-24 6:07 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
On Thu, Aug 23, 2018 at 06:48:07PM -0700, Manasi Navare wrote:
> This patch fixes the PPS4 and PPS register definition macros that were
> resulting into an incorect MMIO address.
>
> Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
> Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
(also checked others around to see if there was similar issues,
but the rest seems right)
> ---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 41ab5b56ee52..64d7e675f7e8 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -10488,7 +10488,7 @@ enum skl_power_gate {
> _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> _ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
> @@ -10503,7 +10503,7 @@ enum skl_power_gate {
> _ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
> _ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) - PIPE_B, \
> - _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
> + _ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
> _ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
` (2 preceding siblings ...)
2018-08-24 6:07 ` [PATCH] " Rodrigo Vivi
@ 2018-08-24 17:14 ` Srivatsa, Anusha
3 siblings, 0 replies; 5+ messages in thread
From: Srivatsa, Anusha @ 2018-08-24 17:14 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx
>-----Original Message-----
>From: Navare, Manasi D
>Sent: Thursday, August 23, 2018 6:48 PM
>To: intel-gfx@lists.freedesktop.org
>Cc: Navare, Manasi D <manasi.d.navare@intel.com>; Srivatsa, Anusha
><anusha.srivatsa@intel.com>
>Subject: [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC
>engine
>
>This patch fixes the PPS4 and PPS register definition macros that were resulting
>into an incorect MMIO address.
>
>Fixes: 2efbb2f099fb ("i915/dp/dsc: Add DSC PPS register definitions")
>Cc: Anusha Srivatsa <anusha.srivatsa@intel.com>
>Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
>---
> drivers/gpu/drm/i915/i915_reg.h | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
>index 41ab5b56ee52..64d7e675f7e8 100644
>--- a/drivers/gpu/drm/i915/i915_reg.h
>+++ b/drivers/gpu/drm/i915/i915_reg.h
>@@ -10488,7 +10488,7 @@ enum skl_power_gate {
>
>_ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
>
>_ICL_DSC0_PICTURE_PARAMETER_SET_4_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_4(pipe) _MMIO_PIPE((pipe) -
>PIPE_B, \
>-
>_ICL_DSC0_PICTURE_PARAMETER_SET_4_PB, \
>+
>_ICL_DSC1_PICTURE_PARAMETER_SET_4_PB, \
>
>_ICL_DSC1_PICTURE_PARAMETER_SET_4_PC)
> #define DSC_INITIAL_DEC_DELAY(dec_delay) ((dec_delay) << 16)
> #define DSC_INITIAL_XMIT_DELAY(xmit_delay) ((xmit_delay) << 0)
>@@ -10503,7 +10503,7 @@ enum skl_power_gate {
>
>_ICL_DSC0_PICTURE_PARAMETER_SET_5_PB, \
>
>_ICL_DSC0_PICTURE_PARAMETER_SET_5_PC)
> #define ICL_DSC1_PICTURE_PARAMETER_SET_5(pipe) _MMIO_PIPE((pipe) -
>PIPE_B, \
>-
>_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC, \
>+
>_ICL_DSC1_PICTURE_PARAMETER_SET_5_PB, \
>
>_ICL_DSC1_PICTURE_PARAMETER_SET_5_PC)
> #define DSC_SCALE_DEC_INT(scale_dec) ((scale_dec) << 16)
> #define DSC_SCALE_INC_INT(scale_inc) ((scale_inc) << 0)
>--
>2.18.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-08-24 17:14 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-24 1:48 [PATCH] drm/i915/dsc: Fix PPS register definition macros for 2nd VDSC engine Manasi Navare
2018-08-24 2:09 ` ✓ Fi.CI.BAT: success for " Patchwork
2018-08-24 2:59 ` ✓ Fi.CI.IGT: " Patchwork
2018-08-24 6:07 ` [PATCH] " Rodrigo Vivi
2018-08-24 17:14 ` Srivatsa, Anusha
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