[PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA

From: Mahesh Kumar <mahesh1.kumar@intel.com>
To: intel-gfx@lists.freedesktop.org
Cc: rodrigo.vivi@intel.com
Subject: [PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA
Date: Fri, 24 Aug 2018 15:02:20 +0530	[thread overview]
Message-ID: <20180824093225.12598-1-mahesh1.kumar@intel.com> (raw)

This series adds support to calculate system memdev parameters and calculate
total system memory bandwidth. This parameters and BW will be used to enable
WM level-0 latency workaround and display memory bandwidth related WA for gen9.

while we are here to enable IPC based on memory configuration lets also 
make sure that we override IPC value set of BIOS incase we decide to
disable IPC in KMS.

Mahesh Kumar (5):
  drm/i915/bxt: Decode memory bandwidth and parameters
  drm/i915/skl+: Decode memory bandwidth and parameters
  drm/i915: Implement 16GB dimm wa for latency level-0
  drm/i915/skl+: don't trust IPC value set by BIOS
  drm/i915/kbl+: Enable IPC only for symmetric memory configurations

 drivers/gpu/drm/i915/i915_drv.c | 300 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  23 +++
 drivers/gpu/drm/i915/i915_reg.h |  48 +++++++
 drivers/gpu/drm/i915/intel_pm.c |  22 ++-
 4 files changed, 390 insertions(+), 3 deletions(-)

-- 
2.16.2

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