[PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA

[PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA

[Mahesh Kumar]

This series adds support to calculate system memdev parameters and calculate
total system memory bandwidth. This parameters and BW will be used to enable
WM level-0 latency workaround and display memory bandwidth related WA for gen9.

while we are here to enable IPC based on memory configuration lets also 
make sure that we override IPC value set of BIOS incase we decide to
disable IPC in KMS.


Mahesh Kumar (5):
  drm/i915/bxt: Decode memory bandwidth and parameters
  drm/i915/skl+: Decode memory bandwidth and parameters
  drm/i915: Implement 16GB dimm wa for latency level-0
  drm/i915/skl+: don't trust IPC value set by BIOS
  drm/i915/kbl+: Enable IPC only for symmetric memory configurations

 drivers/gpu/drm/i915/i915_drv.c | 300 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  23 +++
 drivers/gpu/drm/i915/i915_reg.h |  48 +++++++
 drivers/gpu/drm/i915/intel_pm.c |  22 ++-
 4 files changed, 390 insertions(+), 3 deletions(-)

-- 
2.16.2

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[PATCH V3 1/5] drm/i915/bxt: Decode memory bandwidth and parameters

[Mahesh Kumar]

This patch adds support to decode system memory bandwidth and other
parameters for broxton platform, which will be used for arbitrated
display memory bandwidth calculation in GEN9 based platforms and
WM latency level-0 Work-around calculation on GEN9+ platforms.

Changes since V1:
 - s/memdev_info/dram_info
Changes since V2:
 - Adhere to i915 coding style (Rodrigo)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 117 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  11 ++++
 drivers/gpu/drm/i915/i915_reg.h |  30 +++++++++++
 3 files changed, 158 insertions(+)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 77a4a01ddc08..37fb609e6f80 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1076,6 +1076,117 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 	intel_gvt_sanitize_options(dev_priv);
 }
 
+static int
+bxt_get_dram_info(struct drm_i915_private *dev_priv)
+{
+	struct dram_info *dram_info = &dev_priv->dram_info;
+	u32 dram_channels;
+	u32 mem_freq_khz, val;
+	u8 num_active_channels;
+	int i;
+
+	val = I915_READ(BXT_P_CR_MC_BIOS_REQ_0_0_0);
+	mem_freq_khz = DIV_ROUND_UP((val & BXT_REQ_DATA_MASK) *
+				    BXT_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
+
+	dram_channels = val & BXT_DRAM_CHANNEL_ACTIVE_MASK;
+	num_active_channels = hweight32(dram_channels);
+
+	/* Each active bit represents 4-byte channel */
+	dram_info->bandwidth_kbps = (mem_freq_khz * num_active_channels * 4);
+
+	if (dram_info->bandwidth_kbps == 0) {
+		DRM_INFO("Couldn't get system memory bandwidth\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * Now read each DUNIT8/9/10/11 to check the rank of each dimms.
+	 */
+	for (i = BXT_D_CR_DRP0_DUNIT_START; i <= BXT_D_CR_DRP0_DUNIT_END; i++) {
+		u8 size, width;
+		enum dram_rank rank;
+		u32 tmp;
+
+		val = I915_READ(BXT_D_CR_DRP0_DUNIT(i));
+		if (val == 0xFFFFFFFF)
+			continue;
+
+		dram_info->num_channels++;
+		tmp = val & BXT_DRAM_RANK_MASK;
+
+		if (tmp == BXT_DRAM_RANK_SINGLE)
+			rank = I915_DRAM_RANK_SINGLE;
+		else if (tmp == BXT_DRAM_RANK_DUAL)
+			rank = I915_DRAM_RANK_DUAL;
+		else
+			rank = I915_DRAM_RANK_INVALID;
+
+		tmp = val & BXT_DRAM_SIZE_MASK;
+		if (tmp == BXT_DRAM_SIZE_4GB)
+			size = 4;
+		else if (tmp == BXT_DRAM_SIZE_6GB)
+			size = 6;
+		else if (tmp == BXT_DRAM_SIZE_8GB)
+			size = 8;
+		else if (tmp == BXT_DRAM_SIZE_12GB)
+			size = 12;
+		else if (tmp == BXT_DRAM_SIZE_16GB)
+			size = 16;
+		else
+			size = 0;
+
+		tmp = (val & BXT_DRAM_WIDTH_MASK) >> BXT_DRAM_WIDTH_SHIFT;
+		width = (1 << tmp) * 8;
+		DRM_DEBUG_KMS("dram size:%dGB width:X%d rank:%s\n", size,
+			      width, rank == I915_DRAM_RANK_SINGLE ? "single" :
+			      rank == I915_DRAM_RANK_DUAL ? "dual" : "unknown");
+
+		/*
+		 * If any of the channel is single rank channel,
+		 * worst case output will be same as if single rank
+		 * memory, so consider single rank memory.
+		 */
+		if (dram_info->rank == I915_DRAM_RANK_INVALID)
+			dram_info->rank = rank;
+		else if (rank == I915_DRAM_RANK_SINGLE)
+			dram_info->rank = I915_DRAM_RANK_SINGLE;
+	}
+
+	if (dram_info->rank == I915_DRAM_RANK_INVALID) {
+		DRM_INFO("couldn't get memory rank information\n");
+		return -EINVAL;
+	}
+
+	dram_info->valid = true;
+	return 0;
+}
+
+static void
+intel_get_dram_info(struct drm_i915_private *dev_priv)
+{
+	struct dram_info *dram_info = &dev_priv->dram_info;
+	int ret;
+
+	dram_info->valid = false;
+	dram_info->rank = I915_DRAM_RANK_INVALID;
+	dram_info->bandwidth_kbps = 0;
+	dram_info->num_channels = 0;
+
+	if (!IS_BROXTON(dev_priv))
+		return;
+
+	ret = bxt_get_dram_info(dev_priv);
+	if (ret)
+		return;
+
+	DRM_DEBUG_KMS("DRAM bandwidth:%d KBps, total-channels: %u\n",
+		      dram_info->bandwidth_kbps, dram_info->num_channels);
+	DRM_DEBUG_KMS("DRAM rank: %s rank\n",
+		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?
+		      "dual" : "single");
+}
+
 /**
  * i915_driver_init_hw - setup state requiring device access
  * @dev_priv: device private
@@ -1193,6 +1304,12 @@ static int i915_driver_init_hw(struct drm_i915_private *dev_priv)
 		goto err_msi;
 
 	intel_opregion_setup(dev_priv);
+	/*
+	 * Fill the dram structure to get the system raw bandwidth and
+	 * dram info. This will be used for memory latency calculation.
+	 */
+	intel_get_dram_info(dev_priv);
+
 
 	return 0;
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index e5b9d3c77139..5a8101f7b938 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1944,6 +1944,17 @@ struct drm_i915_private {
 		bool distrust_bios_wm;
 	} wm;
 
+	struct dram_info {
+		bool valid;
+		u8 num_channels;
+		enum dram_rank {
+			I915_DRAM_RANK_INVALID = 0,
+			I915_DRAM_RANK_SINGLE,
+			I915_DRAM_RANK_DUAL
+		} rank;
+		u32 bandwidth_kbps;
+	} dram_info;
+
 	struct i915_runtime_pm runtime_pm;
 
 	struct {
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index a338aaa2b313..5a6cd5a941c3 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9581,6 +9581,36 @@ enum skl_power_gate {
 #define  DC_STATE_DEBUG_MASK_CORES	(1 << 0)
 #define  DC_STATE_DEBUG_MASK_MEMORY_UP	(1 << 1)
 
+#define BXT_P_CR_MC_BIOS_REQ_0_0_0	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x7114)
+#define  BXT_REQ_DATA_MASK			0x3F
+#define  BXT_DRAM_CHANNEL_ACTIVE_SHIFT		12
+#define  BXT_DRAM_CHANNEL_ACTIVE_MASK		(0xF << 12)
+#define  BXT_MEMORY_FREQ_MULTIPLIER_HZ		133333333
+
+#define BXT_D_CR_DRP0_DUNIT8			0x1000
+#define BXT_D_CR_DRP0_DUNIT9			0x1200
+#define  BXT_D_CR_DRP0_DUNIT_START		8
+#define  BXT_D_CR_DRP0_DUNIT_END		11
+#define BXT_D_CR_DRP0_DUNIT(x)	_MMIO(MCHBAR_MIRROR_BASE_SNB + \
+				      _PICK_EVEN((x) - 8, BXT_D_CR_DRP0_DUNIT8,\
+						 BXT_D_CR_DRP0_DUNIT9))
+#define  BXT_DRAM_RANK_MASK			0x3
+#define  BXT_DRAM_RANK_SINGLE			0x1
+#define  BXT_DRAM_RANK_DUAL			0x3
+#define  BXT_DRAM_WIDTH_MASK			(0x3 << 4)
+#define  BXT_DRAM_WIDTH_SHIFT			4
+#define  BXT_DRAM_WIDTH_X8			(0x0 << 4)
+#define  BXT_DRAM_WIDTH_X16			(0x1 << 4)
+#define  BXT_DRAM_WIDTH_X32			(0x2 << 4)
+#define  BXT_DRAM_WIDTH_X64			(0x3 << 4)
+#define  BXT_DRAM_SIZE_MASK			(0x7 << 6)
+#define  BXT_DRAM_SIZE_SHIFT			6
+#define  BXT_DRAM_SIZE_4GB			(0x0 << 6)
+#define  BXT_DRAM_SIZE_6GB			(0x1 << 6)
+#define  BXT_DRAM_SIZE_8GB			(0x2 << 6)
+#define  BXT_DRAM_SIZE_12GB			(0x3 << 6)
+#define  BXT_DRAM_SIZE_16GB			(0x4 << 6)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
-- 
2.16.2

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[PATCH V3 2/5] drm/i915/skl+: Decode memory bandwidth and parameters

[Mahesh Kumar]

This patch adds support to decode system memory bandwidth and other
parameters for skylake and Gen9+ platforms, which will be used for
arbitrated display memory bandwidth calculation in GEN9 based
platforms and WM latency level-0 Work-around calculation on GEN9+.

Changes Since V1:
 - s/memdev_info/dram_info
 - create a struct to hold channel info
Changes Since V2:
 - rewrite code to adhere i915 coding style
 - not valid for GLK

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 145 ++++++++++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h |   8 +++
 drivers/gpu/drm/i915/i915_reg.h |  18 +++++
 3 files changed, 167 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 37fb609e6f80..e09e9ce8fadf 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1076,6 +1076,132 @@ static void intel_sanitize_options(struct drm_i915_private *dev_priv)
 	intel_gvt_sanitize_options(dev_priv);
 }
 
+static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
+{
+	if (size == 0)
+		return I915_DRAM_RANK_INVALID;
+	if (rank == SKL_DRAM_RANK_SINGLE)
+		return I915_DRAM_RANK_SINGLE;
+	else if (rank == SKL_DRAM_RANK_DUAL)
+		return I915_DRAM_RANK_DUAL;
+
+	return I915_DRAM_RANK_INVALID;
+}
+
+static int
+skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
+{
+	u32 tmp_l, tmp_s;
+	u32 s_val = val >> SKL_DRAM_S_SHIFT;
+
+	if (!val)
+		return -EINVAL;
+
+	tmp_l = val & SKL_DRAM_SIZE_MASK;
+	tmp_s = s_val & SKL_DRAM_SIZE_MASK;
+
+	if (tmp_l == 0 && tmp_s == 0)
+		return -EINVAL;
+
+	ch->l_info.size = tmp_l;
+	ch->s_info.size = tmp_s;
+
+	tmp_l = (val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
+	tmp_s = (s_val & SKL_DRAM_WIDTH_MASK) >> SKL_DRAM_WIDTH_SHIFT;
+	ch->l_info.width = (1 << tmp_l) * 8;
+	ch->s_info.width = (1 << tmp_s) * 8;
+
+	tmp_l = val & SKL_DRAM_RANK_MASK;
+	tmp_s = s_val & SKL_DRAM_RANK_MASK;
+	ch->l_info.rank = skl_get_dimm_rank(ch->l_info.size, tmp_l);
+	ch->s_info.rank = skl_get_dimm_rank(ch->s_info.size, tmp_s);
+
+	if (ch->l_info.rank == I915_DRAM_RANK_DUAL ||
+	    ch->s_info.rank == I915_DRAM_RANK_DUAL)
+		ch->rank = I915_DRAM_RANK_DUAL;
+	else if (ch->l_info.rank == I915_DRAM_RANK_SINGLE &&
+		 ch->s_info.rank == I915_DRAM_RANK_SINGLE)
+		ch->rank = I915_DRAM_RANK_DUAL;
+	else
+		ch->rank = I915_DRAM_RANK_SINGLE;
+
+	DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
+		      ch->l_info.size, ch->l_info.width,
+		      ch->l_info.rank ? "dual" : "single",
+		      ch->s_info.size, ch->s_info.width,
+		      ch->s_info.rank ? "dual" : "single");
+
+	return 0;
+}
+
+static int
+skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
+{
+	struct dram_info *dram_info = &dev_priv->dram_info;
+	struct dram_channel_info ch0, ch1;
+	u32 val;
+	int ret;
+
+	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+	ret = skl_dram_get_channel_info(&ch0, val);
+	if (ret == 0)
+		dram_info->num_channels++;
+
+	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+	ret = skl_dram_get_channel_info(&ch1, val);
+	if (ret == 0)
+		dram_info->num_channels++;
+
+	if (dram_info->num_channels == 0) {
+		DRM_INFO("Number of memory channels is zero\n");
+		return -EINVAL;
+	}
+
+	/*
+	 * If any of the channel is single rank channel, worst case output
+	 * will be same as if single rank memory, so consider single rank
+	 * memory.
+	 */
+	if (ch0.rank == I915_DRAM_RANK_SINGLE ||
+	    ch1.rank == I915_DRAM_RANK_SINGLE)
+		dram_info->rank = I915_DRAM_RANK_SINGLE;
+	else
+		dram_info->rank = max(ch0.rank, ch1.rank);
+
+	if (dram_info->rank == I915_DRAM_RANK_INVALID) {
+		DRM_INFO("couldn't get memory rank information\n");
+		return -EINVAL;
+	}
+	return 0;
+}
+
+static int
+skl_get_dram_info(struct drm_i915_private *dev_priv)
+{
+	struct dram_info *dram_info = &dev_priv->dram_info;
+	u32 mem_freq_khz, val;
+	int ret;
+
+	ret = skl_dram_get_channels_info(dev_priv);
+	if (ret)
+		return ret;
+
+	val = I915_READ(SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU);
+	mem_freq_khz = DIV_ROUND_UP((val & SKL_REQ_DATA_MASK) *
+				    SKL_MEMORY_FREQ_MULTIPLIER_HZ, 1000);
+
+	dram_info->bandwidth_kbps = dram_info->num_channels *
+							mem_freq_khz * 8;
+
+	if (dram_info->bandwidth_kbps == 0) {
+		DRM_INFO("Couldn't get system memory bandwidth\n");
+		return -EINVAL;
+	}
+
+	dram_info->valid = true;
+	return 0;
+}
+
 static int
 bxt_get_dram_info(struct drm_i915_private *dev_priv)
 {
@@ -1166,6 +1292,7 @@ static void
 intel_get_dram_info(struct drm_i915_private *dev_priv)
 {
 	struct dram_info *dram_info = &dev_priv->dram_info;
+	char bandwidth_str[32];
 	int ret;
 
 	dram_info->valid = false;
@@ -1173,15 +1300,25 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 	dram_info->bandwidth_kbps = 0;
 	dram_info->num_channels = 0;
 
-	if (!IS_BROXTON(dev_priv))
+	if (INTEL_GEN(dev_priv) < 9 || IS_GEMINILAKE(dev_priv))
 		return;
 
-	ret = bxt_get_dram_info(dev_priv);
+	/* Need to calculate bandwidth only for Gen9 */
+	if (IS_BROXTON(dev_priv))
+		ret = bxt_get_dram_info(dev_priv);
+	else if (INTEL_GEN(dev_priv) == 9)
+		ret = skl_get_dram_info(dev_priv);
+	else
+		ret = skl_dram_get_channels_info(dev_priv);
 	if (ret)
 		return;
 
-	DRM_DEBUG_KMS("DRAM bandwidth:%d KBps, total-channels: %u\n",
-		      dram_info->bandwidth_kbps, dram_info->num_channels);
+	if (dram_info->bandwidth_kbps)
+		sprintf(bandwidth_str, "%d KBps", dram_info->bandwidth_kbps);
+	else
+		sprintf(bandwidth_str, "unknown");
+	DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
+		      bandwidth_str, dram_info->num_channels);
 	DRM_DEBUG_KMS("DRAM rank: %s rank\n",
 		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?
 		      "dual" : "single");
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 5a8101f7b938..0dfa0fdbbae2 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -2168,6 +2168,14 @@ struct drm_i915_private {
 	 */
 };
 
+struct dram_channel_info {
+	struct info {
+		u8 size, width;
+		enum dram_rank rank;
+	} l_info, s_info;
+	enum dram_rank rank;
+};
+
 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
 {
 	return container_of(dev, struct drm_i915_private, drm);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5a6cd5a941c3..66e0e6e6b1d5 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -9611,6 +9611,24 @@ enum skl_power_gate {
 #define  BXT_DRAM_SIZE_12GB			(0x3 << 6)
 #define  BXT_DRAM_SIZE_16GB			(0x4 << 6)
 
+#define SKL_MEMORY_FREQ_MULTIPLIER_HZ		266666666
+#define SKL_MC_BIOS_DATA_0_0_0_MCHBAR_PCU	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5E04)
+#define  SKL_REQ_DATA_MASK			(0xF << 0)
+
+#define SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x500C)
+#define SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN	_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5010)
+#define  SKL_DRAM_S_SHIFT			16
+#define  SKL_DRAM_SIZE_MASK			0x3F
+#define  SKL_DRAM_WIDTH_MASK			(0x3 << 8)
+#define  SKL_DRAM_WIDTH_SHIFT			8
+#define  SKL_DRAM_WIDTH_X8			(0x0 << 8)
+#define  SKL_DRAM_WIDTH_X16			(0x1 << 8)
+#define  SKL_DRAM_WIDTH_X32			(0x2 << 8)
+#define  SKL_DRAM_RANK_MASK			(0x1 << 10)
+#define  SKL_DRAM_RANK_SHIFT			10
+#define  SKL_DRAM_RANK_SINGLE			(0x0 << 10)
+#define  SKL_DRAM_RANK_DUAL			(0x1 << 10)
+
 /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
  * since on HSW we can't write to it using I915_WRITE. */
 #define D_COMP_HSW			_MMIO(MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
-- 
2.16.2

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[PATCH V3 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

[Mahesh Kumar]

Memory with 16GB dimms require an increase of 1us in level-0 latency.
This patch implements the same.
Bspec: 4381

changes since V1:
 - s/memdev_info/dram_info
 - make skl_is_16gb_dimm pure function
Changes since V2:
 - make is_16gb_dimm more generic
 - rebase

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 33 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
 3 files changed, 47 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e09e9ce8fadf..2bc74c01a0e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1088,6 +1088,21 @@ static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
 	return I915_DRAM_RANK_INVALID;
 }
 
+static bool
+skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
+{
+	if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
+		return true;
+	else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
+		return true;
+	else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
+		return true;
+	else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
+		return true;
+
+	return false;
+}
+
 static int
 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
 {
@@ -1125,6 +1140,11 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
 	else
 		ch->rank = I915_DRAM_RANK_SINGLE;
 
+	ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
+					    ch->l_info.width) ||
+			   skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
+					    ch->s_info.width);
+
 	DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
 		      ch->l_info.size, ch->l_info.width,
 		      ch->l_info.rank ? "dual" : "single",
@@ -1157,6 +1177,8 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 		return -EINVAL;
 	}
 
+	dram_info->valid_dimm = true;
+
 	/*
 	 * If any of the channel is single rank channel, worst case output
 	 * will be same as if single rank memory, so consider single rank
@@ -1172,6 +1194,10 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 		DRM_INFO("couldn't get memory rank information\n");
 		return -EINVAL;
 	}
+
+	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
+		dram_info->is_16gb_dimm = true;
+
 	return 0;
 }
 
@@ -1284,6 +1310,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 		return -EINVAL;
 	}
 
+	dram_info->valid_dimm = true;
 	dram_info->valid = true;
 	return 0;
 }
@@ -1296,6 +1323,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 	int ret;
 
 	dram_info->valid = false;
+	dram_info->valid_dimm = false;
+	dram_info->is_16gb_dimm = false;
 	dram_info->rank = I915_DRAM_RANK_INVALID;
 	dram_info->bandwidth_kbps = 0;
 	dram_info->num_channels = 0;
@@ -1319,9 +1348,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 		sprintf(bandwidth_str, "unknown");
 	DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
 		      bandwidth_str, dram_info->num_channels);
-	DRM_DEBUG_KMS("DRAM rank: %s rank\n",
+	DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
 		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?
-		      "dual" : "single");
+		      "dual" : "single", yesno(dram_info->is_16gb_dimm));
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 0dfa0fdbbae2..6c432684c721 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1946,6 +1946,8 @@ struct drm_i915_private {
 
 	struct dram_info {
 		bool valid;
+		bool valid_dimm;
+		bool is_16gb_dimm;
 		u8 num_channels;
 		enum dram_rank {
 			I915_DRAM_RANK_INVALID = 0,
@@ -2174,6 +2176,7 @@ struct dram_channel_info {
 		enum dram_rank rank;
 	} l_info, s_info;
 	enum dram_rank rank;
+	bool is_16gb_dimm;
 };
 
 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99e5fabe93c..9550e24ffc2f 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2875,6 +2875,19 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 			}
 		}
 
+		/*
+		 * WA Level-0 adjustment for 16GB DIMMs: SKL+
+		 * If we could not get dimm info enable this WA to prevent from
+		 * any underrun. If not able to get Dimm info assume 16GB dimm
+		 * to avoid any underrun.
+		 */
+		if (dev_priv->dram_info.valid_dimm) {
+			if (dev_priv->dram_info.is_16gb_dimm)
+				wm[0] += 1;
+		} else {
+			wm[0] += 1;
+		}
+
 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		uint64_t sskpd = I915_READ64(MCH_SSKPD);
 
-- 
2.16.2

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Re: [PATCH V3 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

[Maarten Lankhorst]

Op 24-08-18 om 11:32 schreef Mahesh Kumar:
> Memory with 16GB dimms require an increase of 1us in level-0 latency.
> This patch implements the same.
> Bspec: 4381
>
> changes since V1:
>  - s/memdev_info/dram_info
>  - make skl_is_16gb_dimm pure function
> Changes since V2:
>  - make is_16gb_dimm more generic
>  - rebase
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 33 +++++++++++++++++++++++++++++++--
>  drivers/gpu/drm/i915/i915_drv.h |  3 +++
>  drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
>  3 files changed, 47 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index e09e9ce8fadf..2bc74c01a0e5 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1088,6 +1088,21 @@ static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
>  	return I915_DRAM_RANK_INVALID;
>  }
>  
> +static bool
> +skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
> +{
> +	if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
> +		return true;
> +	else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
> +		return true;
> +	else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
> +		return true;
> +	else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
> +		return true;
> +
> +	return false;
> +}
> +
>  static int
>  skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
>  {
> @@ -1125,6 +1140,11 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
>  	else
>  		ch->rank = I915_DRAM_RANK_SINGLE;
>  
> +	ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
> +					    ch->l_info.width) ||
> +			   skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
> +					    ch->s_info.width);
> +
>  	DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
>  		      ch->l_info.size, ch->l_info.width,
>  		      ch->l_info.rank ? "dual" : "single",
> @@ -1157,6 +1177,8 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  		return -EINVAL;
>  	}
>  
> +	dram_info->valid_dimm = true;
> +
>  	/*
>  	 * If any of the channel is single rank channel, worst case output
>  	 * will be same as if single rank memory, so consider single rank
> @@ -1172,6 +1194,10 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  		DRM_INFO("couldn't get memory rank information\n");
>  		return -EINVAL;
>  	}
> +
> +	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
> +		dram_info->is_16gb_dimm = true;
> +
>  	return 0;
>  }
>  
> @@ -1284,6 +1310,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
>  		return -EINVAL;
>  	}
>  
> +	dram_info->valid_dimm = true;
>  	dram_info->valid = true;
>  	return 0;
>  }
> @@ -1296,6 +1323,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
>  	int ret;
>  
>  	dram_info->valid = false;
> +	dram_info->valid_dimm = false;
> +	dram_info->is_16gb_dimm = false;
>  	dram_info->rank = I915_DRAM_RANK_INVALID;
>  	dram_info->bandwidth_kbps = 0;
>  	dram_info->num_channels = 0;
> @@ -1319,9 +1348,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
>  		sprintf(bandwidth_str, "unknown");
>  	DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
>  		      bandwidth_str, dram_info->num_channels);
> -	DRM_DEBUG_KMS("DRAM rank: %s rank\n",
> +	DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
>  		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?
> -		      "dual" : "single");
> +		      "dual" : "single", yesno(dram_info->is_16gb_dimm));
>  }
>  
>  /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 0dfa0fdbbae2..6c432684c721 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1946,6 +1946,8 @@ struct drm_i915_private {
>  
>  	struct dram_info {
>  		bool valid;
> +		bool valid_dimm;
> +		bool is_16gb_dimm;
>  		u8 num_channels;
>  		enum dram_rank {
>  			I915_DRAM_RANK_INVALID = 0,
> @@ -2174,6 +2176,7 @@ struct dram_channel_info {
>  		enum dram_rank rank;
>  	} l_info, s_info;
>  	enum dram_rank rank;
> +	bool is_16gb_dimm;
>  };
>  
>  static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index d99e5fabe93c..9550e24ffc2f 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -2875,6 +2875,19 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
>  			}
>  		}
>  
> +		/*
> +		 * WA Level-0 adjustment for 16GB DIMMs: SKL+
> +		 * If we could not get dimm info enable this WA to prevent from
> +		 * any underrun. If not able to get Dimm info assume 16GB dimm
> +		 * to avoid any underrun.
> +		 */
> +		if (dev_priv->dram_info.valid_dimm) {
> +			if (dev_priv->dram_info.is_16gb_dimm)
> +				wm[0] += 1;
> +		} else {
> +			wm[0] += 1;
> +		}
Could be simplified to !valid_dimm || is_16_gb_dimm. :)
> +
>  	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
>  		uint64_t sskpd = I915_READ64(MCH_SSKPD);
>  


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[PATCH V4 3/5] drm/i915: Implement 16GB dimm wa for latency level-0

[Mahesh Kumar]

Memory with 16GB dimms require an increase of 1us in level-0 latency.
This patch implements the same.
Bspec: 4381

changes since V1:
 - s/memdev_info/dram_info
 - make skl_is_16gb_dimm pure function
Changes since V2:
 - make is_16gb_dimm more generic
 - rebase
Changes since V3:
 - Simplify condition (Maarten)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 33 +++++++++++++++++++++++++++++++--
 drivers/gpu/drm/i915/i915_drv.h |  3 +++
 drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++
 3 files changed, 44 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index e09e9ce8fadf..2bc74c01a0e5 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1088,6 +1088,21 @@ static enum dram_rank skl_get_dimm_rank(u8 size, u32 rank)
 	return I915_DRAM_RANK_INVALID;
 }
 
+static bool
+skl_is_16gb_dimm(enum dram_rank rank, u8 size, u8 width)
+{
+	if (rank == I915_DRAM_RANK_SINGLE && width == 8 && size == 16)
+		return true;
+	else if (rank == I915_DRAM_RANK_DUAL && width == 8 && size == 32)
+		return true;
+	else if (rank == SKL_DRAM_RANK_SINGLE && width == 16 && size == 8)
+		return true;
+	else if (rank == SKL_DRAM_RANK_DUAL && width == 16 && size == 16)
+		return true;
+
+	return false;
+}
+
 static int
 skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
 {
@@ -1125,6 +1140,11 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
 	else
 		ch->rank = I915_DRAM_RANK_SINGLE;
 
+	ch->is_16gb_dimm = skl_is_16gb_dimm(ch->l_info.rank, ch->l_info.size,
+					    ch->l_info.width) ||
+			   skl_is_16gb_dimm(ch->s_info.rank, ch->s_info.size,
+					    ch->s_info.width);
+
 	DRM_DEBUG_KMS("(size:width:rank) L(%dGB:X%d:%s) S(%dGB:X%d:%s)\n",
 		      ch->l_info.size, ch->l_info.width,
 		      ch->l_info.rank ? "dual" : "single",
@@ -1157,6 +1177,8 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 		return -EINVAL;
 	}
 
+	dram_info->valid_dimm = true;
+
 	/*
 	 * If any of the channel is single rank channel, worst case output
 	 * will be same as if single rank memory, so consider single rank
@@ -1172,6 +1194,10 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 		DRM_INFO("couldn't get memory rank information\n");
 		return -EINVAL;
 	}
+
+	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
+		dram_info->is_16gb_dimm = true;
+
 	return 0;
 }
 
@@ -1284,6 +1310,7 @@ bxt_get_dram_info(struct drm_i915_private *dev_priv)
 		return -EINVAL;
 	}
 
+	dram_info->valid_dimm = true;
 	dram_info->valid = true;
 	return 0;
 }
@@ -1296,6 +1323,8 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 	int ret;
 
 	dram_info->valid = false;
+	dram_info->valid_dimm = false;
+	dram_info->is_16gb_dimm = false;
 	dram_info->rank = I915_DRAM_RANK_INVALID;
 	dram_info->bandwidth_kbps = 0;
 	dram_info->num_channels = 0;
@@ -1319,9 +1348,9 @@ intel_get_dram_info(struct drm_i915_private *dev_priv)
 		sprintf(bandwidth_str, "unknown");
 	DRM_DEBUG_KMS("DRAM bandwidth:%s, total-channels: %u\n",
 		      bandwidth_str, dram_info->num_channels);
-	DRM_DEBUG_KMS("DRAM rank: %s rank\n",
+	DRM_DEBUG_KMS("DRAM rank: %s rank 16GB-dimm:%s\n",
 		      (dram_info->rank == I915_DRAM_RANK_DUAL) ?
-		      "dual" : "single");
+		      "dual" : "single", yesno(dram_info->is_16gb_dimm));
 }
 
 /**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 9195e99a6aba..fe08a883e39f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1946,6 +1946,8 @@ struct drm_i915_private {
 
 	struct dram_info {
 		bool valid;
+		bool valid_dimm;
+		bool is_16gb_dimm;
 		u8 num_channels;
 		enum dram_rank {
 			I915_DRAM_RANK_INVALID = 0,
@@ -2174,6 +2176,7 @@ struct dram_channel_info {
 		enum dram_rank rank;
 	} l_info, s_info;
 	enum dram_rank rank;
+	bool is_16gb_dimm;
 };
 
 static inline struct drm_i915_private *to_i915(const struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index d99e5fabe93c..09463e3d7948 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2875,6 +2875,16 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
 			}
 		}
 
+		/*
+		 * WA Level-0 adjustment for 16GB DIMMs: SKL+
+		 * If we could not get dimm info enable this WA to prevent from
+		 * any underrun. If not able to get Dimm info assume 16GB dimm
+		 * to avoid any underrun.
+		 */
+		if (!dev_priv->dram_info.valid_dimm ||
+		    dev_priv->dram_info.is_16gb_dimm)
+			wm[0] += 1;
+
 	} else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
 		uint64_t sskpd = I915_READ64(MCH_SSKPD);
 
-- 
2.16.2

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[PATCH V1 4/5] drm/i915/skl+: don't trust IPC value set by BIOS

[Mahesh Kumar]

If KMS decide to disable IPC make sure we override IPC configuration set
by BIOS.


Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/intel_pm.c | 4 +---
 1 file changed, 1 insertion(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9550e24ffc2f..77970e38d939 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6121,10 +6121,8 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
 	u32 val;
 
 	/* Display WA #0477 WaDisableIPC: skl */
-	if (IS_SKYLAKE(dev_priv)) {
+	if (IS_SKYLAKE(dev_priv))
 		dev_priv->ipc_enabled = false;
-		return;
-	}
 
 	val = I915_READ(DISP_ARB_CTL2);
 
-- 
2.16.2

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[PATCH V2 5/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

[Mahesh Kumar]

IPC may cause underflows if not used with dual channel symmetric
memory configuration. Disable IPC for non symmetric configurations in
affected platforms.
Display WA #1141

Changes Since V1:
 - Re-arrange the code.
 - update wrapper to return if memory is symmetric (Rodrigo)

Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
---
 drivers/gpu/drm/i915/i915_drv.c | 27 ++++++++++++++++++++++-----
 drivers/gpu/drm/i915/i915_drv.h |  1 +
 drivers/gpu/drm/i915/intel_pm.c |  5 +++++
 3 files changed, 28 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 2bc74c01a0e5..61d756ae7bf0 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -1154,21 +1154,32 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
 	return 0;
 }
 
+static bool
+intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
+			struct dram_channel_info *ch0)
+{
+	return (val_ch0 == val_ch1 &&
+		(ch0->s_info.size == 0 ||
+		 (ch0->l_info.size == ch0->s_info.size &&
+		  ch0->l_info.width == ch0->s_info.width &&
+		  ch0->l_info.rank == ch0->s_info.rank)));
+}
+
 static int
 skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 {
 	struct dram_info *dram_info = &dev_priv->dram_info;
 	struct dram_channel_info ch0, ch1;
-	u32 val;
+	u32 val_ch0, val_ch1;
 	int ret;
 
-	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
-	ret = skl_dram_get_channel_info(&ch0, val);
+	val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
+	ret = skl_dram_get_channel_info(&ch0, val_ch0);
 	if (ret == 0)
 		dram_info->num_channels++;
 
-	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
-	ret = skl_dram_get_channel_info(&ch1, val);
+	val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
+	ret = skl_dram_get_channel_info(&ch1, val_ch1);
 	if (ret == 0)
 		dram_info->num_channels++;
 
@@ -1198,6 +1209,12 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
 	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
 		dram_info->is_16gb_dimm = true;
 
+	dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
+								       val_ch1,
+								       &ch0);
+
+	DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
+		      dev_priv->dram_info.symmetric_memory ? "" : "not ");
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6c432684c721..e7faa046f78a 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1955,6 +1955,7 @@ struct drm_i915_private {
 			I915_DRAM_RANK_DUAL
 		} rank;
 		u32 bandwidth_kbps;
+		bool symmetric_memory;
 	} dram_info;
 
 	struct i915_runtime_pm runtime_pm;
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 77970e38d939..c27646fb4cec 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6124,6 +6124,11 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
 	if (IS_SKYLAKE(dev_priv))
 		dev_priv->ipc_enabled = false;
 
+	/* Display WA #1141: SKL:all KBL:all CFL */
+	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
+	    !dev_priv->dram_info.symmetric_memory)
+		dev_priv->ipc_enabled = false;
+
 	val = I915_READ(DISP_ARB_CTL2);
 
 	if (dev_priv->ipc_enabled)
-- 
2.16.2

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Re: [PATCH V2 5/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

[Maarten Lankhorst]

Op 24-08-18 om 11:32 schreef Mahesh Kumar:
> IPC may cause underflows if not used with dual channel symmetric
> memory configuration. Disable IPC for non symmetric configurations in
> affected platforms.
> Display WA #1141
>
> Changes Since V1:
>  - Re-arrange the code.
>  - update wrapper to return if memory is symmetric (Rodrigo)
>
> Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> ---
>  drivers/gpu/drm/i915/i915_drv.c | 27 ++++++++++++++++++++++-----
>  drivers/gpu/drm/i915/i915_drv.h |  1 +
>  drivers/gpu/drm/i915/intel_pm.c |  5 +++++
>  3 files changed, 28 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 2bc74c01a0e5..61d756ae7bf0 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -1154,21 +1154,32 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
>  	return 0;
>  }
>  
> +static bool
> +intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
> +			struct dram_channel_info *ch0)
> +{
> +	return (val_ch0 == val_ch1 &&
> +		(ch0->s_info.size == 0 ||
> +		 (ch0->l_info.size == ch0->s_info.size &&
> +		  ch0->l_info.width == ch0->s_info.width &&
> +		  ch0->l_info.rank == ch0->s_info.rank)));
> +}
> +
>  static int
>  skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  {
>  	struct dram_info *dram_info = &dev_priv->dram_info;
>  	struct dram_channel_info ch0, ch1;
> -	u32 val;
> +	u32 val_ch0, val_ch1;
>  	int ret;
>  
> -	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> -	ret = skl_dram_get_channel_info(&ch0, val);
> +	val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> +	ret = skl_dram_get_channel_info(&ch0, val_ch0);
>  	if (ret == 0)
>  		dram_info->num_channels++;
>  
> -	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> -	ret = skl_dram_get_channel_info(&ch1, val);
> +	val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> +	ret = skl_dram_get_channel_info(&ch1, val_ch1);
>  	if (ret == 0)
>  		dram_info->num_channels++;
>  
> @@ -1198,6 +1209,12 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
>  	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
>  		dram_info->is_16gb_dimm = true;
>  
> +	dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
> +								       val_ch1,
> +								       &ch0);
> +
> +	DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
> +		      dev_priv->dram_info.symmetric_memory ? "" : "not ");
>  	return 0;
>  }
>  
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6c432684c721..e7faa046f78a 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1955,6 +1955,7 @@ struct drm_i915_private {
>  			I915_DRAM_RANK_DUAL
>  		} rank;
>  		u32 bandwidth_kbps;
> +		bool symmetric_memory;
>  	} dram_info;
>  
>  	struct i915_runtime_pm runtime_pm;
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 77970e38d939..c27646fb4cec 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6124,6 +6124,11 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
>  	if (IS_SKYLAKE(dev_priv))
>  		dev_priv->ipc_enabled = false;
>  
> +	/* Display WA #1141: SKL:all KBL:all CFL */
> +	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
> +	    !dev_priv->dram_info.symmetric_memory)
> +		dev_priv->ipc_enabled = false;
> +
>  	val = I915_READ(DISP_ARB_CTL2);
>  
>  	if (dev_priv->ipc_enabled)

Patch series looks good with minor nit in 3/5 fixed.


Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

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Re: [PATCH V2 5/5] drm/i915/kbl+: Enable IPC only for symmetric memory configurations

[Rodrigo Vivi]

On Fri, Aug 31, 2018 at 12:25:31PM +0200, Maarten Lankhorst wrote:
> Op 24-08-18 om 11:32 schreef Mahesh Kumar:
> > IPC may cause underflows if not used with dual channel symmetric
> > memory configuration. Disable IPC for non symmetric configurations in
> > affected platforms.
> > Display WA #1141
> >
> > Changes Since V1:
> >  - Re-arrange the code.
> >  - update wrapper to return if memory is symmetric (Rodrigo)
> >
> > Signed-off-by: Mahesh Kumar <mahesh1.kumar@intel.com>
> > ---
> >  drivers/gpu/drm/i915/i915_drv.c | 27 ++++++++++++++++++++++-----
> >  drivers/gpu/drm/i915/i915_drv.h |  1 +
> >  drivers/gpu/drm/i915/intel_pm.c |  5 +++++
> >  3 files changed, 28 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> > index 2bc74c01a0e5..61d756ae7bf0 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.c
> > +++ b/drivers/gpu/drm/i915/i915_drv.c
> > @@ -1154,21 +1154,32 @@ skl_dram_get_channel_info(struct dram_channel_info *ch, u32 val)
> >  	return 0;
> >  }
> >  
> > +static bool
> > +intel_is_dram_symmetric(u32 val_ch0, u32 val_ch1,
> > +			struct dram_channel_info *ch0)
> > +{
> > +	return (val_ch0 == val_ch1 &&
> > +		(ch0->s_info.size == 0 ||
> > +		 (ch0->l_info.size == ch0->s_info.size &&
> > +		  ch0->l_info.width == ch0->s_info.width &&
> > +		  ch0->l_info.rank == ch0->s_info.rank)));
> > +}
> > +
> >  static int
> >  skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
> >  {
> >  	struct dram_info *dram_info = &dev_priv->dram_info;
> >  	struct dram_channel_info ch0, ch1;
> > -	u32 val;
> > +	u32 val_ch0, val_ch1;
> >  	int ret;
> >  
> > -	val = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > -	ret = skl_dram_get_channel_info(&ch0, val);
> > +	val_ch0 = I915_READ(SKL_MAD_DIMM_CH0_0_0_0_MCHBAR_MCMAIN);
> > +	ret = skl_dram_get_channel_info(&ch0, val_ch0);
> >  	if (ret == 0)
> >  		dram_info->num_channels++;
> >  
> > -	val = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> > -	ret = skl_dram_get_channel_info(&ch1, val);
> > +	val_ch1 = I915_READ(SKL_MAD_DIMM_CH1_0_0_0_MCHBAR_MCMAIN);
> > +	ret = skl_dram_get_channel_info(&ch1, val_ch1);
> >  	if (ret == 0)
> >  		dram_info->num_channels++;
> >  
> > @@ -1198,6 +1209,12 @@ skl_dram_get_channels_info(struct drm_i915_private *dev_priv)
> >  	if (ch0.is_16gb_dimm || ch1.is_16gb_dimm)
> >  		dram_info->is_16gb_dimm = true;
> >  
> > +	dev_priv->dram_info.symmetric_memory = intel_is_dram_symmetric(val_ch0,
> > +								       val_ch1,
> > +								       &ch0);
> > +
> > +	DRM_DEBUG_KMS("memory configuration is %sSymmetric memory\n",
> > +		      dev_priv->dram_info.symmetric_memory ? "" : "not ");
> >  	return 0;
> >  }
> >  
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index 6c432684c721..e7faa046f78a 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1955,6 +1955,7 @@ struct drm_i915_private {
> >  			I915_DRAM_RANK_DUAL
> >  		} rank;
> >  		u32 bandwidth_kbps;
> > +		bool symmetric_memory;
> >  	} dram_info;
> >  
> >  	struct i915_runtime_pm runtime_pm;
> > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> > index 77970e38d939..c27646fb4cec 100644
> > --- a/drivers/gpu/drm/i915/intel_pm.c
> > +++ b/drivers/gpu/drm/i915/intel_pm.c
> > @@ -6124,6 +6124,11 @@ void intel_enable_ipc(struct drm_i915_private *dev_priv)
> >  	if (IS_SKYLAKE(dev_priv))
> >  		dev_priv->ipc_enabled = false;
> >  
> > +	/* Display WA #1141: SKL:all KBL:all CFL */
> > +	if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) &&
> > +	    !dev_priv->dram_info.symmetric_memory)
> > +		dev_priv->ipc_enabled = false;
> > +
> >  	val = I915_READ(DISP_ARB_CTL2);
> >  
> >  	if (dev_priv->ipc_enabled)
> 
> Patch series looks good with minor nit in 3/5 fixed.
> 
> 
> Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

Series pushed to dinq. Thanks for patches and reviews.

> 
> _______________________________________________
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> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✗ Fi.CI.SPARSE: warning for Decode memdev info and bandwidth and implemnt latency WA (rev3)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev3)
URL   : https://patchwork.freedesktop.org/series/46481/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/bxt: Decode memory bandwidth and parameters
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3685:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3696:16: warning: expression using sizeof(void)

Commit: drm/i915/skl+: Decode memory bandwidth and parameters
+drivers/gpu/drm/i915/i915_drv.c:1169:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1169:35: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3696:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3704:16: warning: expression using sizeof(void)

Commit: drm/i915: Implement 16GB dimm wa for latency level-0
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3704:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void)

Commit: drm/i915/skl+: don't trust IPC value set by BIOS
Okay!

Commit: drm/i915/kbl+: Enable IPC only for symmetric memory configurations
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3708:16: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for Decode memdev info and bandwidth and implemnt latency WA (rev3)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev3)
URL   : https://patchwork.freedesktop.org/series/46481/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4703 -> Patchwork_10005 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/46481/revisions/3/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10005 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_selftest@live_hangcheck:
      fi-cfl-s3:          PASS -> DMESG-FAIL (fdo#106560)

    igt@kms_frontbuffer_tracking@basic:
      {fi-byt-clapper}:   PASS -> FAIL (fdo#103167)

    {igt@pm_rpm@module-reload}:
      fi-cnl-psr:         PASS -> WARN (fdo#107602)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      {fi-bdw-samus}:     DMESG-FAIL (fdo#106560) -> PASS
      fi-skl-guc:         DMESG-FAIL (fdo#107174) -> PASS

    igt@gem_sync@basic-many-each:
      {fi-byt-clapper}:   FAIL -> PASS

    {igt@kms_psr@primary_mmap_gtt}:
      fi-cnl-psr:         DMESG-WARN -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602


== Participating hosts (53 -> 48) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4703 -> Patchwork_10005

  CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10005: a2a83254992b4983e9c32c3e622049a0db88f50a @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

a2a83254992b drm/i915/kbl+: Enable IPC only for symmetric memory configurations
9776ee899bc1 drm/i915/skl+: don't trust IPC value set by BIOS
75013c1382d3 drm/i915: Implement 16GB dimm wa for latency level-0
3d1dd3f4ab6d drm/i915/skl+: Decode memory bandwidth and parameters
70f3f002256d drm/i915/bxt: Decode memory bandwidth and parameters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10005/issues.html
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✓ Fi.CI.BAT: success for Decode memdev info and bandwidth and implemnt latency WA (rev3)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev3)
URL   : https://patchwork.freedesktop.org/series/46481/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4703 -> Patchwork_10006 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/46481/revisions/3/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10006 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_frontbuffer_tracking@basic:
      {fi-byt-clapper}:   PASS -> FAIL (fdo#103167)

    igt@kms_pipe_crc_basic@hang-read-crc-pipe-b:
      {fi-byt-clapper}:   PASS -> FAIL (fdo#107362, fdo#103191)

    {igt@kms_psr@primary_page_flip}:
      {fi-icl-u}:         NOTRUN -> FAIL (fdo#107383) +3

    {igt@pm_rpm@module-reload}:
      fi-cnl-psr:         PASS -> WARN (fdo#107602)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      {fi-bdw-samus}:     DMESG-FAIL (fdo#106560) -> PASS
      fi-skl-guc:         DMESG-FAIL (fdo#107174) -> PASS

    igt@gem_sync@basic-many-each:
      {fi-byt-clapper}:   FAIL -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107174 https://bugs.freedesktop.org/show_bug.cgi?id=107174
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107383 https://bugs.freedesktop.org/show_bug.cgi?id=107383
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602


== Participating hosts (53 -> 49) ==

  Additional (1): fi-icl-u 
  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4703 -> Patchwork_10006

  CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10006: 6e6423a93963b98c9198b87d2c1aee78a0c98c73 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

6e6423a93963 drm/i915/kbl+: Enable IPC only for symmetric memory configurations
ad084286084b drm/i915/skl+: don't trust IPC value set by BIOS
00825915e644 drm/i915: Implement 16GB dimm wa for latency level-0
85f1a226cd8a drm/i915/skl+: Decode memory bandwidth and parameters
6890cf014d0e drm/i915/bxt: Decode memory bandwidth and parameters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10006/issues.html
_______________________________________________
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✗ Fi.CI.IGT: failure for Decode memdev info and bandwidth and implemnt latency WA (rev3)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev3)
URL   : https://patchwork.freedesktop.org/series/46481/
State : failure

== Summary ==

= CI Bug Log - changes from CI_DRM_4703_full -> Patchwork_10005_full =

== Summary - FAILURE ==

  Serious unknown changes coming with Patchwork_10005_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10005_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10005_full:

  === IGT changes ===

    ==== Possible regressions ====

    igt@gem_eio@reset-stress:
      shard-kbl:          PASS -> FAIL

    
    ==== Warnings ====

    igt@kms_chv_cursor_fail@pipe-a-256x256-right-edge:
      shard-snb:          PASS -> SKIP +1

    
== Known issues ==

  Here are the changes found in Patchwork_10005_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_draw_crc@draw-method-rgb565-mmap-wc-xtiled:
      shard-glk:          PASS -> FAIL (fdo#103184)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    igt@kms_vblank@pipe-b-ts-continuation-suspend:
      shard-hsw:          PASS -> FAIL (fdo#104894)

    
    ==== Possible fixes ====

    igt@gem_exec_big:
      shard-hsw:          INCOMPLETE (fdo#103540) -> PASS

    
  fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#104894 https://bugs.freedesktop.org/show_bug.cgi?id=104894
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4703 -> Patchwork_10005

  CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10005: a2a83254992b4983e9c32c3e622049a0db88f50a @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10005/shards.html
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✓ Fi.CI.IGT: success for Decode memdev info and bandwidth and implemnt latency WA (rev3)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev3)
URL   : https://patchwork.freedesktop.org/series/46481/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4703_full -> Patchwork_10006_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10006_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_cursor_legacy@cursor-vs-flip-toggle:
      shard-hsw:          PASS -> FAIL (fdo#103355)

    
    ==== Possible fixes ====

    igt@gem_ctx_isolation@bcs0-s3:
      shard-kbl:          INCOMPLETE (fdo#103665) -> PASS

    igt@gem_exec_big:
      shard-hsw:          INCOMPLETE (fdo#103540) -> PASS

    igt@kms_setmode@basic:
      shard-kbl:          FAIL (fdo#99912) -> PASS

    
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103540 https://bugs.freedesktop.org/show_bug.cgi?id=103540
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4703 -> Patchwork_10006

  CI_DRM_4703: 5dedf9d9259854872430c04a29737924731ba6f1 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4609: 0bc9763af77bbb37f2ed65cc39c398e88db7d8e3 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10006: 6e6423a93963b98c9198b87d2c1aee78a0c98c73 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10006/shards.html
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✗ Fi.CI.CHECKPATCH: warning for Decode memdev info and bandwidth and implemnt latency WA (rev4)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL   : https://patchwork.freedesktop.org/series/46481/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
441057f30f45 drm/i915/bxt: Decode memory bandwidth and parameters
-:162: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#162: FILE: drivers/gpu/drm/i915/i915_drv.h:1948:
+		bool valid;

total: 0 errors, 0 warnings, 1 checks, 182 lines checked
bc3e164750dd drm/i915/skl+: Decode memory bandwidth and parameters
08094101d869 drm/i915: Implement 16GB dimm wa for latency level-0
-:116: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#116: FILE: drivers/gpu/drm/i915/i915_drv.h:1949:
+		bool valid_dimm;

-:117: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#117: FILE: drivers/gpu/drm/i915/i915_drv.h:1950:
+		bool is_16gb_dimm;

-:125: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#125: FILE: drivers/gpu/drm/i915/i915_drv.h:2179:
+	bool is_16gb_dimm;

total: 0 errors, 0 warnings, 3 checks, 107 lines checked
9968070f860e drm/i915/skl+: don't trust IPC value set by BIOS
268a50bd35d9 drm/i915/kbl+: Enable IPC only for symmetric memory configurations
-:82: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
#82: FILE: drivers/gpu/drm/i915/i915_drv.h:1958:
+		bool symmetric_memory;

total: 0 errors, 0 warnings, 1 checks, 67 lines checked

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Re: ✗ Fi.CI.CHECKPATCH: warning for Decode memdev info and bandwidth and implemnt latency WA (rev4)

[Rodrigo Vivi]

On Fri, Aug 31, 2018 at 11:22:01AM -0000, Patchwork wrote:
> == Series Details ==
> 
> Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
> URL   : https://patchwork.freedesktop.org/series/46481/
> State : warning
> 
> == Summary ==
> 
> $ dim checkpatch origin/drm-tip
> 441057f30f45 drm/i915/bxt: Decode memory bandwidth and parameters
> -:162: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384

I'm still asking myself how to proceed with this one here.

We clearly have many more cases of bool structure members on i915.

> #162: FILE: drivers/gpu/drm/i915/i915_drv.h:1948:
> +		bool valid;
> 
> total: 0 errors, 0 warnings, 1 checks, 182 lines checked
> bc3e164750dd drm/i915/skl+: Decode memory bandwidth and parameters
> 08094101d869 drm/i915: Implement 16GB dimm wa for latency level-0
> -:116: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
> #116: FILE: drivers/gpu/drm/i915/i915_drv.h:1949:
> +		bool valid_dimm;
> 
> -:117: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
> #117: FILE: drivers/gpu/drm/i915/i915_drv.h:1950:
> +		bool is_16gb_dimm;
> 
> -:125: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
> #125: FILE: drivers/gpu/drm/i915/i915_drv.h:2179:
> +	bool is_16gb_dimm;
> 
> total: 0 errors, 0 warnings, 3 checks, 107 lines checked
> 9968070f860e drm/i915/skl+: don't trust IPC value set by BIOS
> 268a50bd35d9 drm/i915/kbl+: Enable IPC only for symmetric memory configurations
> -:82: CHECK:BOOL_MEMBER: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384
> #82: FILE: drivers/gpu/drm/i915/i915_drv.h:1958:
> +		bool symmetric_memory;
> 
> total: 0 errors, 0 warnings, 1 checks, 67 lines checked
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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✗ Fi.CI.SPARSE: warning for Decode memdev info and bandwidth and implemnt latency WA (rev4)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL   : https://patchwork.freedesktop.org/series/46481/
State : warning

== Summary ==

$ dim sparse origin/drm-tip
Commit: drm/i915/bxt: Decode memory bandwidth and parameters
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3687:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3698:16: warning: expression using sizeof(void)

Commit: drm/i915/skl+: Decode memory bandwidth and parameters
+drivers/gpu/drm/i915/i915_drv.c:1169:35: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/i915_drv.c:1169:35: warning: expression using sizeof(void)
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3698:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)

Commit: drm/i915: Implement 16GB dimm wa for latency level-0
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3706:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void)

Commit: drm/i915/skl+: don't trust IPC value set by BIOS
Okay!

Commit: drm/i915/kbl+: Enable IPC only for symmetric memory configurations
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3709:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3710:16: warning: expression using sizeof(void)

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✓ Fi.CI.BAT: success for Decode memdev info and bandwidth and implemnt latency WA (rev4)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL   : https://patchwork.freedesktop.org/series/46481/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4748 -> Patchwork_10058 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/46481/revisions/4/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10058 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    {igt@amdgpu/amd_basic@userptr}:
      {fi-kbl-8809g}:     PASS -> INCOMPLETE (fdo#107402)

    {igt@pm_rpm@module-reload}:
      fi-cnl-psr:         PASS -> WARN (fdo#107602, fdo#107708)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    {igt@kms_psr@primary_page_flip}:
      fi-cnl-psr:         FAIL (fdo#107336) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
  fdo#107602 https://bugs.freedesktop.org/show_bug.cgi?id=107602
  fdo#107708 https://bugs.freedesktop.org/show_bug.cgi?id=107708


== Participating hosts (53 -> 48) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4748 -> Patchwork_10058

  CI_DRM_4748: 6caeb081ceb9282503439565e7093c1032758289 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4613: 3f89d7b02dcf662e994c7135b13d52bc8e09a4ea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10058: 268a50bd35d9781b263680138c19715a02b27c72 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

268a50bd35d9 drm/i915/kbl+: Enable IPC only for symmetric memory configurations
9968070f860e drm/i915/skl+: don't trust IPC value set by BIOS
08094101d869 drm/i915: Implement 16GB dimm wa for latency level-0
bc3e164750dd drm/i915/skl+: Decode memory bandwidth and parameters
441057f30f45 drm/i915/bxt: Decode memory bandwidth and parameters

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10058/issues.html
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✓ Fi.CI.IGT: success for Decode memdev info and bandwidth and implemnt latency WA (rev4)

[Patchwork]

== Series Details ==

Series: Decode memdev info and bandwidth and implemnt latency WA (rev4)
URL   : https://patchwork.freedesktop.org/series/46481/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4748_full -> Patchwork_10058_full =

== Summary - WARNING ==

  Minor unknown changes coming with Patchwork_10058_full need to be verified
  manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_10058_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

== Possible new issues ==

  Here are the unknown changes that may have been introduced in Patchwork_10058_full:

  === IGT changes ===

    ==== Warnings ====

    igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled:
      shard-snb:          PASS -> SKIP

    igt@pm_rc6_residency@rc6-accuracy:
      shard-kbl:          SKIP -> PASS

    
== Known issues ==

  Here are the changes found in Patchwork_10058_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@gem_ppgtt@blt-vs-render-ctx0:
      shard-snb:          NOTRUN -> INCOMPLETE (fdo#105411, fdo#106887)

    igt@kms_cursor_legacy@cursor-vs-flip-toggle:
      shard-hsw:          PASS -> FAIL (fdo#103355)

    igt@kms_setmode@basic:
      shard-apl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@gem_ctx_isolation@rcs0-s3:
      shard-kbl:          INCOMPLETE (fdo#107556, fdo#103665) -> PASS

    igt@gem_exec_store@pages-blt:
      shard-snb:          INCOMPLETE (fdo#105411) -> PASS

    igt@kms_cursor_crc@cursor-256x256-suspend:
      shard-apl:          INCOMPLETE (fdo#103927) -> PASS

    igt@kms_cursor_legacy@cursor-vs-flip-varying-size:
      shard-hsw:          FAIL (fdo#103355) -> PASS

    
  fdo#103355 https://bugs.freedesktop.org/show_bug.cgi?id=103355
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#105411 https://bugs.freedesktop.org/show_bug.cgi?id=105411
  fdo#106887 https://bugs.freedesktop.org/show_bug.cgi?id=106887
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4748 -> Patchwork_10058

  CI_DRM_4748: 6caeb081ceb9282503439565e7093c1032758289 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4613: 3f89d7b02dcf662e994c7135b13d52bc8e09a4ea @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10058: 268a50bd35d9781b263680138c19715a02b27c72 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10058/shards.html
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[PATCH 0/5] Decode memdev info and bandwidth and implemnt latency WA

[Mahesh Kumar]

This series adds support to calculate system memdev parameters and calculate
total system memory bandwidth. This parameters and BW will be used to enable
WM level-0 latency workaround and display memory bandwidth related WA for gen9.

while we are here to enable IPC based on memory configuration lets also 
make sure that we override IPC value set of BIOS incase we decide to
disable IPC in KMS.

Mahesh Kumar (5):
  drm/i915/bxt: Decode memory bandwidth and parameters
  drm/i915/skl+: Decode memory bandwidth and parameters
  drm/i915: Implement 16GB dimm wa for latency level-0
  drm/i915/kbl+: Enable IPC only for symmetric memory configurations
  drm/i915/skl+: don't trust IPC value set by BIOS

 drivers/gpu/drm/i915/i915_drv.c | 308 ++++++++++++++++++++++++++++++++++++++++
 drivers/gpu/drm/i915/i915_drv.h |  22 +++
 drivers/gpu/drm/i915/i915_reg.h |  51 +++++++
 drivers/gpu/drm/i915/intel_pm.c |  17 ++-
 4 files changed, 395 insertions(+), 3 deletions(-)

-- 
2.16.2

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