* [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches
@ 2018-08-27 14:33 laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define laurentiu.tudor at nxp.com
` (3 more replies)
0 siblings, 4 replies; 6+ messages in thread
From: laurentiu.tudor at nxp.com @ 2018-08-27 14:33 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
This patch builds on the already existing LS1046A SMMU enablement
infrastructure to add the required device setup and device tree
fixups for enabling SMMU on LS1043A SoCs.
Laurentiu Tudor (4):
armv8: fsl-layerscape: add missing qe base address define
armv8: ls1043a: advertise QMan v3 in configuration
armv8: ls1043a: add icid setup support
armv8: ls1043a: enable icid setup for qman portals
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 90 +++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../include/asm/arch-fsl-layerscape/config.h | 1 +
.../asm/arch-fsl-layerscape/fsl_icid.h | 4 +
.../asm/arch-fsl-layerscape/immap_lsch2.h | 2 +
board/freescale/ls1043aqds/ls1043aqds.c | 3 +
board/freescale/ls1043ardb/ls1043ardb.c | 3 +
drivers/misc/fsl_portals.c | 11 +--
9 files changed, 111 insertions(+), 6 deletions(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
--
2.17.1
^ permalink raw reply [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define
2018-08-27 14:33 [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches laurentiu.tudor at nxp.com
@ 2018-08-27 14:33 ` laurentiu.tudor at nxp.com
2018-09-28 15:45 ` York Sun
2018-08-27 14:33 ` [U-Boot] [PATCH 2/4] armv8: ls1043a: advertise QMan v3 in configuration laurentiu.tudor at nxp.com
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: laurentiu.tudor at nxp.com @ 2018-08-27 14:33 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Add define for quiccengine register block base address.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
index be0a6ae363..8c10526a6c 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h
@@ -85,6 +85,8 @@
#define GPIO3_BASE_ADDR (CONFIG_SYS_IMMR + 0x1320000)
#define GPIO4_BASE_ADDR (CONFIG_SYS_IMMR + 0x1330000)
+#define QE_BASE_ADDR (CONFIG_SYS_IMMR + 0x1400000)
+
#define LPUART_BASE (CONFIG_SYS_IMMR + 0x01950000)
#define EDMA_BASE_ADDR (CONFIG_SYS_IMMR + 0x01c00000)
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 2/4] armv8: ls1043a: advertise QMan v3 in configuration
2018-08-27 14:33 [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define laurentiu.tudor at nxp.com
@ 2018-08-27 14:33 ` laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 3/4] armv8: ls1043a: add icid setup support laurentiu.tudor at nxp.com
2018-08-27 14:34 ` [U-Boot] [PATCH 4/4] armv8: ls1043a: enable icid setup for qman portals laurentiu.tudor at nxp.com
3 siblings, 0 replies; 6+ messages in thread
From: laurentiu.tudor at nxp.com @ 2018-08-27 14:33 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
The QMan IP block in this SoC is version 3.2 so advertise
this in the SoC configuration header.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm/include/asm/arch-fsl-layerscape/config.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h
index 8a05148136..bd4ca88e16 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/config.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h
@@ -195,6 +195,7 @@
/* SoC related */
#ifdef CONFIG_ARCH_LS1043A
#define CONFIG_SYS_FMAN_V3
+#define CONFIG_SYS_FSL_QMAN_V3
#define CONFIG_SYS_NUM_FMAN 1
#define CONFIG_SYS_NUM_FM1_DTSEC 7
#define CONFIG_SYS_NUM_FM1_10GEC 1
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 3/4] armv8: ls1043a: add icid setup support
2018-08-27 14:33 [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 2/4] armv8: ls1043a: advertise QMan v3 in configuration laurentiu.tudor at nxp.com
@ 2018-08-27 14:33 ` laurentiu.tudor at nxp.com
2018-08-27 14:34 ` [U-Boot] [PATCH 4/4] armv8: ls1043a: enable icid setup for qman portals laurentiu.tudor at nxp.com
3 siblings, 0 replies; 6+ messages in thread
From: laurentiu.tudor at nxp.com @ 2018-08-27 14:33 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Reuse the existing ICID setup code done for LS1046A smmu enablement
and add the equivalent setup for LS1043A chips.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 1 +
.../arm/cpu/armv8/fsl-layerscape/ls1043_ids.c | 90 +++++++++++++++++++
arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 +-
.../asm/arch-fsl-layerscape/fsl_icid.h | 4 +
board/freescale/ls1043aqds/ls1043aqds.c | 3 +
board/freescale/ls1043ardb/ls1043ardb.c | 3 +
6 files changed, 102 insertions(+), 1 deletion(-)
create mode 100644 arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
index 5d6f68aad6..91fdbad8be 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile
@@ -29,6 +29,7 @@ endif
ifneq ($(CONFIG_ARCH_LS1043A),)
obj-$(CONFIG_SYS_HAS_SERDES) += ls1043a_serdes.o
obj-$(CONFIG_ARMV8_PSCI) += ls1043a_psci.o
+obj-y += icid.o ls1043_ids.o
endif
ifneq ($(CONFIG_ARCH_LS1012A),)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
new file mode 100644
index 0000000000..0e8649427e
--- /dev/null
+++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1043_ids.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2018 NXP
+ */
+
+#include <common.h>
+#include <asm/arch-fsl-layerscape/immap_lsch2.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
+#include <asm/arch-fsl-layerscape/fsl_portals.h>
+#include <fsl_sec.h>
+
+#ifdef CONFIG_SYS_DPAA_QBMAN
+struct qportal_info qp_info[CONFIG_SYS_QMAN_NUM_PORTALS] = {
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+ SET_QP_INFO(FSL_DPAA1_STREAM_ID_END, 0),
+};
+#endif
+
+struct icid_id_table icid_tbl[] = {
+#ifdef CONFIG_SYS_DPAA_QBMAN
+ SET_QMAN_ICID(FSL_DPAA1_STREAM_ID_START),
+ SET_BMAN_ICID(FSL_DPAA1_STREAM_ID_START + 1),
+#endif
+
+ SET_SDHC_ICID(FSL_SDHC_STREAM_ID),
+
+ SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
+ SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
+ SET_USB_ICID(3, "snps,dwc3", FSL_USB3_STREAM_ID),
+
+ SET_SATA_ICID("fsl,ls1043a-ahci", FSL_SATA_STREAM_ID),
+ SET_QDMA_ICID("fsl,ls1043a-qdma", FSL_QDMA_STREAM_ID),
+ SET_EDMA_ICID(FSL_EDMA_STREAM_ID),
+ SET_ETR_ICID(FSL_ETR_STREAM_ID),
+ SET_DEBUG_ICID(FSL_DEBUG_STREAM_ID),
+ SET_QE_ICID(FSL_QE_STREAM_ID),
+#ifdef CONFIG_FSL_CAAM
+ SET_SEC_QI_ICID(FSL_DPAA1_STREAM_ID_START + 2),
+ SET_SEC_JR_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 3),
+ SET_SEC_JR_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 4),
+ SET_SEC_JR_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 5),
+ SET_SEC_JR_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 6),
+ SET_SEC_RTIC_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 7),
+ SET_SEC_RTIC_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 8),
+ SET_SEC_RTIC_ICID_ENTRY(2, FSL_DPAA1_STREAM_ID_START + 9),
+ SET_SEC_RTIC_ICID_ENTRY(3, FSL_DPAA1_STREAM_ID_START + 10),
+ SET_SEC_DECO_ICID_ENTRY(0, FSL_DPAA1_STREAM_ID_START + 11),
+ SET_SEC_DECO_ICID_ENTRY(1, FSL_DPAA1_STREAM_ID_START + 12),
+#endif
+};
+
+int icid_tbl_sz = ARRAY_SIZE(icid_tbl);
+
+#ifdef CONFIG_SYS_DPAA_FMAN
+struct fman_icid_id_table fman_icid_tbl[] = {
+ /* port id, icid */
+ SET_FMAN_ICID_ENTRY(0x02, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x03, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x04, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x05, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x06, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x07, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x08, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x09, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x0d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x28, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x29, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2a, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2b, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2c, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x2d, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x10, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x11, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x30, FSL_DPAA1_STREAM_ID_END),
+ SET_FMAN_ICID_ENTRY(0x31, FSL_DPAA1_STREAM_ID_END),
+};
+
+int fman_icid_tbl_sz = ARRAY_SIZE(fman_icid_tbl);
+#endif
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
index 3f15cb08ff..54fb0745f9 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c
@@ -634,7 +634,7 @@ void fsl_lsch2_early_init_f(void)
erratum_a008997();
erratum_a009007();
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
set_icids();
#endif
}
diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
index a70c866651..a3f473fe28 100644
--- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
+++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h
@@ -68,6 +68,10 @@ void fdt_fixup_icid(void *blob);
#define SET_DEBUG_ICID(streamid) \
SET_SCFG_ICID(NULL, streamid, debug_icid, 0)
+#define SET_QE_ICID(streamid) \
+ SET_SCFG_ICID("fsl,qe", streamid, qe_icid,\
+ QE_BASE_ADDR)
+
#define SET_QMAN_ICID(streamid) \
SET_ICID_ENTRY("fsl,qman", streamid, streamid, \
offsetof(struct ccsr_qman, liodnr) + \
diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c
index 4fba57242b..44cc509b53 100644
--- a/board/freescale/ls1043aqds/ls1043aqds.c
+++ b/board/freescale/ls1043aqds/ls1043aqds.c
@@ -14,6 +14,7 @@
#include <asm/arch/fdt.h>
#include <asm/arch/mmu.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <ahci.h>
#include <hwconfig.h>
#include <mmc.h>
@@ -353,6 +354,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_board_enet(blob);
#endif
+ fdt_fixup_icid(blob);
+
reg = QIXIS_READ(brdcfg[0]);
reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c
index e7d8650d27..f31f0ec515 100644
--- a/board/freescale/ls1043ardb/ls1043ardb.c
+++ b/board/freescale/ls1043ardb/ls1043ardb.c
@@ -9,6 +9,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/fsl_serdes.h>
#include <asm/arch/soc.h>
+#include <asm/arch-fsl-layerscape/fsl_icid.h>
#include <fdt_support.h>
#include <hwconfig.h>
#include <ahci.h>
@@ -177,6 +178,8 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_fman_ethernet(blob);
#endif
+ fdt_fixup_icid(blob);
+
/*
* qe-hdlc and usb multi-use the pins,
* when set hwconfig to qe-hdlc, delete usb node.
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 4/4] armv8: ls1043a: enable icid setup for qman portals
2018-08-27 14:33 [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches laurentiu.tudor at nxp.com
` (2 preceding siblings ...)
2018-08-27 14:33 ` [U-Boot] [PATCH 3/4] armv8: ls1043a: add icid setup support laurentiu.tudor at nxp.com
@ 2018-08-27 14:34 ` laurentiu.tudor at nxp.com
3 siblings, 0 replies; 6+ messages in thread
From: laurentiu.tudor at nxp.com @ 2018-08-27 14:34 UTC (permalink / raw)
To: u-boot
From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
Enable support for ICID setup of qman portals and the required device
tree fixups.
Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
---
drivers/misc/fsl_portals.c | 11 ++++++-----
1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c
index d3137680ad..45eed22f6e 100644
--- a/drivers/misc/fsl_portals.c
+++ b/drivers/misc/fsl_portals.c
@@ -49,7 +49,7 @@ void setup_qbman_portals(void)
out_be32(&qman->qcsp[i].qcsp_io_cfg, (sdest << 16) | fliodn);
}
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int i;
for (i = 0; i < CONFIG_SYS_QMAN_NUM_PORTALS; i++) {
@@ -197,7 +197,7 @@ void fdt_fixup_qportals(void *blob)
char compat[64];
int compat_len;
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
int smmu_ph = fdt_get_smmu_phandle(blob);
#endif
@@ -211,7 +211,8 @@ void fdt_fixup_qportals(void *blob)
off = fdt_node_offset_by_compatible(blob, -1, "fsl,qman-portal");
while (off != -FDT_ERR_NOTFOUND) {
-#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1046A)
+#if defined(CONFIG_PPC) || defined(CONFIG_ARCH_LS1043A) || \
+defined(CONFIG_ARCH_LS1046A)
#ifdef CONFIG_FSL_CORENET
u32 liodns[2];
#endif
@@ -226,7 +227,7 @@ void fdt_fixup_qportals(void *blob)
int j;
#endif
-#endif /* CONFIG_PPC || CONFIG_ARCH_LS1046A */
+#endif /* CONFIG_PPC || CONFIG_ARCH_LS1043A || CONFIG_ARCH_LS1046A */
err = fdt_setprop(blob, off, "compatible", compat, compat_len);
if (err < 0)
goto err;
@@ -275,7 +276,7 @@ void fdt_fixup_qportals(void *blob)
goto err;
#endif
#else
-#ifdef CONFIG_ARCH_LS1046A
+#if defined(CONFIG_ARCH_LS1043A) || defined(CONFIG_ARCH_LS1046A)
if (smmu_ph >= 0) {
u32 icids[3];
--
2.17.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define
2018-08-27 14:33 ` [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define laurentiu.tudor at nxp.com
@ 2018-09-28 15:45 ` York Sun
0 siblings, 0 replies; 6+ messages in thread
From: York Sun @ 2018-09-28 15:45 UTC (permalink / raw)
To: u-boot
On 08/27/2018 07:34 AM, laurentiu.tudor at nxp.com wrote:
> From: Laurentiu Tudor <laurentiu.tudor@nxp.com>
>
> Add define for quiccengine register block base address.
>
> Signed-off-by: Laurentiu Tudor <laurentiu.tudor@nxp.com>
> ---
This patch set is applied to fsl-qoriq master, awaiting upstream. Thanks.
York
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2018-09-28 15:45 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-08-27 14:33 [U-Boot] [PATCH 0/4] NXP LS1043A SMMU enabling patches laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 1/4] armv8: fsl-layerscape: add missing qe base address define laurentiu.tudor at nxp.com
2018-09-28 15:45 ` York Sun
2018-08-27 14:33 ` [U-Boot] [PATCH 2/4] armv8: ls1043a: advertise QMan v3 in configuration laurentiu.tudor at nxp.com
2018-08-27 14:33 ` [U-Boot] [PATCH 3/4] armv8: ls1043a: add icid setup support laurentiu.tudor at nxp.com
2018-08-27 14:34 ` [U-Boot] [PATCH 4/4] armv8: ls1043a: enable icid setup for qman portals laurentiu.tudor at nxp.com
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