[PATCH] drm/i915: Fix ICL HDMI clock readout

[PATCH] drm/i915: Fix ICL HDMI clock readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
mgr into the clock readout function as well.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
 drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3b115ce4029..68b301e6f41d 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 
 	ref_clock = dev_priv->cdclk.hw.ref;
 
+	/*
+	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
+	 * because the DPLL automatically divides that by 2.
+	 */
+	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
+		ref_clock = 19200;
+
 	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
 
 	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
-- 
2.16.4

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✓ Fi.CI.BAT: success for drm/i915: Fix ICL HDMI clock readout

[Patchwork]

== Series Details ==

Series: drm/i915: Fix ICL HDMI clock readout
URL   : https://patchwork.freedesktop.org/series/48805/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4718 -> Patchwork_10033 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/48805/revisions/1/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10033 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    
    ==== Possible fixes ====

    igt@drv_selftest@live_hangcheck:
      {fi-cfl-8109u}:     DMESG-FAIL (fdo#106560) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
      fi-snb-2520m:       INCOMPLETE (fdo#103713) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
  fdo#106560 https://bugs.freedesktop.org/show_bug.cgi?id=106560
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (54 -> 49) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4718 -> Patchwork_10033

  CI_DRM_4718: c7398fd19cef9b11c79af7292109507b6be075c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4611: b966dd93a30f41581fe1dbf9bc1c4a29b552ca05 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10033: ba9430cfcf157a221066a8db9e64ee371ee461aa @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

ba9430cfcf15 drm/i915: Fix ICL HDMI clock readout

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10033/issues.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH] drm/i915: Fix ICL HDMI clock readout

[Rodrigo Vivi]

On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> mgr into the clock readout function as well.
> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f3b115ce4029..68b301e6f41d 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>  
>  	ref_clock = dev_priv->cdclk.hw.ref;

could we move this up to the beginning of the function and
then reuse that if (INTEL_GEN(dev_priv) >= 11) {  block?

Anyway, this change is needed and right so however you decide
to proceed:

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

>  
> +	/*
> +	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> +	 * because the DPLL automatically divides that by 2.
> +	 */
> +	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> +		ref_clock = 19200;
> +
>  	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
>  
>  	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> -- 
> 2.16.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

✓ Fi.CI.IGT: success for drm/i915: Fix ICL HDMI clock readout

[Patchwork]

== Series Details ==

Series: drm/i915: Fix ICL HDMI clock readout
URL   : https://patchwork.freedesktop.org/series/48805/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4718_full -> Patchwork_10033_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10033_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_cursor_crc@cursor-64x64-suspend:
      shard-kbl:          PASS -> INCOMPLETE (fdo#103665, fdo#107556)

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
      shard-glk:          FAIL (fdo#107589) -> PASS

    igt@kms_flip@2x-flip-vs-expired-vblank:
      shard-glk:          FAIL (fdo#105363) -> PASS

    igt@kms_pipe_crc_basic@read-crc-pipe-b:
      shard-glk:          DMESG-WARN (fdo#105763) -> PASS +1

    
  fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
  fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
  fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
  fdo#107556 https://bugs.freedesktop.org/show_bug.cgi?id=107556
  fdo#107589 https://bugs.freedesktop.org/show_bug.cgi?id=107589
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4718 -> Patchwork_10033

  CI_DRM_4718: c7398fd19cef9b11c79af7292109507b6be075c4 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4611: b966dd93a30f41581fe1dbf9bc1c4a29b552ca05 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10033: ba9430cfcf157a221066a8db9e64ee371ee461aa @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10033/shards.html
_______________________________________________
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Intel-gfx@lists.freedesktop.org
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Re: [PATCH] drm/i915: Fix ICL HDMI clock readout

[Ville Syrjälä]

On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > mgr into the clock readout function as well.
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> >  1 file changed, 7 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3b115ce4029..68b301e6f41d 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >  
> >  	ref_clock = dev_priv->cdclk.hw.ref;
> 
> could we move this up to the beginning of the function and
> then reuse that if (INTEL_GEN(dev_priv) >= 11) {  block?

Possible? Sure. Clearer? Not so sure.

Probably the correct answer would be to add some kind of
cnl_pll_ref_clock() helper that encapsulats the magic exception,
and then use that from all the places that need it.

> 
> Anyway, this change is needed and right so however you decide
> to proceed:
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> >  
> > +	/*
> > +	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > +	 * because the DPLL automatically divides that by 2.
> > +	 */
> > +	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> > +		ref_clock = 19200;
> > +
> >  	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> >  
> >  	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > -- 
> > 2.16.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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Re: [PATCH] drm/i915: Fix ICL HDMI clock readout

[Rodrigo Vivi]

On Thu, Aug 30, 2018 at 06:48:45PM +0300, Ville Syrjälä wrote:
> On Tue, Aug 28, 2018 at 01:36:22PM -0700, Rodrigo Vivi wrote:
> > On Tue, Aug 28, 2018 at 06:32:01PM +0300, Ville Syrjala wrote:
> > > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > 
> > > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > > mgr into the clock readout function as well.
> > > 
> > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/intel_ddi.c | 7 +++++++
> > >  1 file changed, 7 insertions(+)
> > > 
> > > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > > index f3b115ce4029..68b301e6f41d 100644
> > > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > > @@ -1416,6 +1416,13 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> > >  
> > >  	ref_clock = dev_priv->cdclk.hw.ref;
> > 
> > could we move this up to the beginning of the function and
> > then reuse that if (INTEL_GEN(dev_priv) >= 11) {  block?
> 
> Possible? Sure. Clearer? Not so sure.

yeap... I'm not confident this would be clearer...

> 
> Probably the correct answer would be to add some kind of
> cnl_pll_ref_clock() helper that encapsulats the magic exception,
> and then use that from all the places that need it.

hmm... probably

> 
> > 
> > Anyway, this change is needed and right so however you decide
> > to proceed:
> > 
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > 
> > >  
> > > +	/*
> > > +	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > > +	 * because the DPLL automatically divides that by 2.
> > > +	 */
> > > +	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)

what about to at least make it (INTEL_GEN(dev_priv) >= 11)
to be compatible with above's statement?

> > > +		ref_clock = 19200;
> > > +
> > >  	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> > >  
> > >  	dco_freq += (((cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
> > > -- 
> > > 2.16.4
> > > 
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> 
> -- 
> Ville Syrjälä
> Intel
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[PATCH v2] drm/i915: Fix ICL+ HDMI clock readout

[Ville Syrjala]

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
mgr into the clock readout function as well.

v2: Refactor the code into a common function
    s/is_icl/gen11+/ (Rodrigo)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v1
---
 drivers/gpu/drm/i915/intel_ddi.c      |  2 +-
 drivers/gpu/drm/i915/intel_dpll_mgr.c | 23 +++++++++++++++--------
 drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
 3 files changed, 17 insertions(+), 9 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index f3b115ce4029..3e64488a2b0a 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -1414,7 +1414,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
 		break;
 	}
 
-	ref_clock = dev_priv->cdclk.hw.ref;
+	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
 
 	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
 
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
index 04d41bc1a4bb..e6cac9225536 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
@@ -2212,6 +2212,20 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
 	params->dco_fraction = dco & 0x7fff;
 }
 
+int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
+{
+	int ref_clock = dev_priv->cdclk.hw.ref;
+
+	/*
+	 * For ICL+, the spec states: if reference frequency is 38.4,
+	 * use 19.2 because the DPLL automatically divides that by 2.
+	 */
+	if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
+		ref_clock = 19200;
+
+	return ref_clock;
+}
+
 static bool
 cnl_ddi_calculate_wrpll(int clock,
 			struct drm_i915_private *dev_priv,
@@ -2251,14 +2265,7 @@ cnl_ddi_calculate_wrpll(int clock,
 
 	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
 
-	ref_clock = dev_priv->cdclk.hw.ref;
-
-	/*
-	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
-	 * because the DPLL automatically divides that by 2.
-	 */
-	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
-		ref_clock = 19200;
+	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
 
 	cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
 				  kdiv);
diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
index 7e522cf4f13f..bf0de8a4dc63 100644
--- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
+++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
@@ -344,5 +344,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
 			      struct intel_dpll_hw_state *hw_state);
 int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
 			       uint32_t pll_id);
+int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
 
 #endif /* _INTEL_DPLL_MGR_H_ */
-- 
2.16.4

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✓ Fi.CI.BAT: success for drm/i915: Fix ICL HDMI clock readout (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix ICL HDMI clock readout (rev2)
URL   : https://patchwork.freedesktop.org/series/48805/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4757 -> Patchwork_10072 =

== Summary - SUCCESS ==

  No regressions found.

  External URL: https://patchwork.freedesktop.org/api/1.0/series/48805/revisions/2/mbox/

== Known issues ==

  Here are the changes found in Patchwork_10072 that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@amdgpu/amd_basic@userptr:
      fi-kbl-8809g:       PASS -> INCOMPLETE (fdo#107402)

    igt@drv_module_reload@basic-reload:
      fi-blb-e6850:       PASS -> INCOMPLETE (fdo#107718)

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
      {fi-byt-clapper}:   PASS -> FAIL (fdo#107362)

    igt@prime_vgem@basic-fence-flip:
      fi-ilk-650:         PASS -> FAIL (fdo#104008)

    
    ==== Possible fixes ====

    igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b-frame-sequence:
      {fi-byt-clapper}:   FAIL (fdo#103191, fdo#107362) -> PASS

    igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
      fi-bxt-dsi:         INCOMPLETE (fdo#103927) -> PASS

    igt@kms_psr@primary_page_flip:
      fi-cnl-psr:         FAIL (fdo#107336) -> PASS

    
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
  fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
  fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
  fdo#107336 https://bugs.freedesktop.org/show_bug.cgi?id=107336
  fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
  fdo#107402 https://bugs.freedesktop.org/show_bug.cgi?id=107402
  fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718


== Participating hosts (53 -> 48) ==

  Missing    (5): fi-ctg-p8600 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u 


== Build changes ==

    * Linux: CI_DRM_4757 -> Patchwork_10072

  CI_DRM_4757: 1465de895e2b5d9e74e9a85189c9075155efa30d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4621: 125eee6e981eac0a004aeb4f327439a132ceac5c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10072: 7ea7034989566579e4784e861a66d533949ca598 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

7ea703498956 drm/i915: Fix ICL+ HDMI clock readout

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10072/issues.html
_______________________________________________
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✓ Fi.CI.IGT: success for drm/i915: Fix ICL HDMI clock readout (rev2)

[Patchwork]

== Series Details ==

Series: drm/i915: Fix ICL HDMI clock readout (rev2)
URL   : https://patchwork.freedesktop.org/series/48805/
State : success

== Summary ==

= CI Bug Log - changes from CI_DRM_4757_full -> Patchwork_10072_full =

== Summary - SUCCESS ==

  No regressions found.

  

== Known issues ==

  Here are the changes found in Patchwork_10072_full that come from known issues:

  === IGT changes ===

    ==== Issues hit ====

    igt@kms_plane_lowres@pipe-b-tiling-x:
      shard-kbl:          PASS -> DMESG-WARN (fdo#105345)

    igt@kms_setmode@basic:
      shard-kbl:          PASS -> FAIL (fdo#99912)

    
    ==== Possible fixes ====

    igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
      shard-apl:          DMESG-WARN (fdo#105602, fdo#103558) -> PASS +2

    igt@kms_setmode@basic:
      shard-apl:          FAIL (fdo#99912) -> PASS

    igt@kms_vblank@pipe-b-ts-continuation-idle-hang:
      shard-apl:          DMESG-WARN -> PASS

    igt@pm_rc6_residency@rc6-accuracy:
      shard-glk:          INCOMPLETE (fdo#103359, k.org#198133) -> PASS

    
  fdo#103359 https://bugs.freedesktop.org/show_bug.cgi?id=103359
  fdo#103558 https://bugs.freedesktop.org/show_bug.cgi?id=103558
  fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345
  fdo#105602 https://bugs.freedesktop.org/show_bug.cgi?id=105602
  fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
  k.org#198133 https://bugzilla.kernel.org/show_bug.cgi?id=198133


== Participating hosts (5 -> 5) ==

  No changes in participating hosts


== Build changes ==

    * Linux: CI_DRM_4757 -> Patchwork_10072

  CI_DRM_4757: 1465de895e2b5d9e74e9a85189c9075155efa30d @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_4621: 125eee6e981eac0a004aeb4f327439a132ceac5c @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_10072: 7ea7034989566579e4784e861a66d533949ca598 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10072/shards.html
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Re: [PATCH v2] drm/i915: Fix ICL+ HDMI clock readout

[Rodrigo Vivi]

On Mon, Sep 03, 2018 at 05:28:41PM +0300, Ville Syrjala wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> mgr into the clock readout function as well.
> 
> v2: Refactor the code into a common function
>     s/is_icl/gen11+/ (Rodrigo)

neat

> 
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v1

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_ddi.c      |  2 +-
>  drivers/gpu/drm/i915/intel_dpll_mgr.c | 23 +++++++++++++++--------
>  drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
>  3 files changed, 17 insertions(+), 9 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index f3b115ce4029..3e64488a2b0a 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -1414,7 +1414,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
>  		break;
>  	}
>  
> -	ref_clock = dev_priv->cdclk.hw.ref;
> +	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
>  
>  	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
>  
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> index 04d41bc1a4bb..e6cac9225536 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> @@ -2212,6 +2212,20 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
>  	params->dco_fraction = dco & 0x7fff;
>  }
>  
> +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
> +{
> +	int ref_clock = dev_priv->cdclk.hw.ref;
> +
> +	/*
> +	 * For ICL+, the spec states: if reference frequency is 38.4,
> +	 * use 19.2 because the DPLL automatically divides that by 2.
> +	 */
> +	if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
> +		ref_clock = 19200;
> +
> +	return ref_clock;
> +}
> +
>  static bool
>  cnl_ddi_calculate_wrpll(int clock,
>  			struct drm_i915_private *dev_priv,
> @@ -2251,14 +2265,7 @@ cnl_ddi_calculate_wrpll(int clock,
>  
>  	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
>  
> -	ref_clock = dev_priv->cdclk.hw.ref;
> -
> -	/*
> -	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> -	 * because the DPLL automatically divides that by 2.
> -	 */
> -	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> -		ref_clock = 19200;
> +	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
>  
>  	cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
>  				  kdiv);
> diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> index 7e522cf4f13f..bf0de8a4dc63 100644
> --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> @@ -344,5 +344,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
>  			      struct intel_dpll_hw_state *hw_state);
>  int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
>  			       uint32_t pll_id);
> +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
>  
>  #endif /* _INTEL_DPLL_MGR_H_ */
> -- 
> 2.16.4
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
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Re: [PATCH v2] drm/i915: Fix ICL+ HDMI clock readout

[Ville Syrjälä]

On Mon, Sep 03, 2018 at 10:21:30PM -0700, Rodrigo Vivi wrote:
> On Mon, Sep 03, 2018 at 05:28:41PM +0300, Ville Syrjala wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > 
> > Copy the 38.4 vs. 19.2 MHz ref clock exception from the dpll
> > mgr into the clock readout function as well.
> > 
> > v2: Refactor the code into a common function
> >     s/is_icl/gen11+/ (Rodrigo)
> 
> neat
> 
> > 
> > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107722
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com> #v1
> 
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

Thanks. Pushed.

> 
> > ---
> >  drivers/gpu/drm/i915/intel_ddi.c      |  2 +-
> >  drivers/gpu/drm/i915/intel_dpll_mgr.c | 23 +++++++++++++++--------
> >  drivers/gpu/drm/i915/intel_dpll_mgr.h |  1 +
> >  3 files changed, 17 insertions(+), 9 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> > index f3b115ce4029..3e64488a2b0a 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -1414,7 +1414,7 @@ static int cnl_calc_wrpll_link(struct drm_i915_private *dev_priv,
> >  		break;
> >  	}
> >  
> > -	ref_clock = dev_priv->cdclk.hw.ref;
> > +	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> >  
> >  	dco_freq = (cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * ref_clock;
> >  
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.c b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > index 04d41bc1a4bb..e6cac9225536 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.c
> > @@ -2212,6 +2212,20 @@ static void cnl_wrpll_params_populate(struct skl_wrpll_params *params,
> >  	params->dco_fraction = dco & 0x7fff;
> >  }
> >  
> > +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv)
> > +{
> > +	int ref_clock = dev_priv->cdclk.hw.ref;
> > +
> > +	/*
> > +	 * For ICL+, the spec states: if reference frequency is 38.4,
> > +	 * use 19.2 because the DPLL automatically divides that by 2.
> > +	 */
> > +	if (INTEL_GEN(dev_priv) >= 11 && ref_clock == 38400)
> > +		ref_clock = 19200;
> > +
> > +	return ref_clock;
> > +}
> > +
> >  static bool
> >  cnl_ddi_calculate_wrpll(int clock,
> >  			struct drm_i915_private *dev_priv,
> > @@ -2251,14 +2265,7 @@ cnl_ddi_calculate_wrpll(int clock,
> >  
> >  	cnl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
> >  
> > -	ref_clock = dev_priv->cdclk.hw.ref;
> > -
> > -	/*
> > -	 * For ICL, the spec states: if reference frequency is 38.4, use 19.2
> > -	 * because the DPLL automatically divides that by 2.
> > -	 */
> > -	if (IS_ICELAKE(dev_priv) && ref_clock == 38400)
> > -		ref_clock = 19200;
> > +	ref_clock = cnl_hdmi_pll_ref_clock(dev_priv);
> >  
> >  	cnl_wrpll_params_populate(wrpll_params, best_dco, ref_clock, pdiv, qdiv,
> >  				  kdiv);
> > diff --git a/drivers/gpu/drm/i915/intel_dpll_mgr.h b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > index 7e522cf4f13f..bf0de8a4dc63 100644
> > --- a/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > +++ b/drivers/gpu/drm/i915/intel_dpll_mgr.h
> > @@ -344,5 +344,6 @@ void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
> >  			      struct intel_dpll_hw_state *hw_state);
> >  int icl_calc_dp_combo_pll_link(struct drm_i915_private *dev_priv,
> >  			       uint32_t pll_id);
> > +int cnl_hdmi_pll_ref_clock(struct drm_i915_private *dev_priv);
> >  
> >  #endif /* _INTEL_DPLL_MGR_H_ */
> > -- 
> > 2.16.4
> > 
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Ville Syrjälä
Intel
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