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* [radeon-alex:drm-next-4.20-wip 229/235] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.c:202:34: sparse: expression using sizeof(void)
@ 2018-08-29  6:55 kbuild test robot
  0 siblings, 0 replies; only message in thread
From: kbuild test robot @ 2018-08-29  6:55 UTC (permalink / raw)
  To: Amber Lin; +Cc: Alex Deucher, Felix Kuehling, kbuild-all, dri-devel

tree:   git://people.freedesktop.org/~agd5f/linux.git drm-next-4.20-wip
head:   bdb1922abd620d24715906bac4d119274d98f4c9
commit: 04d5e2765802241b54ee93d1e655123c39fa7385 [229/235] drm/amdgpu: Merge amdkfd into amdgpu
reproduce:
        # apt-get install sparse
        git checkout 04d5e2765802241b54ee93d1e655123c39fa7385
        make ARCH=x86_64 allmodconfig
        make C=1 CF=-D__CHECK_ENDIAN__


sparse warnings: (new ones prefixed by >>)

>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.c:202:34: sparse: expression using sizeof(void)
--
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.c:204:33: sparse: expression using sizeof(void)
--
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue_vi.c:134:31: sparse: expression using sizeof(void)
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue_vi.c:134:31: sparse: expression using sizeof(void)
--
   include/linux/slab.h:631:13: sparse: undefined identifier '__builtin_mul_overflow'
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.c:648:27: sparse: expression using sizeof(void)
   include/linux/slab.h:631:13: sparse: call with no type!
--
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:37:16: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:43:17: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:47:21: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:48:21: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:73:21: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:74:21: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:75:17: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:76:16: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:77:22: sparse: cast to restricted __le32
   drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.c:90:36: sparse: cast to restricted __le32
--
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_iommu.c:87:23: sparse: expression using sizeof(void)
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_iommu.c:87:23: sparse: expression using sizeof(void)
--
>> drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pm4_headers_ai.h:517:80: sparse: dubious one-bit signed bitfield

vim +202 drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.c

d696d536f Ben Goz        2015-01-12  159  
d696d536f Ben Goz        2015-01-12  160  static int __update_mqd(struct mqd_manager *mm, void *mqd,
d696d536f Ben Goz        2015-01-12  161  			struct queue_properties *q, unsigned int mtype,
d696d536f Ben Goz        2015-01-12  162  			unsigned int atc_bit)
d696d536f Ben Goz        2015-01-12  163  {
d696d536f Ben Goz        2015-01-12  164  	struct vi_mqd *m;
d696d536f Ben Goz        2015-01-12  165  
d696d536f Ben Goz        2015-01-12  166  	m = get_mqd(mqd);
d696d536f Ben Goz        2015-01-12  167  
d696d536f Ben Goz        2015-01-12  168  	m->cp_hqd_pq_control = 5 << CP_HQD_PQ_CONTROL__RPTR_BLOCK_SIZE__SHIFT |
d696d536f Ben Goz        2015-01-12  169  			atc_bit << CP_HQD_PQ_CONTROL__PQ_ATC__SHIFT |
d696d536f Ben Goz        2015-01-12  170  			mtype << CP_HQD_PQ_CONTROL__MTYPE__SHIFT;
115c8c410 Felix Kuehling 2017-11-06  171  	m->cp_hqd_pq_control |=	order_base_2(q->queue_size / 4) - 1;
79775b627 Kent Russell   2017-08-15  172  	pr_debug("cp_hqd_pq_control 0x%x\n", m->cp_hqd_pq_control);
d696d536f Ben Goz        2015-01-12  173  
d696d536f Ben Goz        2015-01-12  174  	m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8);
d696d536f Ben Goz        2015-01-12  175  	m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8);
d696d536f Ben Goz        2015-01-12  176  
d696d536f Ben Goz        2015-01-12  177  	m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr);
d696d536f Ben Goz        2015-01-12  178  	m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr);
ee04955af Felix Kuehling 2018-01-04  179  	m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr);
ee04955af Felix Kuehling 2018-01-04  180  	m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr);
d696d536f Ben Goz        2015-01-12  181  
d696d536f Ben Goz        2015-01-12  182  	m->cp_hqd_pq_doorbell_control =
d696d536f Ben Goz        2015-01-12  183  		q->doorbell_off <<
d696d536f Ben Goz        2015-01-12  184  			CP_HQD_PQ_DOORBELL_CONTROL__DOORBELL_OFFSET__SHIFT;
79775b627 Kent Russell   2017-08-15  185  	pr_debug("cp_hqd_pq_doorbell_control 0x%x\n",
d696d536f Ben Goz        2015-01-12  186  			m->cp_hqd_pq_doorbell_control);
d696d536f Ben Goz        2015-01-12  187  
d696d536f Ben Goz        2015-01-12  188  	m->cp_hqd_eop_control = atc_bit << CP_HQD_EOP_CONTROL__EOP_ATC__SHIFT |
d696d536f Ben Goz        2015-01-12  189  			mtype << CP_HQD_EOP_CONTROL__MTYPE__SHIFT;
d696d536f Ben Goz        2015-01-12  190  
d696d536f Ben Goz        2015-01-12  191  	m->cp_hqd_ib_control = atc_bit << CP_HQD_IB_CONTROL__IB_ATC__SHIFT |
d696d536f Ben Goz        2015-01-12  192  			3 << CP_HQD_IB_CONTROL__MIN_IB_AVAIL_SIZE__SHIFT |
d696d536f Ben Goz        2015-01-12  193  			mtype << CP_HQD_IB_CONTROL__MTYPE__SHIFT;
d696d536f Ben Goz        2015-01-12  194  
af68d87ca Jay Cornwall   2017-08-15  195  	/*
af68d87ca Jay Cornwall   2017-08-15  196  	 * HW does not clamp this field correctly. Maximum EOP queue size
af68d87ca Jay Cornwall   2017-08-15  197  	 * is constrained by per-SE EOP done signal count, which is 8-bit.
af68d87ca Jay Cornwall   2017-08-15  198  	 * Limit is 0xFF EOP entries (= 0x7F8 dwords). CP will not submit
af68d87ca Jay Cornwall   2017-08-15  199  	 * more than (EOP entry count - 1) so a queue size of 0x800 dwords
af68d87ca Jay Cornwall   2017-08-15  200  	 * is safe, giving a maximum field value of 0xA.
af68d87ca Jay Cornwall   2017-08-15  201  	 */
af68d87ca Jay Cornwall   2017-08-15 @202  	m->cp_hqd_eop_control |= min(0xA,
115c8c410 Felix Kuehling 2017-11-06  203  		order_base_2(q->eop_ring_buffer_size / 4) - 1);
d696d536f Ben Goz        2015-01-12  204  	m->cp_hqd_eop_base_addr_lo =
d696d536f Ben Goz        2015-01-12  205  			lower_32_bits(q->eop_ring_buffer_address >> 8);
d696d536f Ben Goz        2015-01-12  206  	m->cp_hqd_eop_base_addr_hi =
d696d536f Ben Goz        2015-01-12  207  			upper_32_bits(q->eop_ring_buffer_address >> 8);
d696d536f Ben Goz        2015-01-12  208  
d696d536f Ben Goz        2015-01-12  209  	m->cp_hqd_iq_timer = atc_bit << CP_HQD_IQ_TIMER__IQ_ATC__SHIFT |
d696d536f Ben Goz        2015-01-12  210  			mtype << CP_HQD_IQ_TIMER__MTYPE__SHIFT;
d696d536f Ben Goz        2015-01-12  211  
d696d536f Ben Goz        2015-01-12  212  	m->cp_hqd_vmid = q->vmid;
d696d536f Ben Goz        2015-01-12  213  
d696d536f Ben Goz        2015-01-12  214  	if (q->format == KFD_QUEUE_FORMAT_AQL) {
d696d536f Ben Goz        2015-01-12  215  		m->cp_hqd_pq_control |= CP_HQD_PQ_CONTROL__NO_UPDATE_RPTR_MASK |
d696d536f Ben Goz        2015-01-12  216  				2 << CP_HQD_PQ_CONTROL__SLOT_BASED_WPTR__SHIFT;
d696d536f Ben Goz        2015-01-12  217  	}
d696d536f Ben Goz        2015-01-12  218  
373d70808 Felix Kuehling 2017-11-14  219  	if (mm->dev->cwsr_enabled && q->ctx_save_restore_area_address)
373d70808 Felix Kuehling 2017-11-14  220  		m->cp_hqd_ctx_save_control =
373d70808 Felix Kuehling 2017-11-14  221  			atc_bit << CP_HQD_CTX_SAVE_CONTROL__ATC__SHIFT |
373d70808 Felix Kuehling 2017-11-14  222  			mtype << CP_HQD_CTX_SAVE_CONTROL__MTYPE__SHIFT;
373d70808 Felix Kuehling 2017-11-14  223  
39e7f3318 Felix Kuehling 2018-07-14  224  	update_cu_mask(mm, mqd, q);
39e7f3318 Felix Kuehling 2018-07-14  225  
bba9662db Jay Cornwall   2017-11-01  226  	q->is_active = (q->queue_size > 0 &&
d696d536f Ben Goz        2015-01-12  227  			q->queue_address != 0 &&
26103436d Felix Kuehling 2018-02-06  228  			q->queue_percent > 0 &&
26103436d Felix Kuehling 2018-02-06  229  			!q->is_evicted);
d696d536f Ben Goz        2015-01-12  230  
d696d536f Ben Goz        2015-01-12  231  	return 0;
d696d536f Ben Goz        2015-01-12  232  }
d696d536f Ben Goz        2015-01-12  233  

:::::: The code at line 202 was first introduced by commit
:::::: af68d87cac0664c9118e76727e4273eab56deb83 drm/amdkfd: Clamp EOP queue size correctly on Gfx8

:::::: TO: Jay Cornwall <Jay.Cornwall@amd.com>
:::::: CC: Oded Gabbay <oded.gabbay@gmail.com>

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
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2018-08-29  6:55 [radeon-alex:drm-next-4.20-wip 229/235] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.c:202:34: sparse: expression using sizeof(void) kbuild test robot

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