From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, Stefan Agner <stefan@agner.ch> Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v3 16/38] mmc: tegra: Program pad autocal offsets from dt Date: Thu, 30 Aug 2018 18:06:17 +0300 [thread overview] Message-ID: <20180830150639.21048-17-avienamo@nvidia.com> (raw) In-Reply-To: <20180830150639.21048-1-avienamo@nvidia.com> Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 152 ++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index ec07a3ce0247..a3e31f18db48 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -50,6 +50,7 @@ #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) +#define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f @@ -73,6 +74,22 @@ struct sdhci_tegra_soc_data { u32 nvquirks; }; +/* Magic pull up and pull down pad calibration offsets */ +struct sdhci_tegra_autocal_offsets { + u32 pull_up_3v3; + u32 pull_down_3v3; + u32 pull_up_3v3_timeout; + u32 pull_down_3v3_timeout; + u32 pull_up_1v8; + u32 pull_down_1v8; + u32 pull_up_1v8_timeout; + u32 pull_down_1v8_timeout; + u32 pull_up_sdr104; + u32 pull_down_sdr104; + u32 pull_up_hs400; + u32 pull_down_hs400; +}; + struct sdhci_tegra { const struct sdhci_tegra_soc_data *soc_data; struct gpio_desc *power_gpio; @@ -84,6 +101,8 @@ struct sdhci_tegra { struct pinctrl *pinctrl_sdmmc; struct pinctrl_state *pinctrl_state_3v3; struct pinctrl_state *pinctrl_state_1v8; + + struct sdhci_tegra_autocal_offsets autocal_offsets; }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -281,12 +300,45 @@ static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) return status; } +static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, + u16 pdpu) +{ + u32 reg; + + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; + reg |= pdpu; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct sdhci_tegra_autocal_offsets offsets = + tegra_host->autocal_offsets; + struct mmc_ios *ios = &host->mmc->ios; bool card_clk_enabled; + u16 pdpu; u32 reg; int ret; + switch (ios->timing) { + case MMC_TIMING_UHS_SDR104: + pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; + break; + case MMC_TIMING_MMC_HS400: + pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; + break; + default: + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; + else + pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; + } + + tegra_sdhci_set_pad_autocal_offset(host, pdpu); + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); tegra_sdhci_configure_cal_pad(host, true); @@ -305,8 +357,104 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) tegra_sdhci_configure_card_clk(host, card_clk_enabled); - if (ret) + if (ret) { dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); + + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + pdpu = offsets.pull_down_1v8_timeout << 8 | + offsets.pull_up_1v8_timeout; + else + pdpu = offsets.pull_down_3v3_timeout << 8 | + offsets.pull_up_3v3_timeout; + + /* Disable automatic calibration and use fixed offsets */ + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg &= ~SDHCI_AUTO_CAL_ENABLE; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); + + tegra_sdhci_set_pad_autocal_offset(host, pdpu); + } +} + +static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct sdhci_tegra_autocal_offsets *autocal = + &tegra_host->autocal_offsets; + int err; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-3v3", + &autocal->pull_up_3v3); + if (err) + autocal->pull_up_3v3 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-3v3", + &autocal->pull_down_3v3); + if (err) + autocal->pull_down_3v3 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-1v8", + &autocal->pull_up_1v8); + if (err) + autocal->pull_up_1v8 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-1v8", + &autocal->pull_down_1v8); + if (err) + autocal->pull_down_1v8 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-3v3-timeout", + &autocal->pull_up_3v3); + if (err) + autocal->pull_up_3v3_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-3v3-timeout", + &autocal->pull_down_3v3); + if (err) + autocal->pull_down_3v3_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-1v8-timeout", + &autocal->pull_up_1v8); + if (err) + autocal->pull_up_1v8_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-1v8-timeout", + &autocal->pull_down_1v8); + if (err) + autocal->pull_down_1v8_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-sdr104", + &autocal->pull_up_sdr104); + if (err) + autocal->pull_up_sdr104 = autocal->pull_up_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-sdr104", + &autocal->pull_down_sdr104); + if (err) + autocal->pull_down_sdr104 = autocal->pull_down_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-hs400", + &autocal->pull_up_hs400); + if (err) + autocal->pull_up_hs400 = autocal->pull_up_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-hs400", + &autocal->pull_down_hs400); + if (err) + autocal->pull_down_hs400 = autocal->pull_down_1v8; } static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) @@ -698,6 +846,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) host->mmc->caps |= MMC_CAP_1_8V_DDR; + tegra_sdhci_parse_pad_autocal_dt(host); + tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", GPIOD_OUT_HIGH); if (IS_ERR(tegra_host->power_gpio)) { -- 2.18.0
WARNING: multiple messages have this Message-ID (diff)
From: Aapo Vienamo <avienamo@nvidia.com> To: Rob Herring <robh+dt@kernel.org>, Mark Rutland <mark.rutland@arm.com>, Thierry Reding <thierry.reding@gmail.com>, Jonathan Hunter <jonathanh@nvidia.com>, Ulf Hansson <ulf.hansson@linaro.org>, Adrian Hunter <adrian.hunter@intel.com>, Mikko Perttunen <mperttunen@nvidia.com>, Stefan Agner <stefan@agner.ch> Cc: <devicetree@vger.kernel.org>, <linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>, <linux-mmc@vger.kernel.org>, Aapo Vienamo <avienamo@nvidia.com> Subject: [PATCH v3 16/38] mmc: tegra: Program pad autocal offsets from dt Date: Thu, 30 Aug 2018 18:06:17 +0300 [thread overview] Message-ID: <20180830150639.21048-17-avienamo@nvidia.com> (raw) In-Reply-To: <20180830150639.21048-1-avienamo@nvidia.com> Parse the pad drive strength calibration offsets from the device tree. Program the calibration offsets in accordance with the current signaling mode. Signed-off-by: Aapo Vienamo <avienamo@nvidia.com> Acked-by: Thierry Reding <treding@nvidia.com> --- drivers/mmc/host/sdhci-tegra.c | 152 ++++++++++++++++++++++++++++++++- 1 file changed, 151 insertions(+), 1 deletion(-) diff --git a/drivers/mmc/host/sdhci-tegra.c b/drivers/mmc/host/sdhci-tegra.c index ec07a3ce0247..a3e31f18db48 100644 --- a/drivers/mmc/host/sdhci-tegra.c +++ b/drivers/mmc/host/sdhci-tegra.c @@ -50,6 +50,7 @@ #define SDHCI_TEGRA_AUTO_CAL_CONFIG 0x1e4 #define SDHCI_AUTO_CAL_START BIT(31) #define SDHCI_AUTO_CAL_ENABLE BIT(29) +#define SDHCI_AUTO_CAL_PDPU_OFFSET_MASK 0x0000ffff #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL 0x1e0 #define SDHCI_TEGRA_SDMEM_COMP_PADCTRL_VREF_SEL_MASK 0x0000000f @@ -73,6 +74,22 @@ struct sdhci_tegra_soc_data { u32 nvquirks; }; +/* Magic pull up and pull down pad calibration offsets */ +struct sdhci_tegra_autocal_offsets { + u32 pull_up_3v3; + u32 pull_down_3v3; + u32 pull_up_3v3_timeout; + u32 pull_down_3v3_timeout; + u32 pull_up_1v8; + u32 pull_down_1v8; + u32 pull_up_1v8_timeout; + u32 pull_down_1v8_timeout; + u32 pull_up_sdr104; + u32 pull_down_sdr104; + u32 pull_up_hs400; + u32 pull_down_hs400; +}; + struct sdhci_tegra { const struct sdhci_tegra_soc_data *soc_data; struct gpio_desc *power_gpio; @@ -84,6 +101,8 @@ struct sdhci_tegra { struct pinctrl *pinctrl_sdmmc; struct pinctrl_state *pinctrl_state_3v3; struct pinctrl_state *pinctrl_state_1v8; + + struct sdhci_tegra_autocal_offsets autocal_offsets; }; static u16 tegra_sdhci_readw(struct sdhci_host *host, int reg) @@ -281,12 +300,45 @@ static bool tegra_sdhci_configure_card_clk(struct sdhci_host *host, bool enable) return status; } +static void tegra_sdhci_set_pad_autocal_offset(struct sdhci_host *host, + u16 pdpu) +{ + u32 reg; + + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg &= ~SDHCI_AUTO_CAL_PDPU_OFFSET_MASK; + reg |= pdpu; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); +} + static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) { + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct sdhci_tegra_autocal_offsets offsets = + tegra_host->autocal_offsets; + struct mmc_ios *ios = &host->mmc->ios; bool card_clk_enabled; + u16 pdpu; u32 reg; int ret; + switch (ios->timing) { + case MMC_TIMING_UHS_SDR104: + pdpu = offsets.pull_down_sdr104 << 8 | offsets.pull_up_sdr104; + break; + case MMC_TIMING_MMC_HS400: + pdpu = offsets.pull_down_hs400 << 8 | offsets.pull_up_hs400; + break; + default: + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + pdpu = offsets.pull_down_1v8 << 8 | offsets.pull_up_1v8; + else + pdpu = offsets.pull_down_3v3 << 8 | offsets.pull_up_3v3; + } + + tegra_sdhci_set_pad_autocal_offset(host, pdpu); + card_clk_enabled = tegra_sdhci_configure_card_clk(host, false); tegra_sdhci_configure_cal_pad(host, true); @@ -305,8 +357,104 @@ static void tegra_sdhci_pad_autocalib(struct sdhci_host *host) tegra_sdhci_configure_card_clk(host, card_clk_enabled); - if (ret) + if (ret) { dev_err(mmc_dev(host->mmc), "Pad autocal timed out\n"); + + if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) + pdpu = offsets.pull_down_1v8_timeout << 8 | + offsets.pull_up_1v8_timeout; + else + pdpu = offsets.pull_down_3v3_timeout << 8 | + offsets.pull_up_3v3_timeout; + + /* Disable automatic calibration and use fixed offsets */ + reg = sdhci_readl(host, SDHCI_TEGRA_AUTO_CAL_CONFIG); + reg &= ~SDHCI_AUTO_CAL_ENABLE; + sdhci_writel(host, reg, SDHCI_TEGRA_AUTO_CAL_CONFIG); + + tegra_sdhci_set_pad_autocal_offset(host, pdpu); + } +} + +static void tegra_sdhci_parse_pad_autocal_dt(struct sdhci_host *host) +{ + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_tegra *tegra_host = sdhci_pltfm_priv(pltfm_host); + struct sdhci_tegra_autocal_offsets *autocal = + &tegra_host->autocal_offsets; + int err; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-3v3", + &autocal->pull_up_3v3); + if (err) + autocal->pull_up_3v3 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-3v3", + &autocal->pull_down_3v3); + if (err) + autocal->pull_down_3v3 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-1v8", + &autocal->pull_up_1v8); + if (err) + autocal->pull_up_1v8 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-1v8", + &autocal->pull_down_1v8); + if (err) + autocal->pull_down_1v8 = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-3v3-timeout", + &autocal->pull_up_3v3); + if (err) + autocal->pull_up_3v3_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-3v3-timeout", + &autocal->pull_down_3v3); + if (err) + autocal->pull_down_3v3_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-1v8-timeout", + &autocal->pull_up_1v8); + if (err) + autocal->pull_up_1v8_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-1v8-timeout", + &autocal->pull_down_1v8); + if (err) + autocal->pull_down_1v8_timeout = 0; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-sdr104", + &autocal->pull_up_sdr104); + if (err) + autocal->pull_up_sdr104 = autocal->pull_up_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-sdr104", + &autocal->pull_down_sdr104); + if (err) + autocal->pull_down_sdr104 = autocal->pull_down_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-up-offset-hs400", + &autocal->pull_up_hs400); + if (err) + autocal->pull_up_hs400 = autocal->pull_up_1v8; + + err = device_property_read_u32(host->mmc->parent, + "nvidia,pad-autocal-pull-down-offset-hs400", + &autocal->pull_down_hs400); + if (err) + autocal->pull_down_hs400 = autocal->pull_down_1v8; } static void tegra_sdhci_set_clock(struct sdhci_host *host, unsigned int clock) @@ -698,6 +846,8 @@ static int sdhci_tegra_probe(struct platform_device *pdev) if (tegra_host->soc_data->nvquirks & NVQUIRK_ENABLE_DDR50) host->mmc->caps |= MMC_CAP_1_8V_DDR; + tegra_sdhci_parse_pad_autocal_dt(host); + tegra_host->power_gpio = devm_gpiod_get_optional(&pdev->dev, "power", GPIOD_OUT_HIGH); if (IS_ERR(tegra_host->power_gpio)) { -- 2.18.0
next prev parent reply other threads:[~2018-08-30 15:06 UTC|newest] Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top 2018-08-30 15:06 [PATCH v3 00/38] Tegra SDHCI add support for HS200 and UHS signaling Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 01/38] dt-bindings: Add Tegra PMC pad configuration bindings Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 02/38] dt-bindings: mmc: tegra: Add pad voltage control properties Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 03/38] dt-bindings: Add Tegra SDHCI pad pdpu offset bindings Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 04/38] dt-bindings: mmc: Add Tegra SDHCI sampling trimmer values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:15 ` Ulf Hansson 2018-08-30 15:06 ` [PATCH v3 05/38] soc/tegra: pmc: Fix pad voltage configuration for Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 06/38] soc/tegra: pmc: Factor out DPD register bit calculation Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 07/38] soc/tegra: pmc: Implement tegra_io_pad_is_powered() Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 08/38] soc/tegra: pmc: Use X macro to generate IO pad tables Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 09/38] soc/tegra: pmc: Remove public pad voltage APIs Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 10/38] soc/tegra: pmc: Implement pad configuration via pinctrl Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 11/38] mmc: tegra: Reconfigure pad voltages during voltage switching Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 13:16 ` Ulf Hansson 2018-08-31 13:59 ` Thierry Reding 2018-08-30 15:06 ` [PATCH v3 12/38] mmc: tegra: Poll for calibration completion Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 13/38] mmc: tegra: Set calibration pad voltage reference Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 14/38] mmc: tegra: Power on the calibration pad Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 15/38] mmc: tegra: Disable card clock during pad calibration Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo [this message] 2018-08-30 15:06 ` [PATCH v3 16/38] mmc: tegra: Program pad autocal offsets from dt Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 17/38] mmc: tegra: Perform pad calibration after voltage switch Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 18/38] mmc: tegra: Enable pad calibration on Tegra210 and Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 19/38] mmc: tegra: Add a workaround for tap value change glitch Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 20/38] mmc: tegra: Parse default trim and tap from dt Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 21/38] mmc: tegra: Configure default tap values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 22/38] mmc: tegra: Configure default trim value on reset Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 23/38] mmc: tegra: Use standard SDHCI tuning on Tegra210 and Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 24/38] mmc: tegra: Remove tegra_sdhci_writew() from tegra210_sdhci_ops Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 25/38] mmc: tegra: Disable card clock during tuning cmd on Tegra210 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 26/38] mmc: tegra: Enable UHS and HS200 modes for Tegra210 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 27/38] mmc: tegra: Enable UHS and HS200 modes for Tegra186 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 28/38] arm64: dts: Add Tegra210 sdmmc pinctrl voltage states Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 29/38] arm64: dts: Add Tegra186 " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 30/38] arm64: dts: tegra210-p2180: Allow ldo2 to go down to 1.8 V Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 31/38] arm64: dts: tegra210-p2180: Correct sdmmc4 vqmmc-supply Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 32/38] arm64: dts: tegra210-p2597: Remove no-1-8-v from sdmmc1 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 33/38] arm64: dts: tegra186: Add sdmmc pad auto calibration offsets Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 34/38] arm64: dts: tegra210: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 35/38] arm64: dts: tegra210: Add SDHCI tap and trim values Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 36/38] arm64: dts: tegra186: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 37/38] arm64: dts: tegra186: Assign clocks for sdmmc1 and sdmmc4 Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-30 15:06 ` [PATCH v3 38/38] arm64: dts: tegra210: " Aapo Vienamo 2018-08-30 15:06 ` Aapo Vienamo 2018-08-31 7:20 ` [PATCH v3 00/38] Tegra SDHCI add support for HS200 and UHS signaling Adrian Hunter
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20180830150639.21048-17-avienamo@nvidia.com \ --to=avienamo@nvidia.com \ --cc=adrian.hunter@intel.com \ --cc=devicetree@vger.kernel.org \ --cc=jonathanh@nvidia.com \ --cc=linux-kernel@vger.kernel.org \ --cc=linux-mmc@vger.kernel.org \ --cc=linux-tegra@vger.kernel.org \ --cc=mark.rutland@arm.com \ --cc=mperttunen@nvidia.com \ --cc=robh+dt@kernel.org \ --cc=stefan@agner.ch \ --cc=thierry.reding@gmail.com \ --cc=ulf.hansson@linaro.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.