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From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
	Jonathan Hunter <jonathanh@nvidia.com>,
	Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH v1 2/2] ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30
Date: Thu, 30 Aug 2018 22:04:54 +0300	[thread overview]
Message-ID: <20180830190454.8729-3-digetx@gmail.com> (raw)
In-Reply-To: <20180830190454.8729-1-digetx@gmail.com>

The early-resume code shall not switch CPU to PLLX because PLLX
configuration could be unstable or PLLX could be even disabled if
CPU entered suspend on PLLP, it the case if CPUFREQ driver is active.
The actual PLLX configuration and burst policy shall be restored by
the clock driver.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
 arch/arm/mach-tegra/sleep-tegra30.S | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/arm/mach-tegra/sleep-tegra30.S b/arch/arm/mach-tegra/sleep-tegra30.S
index d572d4b860be..127fc78365fe 100644
--- a/arch/arm/mach-tegra/sleep-tegra30.S
+++ b/arch/arm/mach-tegra/sleep-tegra30.S
@@ -396,8 +396,8 @@ _pll_m_c_x_done:
 	str	r4, [r0, #CLK_RESET_SCLK_BURST]
 
 	cmp	r10, #TEGRA30
-	movweq	r4, #:lower16:((1 << 28) | (0x8))	@ burst policy is PLLX
-	movteq	r4, #:upper16:((1 << 28) | (0x8))
+	movweq	r4, #:lower16:((1 << 28) | (0x4))	@ burst policy is PLLP
+	movteq	r4, #:upper16:((1 << 28) | (0x4))
 	movwne	r4, #:lower16:((1 << 28) | (0xe))
 	movtne	r4, #:upper16:((1 << 28) | (0xe))
 	str	r4, [r0, #CLK_RESET_CCLK_BURST]
-- 
2.18.0

  parent reply	other threads:[~2018-08-30 19:04 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-08-30 19:04 [PATCH v1 0/2] LP1/LP2 suspend-resume CPU clock fixes for Tegra30 Dmitry Osipenko
2018-08-30 19:04 ` [PATCH v1 1/2] ARM: tegra: Switch CPU to PLLP before powergating on Tegra30 Dmitry Osipenko
2018-08-30 19:04 ` Dmitry Osipenko [this message]
2018-10-15 12:34 ` [PATCH v1 0/2] LP1/LP2 suspend-resume CPU clock fixes for Tegra30 Dmitry Osipenko

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