* [PATCH v2 0/3] clk: renesas: r7s9210: Add support for early clocks
@ 2018-09-24 16:49 Chris Brandt
2018-09-24 16:49 ` [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support Chris Brandt
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Chris Brandt @ 2018-09-24 16:49 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Simon Horman, Chris Brandt
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
This series add early clock support to cpg-mssr
Here are some notes I took:
* Switched to using
of_iomap(cpg_np, 0)
instead of
platform_get_resource(pdev, IORESOURCE_MEM, 0)
* All devm_xxx calls were replaced with the traditinal functions because
'dev' is not available for early probe
* some functions are still using dev_dbg and dev_err for messages, but
in early init, dev is set to NULL so it doesn't crash, the messages
just look like this:
(NULL device *): Core clock extal at 24000000 Hz
(NULL device *): clock (1, 35) is ostm1 at 66000000 Hz
* np was added to priv
np is saved because dev->of_node doesn't exist during early init and we
need to avoid using 'dev' for any function that will run during early
init
* all .init functions (r8xxxx_cpg_mssr_init) for the SoCs do not use dev,
except for r8a7791_cpg_mssr_init for the lines:
struct device_node *np = dev->of_node;
of_device_is_compatible(np, "renesas,r8a7793-cpg-mssr")
But, so if early clock support was every needed for r8a7791 or r8a7793,
that line will need to be changed.
* In r7s9210-cpg-mssr.c, I moved updating the clock ratio table to a
separate function (r7s9210_update_table) because it looks cleaner.
Chris Brandt (3):
clk: renesas: cpg-mssr: Add early clock support
clk: renesas: r7s9210: Convert some clocks to early
clk: renesas: r7s9210: Move table update to separate function
drivers/clk/renesas/r7s9210-cpg-mssr.c | 126 ++++++++++++++++++++-------------
drivers/clk/renesas/renesas-cpg-mssr.c | 95 +++++++++++++++++++------
drivers/clk/renesas/renesas-cpg-mssr.h | 13 ++++
3 files changed, 163 insertions(+), 71 deletions(-)
--
2.16.1
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support
2018-09-24 16:49 [PATCH v2 0/3] clk: renesas: r7s9210: Add support for early clocks Chris Brandt
@ 2018-09-24 16:49 ` Chris Brandt
2018-09-26 9:23 ` Geert Uytterhoeven
2018-09-24 16:49 ` [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early Chris Brandt
2018-09-24 16:49 ` [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function Chris Brandt
2 siblings, 1 reply; 11+ messages in thread
From: Chris Brandt @ 2018-09-24 16:49 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Simon Horman, Chris Brandt
Add support for SoCs that need to register core and module clocks early in
order to use OF drivers that exclusively use macros such as
TIMER_OF_DECLARE.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* List early clocks first
* Renamed early_priv to cpg_mssr_priv and make it static
* Always set cpg_mssr_priv(early_priv) because it is used for early and
non-early cases.
* of_iomap returns NULL on error, not negative number
* Removed various unnecessary comments
* Add __init to cpg_mssr_common_init
* fixed dev_set_drvdata was not being called for early drivers
---
drivers/clk/renesas/renesas-cpg-mssr.c | 95 +++++++++++++++++++++++++++-------
drivers/clk/renesas/renesas-cpg-mssr.h | 13 +++++
2 files changed, 88 insertions(+), 20 deletions(-)
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.c b/drivers/clk/renesas/renesas-cpg-mssr.c
index 3df764d3ab20..a6ce3d825bfc 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.c
+++ b/drivers/clk/renesas/renesas-cpg-mssr.c
@@ -127,6 +127,7 @@ struct cpg_mssr_priv {
struct device *dev;
void __iomem *base;
spinlock_t rmw_lock;
+ struct device_node *np;
struct clk **clks;
unsigned int num_core_clks;
@@ -141,6 +142,7 @@ struct cpg_mssr_priv {
} smstpcr_saved[ARRAY_SIZE(smstpcr)];
};
+static struct cpg_mssr_priv *cpg_mssr_priv;
/**
* struct mstp_clock - MSTP gating clock
@@ -316,7 +318,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core,
switch (core->type) {
case CLK_TYPE_IN:
- clk = of_clk_get_by_name(priv->dev->of_node, core->name);
+ clk = of_clk_get_by_name(priv->np, core->name);
break;
case CLK_TYPE_FF:
@@ -877,42 +879,43 @@ static const struct dev_pm_ops cpg_mssr_pm = {
#define DEV_PM_OPS NULL
#endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
-static int __init cpg_mssr_probe(struct platform_device *pdev)
+static int __init cpg_mssr_common_init(struct device *dev,
+ struct device_node *np,
+ const struct cpg_mssr_info *info)
{
- struct device *dev = &pdev->dev;
- struct device_node *np = dev->of_node;
- const struct cpg_mssr_info *info;
struct cpg_mssr_priv *priv;
unsigned int nclks, i;
- struct resource *res;
struct clk **clks;
int error;
- info = of_device_get_match_data(dev);
if (info->init) {
error = info->init(dev);
if (error)
return error;
}
- priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ priv = kzalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
+ priv->np = np;
priv->dev = dev;
spin_lock_init(&priv->rmw_lock);
- res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
- priv->base = devm_ioremap_resource(dev, res);
- if (IS_ERR(priv->base))
- return PTR_ERR(priv->base);
+ priv->base = of_iomap(np, 0);
+ if (!priv->base) {
+ error = -ENOMEM;
+ goto out_err;
+ }
nclks = info->num_total_core_clks + info->num_hw_mod_clks;
- clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
- if (!clks)
- return -ENOMEM;
+ clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
+ if (!clks) {
+ error = -ENOMEM;
+ goto out_err;
+ }
- dev_set_drvdata(dev, priv);
+ cpg_mssr_priv = priv;
priv->clks = clks;
priv->num_core_clks = info->num_total_core_clks;
priv->num_mod_clks = info->num_hw_mod_clks;
@@ -923,16 +926,68 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
for (i = 0; i < nclks; i++)
clks[i] = ERR_PTR(-ENOENT);
+ error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
+ if (error)
+ goto out_err;
+
+ return 0;
+
+out_err:
+ kfree(clks);
+ if (priv->base)
+ iounmap(priv->base);
+ kfree(priv);
+
+ return error;
+}
+
+void __init cpg_mssr_early_init(struct device_node *np,
+ const struct cpg_mssr_info *info)
+{
+ int error;
+ int i;
+
+ error = cpg_mssr_common_init(NULL, np, info);
+ if (error)
+ return;
+
+ for (i = 0; i < info->num_early_core_clks; i++)
+ cpg_mssr_register_core_clk(&info->early_core_clks[i], info,
+ cpg_mssr_priv);
+
+ for (i = 0; i < info->num_early_mod_clks; i++)
+ cpg_mssr_register_mod_clk(&info->early_mod_clks[i], info,
+ cpg_mssr_priv);
+
+}
+
+static int __init cpg_mssr_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct device_node *np = dev->of_node;
+ const struct cpg_mssr_info *info;
+ struct cpg_mssr_priv *priv;
+ unsigned int i;
+ int error;
+
+ info = of_device_get_match_data(dev);
+
+ if (!cpg_mssr_priv) {
+ error = cpg_mssr_common_init(dev, dev->of_node, info);
+ if (error)
+ return error;
+ }
+
+ priv = cpg_mssr_priv;
+ priv->dev = dev;
+ dev_set_drvdata(dev, priv);
+
for (i = 0; i < info->num_core_clks; i++)
cpg_mssr_register_core_clk(&info->core_clks[i], info, priv);
for (i = 0; i < info->num_mod_clks; i++)
cpg_mssr_register_mod_clk(&info->mod_clks[i], info, priv);
- error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
- if (error)
- return error;
-
error = devm_add_action_or_reset(dev,
cpg_mssr_del_clk_provider,
np);
diff --git a/drivers/clk/renesas/renesas-cpg-mssr.h b/drivers/clk/renesas/renesas-cpg-mssr.h
index ae0ab0f164f3..630ad6c6960f 100644
--- a/drivers/clk/renesas/renesas-cpg-mssr.h
+++ b/drivers/clk/renesas/renesas-cpg-mssr.h
@@ -88,6 +88,11 @@ struct device_node;
/**
* SoC-specific CPG/MSSR Description
*
+ * @early_core_clks: Array of Early Core Clock definitions
+ * @num_early_core_clks: Number of entries in early_core_clks[]
+ * @early_mod_clks: Array of Early Module Clock definitions
+ * @num_early_mod_clks: Number of entries in early_mod_clks[]
+ *
* @core_clks: Array of Core Clock definitions
* @num_core_clks: Number of entries in core_clks[]
* @last_dt_core_clk: ID of the last Core Clock exported to DT
@@ -114,6 +119,12 @@ struct device_node;
*/
struct cpg_mssr_info {
+ /* Early Clocks */
+ const struct cpg_core_clk *early_core_clks;
+ unsigned int num_early_core_clks;
+ const struct mssr_mod_clk *early_mod_clks;
+ unsigned int num_early_mod_clks;
+
/* Core Clocks */
const struct cpg_core_clk *core_clks;
unsigned int num_core_clks;
@@ -160,6 +171,8 @@ extern const struct cpg_mssr_info r8a77980_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77990_cpg_mssr_info;
extern const struct cpg_mssr_info r8a77995_cpg_mssr_info;
+void __init cpg_mssr_early_init(struct device_node *np,
+ const struct cpg_mssr_info *info);
/*
* Helpers for fixing up clock tables depending on SoC revision
--
2.16.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early
2018-09-24 16:49 [PATCH v2 0/3] clk: renesas: r7s9210: Add support for early clocks Chris Brandt
2018-09-24 16:49 ` [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support Chris Brandt
@ 2018-09-24 16:49 ` Chris Brandt
2018-09-26 9:24 ` Geert Uytterhoeven
2018-09-24 16:49 ` [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function Chris Brandt
2 siblings, 1 reply; 11+ messages in thread
From: Chris Brandt @ 2018-09-24 16:49 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Simon Horman, Chris Brandt
The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
ostm module clocks to be registers early in boot.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
v2:
* List early clocks first
* Remove unnecessary comments
* Removed new function r7s9210_update_clk_table (to be included in a
separate patch)
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 32 ++++++++++++++++++++++++++------
1 file changed, 26 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index bd1dd4ff2051..7ab9030ef8b9 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -53,7 +53,7 @@ enum clk_ids {
MOD_CLK_BASE
};
-static struct cpg_core_clk r7s9210_core_clks[] = {
+static struct cpg_core_clk r7s9210_early_core_clks[] = {
/* External Clock Inputs */
DEF_INPUT("extal", CLK_EXTAL),
@@ -61,20 +61,26 @@ static struct cpg_core_clk r7s9210_core_clks[] = {
DEF_BASE(".main", CLK_MAIN, CLK_TYPE_RZA_MAIN, CLK_EXTAL),
DEF_BASE(".pll", CLK_PLL, CLK_TYPE_RZA_PLL, CLK_MAIN),
+ /* Core Clock Outputs */
+ DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
+};
+
+static const struct mssr_mod_clk r7s9210_early_mod_clks[] __initconst = {
+ DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
+ DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
+ DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
+};
+
+static struct cpg_core_clk r7s9210_core_clks[] = {
/* Core Clock Outputs */
DEF_FIXED("i", R7S9210_CLK_I, CLK_PLL, 2, 1),
DEF_FIXED("g", R7S9210_CLK_G, CLK_PLL, 4, 1),
DEF_FIXED("b", R7S9210_CLK_B, CLK_PLL, 8, 1),
DEF_FIXED("p1", R7S9210_CLK_P1, CLK_PLL, 16, 1),
- DEF_FIXED("p1c", R7S9210_CLK_P1C, CLK_PLL, 16, 1),
DEF_FIXED("p0", R7S9210_CLK_P0, CLK_PLL, 32, 1),
};
static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
- DEF_MOD_STB("ostm2", 34, R7S9210_CLK_P1C),
- DEF_MOD_STB("ostm1", 35, R7S9210_CLK_P1C),
- DEF_MOD_STB("ostm0", 36, R7S9210_CLK_P1C),
-
DEF_MOD_STB("scif4", 43, R7S9210_CLK_P1C),
DEF_MOD_STB("scif3", 44, R7S9210_CLK_P1C),
DEF_MOD_STB("scif2", 45, R7S9210_CLK_P1C),
@@ -170,6 +176,12 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev,
}
const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
+ /* Early Clocks */
+ .early_core_clks = r7s9210_early_core_clks,
+ .num_early_core_clks = ARRAY_SIZE(r7s9210_early_core_clks),
+ .early_mod_clks = r7s9210_early_mod_clks,
+ .num_early_mod_clks = ARRAY_SIZE(r7s9210_early_mod_clks),
+
/* Core Clocks */
.core_clks = r7s9210_core_clks,
.num_core_clks = ARRAY_SIZE(r7s9210_core_clks),
@@ -187,3 +199,11 @@ const struct cpg_mssr_info r7s9210_cpg_mssr_info __initconst = {
/* RZ/A2 has Standby Control Registers */
.stbyctrl = true,
};
+
+static void __init r7s9210_cpg_mssr_early_init(struct device_node *np)
+{
+ cpg_mssr_early_init(np, &r7s9210_cpg_mssr_info);
+}
+
+CLK_OF_DECLARE_DRIVER(cpg_mstp_clks, "renesas,r7s9210-cpg-mssr",
+ r7s9210_cpg_mssr_early_init);
--
2.16.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function
2018-09-24 16:49 [PATCH v2 0/3] clk: renesas: r7s9210: Add support for early clocks Chris Brandt
2018-09-24 16:49 ` [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support Chris Brandt
2018-09-24 16:49 ` [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early Chris Brandt
@ 2018-09-24 16:49 ` Chris Brandt
2018-09-26 9:27 ` Geert Uytterhoeven
2 siblings, 1 reply; 11+ messages in thread
From: Chris Brandt @ 2018-09-24 16:49 UTC (permalink / raw)
To: Geert Uytterhoeven, Michael Turquette, Stephen Boyd
Cc: linux-clk, linux-renesas-soc, Simon Horman, Chris Brandt
Same functionality, just easier to read.
Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
---
drivers/clk/renesas/r7s9210-cpg-mssr.c | 94 ++++++++++++++++++----------------
1 file changed, 49 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
index 7ab9030ef8b9..f9c22b61883b 100644
--- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
+++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
@@ -97,6 +97,53 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
};
+/* The clock dividers in the table vary based on DT and register settings */
+static void r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base)
+{
+ int i;
+ u16 frqcr;
+ u8 index;
+
+ /* If EXTAL is above 12MHz, then we know it is Mode 1 */
+ if (clk_get_rate(extal_clk) > 12000000)
+ cpg_mode = 1;
+
+ frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
+ if (frqcr == 0x012)
+ index = 0;
+ else if (frqcr == 0x112)
+ index = 1;
+ else if (frqcr == 0x212)
+ index = 2;
+ else if (frqcr == 0x322)
+ index = 3;
+ else if (frqcr == 0x333)
+ index = 4;
+ else
+ BUG_ON(1); /* Illegal FRQCR value */
+
+ for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
+ switch (r7s9210_core_clks[i].id) {
+ case R7S9210_CLK_I:
+ r7s9210_core_clks[i].div = ratio_tab[index].i;
+ break;
+ case R7S9210_CLK_G:
+ r7s9210_core_clks[i].div = ratio_tab[index].g;
+ break;
+ case R7S9210_CLK_B:
+ r7s9210_core_clks[i].div = ratio_tab[index].b;
+ break;
+ case R7S9210_CLK_P1:
+ case R7S9210_CLK_P1C:
+ r7s9210_core_clks[i].div = ratio_tab[index].p1;
+ break;
+ case R7S9210_CLK_P0:
+ r7s9210_core_clks[i].div = 32;
+ break;
+ }
+ }
+}
+
struct clk * __init rza2_cpg_clk_register(struct device *dev,
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
struct clk **clks, void __iomem *base,
@@ -105,9 +152,6 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev,
struct clk *parent;
unsigned int mult = 1;
unsigned int div = 1;
- u16 frqcr;
- u8 index;
- int i;
parent = clks[core->parent];
if (IS_ERR(parent))
@@ -128,48 +172,8 @@ struct clk * __init rza2_cpg_clk_register(struct device *dev,
return ERR_PTR(-EINVAL);
}
- /* Adjust the dividers based on the current FRQCR setting */
- if (core->id == CLK_MAIN) {
-
- /* If EXTAL is above 12MHz, then we know it is Mode 1 */
- if (clk_get_rate(parent) > 12000000)
- cpg_mode = 1;
-
- frqcr = clk_readl(base + CPG_FRQCR) & 0xFFF;
- if (frqcr == 0x012)
- index = 0;
- else if (frqcr == 0x112)
- index = 1;
- else if (frqcr == 0x212)
- index = 2;
- else if (frqcr == 0x322)
- index = 3;
- else if (frqcr == 0x333)
- index = 4;
- else
- BUG_ON(1); /* Illegal FRQCR value */
-
- for (i = 0; i < ARRAY_SIZE(r7s9210_core_clks); i++) {
- switch (r7s9210_core_clks[i].id) {
- case R7S9210_CLK_I:
- r7s9210_core_clks[i].div = ratio_tab[index].i;
- break;
- case R7S9210_CLK_G:
- r7s9210_core_clks[i].div = ratio_tab[index].g;
- break;
- case R7S9210_CLK_B:
- r7s9210_core_clks[i].div = ratio_tab[index].b;
- break;
- case R7S9210_CLK_P1:
- case R7S9210_CLK_P1C:
- r7s9210_core_clks[i].div = ratio_tab[index].p1;
- break;
- case R7S9210_CLK_P0:
- r7s9210_core_clks[i].div = 32;
- break;
- }
- }
- }
+ if (core->id == CLK_MAIN)
+ r7s9210_update_clk_table(parent, base);
return clk_register_fixed_factor(NULL, core->name,
__clk_get_name(parent), 0, mult, div);
--
2.16.1
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support
2018-09-24 16:49 ` [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support Chris Brandt
@ 2018-09-26 9:23 ` Geert Uytterhoeven
2018-09-26 12:30 ` Chris Brandt
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2018-09-26 9:23 UTC (permalink / raw)
To: Chris Brandt
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
Hi Chris,
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt <chris.brandt@renesas.com> wrote:
> Add support for SoCs that need to register core and module clocks early in
> order to use OF drivers that exclusively use macros such as
> TIMER_OF_DECLARE.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
> * List early clocks first
> * Renamed early_priv to cpg_mssr_priv and make it static
> * Always set cpg_mssr_priv(early_priv) because it is used for early and
> non-early cases.
> * of_iomap returns NULL on error, not negative number
> * Removed various unnecessary comments
> * Add __init to cpg_mssr_common_init
> * fixed dev_set_drvdata was not being called for early drivers
Thanks for the update!
Works fine on R-Car Gen2 and Gen3.
> --- a/drivers/clk/renesas/renesas-cpg-mssr.c
> +++ b/drivers/clk/renesas/renesas-cpg-mssr.c
> @@ -877,42 +879,43 @@ static const struct dev_pm_ops cpg_mssr_pm = {
> #define DEV_PM_OPS NULL
> #endif /* CONFIG_PM_SLEEP && CONFIG_ARM_PSCI_FW */
>
> -static int __init cpg_mssr_probe(struct platform_device *pdev)
> +static int __init cpg_mssr_common_init(struct device *dev,
> + struct device_node *np,
> + const struct cpg_mssr_info *info)
> {
> - struct device *dev = &pdev->dev;
> - struct device_node *np = dev->of_node;
> - const struct cpg_mssr_info *info;
> struct cpg_mssr_priv *priv;
> unsigned int nclks, i;
> - struct resource *res;
> struct clk **clks;
In v1, you initialized clks to NULL, which was needed ...
> int error;
>
> - info = of_device_get_match_data(dev);
> if (info->init) {
> error = info->init(dev);
> if (error)
> return error;
> }
>
> - priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
> + priv = kzalloc(sizeof(*priv), GFP_KERNEL);
> if (!priv)
> return -ENOMEM;
>
> + priv->np = np;
> priv->dev = dev;
> spin_lock_init(&priv->rmw_lock);
>
> - res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> - priv->base = devm_ioremap_resource(dev, res);
> - if (IS_ERR(priv->base))
> - return PTR_ERR(priv->base);
> + priv->base = of_iomap(np, 0);
> + if (!priv->base) {
> + error = -ENOMEM;
> + goto out_err;
... because else it's still uninitialized here ...
> + }
>
> nclks = info->num_total_core_clks + info->num_hw_mod_clks;
> - clks = devm_kmalloc_array(dev, nclks, sizeof(*clks), GFP_KERNEL);
> - if (!clks)
> - return -ENOMEM;
> + clks = kmalloc_array(nclks, sizeof(*clks), GFP_KERNEL);
> + if (!clks) {
> + error = -ENOMEM;
> + goto out_err;
> + }
>
> - dev_set_drvdata(dev, priv);
> + cpg_mssr_priv = priv;
> priv->clks = clks;
> priv->num_core_clks = info->num_total_core_clks;
> priv->num_mod_clks = info->num_hw_mod_clks;
> @@ -923,16 +926,68 @@ static int __init cpg_mssr_probe(struct platform_device *pdev)
> for (i = 0; i < nclks; i++)
> clks[i] = ERR_PTR(-ENOENT);
>
> + error = of_clk_add_provider(np, cpg_mssr_clk_src_twocell_get, priv);
> + if (error)
> + goto out_err;
> +
> + return 0;
> +
> +out_err:
> + kfree(clks);
... and freed here.
> + if (priv->base)
> + iounmap(priv->base);
> + kfree(priv);
> +
> + return error;
> +}
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early
2018-09-24 16:49 ` [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early Chris Brandt
@ 2018-09-26 9:24 ` Geert Uytterhoeven
0 siblings, 0 replies; 11+ messages in thread
From: Geert Uytterhoeven @ 2018-09-26 9:24 UTC (permalink / raw)
To: Chris Brandt
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt <chris.brandt@renesas.com> wrote:
> The OSTM timer driver for RZ/A2 uses TIMER_OF_DECLARE which requires the
> ostm module clocks to be registers early in boot.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> v2:
> * List early clocks first
> * Remove unnecessary comments
> * Removed new function r7s9210_update_clk_table (to be included in a
> separate patch)
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function
2018-09-24 16:49 ` [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function Chris Brandt
@ 2018-09-26 9:27 ` Geert Uytterhoeven
2018-09-26 12:34 ` Chris Brandt
0 siblings, 1 reply; 11+ messages in thread
From: Geert Uytterhoeven @ 2018-09-26 9:27 UTC (permalink / raw)
To: Chris Brandt
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
On Mon, Sep 24, 2018 at 6:50 PM Chris Brandt <chris.brandt@renesas.com> wrote:
> Same functionality, just easier to read.
>
> Signed-off-by: Chris Brandt <chris.brandt@renesas.com>
> ---
> drivers/clk/renesas/r7s9210-cpg-mssr.c | 94 ++++++++++++++++++----------------
> 1 file changed, 49 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/clk/renesas/r7s9210-cpg-mssr.c b/drivers/clk/renesas/r7s9210-cpg-mssr.c
> index 7ab9030ef8b9..f9c22b61883b 100644
> --- a/drivers/clk/renesas/r7s9210-cpg-mssr.c
> +++ b/drivers/clk/renesas/r7s9210-cpg-mssr.c
> @@ -97,6 +97,53 @@ static const struct mssr_mod_clk r7s9210_mod_clks[] __initconst = {
>
> };
>
> +/* The clock dividers in the table vary based on DT and register settings */
> +static void r7s9210_update_clk_table(struct clk *extal_clk, void __iomem *base)
Can be __init.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in clk-renesas-for-v4.20, with the above fixed.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support
2018-09-26 9:23 ` Geert Uytterhoeven
@ 2018-09-26 12:30 ` Chris Brandt
0 siblings, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2018-09-26 12:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
Hi Geert
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> Thanks for the update!
> Works fine on R-Car Gen2 and Gen3.
Thank you for checking!
> > struct clk **clks;
>
> In v1, you initialized clks to NULL, which was needed ...
~~~
> > + priv->base = of_iomap(np, 0);
> > + if (!priv->base) {
> > + error = -ENOMEM;
> > + goto out_err;
>
> ... because else it's still uninitialized here ...
~~~
> > +out_err:
> > + kfree(clks);
>
> ... and freed here.
Damn! I could not remember why I set it to NULL. And I moved so much
code around I thought it was a mistake, so I took it out.
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in clk-renesas-for-v4.20, with the above fixed.
OK, I'll send a new version out shortly.
Chris
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support
@ 2018-09-26 12:30 ` Chris Brandt
0 siblings, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2018-09-26 12:30 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
SGkgR2VlcnQNCg0KT24gV2VkbmVzZGF5LCBTZXB0ZW1iZXIgMjYsIDIwMTgsIEdlZXJ0IFV5dHRl
cmhvZXZlbiB3cm90ZToNCj4gVGhhbmtzIGZvciB0aGUgdXBkYXRlIQ0KPiBXb3JrcyBmaW5lIG9u
IFItQ2FyIEdlbjIgYW5kIEdlbjMuDQoNClRoYW5rIHlvdSBmb3IgY2hlY2tpbmchDQoNCg0KPiA+
ICAgICAgICAgc3RydWN0IGNsayAqKmNsa3M7DQo+IA0KPiBJbiB2MSwgeW91IGluaXRpYWxpemVk
IGNsa3MgdG8gTlVMTCwgd2hpY2ggd2FzIG5lZWRlZCAuLi4NCn5+fg0KPiA+ICsgICAgICAgcHJp
di0+YmFzZSA9IG9mX2lvbWFwKG5wLCAwKTsNCj4gPiArICAgICAgIGlmICghcHJpdi0+YmFzZSkg
ew0KPiA+ICsgICAgICAgICAgICAgICBlcnJvciA9IC1FTk9NRU07DQo+ID4gKyAgICAgICAgICAg
ICAgIGdvdG8gb3V0X2VycjsNCj4gDQo+IC4uLiBiZWNhdXNlIGVsc2UgaXQncyBzdGlsbCB1bmlu
aXRpYWxpemVkIGhlcmUgLi4uDQp+fn4NCj4gPiArb3V0X2VycjoNCj4gPiArICAgICAgIGtmcmVl
KGNsa3MpOw0KPiANCj4gLi4uIGFuZCBmcmVlZCBoZXJlLg0KDQpEYW1uISBJIGNvdWxkIG5vdCBy
ZW1lbWJlciB3aHkgSSBzZXQgaXQgdG8gTlVMTC4gQW5kIEkgbW92ZWQgc28gbXVjaCANCmNvZGUg
YXJvdW5kIEkgdGhvdWdodCBpdCB3YXMgYSBtaXN0YWtlLCBzbyBJIHRvb2sgaXQgb3V0Lg0KDQoN
Cg0KPiBSZXZpZXdlZC1ieTogR2VlcnQgVXl0dGVyaG9ldmVuIDxnZWVydCtyZW5lc2FzQGdsaWRl
ci5iZT4NCj4gaS5lLiB3aWxsIHF1ZXVlIGluIGNsay1yZW5lc2FzLWZvci12NC4yMCwgd2l0aCB0
aGUgYWJvdmUgZml4ZWQuDQoNCk9LLCBJJ2xsIHNlbmQgYSBuZXcgdmVyc2lvbiBvdXQgc2hvcnRs
eS4NCg0KQ2hyaXMNCg0K
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function
2018-09-26 9:27 ` Geert Uytterhoeven
@ 2018-09-26 12:34 ` Chris Brandt
0 siblings, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2018-09-26 12:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
Hi Geert,
On Wednesday, September 26, 2018, Geert Uytterhoeven wrote:
> > +/* The clock dividers in the table vary based on DT and register
> settings */
> > +static void r7s9210_update_clk_table(struct clk *extal_clk, void
> __iomem *base)
>
> Can be __init.
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> i.e. will queue in clk-renesas-for-v4.20, with the above fixed.
OK, thank you!
Chris
^ permalink raw reply [flat|nested] 11+ messages in thread
* RE: [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function
@ 2018-09-26 12:34 ` Chris Brandt
0 siblings, 0 replies; 11+ messages in thread
From: Chris Brandt @ 2018-09-26 12:34 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Geert Uytterhoeven, Michael Turquette, Stephen Boyd, linux-clk,
Linux-Renesas, Simon Horman
SGkgR2VlcnQsDQoNCk9uIFdlZG5lc2RheSwgU2VwdGVtYmVyIDI2LCAyMDE4LCBHZWVydCBVeXR0
ZXJob2V2ZW4gd3JvdGU6DQo+ID4gKy8qIFRoZSBjbG9jayBkaXZpZGVycyBpbiB0aGUgdGFibGUg
dmFyeSBiYXNlZCBvbiBEVCBhbmQgcmVnaXN0ZXINCj4gc2V0dGluZ3MgKi8NCj4gPiArc3RhdGlj
IHZvaWQgcjdzOTIxMF91cGRhdGVfY2xrX3RhYmxlKHN0cnVjdCBjbGsgKmV4dGFsX2Nsaywgdm9p
ZA0KPiBfX2lvbWVtICpiYXNlKQ0KPiANCj4gQ2FuIGJlIF9faW5pdC4NCj4gDQo+IFJldmlld2Vk
LWJ5OiBHZWVydCBVeXR0ZXJob2V2ZW4gPGdlZXJ0K3JlbmVzYXNAZ2xpZGVyLmJlPg0KPiBpLmUu
IHdpbGwgcXVldWUgaW4gY2xrLXJlbmVzYXMtZm9yLXY0LjIwLCB3aXRoIHRoZSBhYm92ZSBmaXhl
ZC4NCg0KT0ssIHRoYW5rIHlvdSENCg0KQ2hyaXMNCg0K
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2018-09-26 18:47 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-09-24 16:49 [PATCH v2 0/3] clk: renesas: r7s9210: Add support for early clocks Chris Brandt
2018-09-24 16:49 ` [PATCH v2 1/3] clk: renesas: cpg-mssr: Add early clock support Chris Brandt
2018-09-26 9:23 ` Geert Uytterhoeven
2018-09-26 12:30 ` Chris Brandt
2018-09-26 12:30 ` Chris Brandt
2018-09-24 16:49 ` [PATCH v2 2/3] clk: renesas: r7s9210: Convert some clocks to early Chris Brandt
2018-09-26 9:24 ` Geert Uytterhoeven
2018-09-24 16:49 ` [PATCH v2 3/3] clk: renesas: r7s9210: Move table update to separate function Chris Brandt
2018-09-26 9:27 ` Geert Uytterhoeven
2018-09-26 12:34 ` Chris Brandt
2018-09-26 12:34 ` Chris Brandt
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